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2
LCFC Confidential 2

NM-A621 Rev1.0 Schematic

AMD CARRIZO FP4 Processor with DDRIIIL
3
AMD Exo Pro S3 3

2015-08-17 Rev1.0

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 COVER PAGE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom BE465_NM-A621 Rev
1.0

Date: Thursday, October 01, 2015

E Sheet 1 of 75
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AMD CARRIZO FP4

Memory BUS (DDRIII)
Exo Pro 2G DDR3 S3 PCI-Express 8X Gen2 1DPC DDR3L-SO-DIMM X2
BANK 0, 1, 2, 3
1.35V DDRIIIL 1333/1600 MT/s
1
VRAM 256M*16 *4
Page 16~22
AMD UP TO 16G Page 14~15
1

CARRIZO
USB 2.0 , port 2
int. Camera
Processor USB 2.0 x 2 USB Left
5V 480MHz
USB 3.0 Port 0&1
FP4 BGA 968P USB 2.0 Port 4&5
DP0 29mm * 37mm
eDP Conn. USB3.0 redriver X2
Page 25 USB 3.0 x 2 Page 33
PS8713B
5V 5GT/s
USB 3.0 Port 0&1
DP2 Page 43
HDMI Conn. HDMI_redriver
Page 28 Page 27

PCIe, Port 3
DP1 NGFF Card WLAN
One-Link USB 2.0 Port 0
USB 2.0 Port 7 USB 2.0 , Port 0
2
Page 31 PCIe Port 3 2
USB 3.0 Port 3 page 39

USB 3.0 , Port 2

Realtek USB Right

USB 2.0 Port 6
RTL8111GUS PCIe, Port1 USB charger USB 3.0 Port 2
RJ45 Conn. USB 2.0
Page 38 PCIe , port 1
Page 37
(AOU) Page 53
TPS2546RTER
USB 2.0 Port 6
Page 53 Sub/B
Realtek
RTS5227E JCARD Conn. PCIe, Port 2
Finger printer
PCIe port 6
SD/MMC Page 53 USB 2.0 Port 3
Page 50
3 3
Sub/B

SPI ROM SPI BUS SATA , Port 0

1.8V SATA HDD
8M Page 21 Page 5~12
page 42

LPC BUS HD Audio

3.3V 33MHz
TPM
NPCT652LA0YX
Page 52 Codec SP_OUTR/L
EC CX11852-11Z SPK Conn.
ITE IT8586E/FX Page 44
Page 45

Page 47
HP_R/L_JACK
MIC_CLK/MIC_DATA

4 G-Sensor Touch Pad Thermal Sensor Int. MIC Conn. Ext. MIC Conn. 4

Track Point Int.KBD (JLCD Conn.) HP Conn.

LIS3DHTR F75303M Page 45
Page 52 Page 48 Page 49 Page 51 Sub/B
Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 BLOCK DIAGRAM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
BE465_NM-A621
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, October 01, 2015 Sheet 2 of 75
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SIGNAL
Voltage Rails ( O --> Means ON , X --> Means OFF ) STATE SLP_A# SLP_S3# SLP_S4# SLP_S5# EC_ON SUSP#
+5VS
S0 HIGH HIGH HIGH HIGH ON ON
+3VS
Power Plane +1.5VS S3 (Suspend to RAM) LOW LOW HIGH HIGH ON OFF
+1.05VS
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF
+0.675VS
1 1
+VCC_CORE S5 (Soft OFF) LOW LOW LOW LOW ON OFF
+3VALW +VGA_CORE

B+ +1.35V +3.3VS_VGA
+1.8VS_VGA
+5VALW
+1.35VS_VGA
+1.05VS_VGA
State USB2 Port USB3 Port PCIE Port SATA Port

Port Device Port Device Port Device Port Device

0 WLAN 0 On Board 0 LAN 0 HDD

1 Touch Panel 1 On Board 1 CardReader 1 X
S0 O O O O 2 CMOS 2 SUB/B 2 WLAN
3 FPR 3 ONE-Link DOCK 3 X
4 On Board 0 GPU
S3 O O O X 5 On Board 1 GPU
2 6 SUB/B 2 GPU 2

7 ONE-Link DOCK 3 GPU

S5 S4/AC Only O O X X 4 GPU
5 GPU
S5 S4 6 GPU
Battery only O X X X 7 GPU

S5 S4
AC & Battery X X X X SMBUS Control Table
don't exist
Main WLAN Thermal CP CHARGER
SOURCE VGA BATT SODIMM WiMAX Sensor APU Module IC LAN PHY G-Sensor
PCH

EC_SMB_CK1 IT8586FX
EC_SMB_DA1 +3VL X V X X X X X V X X
3 3
EC_SMB_CK3 IT8586FX
EC_SMB_DA3 +3VALW V
+3VS_VGA
X X X V V X X X V
+3VS +1.8VS +3VALW
ZZZ1 PCB@

APU
APU_SMB0CLK
APU_SMB0DATA +3VS X X V X X X X V X X
+3VS
NM-A621
DA80000YY10
APU_SMB1CLK APU
APU_SMB1DATA
+3VS X X X X X X V X X X

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 NOTE LIST

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
BE465_NM-A621
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, October 01, 2015 Sheet 3 of 75
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BOM Structure Table

VGA and DDR3 Voltage Rails (JET TOPAZ GPIO)
BOM Structure NOTE
GPIO I/O ACTIVE Function Description

GPIO0 OUT N/A EXO@ For GPU_EXO

GPIO5 IN - GPIO5_AC_BATT MESO@ For GPU_MESO
D D

GPIO6 IN - GPIO6 DIS@ For GPU function

GPIO7 OUT N/A X76@ GPU VRAM Setting
GPIO8 OUT - GPIO8_ROMSO TPM@ Trusted Platform Module(TPM)
GPIO9 OUT - GPIO9_ROMSI DIMM1@ JDIMM1 function
GPIO10 OUT - GPIO10_ROMSCK DIMM2@ JDIMM2 function
GPIO11 OUT N/A UMA@ UMA SKU ID
GPIO12 OUT N/A DPRE@ DP re-driver function
GPIO13 OUT N/A NODPRE@ Disable DP re-driver
GPIO15 IN N/A SVI2_SVD MIRROR@ For mirror function
GPIO16 OUT N/A ME@ ME Connector

C
GPIO17 OUT N/A ESD@ For ESD function C

GPIO19 OUT N/A GPIO19_CTF EMI@ For EMI function

GPIO20 IN IN SVI2_SVC NVPRO@ For Non-VPRO function
GPIO21 OUT N/A VPRO@ For VPRO function
GPIO22 OUT N/A GPIO22_ROMCSB U31@ For U3 port1 redriver function
GPIO29 OUT N/A U32@ For U3 port2 redriver function
GPIO30 OUT N/A U33@ For U3 port3 redriver function

+3VS_VGA

+0.95VS_VGA
B B

+1.8VS_VGA

+VGA_CORE RV104 RV105

Memory (GDDR3)
+1.35VS_VGA 10us

1G SA22225SH30*4 PU 8.45K PD 2K
Samsung
RESET
2G SA000063F00*4 PU 3.4K PD 10K

1G SA00005VS10*4 PU 4.53K PD 2K
Hynix
1. all power rail ramp up time should be within 20ms
2G SA00005YL10*4 PU 4.75K NC

1G SA00005M100*4 NC PD 4.75K
Micron
Device ID 2G SA000060I00*4 PU 3.24K PD 5.62K

JET-XT 0x6664
A A

TOPAZ XT 0x6900

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 VGA NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
BE465_NM-A621
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, October 01, 2015 Sheet 4 of 75
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D D

UC1B

PCIE

PCIE1_CRX_DTX_P U10 R1 PCIE1_CTX_DRX_P CC1 1 2 0.1U_0402_10V7-K PCIE1_CTX_C_DRX_P

37 PCIE1_CRX_DTX_P P_GPP_RXP0 P_GPP_TXP0 PCIE1_CTX_C_DRX_P 37
LAN PCIE1_CRX_DTX_n U9 R2 PCIE1_CTX_DRX_N CC2 1 2 0.1U_0402_10V7-K PCIE1_CTX_C_DRX_N
37 PCIE1_CRX_DTX_N P_GPP_RXN0 P_GPP_TXN0 PCIE1_CTX_C_DRX_N 37LAN
PCIE2_CRX_DTX_P T6 R4 PCIE2_CTX_DRX_P CC3 1 2 0.1U_0402_10V7-K PCIE2_CTX_C_DRX_P
53 PCIE2_CRX_DTX_P P_GPP_RXP1 P_GPP_TXP1 PCIE2_CTX_C_DRX_P 53
CardReader PCIE2_CRX_DTX_N T5 R3 PCIE2_CTX_DRX_N CC4 1 2 0.1U_0402_10V7-K PCIE2_CTX_C_DRX_N
53 PCIE2_CRX_DTX_N P_GPP_RXN1 P_GPP_TXN1 PCIE2_CTX_C_DRX_N 53CardReader
PCIE3_CRX_DTX_P T9 N1 PCIE3_CTX_DRX_P CC5 1 2 0.1U_0402_10V7-K PCIE3_CTX_C_DRX_P
39 PCIE3_CRX_DTX_P PCIE3_CRX_DTX_N T8 P_GPP_RXP2 P_GPP_TXP2 N2 PCIE3_CTX_DRX_N 1 2 0.1U_0402_10V7-K PCIE3_CTX_C_DRX_N PCIE3_CTX_C_DRX_P 39
WLAN CC6
39 PCIE3_CRX_DTX_N P_GPP_RXN2 P_GPP_TXN2 PCIE3_CTX_C_DRX_N 39WLAN
P7 N4
P6 P_GPP_RXP3 P_GPP_TXP3 N3
P_GPP_RXN3 P_GPP_TXN3
C C
RC1 1 2 196_0402_0.5% P_ZVDDP U7 U6 P_ZVSS RC2 1 2 196_0402_0.5%
+0.95VS_VDDP P_ZVDDP P_ZVSS/P_RX_ZVDDP

PCIE_CRX_GTX_P0 P10 M2 PCIE_CTX_GRX_P0

PCIE_CRX_GTX_N0 P9 P_GFX_RXP0 P_GFX_TXP0 M1 PCIE_CTX_GRX_N0
P_GFX_RXN0 P_GFX_TXN0
PCIE_CRX_GTX_P1 N6 L1 PCIE_CTX_GRX_P1
PCIE_CRX_GTX_N1 N5 P_GFX_RXP1 P_GFX_TXP1 L2 PCIE_CTX_GRX_N1
P_GFX_RXN1 P_GFX_TXN1
PCIE_CRX_GTX_P2 N9 L4 PCIE_CTX_GRX_P2
PCIE_CRX_GTX_N2 N8 P_GFX_RXP2 P_GFX_TXP2 L3 PCIE_CTX_GRX_N2
P_GFX_RXN2 P_GFX_TXN2
PCIE_CRX_GTX_P3 L7 J1 PCIE_CTX_GRX_P3
PCIE_CRX_GTX_N3 L6 P_GFX_RXP3 P_GFX_TXP3 J2 PCIE_CTX_GRX_N3
P_GFX_RXN3 P_GFX_TXN3
PCIE_CRX_GTX_P4 L10 J4 PCIE_CTX_GRX_P4
PCIE_CRX_GTX_N4 L9 P_GFX_RXP4 P_GFX_TXP4 J3 PCIE_CTX_GRX_N4
P_GFX_RXN4 P_GFX_TXN4
PCIE_CRX_GTX_P5 K6 H2 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N[0..7]
PCIE_CRX_GTX_N5 K5 P_GFX_RXP5 P_GFX_TXP5 H1 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N[0..7] 16
P_GFX_RXN5 P_GFX_TXN5
PCIE_CTX_GRX_P[0..7]
PCIE_CRX_GTX_P6 K9 G1 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P[0..7] 16
PCIE_CRX_GTX_N6 K8 P_GFX_RXP6 P_GFX_TXP6 G2 PCIE_CTX_GRX_N6 PCIE_CRX_GTX_N[0..7]
B B
P_GFX_RXN6 P_GFX_TXN6 PCIE_CRX_GTX_N[0..7] 16
PCIE_CRX_GTX_P7 J7 G4 PCIE_CTX_GRX_P7 PCIE_CRX_GTX_P[0..7]
PCIE_CRX_GTX_N7 J6 P_GFX_RXP7 P_GFX_TXP7 G3 PCIE_CTX_GRX_N7 PCIE_CRX_GTX_P[0..7] 16
P_GFX_RXN7 P_GFX_TXN7

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 APU PEG/PCIe
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
BE465_NM-A621 1.0

Date: Thursday, October 01, 2015 Sheet 5 of 75

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