Digital System Design Lab-4
Computer Engineering Department
UET Taxila
Instructor: Dr Abdul Rehman Aslam
Lab Engineer: Engr. Shahid Bhutta
Acknowledgement: This Lab material is taken from Digital Systems Design Course,
Electrical Engineering Department by Dr Adeel Pasha, LUMS, Pakistan
In this lab you will learn how to Model a finite state machine (FSM) in Verilog.
Objective:
• Describe the Mealy and Moore Machine in Verilog.
• Describe FSM using different styles of state encoding.
Table of Contents
1 Introduction ........................................................................................................................... 3
2 Moore-Model State Machine ................................................................................................ 3
3 Mealy-Model State Machine ................................................................................................. 3
4 FSM Coding Goals ................................................................................................................ 3
5 Commonly used encoding styles for FSM ........................................................................... 4
5.1 Binary encoding: ............................................................................................................ 4
5.2 One-hot code Encoding:................................................................................................. 4
5.3 Trade-off between Binary and One-Hot Encoding: .................................................... 4
6 Writing FSM in Verilog: ....................................................................................................... 4
6.1 Making default next equal all X's assignment ............................................................. 5
6.2 One-hot FSM Coding Style ............................................................................................ 6
7 Lab Tasks ............................................................................................................................... 8
1 Introduction
The traditional methodology for designing state machines has been to draw a state diagram, map
the states into the minimum number of register bits, and determine the next state function for each
register bit. The minimum number of register bits needed can be determined by rounding up the
natural log of the number of states. This methodology results in a minimum number of registers
but usually requires wide gating and complicated logic to encode the next state bit.
A common classification used to describe the type of an FSM is Mealy and Moore state machines.
2 Moore-Model State Machine
A Moore FSM is a state machine where the outputs are only functions of the present state.
Figure 1: Moore State Machine
3 Mealy-Model State Machine
A Mealy FSM is a state machine where the outputs are functions of the present state and one or
more of the inputs.
Figure 2:Mealy State Machine
4 FSM Coding Goals
⚫ The FSM coding style should be easily modified to change state encodings and FSM styles.
⚫ The coding style should be compact.
⚫ The coding style should be easy to code and understand.
⚫ The coding style should facilitate debugging.
⚫ The coding style should yield efficient synthesis results.
5 State encoding styles for FSM
There are two major styles/schemes of state encoding used for FSM.
1. Binary encoding
2. One-hot encoding
5.1 Binary encoding:
A binary-encoded FSM design only requires as many flip-flops as are needed to uniquely encode
the number of states in the state machine.
Required number of FFs = log2 (number of states)
5.2 One-hot code Encoding:
A one-hot FSM design requires a flip-flop for each state in the design and only one flip-flop (the
flip-flop representing the current or "hot" state) is set at a time in a one-hot FSM design.
5.3 Trade-off between Binary and One-Hot Encoding:
For a state machine with 9-16 states, a binary FSM only requires 4 flip-flops while a one-hot FSM
requires 9-16 flip-flops. However, the next-state logic (FF input combinational logic) expression
becomes very simple for one-hot encoding.
6 Writing FSM in Verilog:
We can directly code FSMs in Verilog. Simply write one of each:
• State register: Sequential always block:
❑ On every positive/negative clock edge, the FFs assume new states.
always @ ( posedge clk or negedge reset)
if (!reset) state <= S0;
else state <= next;
• Next-state/FF-Input combinational logic block:
❑ Combinational always block with case ❑
It is derived from the FF input equations.
always @ (state or x) // why both state
and input??
begin
case (state)
next = S0;
S0: if (x) next = S1; Figure
3:
else next = S0;
S1: if (x) next =
S2; else next = S0;
S2: if (x) next =
S3;
else next = S0;
S3: if (x) next = S3;
else next = S0; Example of a Moore Machine
endcase
end
• Output combinational logic block
❑ Combinational always block or assign statements ❑
It is derived from the output equations.
reg y; // why?
always @ (state) //why no input in the sensitivity
list?? begin
y = 0;
if (state == S3) y = 1;
else y = 0;
end
Most of the times, the two combinational blocks can be combined/merged together to make a single block for
next-state and output logic construction
a) You have to provide the following:-
a. Design details [Mealy or Moore]
b. State transition diagram
c. Verilog code + Test bench
d. Simulation waveform (annotated to show correct working of circuit)
e. Conclusion/Summary/Analysis
b) Submit a zip folder “yourID_LabNo_AssignmentNo.rar” containing all your reports
(“yourID_LabNo_ReportNo.docx”) and project files.
7 Lab Tasks
For all the tasks:
a. Draw a state transition diagram of the system, and mention whether it is Mealy or Moore
machine. Justify clearly.
b. Write the verilog code for the state machine of the mentioned system, its state register, output
logic, and next state logic.
c. Write the test bench code to verify the working of the designed FSM.
1. Design and simulate a level-to-pulse converter using the Moore State Machine. [15 Marks]
2. Design a decade counter that counts from (0)10 to (9)10 and then goes back to (0)10. The counter
uses Clock and Reset as input and the outputs are the counting number. You are supposed to
use a synchronous Reset. [10 Marks]
3. Design a sequence recognizer that gives output Z=1 when it recognizes a sequence “10011” in
a single-bit input stream X. Make a non-overlapping machine that resets once a valid sequence
is detected. [15 Marks]
