Scribd
Upload
24 views

COA Assignment of Unit-1 and Unit-2

The document contains 22 questions related to computer organization and architecture. It covers topics like combination and sequential circuits, boolean algebra, data representation, flip flops, registers, arithmetic operations, memory and addressing modes. Students need to answer the questions by the given deadline while referring to the provided material like slides, textbooks and video lectures.

Uploaded by

Shruti Jha
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
24 views

COA Assignment of Unit-1 and Unit-2

The document contains 22 questions related to computer organization and architecture. It covers topics like combination and sequential circuits, boolean algebra, data representation, flip flops, registers, arithmetic operations, memory and addressing modes. Students need to answer the questions by the given deadline while referring to the provided material like slides, textbooks and video lectures.

Uploaded by

Shruti Jha
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

Indira Gandhi Delhi Technical University for Women

Department of Information Technology


Assignment-1
Unit-1
B.Tech (IT), 4th Semester

Name of Subject: Computer Organization and Architecture (BCS-202)


Date of Issue: February 22, 2024
Date of Submission of Assignment: March 20, 2024

Unit-1
Q. 1 List the difference between the Combination and Sequential Circuit along with at least FOUR
examples each.
Q. 2 Describe the Decoder, Multiplexer, and De-multiplexer circuits with diagrams and examples.
(Source of Solution: PPTs shared of the Lecture)
Q. 3 Solve the given expression to a minimum number of literals F= A B+ A’C +ABC + A’ B C using
Boolean algebra and draw the logic circuit diagram using basic gates for simplified function.
(Source of Solution: PPTs shared of the Lecture)
Q. 4 Simplify the given Expression F= A B C+ A B C’ +A’ C + A’ B C + A’ B’ C using Boolean
algebra and also draw the logic circuit diagram using basic gates for simplified function.
(Source of Solution: PPTs shared of the Lecture)
Q. 5 Describe Boolean expressions and truth tables of following the 2-inputs and 3-inputs:
(a) Basic gates (AND, OR, NOT, EX-OR, EX-NOR)
(b) Universal gates (NAND, NOR).
(Source of Solution: PPTs shared of the Lecture)
Q. 6 Perform the following implementation/realization with NAND gate:
(i) AND Gate
(ii) OR Gate
(iii) NOT Gate
(iv) EX-OR Gate
(v) EX-NOR Gate
(Source of Solution: PPTs shared of the Lecture)
Q. 7 Perform the following implementation/realization with NOR gate:
(i) AND Gate
(ii) OR Gate
(iii) NOT Gate
(iv) EX-OR Gate
(v) EX-NOR Gate
(Source of Solution: PPTs shared of the Lecture)
Q. 8 Determine the following operations:
(a) Add (367)8 and (715)8 without converting to decimal.
(b) Add (296)12 and (57)12 without converting to decimal.
(c) Octal number (1076)8 to Hexadecimal number (?)16
(d) Add (5)10 to (6)10 in binary and Subtract (-6)10 from (7)10 in binary.

1
(Source of Solution: PPTs shared of the Lecture)
Q. 9 Describe the following methods of data representation/number representation applicable in
computers also explain the reference of one over another:
(a) Unsigned and signed magnitude representation of number system with examples
(b) Fixed Point Representation concept with examples
(c) Floating Point Representation concept with examples
(d) Concept of Overflow in Computer Arithmetic with an example.
(Source of Material: Chapter-3 Moris Mano Book-Data Representation, PPTs & Video
Lectures, Pages-67-83)
Q.10 b) Simplify the Boolean function F together with don’t-care conditions d in Sum of Product (SOP) form
using K map for:
F (A, B, C, D) = Σ m (0, 1, 3, 7, 8, 9, 10)
d (A, B, C, D) = Σ m (3, 11, 14). Draw the logic circuit for the obtained SOP.
(Source of Solution: PPTs shared of the Lecture)
Q.11 Apply the concept of four variable K-Map and find the Sum of Product (SOP) for given min-terms
and also Draw the circuit diagram for the SOP obtained: F (A, B, C, D) = Σ m (0, 1, 2, 8, 9, 10) &
d (A, B, C, D) = Σ m (6, 14)
(Source of Solution: PPTs shared of the Lecture)
Q.12 Describe the concept of 2’s complement and also describe Floating Point Representation in IEEE
754 Standard (Sign bit, Exponent and Mantissa) for 8 bits, 16 Bits, and 32 bits binary numbers
representation.
(Source of Solution: Video Lectures shared)
Q.13 Determine the 1’s Complement for the following.
(a) (0011 0111)2
(b) (0111 1111)2
(c) (1011 0000)2
(d) (0001 1111)2
Q. 14 Determine the 2’s Complement for the following numbers in 8 bits and also represent in IEEE 754
Floating Point Representation.
(a) (0011 0111)2
(b) (0111 1111)2
(c) (1011 0000)2
(d) (0001 1111)2
(Source of Material: Chapter-3 Moris Mano Book-Data Representation, PPTs & Video
Lectures, Pages-67-83)
Q. 15 Describe the functionality of following Flip Flops either NAND or NOR gate along with Logic
Block Diagram, Logic Circuit Diagram, Truth Table and Boolean Equation:
(a) S-R Flip-Flop,
(b) D Flip Flop
(c) J-K Flip-Flop &
(d) T Flip-Flop.
(Source of Solution: PPTs shared of the Lecture)
Q. 16 Describe the following Arithmetic Micro-operations logic circuit Circuits:
(a) Half adder and Full adders
2
(b) Half subtractor and Full subtractor
(c) Parallel adder concept to perform adder and subtraction operations from same circuit for more
than 3-bit numbers.
(Source of Material: Chapter-4-Moris Mano-Register Transfer and Microoperations- Pages-
103-106 & Figure 4.6 & Figure-4.7)
Q. 17 Describe the following Register Transfer and Micro-Operations Concepts:
(a) Arithmetic Micro-operations with examples
(b) Logic Micro-operations with examples
(c) Concept of Bus and Classification of Bus structures applicable in computers organization.
(Chapter-4 Moris Mano-Register Transfer and Microoperations, Pages-93 -103 and Figure
4.3 & Figure 4.5)
Implement the Full Adder circuit with Decoder logic.
(Source of Solution: PPTs shared of the Lecture)
Q. 18 Full adder logic implementation using 3 to 8 Decoder circuit.
(Source of Solution: PPTs shared of the Lecture)
Q. 19 Describe the classification of Shift Registers and Counters.
(Source of Solution: PPTs shared of the Lecture)
Q. 20 Using the DeMorgan’s Theorem, prove that the following
(A+B)’ (A’+B’)’ = 0; and (ii) A + A’ B + A’ B’ = 1
Q. 21 (d) Add the following numbers in the given base without converting to decimal:
i. (1230)4 and (23)4
ii. (135.4)6 and (43.2)6
iii. (367)8 and (715)8
iv. (296)12 and (57)12
Q.22 Design a 3-bit Asynchronous Binary Counter along with Logic Circuit, Truth Table and Timing
Diagram.
Assignment-2
Unit-2
Date of Issue: March 1, 2024
Date of Submission of Assignment: March 25, 2024

Q. 1 What is the basic Computer Organization and Design:


Explain the instructions part of instructions along with instruction cycle in depth with examples.
Or
Describe the concept of instructions with the support of instruction cycle: along with Instruction
Codes, Computer Instructions, Timing & Control Diagram, & Instruction Cycle.
(Source of Reading Material: Chapter-5, Moris Mano- Basic Computer Organization and
Design, Subtopic 5.3, 5.4, 5.5. Pages- 132- , Figure-5.5, Figure-5.5, Figure-5.6, Table-5.2)
Q. 2 Draw and describe General Register Organization with register set with common ALU. Write the
field, symbol, control word to perform any one operation: (i) R1<- R2+R3; (ii) R1<- R2-R3.
Q. 3 What is RISC and CISC architecture and list the major characteristics of both.
(Source of Material: Chapter-8 Moris Mano, Pages-282-285).
Q. 4 Write the difference between CISC and RISC.
(Source of Material: Chapter-8 Moris Mano, Pages-282-285).
Q.5 Describe the following with suitable diagram:
(a) Explain the in depth the concept of microprogrammed control with suitable diagrams
3
(Source of Material: Figure 7.1 (pages-213-2015) & Figure 7.8 (Pages 23125)
(b) What is the concept of instruction sequence generation.
Or
Classify the instructions with example for specific program.
(Source of Material: Pages-2016-2020 along with Figure 7.2 Figure 7.3 and Figure 7.4).
Q. 6 Describe the Functioning of Central Processing Unit (CPU) and Control Registers used in
Computer.
(Source of Material: Chapter-8 Moris Mano, Pages-241-247, Figure 8.1 and Figure 8.2 &
Table 1, Table-2 & Table-3).
Q.7 Draw the circuits, list the difference and merit of SRAM and DRAM one over another.
Q. 8 Illustrate the following:
(i) Instruction Code and operation code
(ii) What are the computer Registers and list the registers for the basic computer.
Q.9 Differentiate between direct addressing and indirect addressing along with suitable examples and
explain how addressing mode is chosen.
Q.10 Develop and describe the algorithm using the flow chart for addition/subtraction of two number
represented in signed magnitude representation.
Q. 11 What is the concept of BCD Adder. Describe the Block Diagram of BCD Adder for TWO
Number Addition/Subtraction.
Q.12 What are the addressing modes, Describe it with examples.
Q.13 Draw and describe the computer configuration in following terms:
(i) Computer Hardware Configuration
(ii) Instruction Formats
Q.14 Draw the circuits, list the difference and merit of SRAM and DRAM one over another.
Q.15 Explain the following
(a) Program Counter (PC)
(b) Accumulator Counter (AC)
(c) Data Transfer Instructions (Any FOUR)
(d) Arithmetic Instructions (Any FOUR)
Q.16 How addressing mode is chosen? Differentiate between direct addressing and indirect addressing
along with suitable examples.
Q.17 Develop and describe the algorithm using the flow chart for addition/subtraction of two number
represented in signed magnitude representation. Draw the hardware for signed magnitude addition
and subtraction.

You might also like