DIGITAL LOGIC AND

COMPUTER ORGANIZATION
Lecture 13: Binary Arithmetic
ELEC3010
ACKNOWLEGEMENT

I would like to express my special thanks to Professor Zhiru Zhang

School of Electrical and Computer Engineering, Cornell University
and Prof. Rudy Lauwereins, KU Leuven for sharing their teaching
materials.

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COVERED IN THIS COURSE
❑ Binary numbers and logic gates
❑ Boolean algebra and combinational logic
❑ Sequential logic and state machines
❑ Binary arithmetic
Digital logic
❑ Memories

❑ Instruction set architecture

❑ Processor organization Computer
❑ Caches and virtual memory
❑ Input/output Organization
❑ Advanced topics
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 MOTIVATION EXAMPLE 1
❑ How are these number stored in computer memory?
int x, y, z;
float a, b, c;
x=108; y= -108;
a=10.25; b=-10.25;
❑ How are these operations performed by computers?
z = x+y;
c = a*b;
x = y*8;

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MOTIVATION EXAMPLE 2

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 COMBINATIONAL LOGIC BUILDING BLOCKS
1. Multiplexer
2. Decoder/Encoder
3. Comparators
4. Adder/Subtractor/Multiplier/Divider
5. Shifters and rotators
6. ALU

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 1-BIT FULL ADDER
A
BINARY
▪ inputs: A, B, Carry-in (Cin)
B S
Cin ADDER Cout ▪ outputs: Sum, Carry-out (Cout)
A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

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 4-BIT ADDER
0 0 0 0 1 1 0 1
A3 B 3 A2 B 2 A1 B 1 A0 B 0

0 0 1 0 0C
Cout in

S3 S2 S1 S0
0 1 0 1
• Adds two 4-bit numbers, along with carry-in
• Computes 4-bit result and carry out Ripple Carry Adder
• 3+2=5
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 OVERFLOW
-1 = 1111 = 15
When can overflow occur? -2 = 1110 = 14
-3 = 1101 = 13
• adding a negative and a positive? -4 = 1100 = 12
• Overflow cannot occur (Why?) -5 = 1011 = 11
-6 = 1010 = 10
-7 = 1001 =9
• adding two positives? -8 = 1000 =8
+7 = 0111 =7
• Overflow can occur (Why?) +6 = 0110 =6
+5 = 0101 =5
+4 = 0100 =4
+3 = 0011 =3
• adding two negatives? +2 = 0010 =2
+1 = 0001 =1
• Overflow can occur (Why?) 0= 0000 =0

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 OVERFLOW
MSB
When can overflow occur?
A B Cin Cout S
AMSB BMSB
0 0 0 0 0
Cout_MSB 0 0 1 0 1
Wrong
Cin_MSB Sign
over
0 1 0 0 1
flow 0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
SMSB
1 1 0 1 0 Wrong
Rule of thumb:
Sign
• Overflow happened if msb’s carry in != carry out 1 1 1 1 1

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BINARY SUBTRACTION
Two’s Complement Subtraction
• Subtraction is addition with a negated operand
• Negation is done by inverting all bits and adding one
A – B = A + (-B) = A + (B ഥ + 1)
B3 B2 B1 B0
A3 A2 A1 A0

1
Cout

S3 S2 S1 S0
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 FOUR BIT ADDER / SUBTRACTOR

A3 B 3 A2 B2 A1 B 1 A0 B 0

mux mux mux mux

over
flow 0=add
1=sub

S3 S2 S1 S0
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FOUR BIT ADDER / SUBTRACTOR

A0 B 0 A0 B 0
sub? B0 newB0

0 0 0

mux 0 1 1
1 0 1
1 1 0
0=add 0=add
1=sub if subtracting, invert B0 1=sub
S0 Before: 2 inverters, 2 AND gates, 1 OR gate S0 After: 1 XOR gate
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 ADDER IMPLEMENTATIONS
❑ Many different adder implementations exist, which differ in speed and
circuit complexity
❑ Ripple carry adder is simple but slow
• Each 1-bit full adder must wait for the carry bit to be calculated from the previous
full adder
❑ Common techniques to speed up carry propagation
• Carry lookahead
• Carry select
• Carry save
• etc.

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 SHIFTERS
❑ Logical shifter: shifts value to left or right and fills empty spaces with 0’s
▪ Ex: 11001 >> 2 =
▪ Ex: 11001 << 2 =

❑Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with
the old most significant bit (msb).
▪ Ex: 11001 >>> 2 =
▪ Ex: 11001 <<< 2 =

❑Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into
the other end
▪ Ex: 11001 ROR 2 =
▪ Ex: 11001 ROL 2 =

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SHIFTERS

• Logical shifter:
– Ex: 11001 >> 2 = 00110
– Ex: 11001 << 2 = 00100
• Arithmetic shifter:
– Ex: 11001 >>> 2 = 11110
– Ex: 11001 <<< 2 = 00100
• Rotator:
– Ex: 11001 ROR 2 = 01110
– Ex: 11001 ROL 2 = 00111

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SHIFTER DESIGN
A 3 A 2 A1 A0 shamt1:0
2
00 S1:0
01

10
Y3
11

shamt1:0 00
S1:0
01

2 10
Y2
11

A3:0 4 >> 4 Y3:0 00

S1:0
01

10
Y1
11

00
S1:0
01

10
Y0
11

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 SHIFTERS AS MULTIPLIERS, DIVIDERS

❑A << N = A × 2N
• Example: 00001 << 2 = 00100 (1 × 22 = 4)
• Example: 11101 << 2 = 10100 (-3 × 22 = -12)
❑A >>> N = A ÷ 2N
• Example: 01000 >>> 2 = 00010 (8 ÷ 22 = 2)
• Example: 10000 >>> 2 = 11100 (-16 ÷ 22 = -4)

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 ARITHMETIC LOGIC UNIT (ALU)

❑ ALU: Combinational logic circuit that combines a variety

of operations into a single unit.
❑ Common operations may include
▪ Addition and subtraction
▪ Logical (OR, AND)
▪ Shift
▪ Comparisons

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A SIMPLE 8-BIT ALU

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 ALU OPERATIONS, INPUTS & OUTPUTS

❑ Operations
▪ Addition and Subtraction
▪ Bitwise AND and OR ❑ Outputs
▪ Left Shift and Right Shift ▪ Y, Carry Out (CO)
❑ Inputs ▪ Shift Out (SO)
▪ A, B, Carry In (CI) ▪ Flags regarding the result of
▪ Shift In (SI) the operation
▪ Code indicating operation to be ➢ Overflow flag (O), Zero flag (Z)
performed (OP)
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ALU BLOCK DIAGRAM

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EXAMPLE: ALU OPERATION ENCODINGS

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 NUMBERS WITH FRACTIONS

❑Two common notations:

▪ Fixed-point: binary point fixed
▪ Floating-point: binary point floats to the right of the most
significant 1

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 FIXED-POINT NUMBERS

❑ 6.75 using 4 integer bits and 4 fraction bits:

01101100
0110.1100
22 + 21 + 2-1 + 2-2 = 6.75

• Binary point is implied

• The number of integer and fraction bits must be agreed upon
beforehand
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 CAN YOU DO IT?

❑ Represent 7.510 using 4 integer bits and 4 fraction

bits.

01111000

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 CAN YOU DO IT?

❑ Represent -7.510 using 4 integer bits and 4 fraction

bits.

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 FLOATING-POINT NUMBERS
❑ Binary point floats to the right of the most significant 1
❑ Similar to decimal scientific notation
❑ For example, write 27310 in scientific notation:
273 = 27.3 × 101 = 2.73 × 102
❑ In general, a number is written in scientific notation as:
± M × BE
▪ M = mantissa
▪ B = base
▪ E = exponent
▪ In the example, M = 2.73, B = 10, and E = 2
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FLOATING-POINT NUMBERS
• IEEE-754 format for single-precision
31 30 23 22 0

S biased exponent e fraction f of normalized mantissa

1 sign bit: 0 positive, 1 negative

8 bit biased exponent= exponent + 127
24 bit normalized mantissa = 1 hidden bit + 23 bit fraction

Normalized Mantissa lies between 1 and 2 : 1.f

Example: Represent 0.1011 in IEEE-754 format

Sign bit s=0

Normalize mantissa: 0.1011=1.011*2-1
Biased exponent: -1 + 127=126=01111110
IEEE format: 0 01111110 0110000000000000000000
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 CAN YOU DO IT?
❑ Represent -7.510 using IEEE-754 format

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 FLOATING-POINT PRECISION
❑ Single-Precision:
▪ 32-bit
▪ 1 sign bit, 8 exponent bits, 23 fraction bits
▪ bias = 127
❑ Double-Precision:
▪ 64-bit
▪ 1 sign bit, 11 exponent bits, 52 fraction bits
▪ bias = 1023

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 FLOATING-POINT ADDITION
1. Extract exponent and fraction bits
2. Prepend leading 1 to form mantissa
3. Compare exponents
4. Shift smaller mantissa if necessary
5. Add mantissas
6. Normalize mantissa and adjust exponent if necessary
7. Round result
8. Assemble exponent and fraction back into floating-point
format
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 SEQUENTIAL LOGIC BUILDING BLOCKS
1. Counters
2. Shift registers

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 COUNTERS
❑ Increments on each clock edge
❑ Used to cycle through numbers. For example,
000, 001, 010, 011, 100, 101, 110, 111, 000, 001…
❑ Example uses:
▪ Digital clock displays Symbol Implementation
▪ Program counter: keeps track
CLK
CLK
of current instruction executing N
N N
Q

+
Q N N r
1
Reset
Reset

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 SHIFT REGISTERS
❑ Shift a new bit in on each clock edge
❑ Shift a bit out on each clock edge
❑ Serial-to-parallel converter: converts serial input (Sin) to
parallel output (Q0:N-1)
Symbol: Implementation:
CLK
N
Q Sin Sout

Sin Sout
Q0 Q1 Q2 QN-1
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 SHIFT REGISTER WITH PARALLEL LOAD
❑ When Load = 1, acts as a normal N-bit register
❑ When Load = 0, acts as a shift register
❑ Now can act as a serial-to-parallel converter (Sin to Q0:N-1)
or a parallel-to-serial converter (D0:N-1 to Sout)
D0 D1 D2 DN-1
Load
Clk
Sin 0 0 0 0 Sout
1 1 1 1

Q0 Q1 Q2 QN-1

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 BEFORE NEXT CLASS

• Textbook: 5.5
• Next time: Memories

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