HiperLCS-2 Chipset

Off-Line LLC Switcher ICs with Integrated 600 V FREDFETs

Synchronous Rectification and FluxLink Feedback

Product Highlights Applications

• High efficiency power supplies up to 220 W continuous
Highly Integrated, Compact Footprint • Consumer electronics − TV, PC, e-bike and tool chargers
• Up to 98.1% efficiency
• Very low component count and small footprint package
Description
• Eliminates heat sink up to 220 W continuous The HiperLCS™-2 chipset achieves high efficiency and compact size in
• Self-powered start-up power supplies up to 220 W with no heat sink. This IC chipset
• 600 V FREDFET, rugged fast recovery body diode, current sensing simplifies the design and manufacture of LLC resonant power converters.
• HB auto dead time and hard switch detect The LCS72xxC primary-side devices incorporate 600 V FREDFET in a
• Selectable center frequency (90, 120, 180, 240 kHz) half-bridge arrangement with control, level shifting, drive and self-
• Secondary-side sensing and feedback control with fast powered start-up. The LSR2000C master controller device provides
transient response reinforced isolated feedback, output sensing and SR management.
• Synchronous rectification driver
• Integrated FluxLink™, HIPOT-isolated control link HiperLCS-2 chipset incorporates multiple protection features including
line over and undervoltage protection, output overvoltage and
EcoSmart™ – Energy Efficient
over-temperature shutdown. Device fault response options support
• As low as 41 mW no-load including line sense
common combinations of latching and auto-restart behaviors required
• Output always in regulation, 0-100% load step
by applications such as chargers, adapters, consumer electronics and
• Easily meets all global energy efficiency regulations
industrial systems.
Advanced Protection / Safety Features
• HB and SR shoot-through protection Output Power Table
• Power-up pin open/short check
• System short-circuits, thermal, HB OCP, FB open, Safety 385 VDC ±5%
Power
fast input line UV/OV and PMAX protection Isolation
Device
Device Adapter1 Peak Power2
Optional Features
• Auto-restart or latching fault response for output OVP/UVP LCS7260C 80 W 135 W
• Latching or hysteretic primary over-temperature protection LCS7262C LSR2000C 120 W 205 W
• External faults detect and remote on/off
LCS7265C 220 W 375 W
• Inrush-relay drive output pin
• Provides start-up bias for PFC stage Table 1. Output Power Table.
Notes:
Full Safety and Regulatory Compliance
1. Power Device: Minimum continuous power in a typical non-ventilated enclosed
• Reinforced isolation, isolation voltage >4000 VAC typical size adapter measured at 40 °C ambient. Max output power is
• UL1577, CQC and TUV (EN62368-1) safety approved dependent on the design, with condition that TJ <110 °C.
2. Power Device: Minimum peak power capability (not thermally limited).

B+

BPH 5VH HD
+V

HSD

HB
RTN

HiperLCS2-HB
CONTROL LCS726x
L

FL

PP BPL

BM

Figure 2. Primary-Side Package. GP GD 5VL S

Figure 3. HiperLCS2-SR.
CMP
GSA

InSOP-24C Top View. Safety Isolation Package,

D1

D2

G1

G2

PS
FB
IS

5VL

FL
BPS
GSB
InSOP-24D Top View.
SEC Controller
5VS

GP
B- HiperLCS2-SR
LSR2000 PI-9307-021522

Figure 1. Typical Application Schematic.

www.power.com July 2023

This Product is Covered by Patents and/or Pending Patent Applications.
 HiperLCS-2

HD
HD HS THERMAL GATE DRIVE &
DETECT AUTO DEAD TIME BPH
BPH CONTROL
BPH AND SenseFET
5 V REGULATOR LEVEL SHIFT Power
5VH SUPPLY COMMUNICATIONS FREDFET
MANAGEMENT
HB

PRE-CHARGE
LEVEL SHIFT
BPL HD COMMUNICATIONS
GP
BPL AND
5VL
5 V REGULATOR LS THERMAL
SUPPLY DETECT
L MANAGEMENT
BPL
LINE UV/OV Power
UV/OV FREDFET
GATE DRIVE & SenseFET
FAULT AUTO DEAD TIME
FAULT CONTROLLER CONTROL
OUT
LOSSLESS
PP PP CURRENT SENSE
INTERFACE
S
BM

FL GD

GP
PI-9293-021121

Figure 4. Primary Controller (Low-Side and High-Side), Block Diagram.

BPS

GATE DRIVE
SUPPLY

GATE DRIVE G1

GS
G2

GATE DRIVE
GS D1

D2
D1 and D2
INTERFACE

BPS
BPS INPUT
5 V REGULAR
SUPPLY 5VS
MANAGEMENT
FB

5VL FB and CMP

INTERFACE CMP

CONTROLLER
WINDING IS
FL RECEIVER TRANSMITTER
SENSE
SAFETY SAFETY
INTERFACE
ISOLATED ISOLATED

PS PS

SAFETY INTERFACE
ISOLATION
BARRIER FAULT
GP OUTPUT
GS
PI-9294-061421

Figure 5. Safety Isolation and Secondary Controller Block Diagram.

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Pin Functional Description – Primary-Side Device

LCS726xC
Low-Side

PRIMARY GROUND (GD) (Pin 1) S 24 1 GD

Primary gate-drive ground. Should be capacitively decoupled to 2 BM
primary supply pin (BPL).
HB 3 GP
4 NC
BURST MODE (BM) (Pin 2) 5 BPL
Small signal output indicating deep burst mode operation. Can be 6 5VL
HB 16-19 7 FL
coupled to control external primary-side circuits. 8 PP
PRIMARY GROUND (GP) (Pin 3) 9 NC
BPH 15 HD 10 GP
Small signal primary ground. Should be capacitively decoupled to 5VH 14 11 NC
primary 5 V (5VL) pin. NC 13 12 L
NO CONNECTION (NC) (Pin 4)
Pin not connected. Leave open.
BYPASS LOW-SIDE (BPL) (Pin 5) PI-8894-020321
Power supply pin for primary low-side device. Should be capacitively
decoupled to primary gate-drive ground (GD) pin. Figure 6. HiperLCS2 Primary-Side LCS726XC, InSOP-24C (Bottom View.)

PRIMARY LOW-SIDE 5 V (5VL) (Pin 6)

Primary low-side small signal 5 V IC-supply pin. Also provides bias
power to the Primary-side of the Isolation device (LSR2000). 5VL High-Side
should be capacitively decoupled to primary small signal ground (GP).
NO CONNECT (NC) (Pin 13)
FLUXLINK INPUT (FL) (Pin 7)
Pin not connected. Leave open.
Small signal input for FLUX LINK signal.
HIGH-SIDE 5 V (5VH) (Pin 14)
PROGRAM PRIMARY (PP) (Pin 8)
Primary high-side small signal 5 V IC-supply pin. Should be capacitively
Small signal connection for customer configuration selection
decoupled to half-bridge (HB). NOTE: this pin floats on the half-
components. Also used in some configurations as small signal
bridge switching voltage, can be at high-voltage with respect to
current input to receive power-good (remote on/off), signal to
primary grounds.
command device activation. Likewise used in some configurations as
small signal current input for external fault. This pin also outputs BYPASS HIGH-SIDE (BPH) (Pin 15)
logic level error code during fault conditions. Power supply for primary high-side device. Should be capacitively
decoupled to half-bridge (HB) pin. NOTE: this pin floats on the
NO CONNECT (NC) (Pin 9)
half-bridge switching voltage, can be at high-voltage with respect to
Pin not connected. Leave open.
primary grounds.
PRIMARY GROUND (GP) (Pin 10)
HALF-BRIDGE (HB) (Pins 16-19 and Back Side HB Pad)
Small signal primary ground. Should be capacitively decoupled to
High-voltage and high current connection point for low-side MOSFET
primary 5 V (5VL) pin.
DRAIN and high-side MOSFET SOURCE. The half-bridge node
NO CONNECT (NC) (Pin 11) typically switches between primary ground and primary input bus (HD).
Pin not connected. Leave open.
SOURCE (S) (Pin 24)
LINE SENSE (L) (Pin 12) High current Power ground return for half-bridge switch
High-voltage small signal current input pin. Used to detect line-input current. Also, at same potential as other small-signal
voltage. Also used in some configurations as small signal input to primary grounds.
receive power-good (remote on/off) signal to command device
HD (Pin Back-Side Solder Pad)
activation.
High current, high-side MOSFET Drain and connection to system
high-voltage input bus.

Figure 7. Primary-Side Packages.

InSOP-24C Top View, InSOP-24C Bottom View.

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Pin Functional Description – Safety Isolation and

Secondary-Side Device LSR2000C
SECONDARY 5 V (5VS) (Pin 1)
Connection point for an external decoupling capacitor for the
secondary IC supply. Should be capacitively decoupled to secondary NC 13 12 GSA
ground (GSB). FL 14 11 D1
5VL 15 10 D2
SECONDARY GROUND (GSB) (Pin 2) 9 G1
Small signal ground for secondary-side (5VS, IS, CMP, FB, PS). 8 G2
GP 16-19 7 BPS
WINDING SENSE (IS) (Pin 3) 6 PS
Secondary-side, small signal current input connection to an external 5 FB
4 CMP
resistor and capacitor. 3 IS
COMPENSATION (CMP) (Pin 4) 2 GSB
NC 24 1 5VS
Secondary-side, small signal connection to external frequency
compensation resistor capacitor network.
FEEDBACK (FB) (Pin 5)
Secondary-side, small signal feedback signal to secondary control. PI-8893-031721
PROGRAM SECONDARY (PS) (Pin 6)
Figure 8. HiperLCS-2 Safety Isolation and Secondary-Side LSR2000C,
Secondary-side, small signal connection for customer configuration InSOP-24D (Top View).
selection components. This pin also outputs logic level fault code
during fault conditions.
SECONDARY BYPASS (BPS) (Pin 7) NO CONNECT (NC) (Pin 13)
Secondary-side power supply pin for secondary device. No connection. Leave open.
SR GATE2 DRIVE (G2) (Pin 8) FLUXLINK (FL) (Pin 14)
Secondary-side, output for driving secondary synchronous rectifier Primary-side small signal output is the FluxLink primary output pin.
(SR) MOSFET for first output phase.
PRIMARY 5V (5VL) (Pin 15)
SR GATE1 DRIVE (G1) (Pin 9) Primary-side connection point for an external primary decoupling
Secondray-side, output for driving secondary synchronous rectifier capacitor for the primary IC supply. Should be capacitively decoupled
(SR) MOSFET for second output phase. to primary ground (GP).
SR DRAIN2 SENSE (D2) (Pin 10) PRIMARY GROUND (GP) (Pins 16-19)
Secondary-side, medium voltage small signal input for sensing Primary-side ground reference for primary BYPASS pin.
SR DRAIN/SOURCE voltage.
NO CONNECT (NC) (Pin 24)
SR DRAIN1 SENSE (D1) (Pin 11) No connection. Leave open.
Secondary-side, medium voltage small signal input for sensing SR
DRAIN/SOURCE voltage.
SECONDARY GROUND (GSA) (Pin 12)
Power ground for secondary-side (BPS, G1, G2, D1, D2).

Figure 9. HiperLCS2–SR, Safety Isolation Package.

InSOP-24D Top View, InSOP-24D Bottom View.

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 HiperLCS-2

HiperLCS-2 Basic Operation level IHB(IOVL-) is selected by grounding L pin and using PP pin PG
function instead. Selecting IHB(IOVL-) will slow the output voltage
The HiperLCS-2 is designed for half-bridge LLC converters, which are positive start-up slope and minimizes magnitude of output overshoot.
high-efficiency resonant ZVS, variable frequency converters. Selecting IHB(IOVL-) is recommended for systems using an active PFC
boosted input bus and requires the PFC boost to provide a power-
HiperLCS-2 comes as a chipset with two devices: the power-device, good (PG) signal to the PP pin. Engagement of arbitrary output loads
and the isolation device. The power-device (LCS726x) is on the will slow the output voltage-rise but will not change the polarity of
primary side of the isolation barrier and includes an LLC controller the output voltage slope. Primary control of switching continues until
with built-in high-side and low-drivers and half-bridge power-MOSFETs. the output voltage reaches close to regulation at which point the
The isolation-device (LSR2000) straddles the isolation barrier to secondary will take control of switching.
facilitate communications to the power-device (primary device). The
isolation-device also includes the secondary controller and SR-driver. Auto Dead Time
The HiperLCS-2 is able to operate with nominal frequencies of up to The LLC-converter has a structure where positive and return voltages
240 kHz. It offers extremely high conversion efficiency coupled with connect sequentially via power-MOSFET’s to the mid-point or
low-component count and rugged protection features. half-bridge node. The half-bridge connects to a resonant-tank
network which is then series connected to typically power-return
HiperLCS-2 Primary-Side Power-Device Operation (ground) and coupled to output load. The high-side power-MOSFET
Start-Up Self-Bias and low-side power-MOSFET are driven sequentially (i.e., neither
The HiperLCS-2 provides self-powered start-up. This means that the MOSFET is on at the same time). During on-time the resonant-tank
system provides a high-voltage bus to the HD pin and the HiperLCS-2 delivers some energy to the output and stores the remaining energy.
device will take care the rest. Self-powering is accomplished using When the first power-MOSFET turns-off, there is a period of dead
internal high-voltage current sources. The first current source is time before the second power-MOSFET turns on. During dead time
connected between HD and the BPL pin. When voltage is applied to some of the remaining stored energy in the resonant tank, continues
HD, the BPL will begin to charge any capacitance connected to this to circulate current in the lumped half-bridge capacitance, causing the
pin. There is a low pre-charge current which allows initial charging half-bridge voltage to slew towards the next switch. The half-bridge
voltage to be established, and then as BPL voltage increases, this voltage slew continues until either the voltage is clamped by a
charge current is stepped to a much higher level allowing faster MOSFET body-diode (ZVS), or the tank runs out of energy (non-ZVS).
start-up times. This higher current capability of the BPL charging also The goal for the LLC-converter is to always run in ZVS (zero-voltage-
allows the HiperLCS-2 to provide bias power to a PFC stage and allow switching), operation. This is where the voltage across the next
the PFC to begin switching prior to the HiperLCS-2. Once the BPL power-MOSFET is close to zero prior to turning on the power-MOSFET.
self-charge reaches the target voltage it will enter hysteretic control. This results in near zero capacitive (COSS) MOSFET losses. After the
The internal current source is disabled during normal operation once first power-MOSFET turns-off, the HiperLCS-2 auto-dead time function
an external bias (from a transformer bias winding), becomes active. holds off second power-MOSFET until the controller detects either the
The BPH pin is charged in very similar way to BPL, but the charge end of half-bridge voltage-slew or abnormally reaches maximum dead
current from HD to BPH is lower. The BPH pin internal charge current time. Following this the second power MOSFET will turn-on. The
will likewise be disabled once external bias becomes available. dead time of a given LLC-converter may vary with input voltage and
output load. The HiperLCS-2 will automatically adjust dead times in
In order to begin switching of an LLC converter ideally, we would the range from ~90-500 ns.
prefer the half-bridge and resonant capacitor voltages to be in a
known condition (preferably close to zero). The HiperLCS-2 achieves
Frequency
this using a high-voltage current source connected to the HB pin. Min Nom Max Unit
Range
This HB current source pre-conditions the resonant tank components
pulling current to ground (return), prior to beginning switching. Doing 0 23 90 135 kHz
this means that at initial start or restart, the HiperLCS-2 always starts
with known tank conditions. The result is that the HiperLCS-2 can 1 30 120 183 kHz
achieve resonant switching on the second switch edge. The
pre-condition HB-current source is active prior to switching while the 2 45 180 270 kHz
high-side device is below UV condition.
3 60 240 366 kHz
After all the charging conditions are complete and all undervoltage
conditions are cleared, HiperLCS-2 begins switching with the Table 2. Table of Primary and Secondary Frequency Ranges Selections.
Primary Device Frequency Range Selection via PP Pin Resistor
high-side power-MOSFET first. (see data table). Secondary Device Frequency Range Selection
by Part Number.
Start-Up Primary Soft-Start
The HiperLCS-2 begins primary switching at a frequency approximately Primary Protection and Fault Response
1.5x the maximum of the selected switching frequency range. The If secondary controller does not wake up within 32 ms of primary
switching frequency is ramped down quickly to build current in the switching start, then the power device will declare fault. If hand over
resonant tank. Once the resonant tank achieves target current to secondary control does not occur within a further 32 ms after
(IHB(IOVL)), the frequency is then indirectly regulated to maintain tank secondary wake-up, then the primary will declare a fault. As with all
current at this level. The result at the system output capacitor, is faults, the primary is the master of fault management. When a fault
equivalent to a very high-power current source. This results in a is declared (primary or secondary), the device will go into either
monotonic rise at the voltage on the output capacitor. The positive latching (off) or non-latching fault handling.
slew rate of the output voltage-rise will be a function of resonant tank
and output capacitor values. There are two selectable thresholds, For non-latching faults the primary device will initiate auto-restart.
IHB(OVL) and IHB(IOVL-). The higher level IHB(OVL), is the default value, Auto-restart has two responses a short fault response and a long
selected by using L pin for input voltage UV/OV functions. The lower response (see Table 2).

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 HiperLCS-2

Short fault auto-restart occurs for fault events that are detected while continuously monitored. Overvoltage and undervoltage both have
operating in secondary control. This auto-restart off-period is hysteresis to prevent chatter. On exiting undervoltage the device
approximately 200 ms. All faults that trigger during primary control goes through a restart. However, for overvoltage the device switching
result in analog auto-restart response where the off-time is around 5 is blocked while the condition persists but allowed to continue when
seconds. condition is removed. Note: that the L pin detects at power-up
whether the pin is connected to ground or if there is a resistor
The short-auto-restart event allows quick restart for occasional faults. between the HD pin and L pin. If the L pin is connected to ground
The long auto-restart ensures that repetitive auto-restart maintains a then the PP pin power-good input function is used instead to indicate
very low auto-restart-attempt versus auto-restart-off-time ratio. This line-UV/OV conditions.
in turn ensures that the persistent fault does not create excess
electrical nor thermal stress on the part. The BPL pin provides main supply voltage into the low-side driver and
controller. This voltage is internally regulated to provide 5 V at 5VL
The primary includes many layers of device self-protection to achieve pin. Note: the 5VL pin is not intended to provide power to any
rugged performance in the event of faults. external devices other than the isolation device. The BPH and 5VH
pins provide similar functions on the high-side driver. Both must be
At power-up the device completes FMEA checks (failure-mode effect externally decoupled to ground with a capacitor.
analysis) on device pins. If faults are observed the device will not
start switching. Note that such an FMEA fault will not report an error The BPL, 5VL, BPH and 5VH pins are monitored for undervoltage
code on the PP pin if it occurs prior to switching. Fault reporting condition. At start-up the device will not begin switching until all are
messages on the PP pin are only generated for faults which occur above their respective UV thresholds. The pins are also monitored
after switching has started. during normal switching and UV will trigger auto-restart. Please note
that unlike faults, a UV-condition on BPL, 5VL, BPH, 5VH will force a
Primary half-bridge current is internally sensed during low-side restart but will not output a fault to the PP pin.
MOSFET on-time. This is used for both primary start-up and also for
Miscellaneous Primary Functions
safety current limits during secondary mode.
At power-up, the PP pin is used to read customer configuration
(resistor) settings (see Table 2), which select for the primary start-up
The primary device also includes (high-side controller) over-temperature
frequency range (90, 120, 180, 240 kHz), and latching/non-latching
protection. This protects against excessive power dissipation in the
fault handling. The PP pin may also be used to receive a power-good
primary package. The device also has ambient (low-side controller)
input signal from an external system (such as PFC controller) when
thermal protection, which prevents restart until the temperature has
the L pin is connected to ground. As mentioned previously, when PP
lowered sufficiently to allow restart. This prevents thermal
pin (PG) function is used, the start-up current is set to the lower
temperature built up which might otherwise occur in the event of
value of IHB(IOVL-). This is intended only for PFC-boost applications
immediate restart for repeat fault conditions. Thermal fault triggers
where the IHB(IOVL-) slows the output voltage rise and reduces output
either latching or non-latching response (PP pin select).
overshoot. The same PP pin (PG) signal could be used for remote-
on/off. The PP pin can also receive an external fault signal to disable
The L pin detects input voltage for undervoltage and overvoltage
device under fault or other conditions – this signal is handled with
protection. The input voltage is coupled via a resistor connected to
latching/non-latching fault response. During fault conditions the PP
L pin. The L pin is polled during burst operation to reduce system
pin is also used to output device error codes to help with debug. The
consumption. During continuous switching (non-burst) the L pin is
error code is output as a binary non-return-to-zero (NRZ) bit stream.

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 HiperLCS-2

Primary Device PP Pin Error Fault Codes

Hex Fault
Bit PP Pin Error Fault Name Description
Code Action

31:28 X I 1111 Fixed Pre-amble.

27:20 X I 000 0000 0 Fixed Pre-amble.

19 X N x

18:16 X N xxx

High-side MOSFET over-temperature fault. Prevents start-up switching while

15 8000h A HSD_OT fault is activated and then monitored again after hand over to secondary
control mode.

Low-side controller ambient over temperature fault. Prevents start-up

14 4000h A AMB_OT switching while fault is activated and then monitored again after hand over
to secondary control mode.

High-side BPH undervoltage. Prevents start-up switching while fault is

13 2000h I BPH_UVN
activated. Not monitored in secondary control.

Line overvoltage – activation of this fault L = OV+ causes device to stop

switching and triggers latching/non-latching response based on PP pin
12 1000h I L_OV
selection. Restart occurs when both auto-restart period is completed and
fault clears L = OV-. Fault monitored in all switching modes.

Line undervoltage. Prevents start-up switching while fault is activated. Fault

11 800h A L_UV
monitored in all switching modes.

External Fault on PP pin. Can be latching/non-latching based on PP pin

10 400h A/L EXT_FAULT selection and/or device SKU. External circuit required to trigger this fault.
Often used for secondary VOUT OV detection.

Remote-off on PP pin (note: when L pin not used REM_OFF also generated
9 200h I REM_OFF concurrently at EXT_FAULT ). Prevents start-up switching while fault is
activated.

8 X N x

Lost FluxLink is monitored after start-up and hand over to secondary control
mode and only when not in burst-mode. This occurs after XXXus of
7 80h A LOST_FL_FAULT observing an unchanged/static FL signal while no in burst-mode. This fault
can often be triggered when secondary bias is lost (BPS_UV), and secondary
device stops operating.

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 HiperLCS-2

Hex Fault
Bit PP Pin Error Fault Name Description
Code Action

Lost FluxLink in burst_off (in super light load). A burst packet should occur a
minimum of every 50 ms. This fault is activated if the burst packet doesn’t
6 40h A 100MS_FL_FAULT
arrive by 100 mS. This fault can often be triggered when secondary bias is
lost (BPS_UV), and secondary device stops operating.

Primary mode switch frequency reached FMIN. Reaching FMIN during

5 20h A START_FAULT start-up is very uncommon. This fault may indicate resonant LLC tank
frequency problem or incorrect PP pin frequency-range selection.

Start-up problem. From start of primary switching, secondary should send

wake-up command within 32 ms and hand over should occur to secondary
control within 64 ms. Also during start-up frequency confirmation received
4 10h A PCD_SS_FAULT
signal should be received. If any of these do not occur, then error will be
activated. May indicate excessive COUT, excessive load, or insufficient power
delivery.

Secondary control fault is registered on the primary controller, when ALL

3 8h A SEC_FAULT secondary faults declared by the secondary control. For details of secondary
fault see PS pin fault error code table.

Secondary sending 2 pulse message unexpectedly in secondary control.

Three messages required to trigger the fault. This fault is usually caused by
2 4h A SCD_2PULSE_FAULT
grounding issues on primary ground, or magnetic coupling from the LLC
transformer to the LSR2000C.

1 2h A I_SAFETY_LIM Safety current limit fault in low-side MOSFET.

Frequency confirmation failure fault. The primary control (PP selected),

frequency-range, does not match frequency code received from the second-
0 1h A FREQ_FAULT
ary controller. May be wrong PP pin resistor, or wrong secondary controller
device.

Fault Action:
A = ALL auto-restart or ALL latch off, L = latch-off , I = information only, N = not used (ignore).
Note: Latch-off or auto-restart response is selected via PP pin. See Table 5. PP pin selection 0-3 for auto-restart, selections 4-7 for latch-off.

Table 3. LCS726x – Primary-Side PP Pin Error Fault Reporting.

LSR2000C – Primary PP Pin and Side PS Pin Error

Fault Bitstream
Note1: The below PP pin error fault-code bit stream message may Note2: Similarly, the PS pin error fault-code bit stream message may
include multiple (concurrent) fault bits. The Fault bit stream is include multiple (concurrent) fault bits. The Fault bit stream is
repetitively sent out PP pin during fault-off period. Message initially repetitively sent out PS pin during fault-off period. Message initially
starts and bit-15 and continues to bit0. Then repeats continuously starts and bit-15 and continues to bit0. Then repeats continuously
starting with MSB (Bit 31) pre-amble and ending with LSB (Bit 0). For starting with MSB (Bit 31) pre-amble and ending with LSB (Bit 0). For
a bit period of T, logic-1 (high for 2/3.T, low for 1/3.T), and logic-0 a bit period of T, logic-1 (high for 2/3.T, low for 1/3.T), and logic-0
(high for 1/3.T, low for 2/3.T). (high for 1/3.T, low for 2/3.T).

Below example shows primary-side PP pin bitstream during high-side

over-temperature fault (HSD_OT).

Preamble 0h 00h 80h 00h

PP Pin Voltage
Fault Bitstream

Bit Number: 15 8 7 0 31 24 23 16 15 8 7 0 31 24

PI-9641-100722

Error Code = 0008000h : HSD_OT (high-side over-temperature fault)

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 HiperLCS-2

Secondary Device PS Pin Error Fault Codes

Hex Fault
Bit PS Pin Error Fault Name Description
Code Action

31:28 X I 1111 Fixed Pre-amble.

27:24 X I 0000 Fixed Pre-amble.

23:18 X N xxxxxx

Information only: read-out of the Secondary device internal Frequency

17:16 X I FREQ_MODE_INFO Range 0-3 value. Helpful for debugging frequency confirmation faults
(FREQ_FAULT), reported on the primary device.

15:14 X N xx

BPS undervoltage fault. This causes the secondary controller to stop

13 2000h P BPS UV FLT
operating and enter power-up state.

12 1000h N x

FB pin overvoltage fault. Note: this fault is only active after hand over to
11 800h A SEC_FB_OV_FLT
secondary control.

10 400h N x

9 200h N x

8:7 X N xx

Secondary controller over-temperature fault. Device switching stops while

6 40h A SEC_OT_FAULT
fault is active.

Phase inversion fault is only active after start-up and hand over to secondary
control mode. The VIS clock is compared to the internal FL clock. If the two
5 20h I SEC_PHINV_FAULT clocks are out of phase during 800 ms fault timer, the fault is asserted.
Cumulative switching cycles with phase inversion are required. A single
switching cycle without phase inversion resets the fault timer.

4:3 X N x

Output UV Fault become active after start-up and hand over to secondary
2 4h A VOUT_UV_FLT mode. Fault is activated if FB pin remains below VFBBSTN(TH) for 64 ms. This
fault is disabled in CC mode (PPsel6, PPsel7).

1 X N x

Secondary start-up fault. From end of frequency confirmation (before hand

over), secondary output voltage (monitored by FB pin), if output does not
0 1h A VFB_START_FLT
reach regulation within 64 ms, the fault is activated. This fault is disabled in
CC mode (PPsel6, PPsel7).

Fault Action:
A = auto-restart, P = power-up reset state, I = information only, N = not-used (ignore).

Table 4. LSR2000C – Secondary-Side PS Pin Error Fault Reporting.

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device uses 3 signals to achieve closed loop control. The FB pin

PP Pin Selection Frequency Range Fault Response signal is coupled via resistor divider from the output voltage. This FB
pin voltage represents a scaled version of the output voltage. The FB
0 0 Auto-on
pin generates an error signal with respect to an internal 3.75 V DC
1 1 Auto-on reference. The error signal is output via an OTA, operational trans-
conductance (voltage input to current output) amplifier in the form of
2 2 Auto-on an error current signal to the CMP pin. The gain of the OTA amplifier
is dependent on the magnitude of the error signal. Low gain (e.g., 1x.),
3 3 Auto-on is used for small errors, but once error exceeds a threshold the gain is
increased to high gain (e.g. 4x.). This non-linear amplification (NLA)
4 0 Latch-off allows for extremely fast large-signal transient response.
5 1 Latch-off
The CMP pin is coupled to an external resistor capacitor compensation
6 2 Latch-off network (two poles one zero). This compensation network is tailored
to achieve good phase-gain response. The error current signal is
7 3 Latch-off integrated and filtered by the compensation network. When the
system is in regulation the error-current-signal should be extremely
PP External Fault All Latch-off small, thus a small current causing very small variations in the CMP
voltage (compensation network). Both leakage and magnetizing
Table 5. Table of Primary-Side PP Pin Functionality Selections. See Data Table signals.
for PP Pin Selection Resistor Values.
The IS pin senses the winding voltage from the transformer. The
The BM pin is used to signal that the HiperLCS-2 is operating at low sense winding is coupled to the primary of the transformer (both
load. Amongst its uses, this signal can be used to turn-on/off an leakage and magnetizing signals), generating a voltage whose
inrush bypass relay. It could also be used to change the set-point of magnitude is similar in scale to that of the main output voltage
the PFC boost voltage. winding. The IS pin has internal clamping at 2.5 V. The sense
winding voltage is AC coupled (via capacitor) and then converted to a
The FL pin input is used to receive secondary communications, such current using a resistor into the IS pin. The magnitude of the current
as regulation, burst modes and faults. This input receives a digital is low, below 35 mA, thus causing minimal system loss.
0-5 V signal from the FL-output of the isolation device.
HiperLCS-2 Secondary-Side Isolation-Device Internally the IS pin AC-coupled current signal is compared against
Operation the CMP pin voltage. When the two cross this indicates the end of a
half-cycle.
Communications to Primary-Device
As mentioned earlier the primary device will autonomously start-up The IS pin signal contains, amongst other things, information about
and begin switching, with primary remaining in control until the primary input current. This means that the overall system implements
output voltage reaches close to regulation. At this point the a current mode control. The control system does not directly control
secondary will take control (primary will hand over control to frequency, but instead controls half-cycle by half-cycle in time-domain.
secondary) and all further switching is then controlled from the However, the frequency is an indirect function of the control loop,
secondary side controller. thus in steady state the frequency will be stable and a function of
resonant tank, input voltage and output power, etc.
The secondary-device communicates to the primary-device via the
FluxLink isolated communications. Communication commands include
hand over (i.e., secondary taking control), half-bridge switching, burst Burst Constant
PS Pin Burst
mode and declaration of fault condition. Threshold Current
Selection Control
(%) ** Compatible
The isolation-device FL-output is connected to the primary FL-input.
0 15 No Internal
Secondary Fault Handling
After hand over the secondary remains in control until either: a 5 2 No Internal
UV-event occurs (primary or secondary), or until a fault occurs
(primary or secondary). Under either of these conditions UV or fault, 6 15 Yes Internal
the control reverts back to primary control. Also, under either of
7 2 Yes Internal
these conditions the primary would enter auto-restart. For auto-
restart, the device has two functionalities, either latch (off-condition),
Table 6. Table of Secondary-Side PS Pin Functionality Selections. Selected via
or non-latching (i.e., auto-restart). PS Pin Resistor (see data table). **Approximate Burst Percentage of
Maximum Continuous System Output Power.
After auto-restart off-time, the primary restart is the same as for first
Burst Mode
power-up as described earlier in primary control section.
The CMP pin voltage is inversely proportional to primary input
current. This voltage is used to determine when the system should
Note that the primary is the device which handles all system level
enter burst mode. Thus, for a given input voltage the burst mode
fault events. Any secondary fault is reported to the primary and
entry point is a function of output power. This function is compensated
ultimate system level fault response comes from the primary.
for input voltage, such that the burst-entry point should be at
Secondary Control relatively similar power levels over the entire input voltage range.
The secondary takes control of switching as the output voltage For the HiperLCS-2 the burst mode is used for more than one reason.
approaches regulation. Once in secondary control, the secondary

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The first reason for burst is to maintain system efficiency. In full SR (Synchronous Rectifier) Control
frequency mode the system efficiency naturally drops significantly The D1 and D2 pins monitor the drain voltage of the SR MOSFET’s.
below 10% load. So, the first goal is to enter burst mode before 10%. When D1 and D2 go below ground this indicates the potential start of
The regulation is achieved by switching less often but continuing to SR conduction. Pins D1 and D2 require a small series resistor to
deliver the equivalent of about 10% power per switched half-cycle. prevent excessive substrate current when below ground voltage.
Under certain conditions, there may be ringing on D1 and D2, and the
The second goal once in burst is to maintain output regulation. ring may temporarily go below ground only to rise back above
This is achieved using three modes of burst regulation. ground. The HiperLCS-2 therefore employs a learning engine to
ignore the ringing. Therefore, when the ring-filtered value of D1
The third goal once in burst is to maintain the switching frequency (or D2) goes below a turn-on threshold, the associated SR MOSFET is
envelope well below the audio resonant frequency of the LLC then activated. Once activated the D1 (or D2) signals then monitor
transformer. The audio/mechanical resonance LLC-transformers is the on-state Drain-Source voltage across the SR MOSFET. This gives
typically in the 7-12 kHz range. Thus, in burst the HiperLCS-2 intends an indication of conduction current. For an LLC-converter in
to maintain switching frequency envelope below approximately 1 kHz. discontinuous conduction mode (DCM), the rectified output current
Being well below the audio resonance of the transformer means that (i.e., power delivered to the secondary), will reach zero before the
there will be little or no noise from the transformer. end of the half-cycle. In discontinuous mode (DCM) LLC operation,
the detected D1 (or D2) will terminate the SR-conduction when
The fourth goal is to maintain ability to satisfy 0-100% load step current approaches zero. The secondary controller turns off the
without losing regulation. SR MOSFET before reverse conduction. For an LLC-converter
operating in continuous conduction mode (CCM), the current will not
To help achieve the goals above, the HiperLCS-2 uses 3 modes of reach zero prior to the end of the half-cycle. Therefore, to prevent
operation when in burst. reverse SR MOSFET current, the HiperLCS-2 will terminate SR-
conduction prior to half-bridge switching. This can be done because
On entering burst, the highest power burst mode is called the half-bridge switching signal is originated at the secondary
intermediate mode (IM-burst). In this mode the system is still in controller. Thus, the secondary control can turn off the SR MOSFET
closed loop analog control via the CMP pin. The IM-burst works by at exactly the latest possible moment to guarantee no shoot-thru in
forcing off-time at a 1.5 ms repeat period. The IM-mode off-time is CCM mode. This is something that allows the HiperLCS-2 to safely
terminated once the output voltage decays to a minimum value operate in CCM-mode with maximum SR conduction. Note: that in
(VOUTMIN). At this point switching begins again and the analog CCM mode, the primary and secondary rms currents are reduced vs.
control loop closes to reach regulation. Regulation is then maintained DCM mode. Therefore, being able to operate in safely in CCM mode
until the off-to-off timer again reaches the 1.5 ms period. Then the generally results in higher system efficiency.
next IM-mode off-time begins.
SR Driver Voltage Clamp
The G1 and G2 pins respectively drive the SR MOSFET’s for each
The next level down in terms of output power, is the light-load
phase of the LLC secondary. The BPS pin voltage supplies drive
LL-mode burst. During this mode the CMP is no longer used.
current to the G1 and G2 gate-drive outputs. However, the BPS pin
Instead, an internal VCMP_BURST is used, where VCMP_BURST
is able to accommodate a voltage range of up to 24 V. This would
corresponds to the equivalent of 10% load. The LL-mode burst
exceed the maximum gate withstand for most SR MOSFETs. Also,
switching begins when output voltage reaches VOUTMIN. The
most SR MOSFET’s are fully enhanced at voltages well below that.
switching continues, terminating when output voltage exceeds
In order to limit the SR-MOSFET gate-charge/discharge energy, the
VOUTMAX. The device enters LL-off-time until the voltage again
HiperLCS-2 provides an internal voltage clamp to limit the maximum
reaches VOUTMIN. During the LL-burst switching each half-cycle
voltage output on the G1 and G2 SR-drive pins. The gate-drive
delivers equal power (determined by internal VCMP_BURST) and
voltage is internally controlled to a maximum of either 11.5 V or 6.5 V.
approximately equal to 10% load.
The maximum voltage depends on the selected frequency range of
the device. Frequency ranges 0,1 (90, 120 kHz), receive 11.5 V
The lowest level of burst in terms of output power is super-light
whereas higher frequency ranges 2,3 (180, 240 kHz) receive 6.5 V
SL-burst. During this mode the switching occurs after a maximum
drive limits. Limiting the SR MOSFET drive voltage limits the
off-time of 50 ms. The start SL-burst switching depends on the 50 ms
gate-charge/discharge losses. Typically, higher frequency SR MOSFET’s
off-time only. If the output voltage drops as far as VOUTMIN then the
are structurally optimized to have lower VGS turn-on thresholds and
device will move back to LL-burst. During SL-burst switch, the burst
thus fully enhanced at lower voltages.
switches until either it reaches VOUTMAX or reaches 60 ms of total
switching time. Layout Connections and Recommended Values
During PC-board layout, it is important to understand the current
With the burst modes of the HiperLCS-2 the device is able to achieve return pin for each signal, so that correct routing paths can be
exceptional system no-load performance. Unlike other systems implemented. The following table shows that information along with
though it can still accommodate a full 0-100% load step without generic recommended external component values. Obviously for all
dropping out of regulation. The burst mode also intrinsically designs component values may change or be optimized to suit
manages audio noise. The output ripple during burst is also entirely specific conditions, however the recommended values are given as a
bounded by the VOUTMIN and VOUTMAX of the system. The device good starting point.
achieves 1% system regulation, internally the FB pin VOUTMAX and
VOUTMIN thresholds are fixed at ±0.65% of VOUTREG.

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Isolation Most Returned to Recommended

Device Pin Notes
Barrier Sensitive Pin Value
Primary Low-Side Control
Primary LCS726x BM GP

1 mF / 35 V SMD right
The gate-drive energy comes from this pin. Large
at pin. Usually also
Primary LCS726x BPL GD BPL pin capacitance will also be needed away from
47 mF further from
pin.
pin

1 mF / 10 V SMD
Primary LCS726x 5VL GP
right at pin

GP There is a connection from isolation device LSR2000

Primary LCS726x FL ** (LSR2000 to LCS726x. The 5VL, GP and FL pins of both
device) devices should be directly connected.

Primary LCS726x PP GP RPP at pin See data table for selection values.

Split resistance into at least 3 SMD resistors. Ensure

Primary LCS726x L ** GP 4 MW
that all resistors are located close to L pin.
Primary High-Side Control
1 mF / 35 V SMD right
Primary LCS726x BPH HB at pin. Usually also
10 mF further from pin

220 nF / 10 V SMD
Primary LCS726x 5VH HB
right at pin

Heat
Primary LCS726x S If heat sink used ensure that it is grounded to S pin.
Sink
Primary FluxLink
There is a connection from isolation device LSR2000
Primary LSR2000 5VL GP(LSR2000) to LCS726x. The 5VL, GP and FL pins of both
devices should be directly connected.

There is a connection from isolation device LSR2000

Primary LSR2000 GP GP(LCS726x) to LCS726x. The 5VL, GP and FL pins of both
devices should be directly connected.

There is a connection from isolation device LSR2000

Primary LSR2000 FL ** GP(LCS726x) to LCS726x. The 5VL, GP and FL pins of both
devices should be directly connected.

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Isolation Most Returned to Recommended

Device Pin Notes
Barrier Sensitive Pin Value
Secondary Control

Secondary LSR2000 D1 ** GSA 499 ohm Switch signal hence pay attention to layout/coupling.

Secondary LSR2000 D2 ** GSA 499 ohm Switch signal hence pay attention to layout/coupling.

High current gate-drive. Wider PC-board trace to

Secondary LSR2000 G1 GSA 4.7 ohm
limit inductance.

High current gate-drive. Wider PC-board trace to

Secondary LSR2000 G2 GSA 4.7 ohm
limit inductance.

1 mF / 35 V SMD right
Secondary LSR2000 BPS GSA at pin. Usually also
47 mF further from pin

10 mF / 10 V SMD Note: this pin also has high internal current spikes,
Secondary LSR2000 5VS GSB
right at pin hence larger capacitor right at the pin.

Note: the RIS resistor is typically split into two series

RIS resistor + 470 pF resistors to share the voltage rating. Series resistors
Secondary LSR2000 IS ** GSB
/ 200 V capacitor are placed as close as possible to the IS pin to limit
external noise coupling.
Initial values (150k +
Compensation components may require modification
Secondary LSR2000 CMP GSB 2.2 nF) // 100 pF. All
to optimize phase-gain response.
components at pin

The resistor divider 10 kW low-side resistor is used

to give a good balance between no-load consump-
10 k lower resistor
Secondary LSR2000 FB ** GSB tion and noise rejection. Lower values will give more
value, at pin
noise immunity but will also increase no-load
consumption.

Secondary LSR2000 PS GSB RPS at pin See data table for selection values.

Table 7. Data Sheet Body Table.

Basic Layout Guidelines There are two different examples of how to connect the L pin to VIN.
The first (incorrect) would be to place all the resistors close to VIN
The HiperLCS-2 is a high-frequency power device and requires careful and then run a long PC-board trace to the L pin. This is incorrect
attention to circuit board layout in order to achieve maximum since the node from resistor to L pin is high-impedance and a long
performance. The bypass capacitors need to be positioned and laid PC-board trace would allow noise pickup injected into the L pin. The
out carefully to minimize trace lengths to the pins they serve. second (correct) method would be to place ALL the resistors close to
Surface mount (SMD) components are recommended for minimum the L pin and run a long PC-board trace to VIN. This method is
component and PC-board stray inductance. correct since the node from resistor to VIN is very low-impedance
and thus very unlikely to pick-up noise. On the secondary-side
The HiperLCS-2 has several sensitive pins, used for sensing analog control, the FB, CMP, IS and D1/D2 pins may be sensitive to layout.
signals. Good device performance can be achieved by paying special
attention to the layout at and around these pins. The FB pin is a high impedance voltage input pin. It is connected to
VOUT via a resistor divider (RUPPER, RLOWER). VOUT is a low-impedence
On the primary-side control, both the FL pin and L pin have may be node, so this may be the long PC-board connection. The node from
sensitive to layout. RUPPER to RLOWER, is high impedance and should be placed as close and
tightly coupled as possible to the FB and GSB pins. The general
The FL pin output is essentially a digital output, so for this pin the
recommendation for RLOWER is 10 kW, which is a good compromise
issue is to ensure that the GP, FL and 5VL are all directly connected
between no-load consumption and noise immunity. Further reducing
between the primary and isolation devices. If the grounding is not
RLOWER would increase noise immunity but increase no-load consumption.
done correctly this can lead to potential noise pickup.
Note that any noise injected into the FB pin could be observed as
duty-cycle and/or frequency variation.
For the L pin this is a sensitive analog input pin. The L pin senses
input voltage via a resistor (typically 4 MW). The resistor is typically
The CMP pin is a high impedance current output and voltage-input
made of a series of SMD resistors. Splitting the resistance into
pin. The compensation network of one-resistor and two capacitors’ is
several devices will minimize the voltage stress on each resistor.
should be place as closely and tightly coupled as possible to the CMP

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and GSB pins. Any noise injected to the CMP pin could be observed ground. All of these devices should be kelvin connected to this
as duty-cycle and/or frequency variation. ground. The ground should then have a single direct PC-board trace
back to the primary bulk-capacitor ground.
The IS pin is a current input, with a forced voltage on the pin. The IS
pin signal passes from the winding-sense pin of the transformer Note:
through series capacitor CIS and resistor RIS connected to the IS pin. HiperLCS-2 Secondary-side only has one power pin and this is the
The transformer winding signal pin should first be connected to the GSA pin. The GSA pin should be tightly connected to the SOURCE of
CIS capacitor and then in series to the RIS resistor. The RIS resistor both SR MOSFET’s (SR1 and SR2). Both SR MOSFET’s should be
should be split into two SMD resistors, the last of which should be co-located as close as possible with a shared Source connection
terminated right at the IS pin of the HiperLCS-2 device. The point. The GSA pin should be connected at the mid-point between
transformer should have both a winding sense signal pin and also a SR1 and SR2 SOURCE pin connections. The G1 and G2 secondary
winding-sense small signal ground pin. The winding sense small gate-driver pins do drive substantial gate current and so should be
signal transformer ground pin should be connected to the GSB pin of kept to a short (and equal) length(s). The D1 and D2 DRAIN sense
the HiperLCS-2. The winding sense transformer signal pin is a pins, should also be kept to equal lengths. The location of the GSA
low-impedance node and therefore this may be the long PC-board pin connection to SR MOSFET source, will determine the accuracy of
connection. This trace however is carrying a large magnitude D1/D2 detection. This can affect the current-sensed turn-off point for
(medium voltage) AC coupled signal. Thus, care needs to be taken to SR1 and SR2 when operating in DCM (discontinuous) mode. If fine
keep these signals away from other small signal sensitive inputs of tuning is required, moving the GSA connection point closer to one of
the device. the two MOSFET’s can change the relative turn-off points for SR1 and
SR2. Also, fine tuning of both turn-off points can be achieved by
The D1/D2 pins are both high impedance voltage inputs. The D1/D2 changing the resistor (RD1 or RD2), in series with D1 or D2 pins. The
are connected via a low-value resistor (typically 499 W), to the resistor is typically 499 W, but may be adjusted in the range
respective Drain of the SR MOSFET with respect to GSA pin. The SR 250 – 1 kW. These small changes will adjust the turn-off current of
MOSFET Drain point is a low-impedance node so may be the long SR1 or SR2 (larger resistor increases current at which SR will
PC-board connection. This trace however is carrying a large magnitude turn-off).
(medium voltage) AC coupled signal. Thus, care needs to be taken to
Key Design Details
keep these signals away from other small signal sensitive inputs of
the device. The LLC can be optimized for different criteria. The HiperLCS-2 has
four frequency ranges of operation with nominal frequencies of 90,
Transformer T1 is a source of both high di/dt signals and dv/dt noise. 120, 180, 240 kHz. For highest possible efficiency, lower frequency
The high di/dt can couple magnetically (PC-board loop signal loop designs generally give marginally better results. However high-
area coupling), to sensitive circuitry. The high dv/dt inject noise via frequency designs are very close in efficiency. High-frequency design
electrostatic (stray capacitive), coupling. Electrostatic noise coupling may yield smaller magnetic size and smaller resonant capacitor. For
can be reduced by grounding the transformer core, but it is not most designs litz wire is recommended. For a given design the
economically feasible to reduce the stray magnetic field around the optimal diameter and number of strands is automatically calculated
transformer without drastically reducing its efficiency. Where by Power Integrations design tools (PIXlS HiperLCS-2 Spreadsheet),
possible, sensitive signal paths and components should be located that assist with the entire design process.
away from the transformer to avoid noise pickup. The secondary
transformer main output windings should be twisted together prior to For most designs low-loss ferrite cores lower the magnetizing losses
winding. Twisting the wires together will minimize differences in and a recommended for best efficiency. Likewise, the maximum
secondary leakage and will enhance current balance between the flux-density also has strong effect on hysteretic magnetic losses.
windings. Also as importantly please ensure that all secondary wires Lowering maximum flux-density (i.e., increasing secondary turns), can
are twisted together prior to termination on the transformer pin. often give a higher efficiency design (especially at higher frequencies).
Twisting the terminate wires will minimize wire-loop area and
minimize the ability of the windings to couple stray flux to other For nominal input voltage and 100% load, it is recommended that the
system signals. magnetizing inductance (LM) is adjusted to give a half-bridge slew rate
of approximately 250 ns at 380 VDC. Such a design should achieve
HiperLCS-2 primary-side power pins are the S, HB and HD pins. ZVS operation for all load and input voltage conditions. Lowering the
Unlike some designs, the HiperLCS-2 is intended for use with only a magnetizing inductance beyond this target, will result in higher
single resonant capacitor. This is typically connected to primary- circulating currents and higher resistive losses. For all HiperLCS-2
return (primary ground). The HB pin is connected to the LLC designs, the goal is for the resonant tank to still be able to achieve
transformer and the transformer to the resonant capacitor, this path ZVS operation at the FMAX limit for the chosen frequency range. This
length of PC-board connection should be minimized. Care should be is important since when the converter sees a load transient (when
taken to minimize return path (primary-ground) between the resonant load is say stepped to zero), the frequency may temporarily reach
capacitor and S pin of the HiperLCS-2 and the PC-board connection FMAX limit prior to entering burst mode. For this reason, it is important
between resonant capacitor and device. The HD pin connection to choose the frequency range that offers the appropriate range of
should also include a local decoupling capacitor from HD to primary frequencies needed for the operational scope of the converter. Note
ground (S pin potential). The goal of the local decoupling capacitor the FMIN limit of the chosen frequency range will become active at
is to reduce the path length for high magnitude switched currents. lowest input voltage and highest load. Typically, the FMIN limit is only
reached under fault conditions.
Primary-side power ground (i.e., local decoupling capacitor ground,
S pin, resonant capacitor ground), should all have an independent The resonant inductance LRES (or often referred to as leakage
and direct PC-board trace back to the bulk-capacitor ground. inductance), should be designed to provide maximum overload power.
Primary-side small signal ground. This is the node shared by primary
GP pin, isolation device GP pin, BPL pin capacitor(s) ground, For the HiperLCS-2, it is recommended that the design be optimized
transformer primary bias ground pin, primary bias capacitor(s) for operation at resonance, CRM at nominal input voltage and 50%

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load. At higher input voltages the converter may enter continuous Y capacitor should also be kelvin connected at bulk capacitor C1.
mode, CCM operation. For some converters this may present a risk
LLC Secondary Schematic
of shoot-through, but the HiperLCS-2 is uniquely designed to allow
the system to enter continuous conduction mode, CCM without risk of Transformer output pins T1 FL3/FL4 provide the positive output
shoot-through or other anti-social converter behavior. voltage, which is rectified and filtered by capacitors C27, C28, C30,
C31 and C32. These capacitors must combine to provide low ESR
LLC Primary Schematic which mostly defines the output ripple of the system. Also, the
The HiperLCS-2 receives a rectified and filtered DC input bus voltage combined C-value total of these capacitors should be chosen to
(VBULK+). The input bus voltage is sensed via three series resistors match the desired burst threshold. These capacitors are decoupled
R24, R25, R26 connected in series to the L pin. An external PFC to secondary ground (GND). Transformer output pins T1 FL1/FL2 are
power-good signal may be connected via resistor R1 to the PP pin. the return path rectified via synchronous rectifier MOSFETs Q4 and
Primary-side detected output overvoltage is sensed at the primary Q5 to secondary ground. The secondary power path is from T1 FL3/
bias-winding (T1-5/6), via Zener diode VR1 and resistor R34. This FL4 through C27, C28, C30, C31, C32 and returning via Q4, Q5 to
OVP signal is then coupled to the PP pin via resistor R32 and transformer T1 FL1/FL2. This secondary power path should be kept
transistor Q3. When Zener VR1 conducts, current will be pulled from as short and symmetrical as possible between each of the two phases
PP pin to ground via transistor Q3. Resistor R33 selects the PP pin of the LLC and the layout should use wide high current traces.
programming (primary frequency range and fault-response). The BM
pin may be coupled to an external circuit which could drive an in-rush The LSR2000C (U3) is decoupled at 5VS and BPS pins by capacitors
relay and/or change PFC voltage as a function (BM becomes active C9 and C33/C34. The secondary bias winding T1 pin 12 is rectified
during burst mode). via diode D7 and filtered by capacitor C33/C34. At no-load the
secondary bias voltage may drop to a lower voltage and additional
The 5VL and BPL pins are decoupled by capacitors C24 and C22 no-load bias comes from output voltage (+24 V) via resistor R30 and
respectively. Diode D6 rectifies primary bias winding voltage (T1 pin Zener diode VR1. Output voltage is sensed via resistor bridge R36
5) and decouples to capacitor C27, the voltage is fed through resistor and R37 with local capacitor decoupling C29 to remove any high-
R31 to decoupling capacitor C21. Before switching during start-up, frequency noise.
charge bias current is provided from the BPL pin and out to capacitor
C21 via resistor R30. Capacitor C21 is also available to supply start-up Compensation is provided between CMP and GSB, via components
bias to external PFC stage. Resistor R30 limits output current from R44/C36 which provide a pole and zero and C35 which adds another
BPL in the event of a large current draw from external PFC stage. pole. These compensation component values provide a good starting
During normal operation the bias current comes from the bias point for most designs. The transformer IS winding T1/9, provides a
winding to capacitor C21. In the event of high bias-winding voltage, medium voltage signal which is capacitor coupled via C37 and then
resistor R31 limits the shunt-current that may be consumed by the via resistors R48, R49 to the IS pin. The IS signal is a sensitive
BPL pin when clamping BPL internally to ground via shunt regulation. high-frequency analog signal and so care should be taken with layout,
Note that the bias winding voltage may vary over a 25% range from to keep capacitor C37 away from the IS pin to reduce stray capacitive
zero to full output load. For best no-load performance, the bias coupling, but the resistor R48 should be terminated at the IS pin for
winding is intended to deliver a minimum of 15 V to the bias winding best noise immunity. The IS winding a scaled sum of primary winding
at zero load conditions, while the BPL pin shunt will engage if the bias inductance (LR + LM) voltages.
winding grossly exceeds 21 V.
The D1/D2 pins sense the synchronous rectifier (Q4, Q5), drain
In normal switching, during the low-side power MOSFET-on period voltages via resistors R40, R45. The resistors are required to limit
the high-side bootstrap is charged via diode D4 and resistor R23 into below-ground current into the D1, D2 pins. The minimum value of
capacitor C6. Resistor R23 limits the current into capacitor C6 in the R40, R45 should be 200 ohms, but these resistor values can be
event that the capacitor voltage is fully depleted. Since the C6 increased 2x to 5x to offer adjustment to SR turn-off threshold.
charge current flows through the low-side power MOSFET, the Increasing resistor R40 and R45 values will cause SR to turn off at
removal of resistor R23 may under worst-case conditions result in higher SR current. Alternately put, increasing resistor R40 and R45
trigging of low-side safety current limit. Resistor R22 and capacitor values will cause SR to turn off early in the conduction cycle.
C17 provide further filtering of high-frequency ripple. The high-side
5VH is decoupled via capacitor C19. Note that all high-side Synchronous MOSFET Q4, Q5 drive is coupled from G1/G2 pins via
decoupling is with reference to HB potential. resistors R39, R43. The drive resistors are optional and intended to
limit super high-frequency MOSFET drive ring. Local pull-down
Resonant tank inductor components T1 pins 1/2 (integrated resistors R38, R42 are present to ensure the MOSFET Q4, Q5 remain
transformer includes resonance LR and magnetizing inductance LM), off in the FMEA case where gate-drive is absent for some reason.
are connected from HB in series through resonant capacitor C18 to
primary return RTN (primary ground). Note, a kelvin connection is The PS pin resistor R50 selects secondary-side user functions (such
preferred, from C18 directly to the input bulk-capacitor terminal and as CV or CC mode, etc.).
low-side power MOSFET SOURCE pin GD. Kelvin connection prevents
the high magnitude tank switching currents from polluting other small
signal grounds (GP). Safety capacitor C10 provides Y capacitor
connection from primary ground (RTN) to secondary zero-volts (GND).

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 HiperLCS-2

VBULK+ R22 R23

10 Ω 2.2 Ω
1% 1%
R24
1.6 MΩ
1% C17 C6
C19 1 µF 10 µF
220 nF 50 V 35 V
R25 25 V
1.6 MΩ
1%
HiperLCS2-HB
U1
LCS726x BPH 5VH HD
FL2 D2A
D4
MURS160T3G
R26
1.6 MΩ
1% FL3-FL4 +24 V
HSD

FL1 D1A
CONTROL
L
HB 1 12 SBIAS
280 – 400 R1 FL FLI C20
VDC 18.2 kΩ
1% 68 nF D5 D6
PG IN PP 630 V
R31
PCD ES1A-13F 750 Ω B180B-13-F
BPL 5 11 GSB
BM
R30
BM OUT 10 Ω
5VL VR1
MMSZ5256B-7-F
6 10 GSB
C22 C21 OVP C27
1 µF 47 µF 22 µF
50 V 25 V 35 V
GP3 GP10 GD S IS
R34 2 9
10 kΩ T2
R32
47 kΩ 5VL ETD34
OVP R33
158 kΩ C25
1% C24 18 nF
Q3 1 µF
MMBTA06LT1 600 V
16 V Plastic
GP Film
C41
2.2 nF
RTN 250 VAC SG

PI-9291-021522

Figure 10. HiperLCS-2 Primary-Side 220 W, 24 V LCS726xC.

FL3 FL4

+24 V +24 V

R30 R36
200 Ω 133 kΩ
VR1 1%
MMSZ5245B-7-F C29 C32 C27 C30 C28 C31
100 nF 10 µF 330 µF 10 µF 330 µF 330 µF
SBIAS 50 V 50 V 35 V 50 V 35 V 35 V
R37
24.3 kΩ
Q4 R38 D7 1%
D2A AON6242 10 kΩ B180B-13-F GND

FL2

R39
4.7 Ω

R40
499 Ω C34
1% 100 µF
25 V

Q5
D1A AON6242
FL1 C33
R42
10 kΩ 10 µF C35
1% 35V 100 pF
50 V

R43 R44 C36

4.7 Ω 150 kΩ 2.2 nF
1% 50 V

R45 IS
499 Ω
1% R48 R49 C37
274 kΩ 715 kΩ 470 pF
5VL 1% 1% 200 V
R50
CMP
GSA

BPS

C38
D1

D2

G1

G2

75 kΩ
FB

IS

5VL
100 nF 1%
50 V PS GSB
FL FL FLIN GSB
FLR

FLOUT SEC Controller

5VS

C9
GP HiperLCS2-SR 10 µF
GP 10 V
U3 PI-9292-021022
LSR2000

Figure 11. HiperLCS-2 Isolation and Secondary-Side 220 W, 24 V LSR2000C.

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 HiperLCS-2

Figure 12. PCB Layout (Top View).

Figure 13. PCB Layout (Bottom View).

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 HiperLCS-2

Absolute Maximum Ratings1,2 – LCS726xC

HD Pin Voltage2 ........................................................ -1.3 V to 600 V Notes:
HB Pin Voltage2.......................................................... -1.3 V to 600 V 1. Maximum ratings specified may be applied one at a time without .
DC Output Current4,5: causing permanent damage to the product. Exposure to Absolute
LCS7260 ...................................................2.9 A Maximum Ratings conditions for extended periods of time may
LCS7262 ...................................................5.8 A affect product reliability.
LCS7265 ................................................. 10.9 A 2. All voltages referenced to low-side Source S and signal ground GP,
BPH Pin Voltage3,5 ........................................................ -0.3 V to 27 V GD except noted otherwise, TA = 25 °C.
BPL Pin Voltage5 ......................................................... -0.3 V to 27 V 3. Referenced to Half-bridge Connection HB, TA = 25 °C.
BPL Pin Current .....................................................................50 mA 4. Continuous DC output current per FREDFET calculated at 25 °C
5VH Pin Voltage3 ..............................................................-0.3 to 6 V case and 125 °C junction temperature.
5VL Pin Voltage ...............................................................-0.3 to 6 V 5. Normally limited by internal circuitry.
FL, PP Pin Voltage.............................................................-0.3 to 6 V
BM Pin Voltage.................................................................-0.3 to 6 V
BM Pin Current....................................................................... 10 mA
L Pin Voltage............................................................. -0.3 V to 600 V
L Pin Current............................................................................1 mA
S Pin to GP or GD Pin Voltage................................................±0.33 V
Junction Temperature5:
FREDFET..................................-40 °C to 160 °C
Driver.......................................-40 °C to 150 °C
Storage Temperature .............................................. -65 °C to 150 °C
Ambient Temperature ............................................. -40 °C to 105 °C
Lead Temperature4 ............................................................... 260 °C

Thermal Resistance
Thermal Resistance: InSOP-24C Package Notes:
LCS7260C (qJA).....................74 °C/W1, 59 °C/W2 1. Individual exposed pad (HB or HD), soldered to 0.36 sq. in.
LCS7262C (qJA).....................68 °C/W1, 53 °C/W2 (232 mm²), 2 oz. (610 g/m²) copper clad.
LCS7265C (qJA).....................63 °C/W1, 51 °C/W2 2. Individual exposed pad (HB or HD), soldered to 1.0 sq. in.
(645 mm²), 2 oz. (610 g/m²) copper clad.

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Conditions
TJC = 0 °C to 100 °C
Parameter Symbol Min Typ Max Units
BP = BPH = 18 V
(Unless Otherwise Specified)
Primary High-Side Controller/Driver
BPH Pin
BPH-HB Undervoltage
VBPH(UV+) 12.4 13.2 14 V
Start Threshold

BPH-HB Undervoltage
VBPH(UV-) 10.15 10.8 11.3 V
Stop Threshold

BPH-HB Start/Stop
VBPH(UV)(HYST) 2.4 V
Hysteresis

BPH (HD) Charge Output

IBPH(CH) -1.3 mA
Current

BPH-HB UV to Shunt
VBPH(SHGAP) See Note D 9 V
Spacing

BPH-HB Shunt Onset

VBPH(SHON) IBPHSH = 250 mA 23.00 24.48 25.85 V
Voltage

BPH-HB Shunt Max

VBPH(SHMX) IBPHSH = 26 mA 23.50 24.55 26.50 V
Voltage

BPH Shunt Current IBPH(SH) 0 26 mA

LCS7260C 1.4 1.7 2.0 mA

BPH Pin Current
IBPH(SW) FSW = 208 kHz LCS7262C 1.9 2.2 2.5 mA
Consumption Switching
LCS7265C 3.0 3.3 3.6 mA

BPH Pin Current Non-

IBPH(NSW) No switching VBPH > VBPH(UV+) 90 115 150 mA
Switching Consumption
5VH Pin
5VH-HB Power-Up
V5VH(UV+) See Note A 4.85 4.9 4.99 V
Threshold
5VH-HB Power-Up
V5VH(UV-) See Note A 4.45 4.55 4.7 V
Threshold
5VH-HB Power-Up
V5VH(UV)(HYST) See Note A 0.3 0.35 0.4 V
Hysteresis

5VH-HB Output Voltage V5VH I5VH = 0 mA 5.17 V

Primary Low-Side Controller/Driver
BPL Pin
BPL Undervoltage Start
VBPL(UV+) 13 13.7 14.3 V
Threshold

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Conditions
TJC = 0 °C to 100 °C
Parameter Symbol Min Typ Max Units
BP = BPH = 18 V
(Unless Otherwise Specified)
Primary Low-Side Controller/Driver (cont.)
BPL Undervoltage Stop
VBPL(UV-) 10.4 11.4 12 V
Threshold

BPL Start/Stop
VBPL(UV)(HYST) 2.3 V
Hysteresis

BPL (HD) Low Charge

IBPL(CH)LO VHB = 50 V, VBP = 0 V -2.2 -1.9 -1.55 mA
Current

BPL (HD) Charge Output

IBPL(CH) VHB = 50 V, VBP = 10 V -10 -7.7 -4.2 mA
Current

BPL UV to Shunt Spacing VBPL(SHGAP) See Note D 9 V

BPL Shunt Onset

VBPL(SHON) IBPLSH = 500 mA 20.56 21.61 22.68 V
Voltage

BPL Shunt Max Voltage VBPL(SHMX) IBPLSH = 26 mA 20.70 21.83 23.50 V

LCS7260C 2.4 2.7 3.2 mA

BPL Pin Current
IBPL(SW) FSW = 208 kHz LCS7262C 3 3.3 3.6 mA
Switching Consumption
LCS7265C 4.1 4.5 5.0 mA

BPL Pin Current Non-

IBPL(NSW) No switching VBPL > VBPL(UV+) 600 780 950 mA
Switching Consumption
5VL Pin
5VL Power-Up C5VL = 1 mF / 10 V ceramic
V5VL(UV+) 4.85 4.9 4.99 V
Threshold See Note A

5VL Power-Up C5VL = 1 mF / 10 V ceramic

V5VL(UV-) 4.45 4.55 4.70 V
Threshold See Note A

5VL Power-Up C5VL = 1 mF / 10 V ceramic

V5VL(HYST) 0.30 0.35 0.40 V
Threshold See Note A

5VL Output Voltage V5VL I5VL = 0 mA 5.15 V

BM Pin
BM – On Trigger Period
TBM(ON) See Note A 5 ms
(no FL)

BM – On Trigger
TBM(DB) See Note A 5 sec
Debounce

BM – Off Trigger Period

TBM(OFF) See Note A 2 ms
(FL present)
BM Driving High, VBM = 0 V
BM – Current Source IBM(SRC) -19 mA
See Note A, C
BM Driving Low, VBM = V5VL
BM – Current Sink IBM(SNK) 24 mA
See Note A
BM – On-Output Voltage VBM(ON) IBM = - 2 mA 4.2 4.65 V

BM – Off-Output Voltage VBM(OFF) IBM = + 2 mA 0.005 0.1 V

FL Pin
FL – Logic 1 Input
VFL(IH) 3.2 3.5 V
High-Voltage
FL – Logic 0 Input
VFL(IL) 1.2 1.5 V
Low-Voltage

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Conditions
TJC = 0 °C to 100 °C
Parameter Symbol Min Typ Max Units
BP = BPH = 18 V
(Unless Otherwise Specified)
Primary Low-Side Controller/Driver (cont.)
L Pin
L Pin Breakdown
VL(BV) L Pin Disabled (Burst Off-State) 600 V
Voltage

L Pin UV Stop Threshold

IL(UV-) 44 49 54 mA
Current

L Pin UV Restart
IL(UV+) 58 63.5 69 mA
Threshold Current

L Pin OV Restart
IL(OV-) 98 108 118 mA
Threshold Current

L Pin OV Stop Threshold

IL(OV+) 110 123 135 mA
Current

L Pin UV Hysteresis
IL(UV)(HYST) 12.0 14.6 17.2
Current

L Pin OV Hysteresis
IL(OV)(HYST) 12.5 15.2 18.2
Current

L Pin Sink Current IL(SNK) See Note A, C 200 mA

L Pin Sink Voltage

VL(SNK)(UV-) IL(SNK) = IL(UV-) 1.6 V
UV Stop

L Pin Sink Voltage

VL(SNK)(UV+) IL(SNK) = IL(UV+) 1.7 V
UV Start

L Pin Sink Voltage

VL(SNK)(OV-) IL(SNK) = IL(OV-) 2.0 V
OV Start

L Pin Sink Voltage

VL(SNK)(OV+) IL(SNK) = IL(OV+) 2.1 V
OV Stop
PP Pin
PP Pin Remote-Off
IPP(REM-) -17 -13.5 -10 mA
Threshold

PP Pin Remote-On
IPP(REM+) -47 -39 -32 mA
Threshold

PP Pin Remote-On/Off
IPP(REM)(HYST) 20 25.5 31 mA
Hysteresis

PP Pin Remote-On
VPP(REM+) 0.81 V
Voltage

PP Pin Remote-Off
VPP(REM-) 0.86 V
Voltage

PP Pin Fault Clear

IPP(FLT-) -93 -79 -66 mA
Threshold

PP Pin Fault Assert

IPP(FLT+) -95 -81 -68 mA
Threshold

PP Pin Remote-On/Off
IPP(FLT)(HYST) 1 mA
Hysteresis

PP Pin Fault Assert

VPP(FLT+) 0.75 V
Voltage

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Conditions
TJC = 0 °C to 100 °C
Parameter Symbol Min Typ Max Units
BP = BPH = 18 V
(Unless Otherwise Specified)
Primary Low-Side Controller/Driver (cont.)
PP Pin Selection0
RPP(SEL0) Required Resistor 1% E96 series 59 kW
Resistor

PP Pin Selection1
RPP(SEL1) Required Resistor 1% E96 series 158 kW
Resistor

PP Pin Selection2
RPP(SEL2) Required Resistor 1% E96 series 226 kW
Resistor

PP Pin Selection3
RPP(SEL3) Required Resistor 1% E96 series 316 kW
Resistor

PP Pin Selection4
RPP(SEL4) Required Resistor 1% E96 series 412 kW
Resistor

PP Pin Selection5
RPP(SEL5) Required Resistor 1% E96 series 536 kW
Resistor

PP Pin Selection6
RPP(SEL6) Required Resistor 1% E96 series 715 kW
Resistor

PP Pin Selection7
RPP(SEL7) Required Resistor 1% E96 series 1020 kW
Resistor
HB MOSFET
HB-S Breakdown
VHBS(BV) 600 V
Voltage Rating

HB-S Reverse
VHBS(BV) See Note A -1.5 V
Voltage Rating

HB Start-Up PreCharge
IHB(PRE) 2 mA
Current to S Pin

IHB = 0.8 A, TJS = 25 ºC,

LCS7260 1.49 W
400 ms Single Pulse

IHB = 1.6 A, TJS = 25 ºC,

HB RDS(ON) RDS(ON) LCS7262 0.73 W
400 ms Single Pulse

IHB = 3.2 A, TJS = 25 ºC,

LCS7265 0.41 W
400 ms Single Pulse

LCS7260 44 nC
Combined HB QOSS VGS = 0 V, VDS = 0 - 480 V,
QHBOSS(480V) LCS7262 87 nC
(0 .. 480 VDC) See Note D
LCS7265 159 nC

LCS7260 2.7 A
HB Safety
IHB(SFTY) See Note C LCS7262 5.4 A
Current Limit
LCS7265 10.1 A

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 HiperLCS-2

Conditions
TJC = 0 °C to 100 °C
Parameter Symbol Min Typ Max Units
BP = BPH = 18 V
(Unless Otherwise Specified)
Primary Low-Side Controller/Driver (cont.)
HB MOSFET
LCS7260 1.9 A
HB Start-Up
IHB(IOVL) See Note C LCS7262 3.7 A
Current Limit
LCS7265 7.0 A

LCS7260 0.66 A
HB Start-Up
Reduced Current IHB(IOVL-) See Note C, D LCS7262 1.29 A
Limit
LCS7265 2.43 A
HB Diode
LCS7260 1.13 V
IF = 1.0 A, VGS = 0 V,
HB Diode
VHB(F) TJ = 100 °C LCS7262 0.9 V
Forward Voltage
See Note D
LCS7265 0.8 V

IF = IHB(RRM) A, di/dt = 200 A/ms,

LCS7260 4.0 A
VR = 400 V, TJ = 125 °C
HB Diode Reverse
IHB(RRM)
Recovery Current IF = IHB(RRM) A, di/dt = 200 A/ms, LCS7262 5.6 A
VR = 400 V, TJ = 125 °C
See Note D LCS7265 8 A

LCS7260 110 ns
IF = IHB(RRM) A, di/dt = 200 A/ms,
HB Diode Reverse
THB(RR) VR = 400 V, TJ = 125 °C LCS7262 170 ns
Recovery Time
See Note D
LCS7265 200 ns

LCS7260 220 nC
IF = IHB(RRM) A, di/dt = 200 A/ms,
HB Diode Reverse
QHB(RR) VR = 400 V, TJ = 125 °C LCS7262 480 nC
Recovery Charge
See Note D
LCS7265 840 nC

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 HiperLCS-2

Conditions
TJC = 0 °C to 100 °C
Parameter Symbol Min Typ Max Units
BP = BPH = 18 V
(Unless Otherwise Specified)
Primary Low-Side Controller/Driver (cont.)
HD Pin
HD-S Breakdown
VHDS(BV) 600 V
Voltage

HD-HB Breakdown
VHBHD(BV) 600 V
Voltage Rating

HD-HB Reverse
VHBS(BV) See Note A -1.5 V
Voltage Rating

Half-Bridge
HB(OT)(STOP) See Note A 131 139 147 °C
Over-Temperature Stop

Half-Bridge
Over-Temperature HB(OT)(HYST) See Note A 10 14 18 °C
Hysteresis

LS Controller
LS(OT)(STOP) See Note A 115 125 135 °C
Over-Temperature Stop

LS Controller
LS(OT)(START) See Note A 66 78 90 °C
Over-Temperature Start

NOTES:
A. Not tested parameter. Guaranteed by design.
B. In typical LLC application circuit.
C. Normally limited by internal circuitry.
D. Not tested parameter. Based on device characterization.

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 HiperLCS-2

Absolute Maximum Ratings1,2 – LSR2000C

BPS Pin Voltage ...........................................................-0.3 V to 25 V Notes:
BPS Current ................................................................................2 A 1. All voltages referenced to GSA, GSB unless otherwise stated
D1, D2 Pin Voltage .................................................... -1.5 V to 150 V TA = 25 °C.
FB Pin Voltage ..............................................................-0.3 V to 6 V 2. Maximum ratings specified may be applied one at a time without
CMP Pin Voltage ............................................................-0.3 V to 6 V causing permanent damage to the product. Exposure to Absolute
G1, G2 Pin Voltage....................................................... -0.3 V to 20 V Maximum Ratings conditions for extended periods of time may
IS Pin Voltage................................................................-0.3 V to 5 V affect product reliability.
5VS Pin Voltage.............................................................-0.3 V to 6 V 3. Normally limited by internal circuitry.
5VL Pin Voltage (wrt GP)................................................-0.3 V to 6 V 4. 1/16” from case for 5 seconds.
FL Pin Voltage (wrt GP)..................................................-0.3 V to 6 V 5. Absolute maximum voltage for less than 500 msec is 3 V.
Junction Temperature3................................................. -40 to 150 °C
Storage Temperature .............................................. -65 °C to 150 °C
Ambient Temperature ............................................. -40 °C to 105 °C
Lead Temperature4 ............................................................... 260 °C

Thermal Resistance
Thermal Resistance: InSOP-24D Notes:
(qJA).................................................... 90 °C/W1 1. Pins 2 and 12 soldered to a shared 0.36 sq. inch (232 mm2) 2 oz.
(610 g/m2) copper clad.

Parameter Conditions Rating Units

Ratings for UL1577

Secondary-Side TAMB = 25 °C
820 mW
Power Rating See Note A

Secondary-Side
TAMB = 105 °C 300 mW
Power Rating

Secondary-Side TAMB = 25 °C
34 mA
Current Rating See Note A
Package Characteristics
Clearance 11.35 mm (min)

Creepage 11.35 mm (min)

Distance Through
0.4 mm (min)
Insulation (DTI)

Transient Isolation
6 kV (min)
Voltage

Comparative Tracking
600 -
Index (CTI)

Note A: Remark regarding UL testing: the secondary side Pin 7 BPS power the IC internal controller on the secondary side and functioned as a
constant current load. The pin is intended to accept a voltage in the 8-24 VDC range, which is shown on the spec, and drew 818 mW max at
the high end of the voltage range.

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 HiperLCS-2

Conditions
BPS = 12 V
Parameter Symbol Min Typ Max Units
TJ = 0 °C to 100 °C
(Unless Otherwise Specified)
Secondary-Side of Safety Isolation Barrier
Frequency Pin
FMIN Frequency Range 0 FMIN(FR0) LSR2000C H001 21 23 24 kHz

FMIN Frequency Range 1 FMIN(FR1) LSR2000C H002 28 30 32 kHz

FMIN Frequency Range 2 FMIN(FR2) LSR2000C H003 41 45 47 kHz

LSR2000C H004
FMIN Frequency Range 3 FMIN(FR3) 55 60 63 kHz
LSR2000C H005
See Note A
FMAX Frequency Range 0 FMAX(FR0) LSR2000C H001 123 135 141 kHz

FMAX Frequency Range 1 FMAX(FR1) LSR2000C H002 167 183 191 kHz

FMAX Frequency Range 2 FMAX(FR2) LSR2000C H003 246 270 282 kHz

LSR2000C H004
FMAX Frequency Range 3 FMAX(FR3) 334 366 383 kHz
LSR2000C H005
BPS Pin
BPS Undervoltage
VBPS(UV-) 7.0 7.25 7.5 V
Shutdown Threshold
BPS Above UV Start
VBPS(UV+) 7.3 7.55 7.8 V
Threshold
BPS Start/Stop
VBPS(UV)(HYST) 0.29 V
Hysteresis
Operating in super light load switching
BPS Pin Current in Burst IBPS(BURST) 600 mA
G1, G2 floating, See Note D

LSR2000C-H001 (90 kHz) 9.9 mA

LSR2000C-H002 (120 kHz) 12.5 mA

Device with
BPS Pin Current
IBPS(SW) G1,G2 floating, LSR2000C-H003 (180 kHz) 17.6 mA
Consumption
VBPS = VBPS(UV+)
LSR2000C-H004 (240 kHz)
23.2 mA
LSR2000C H005 (240 kHz)
5VS Pin
5VS Secondary C5VS = 1 mF / 10 V Ceramic
V5VS(UV+) 4.25 4.30 4.37 V
Power-Up Threshold See Note A
5VS Secondary C5VS = 1 mF / 10 V Ceramic
V5VSU(V-) 4.15 4.2 4.25 V
Power-Down Threshold See Note A
C5VS = 1 mF / 10 V Ceramic
5VS Hysteresis V5VS(HYST) 0.08 0.1 0.12 V
See Note A

5VS Output Voltage V5VS I5VS = 0 mA, See Note A 5.18 V

IS Pin
IS Pin Input Common
VIS(CM) 2.8 V
Mode Voltage
IS Pin Input
R IS(IN) 3.2 3.7 4.3 kW
Impedance
IS Pin Input Current
IIS(CLP) -44 -39 -32 µA
Clip Threshold
IS Pin Gain GIS(CMP) -74 -72 -70 kV/A

IS Pole FIS(CMP) See Note A 2.1 3.3 4.4 MHz

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Conditions
BPS = 12 V
Parameter Symbol Min Typ Max Units
TJ = 0 °C to 100 °C
(Unless Otherwise Specified)
Secondary-Side of Safety Isolation Barrier (cont.)
CMP Pin
CMP Pin Max Output VFB = VFB(STOP)(TH)
ICMP(OUT)(MAX) 50 80 140 µA
Current See Note D

CMP Pin Burst Off During burst-off condition

RCMP(PULL)(2V5) 1 MW
2.5 V Pull See Note A
FB Pin
FB Pin REF Threshold VFB(REF) VFB when ICMP = 0 3.7 3.75 3.8 V

FB Pin Stop Plus

VFBSTOP(TH) 3.91 3.96 4.01 V
Threshold

FB Pin Stop – VFBREF VFBSTOP(DIFF) Difference VFBSTOP(TH) – VFBREF 194 210 226 mV

FB Pin Max Threshold VFB(MAX)(TH) 3.72 3.77 3.81 V

FB Pin Max – VFBREF VFB(MAX)(DIFF) Difference VFBMAX(TH) – VFBREF 6 19 32 mV

FB Pin Min Threshold VFB(MIN)(TH) 3.69 3.73 3.77 V

FB Pin Min – VFBREF VFBMIN(DIFF) Difference VFBMIN(TH) – VFBREF -32 -19 -6 mV

FB Pin REG Threshold VFBREG(TH) 3.7 3.75 3.8 V

FB Pin REG – VFBREF VFBREG(DIFF) Difference VFBREG(TH) – VFBREF -14 0 14 mV

FB Pin VREG – VMIN

VFBREG(MIN) 6 19 32 mV
Difference

FB Pin VMAX – VMIN

VFB(MAX)MIN 25 39 52 mV
Difference

FB Pin MINBOOST
VFBBSTN(TH) 3.54 3.60 3.65 V
Threshold

FB Pin MINBOOST
VFBBSTN(DIFF) Difference VFBBSTN(TN) – VFBREF -160 -148 -136 mV
VFBREF

FB Pin MAXBOOST
VFBBSTP(TH) 3.75 3.8 3.85 V
Threshold

FB Pin MAXBOOST
VFBBSTP(DIFF) Difference VFBBSTP(TN) – VFBREF 42 55 68 mV
VFBREF

FB CMP Trans Conduc- TJ = 25 °C

GFB(CMP)(NORM) 85 95 105 µA/µV
tance Normal Gain VFB > VFBBSTN(TH) and VFB < VFBBSTP(TH)

FB CMP Trans Conduc- TJ = 25 °C

GFB(CMP)(BST) 325 365 405 µA/µV
tance Boost Gain VFB < VFBBSTN(TH) or VFB > VFBBSTP(TH)

Trans Impedance
GFB(CMP)(RATIO) See Note D 93 %
100 °C / 25 °C Ratio

FB Pole Frequency FB(BW) See Note A 187 316 654 kHz

FB Pin Bleed Current IFB(DN) TJ = 25 °C, See Note A 100 nA

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 HiperLCS-2

Conditions
BPS = 12 V
Parameter Symbol Min Typ Max Units
TJ = 0 °C to 100 °C
(Unless Otherwise Specified)
Secondary-Side of Safety Isolation Barrier (cont.)
PS Pin
PS Pin Remote-OFF
IPS(REM-) -26 -22 -17 µA
Threshold

PS Pin Remote-ON
IPS(REM+) -47 -40 -33 µA
Threshold

PS Pin Remote ON-OFF

IPS(REM)(HYST) 18 µA
Hysteresis

PS Pin Remote-OFF
VPS(REM-) See Note A 0.85 V
Voltage

PS Pin Remote-ON
VPS(REM+) See Note A 0.85 V
Voltage

PS Pin Selection0
RPS(SEL0) Required Resistor 1% E96 Series 75 kW
Resistor

PS Pin Selection1
RPS(SEL1) Required Resistor 1% E96 Series 75 kW
Resistor

PS Pin Selection2
RPS(SEL2) Required Resistor 1% E96 Series 75 kW
Resistor

PS Pin Selection3
RPS(SEL3) Required Resistor 1% E96 Series 169 kW
Resistor

PS Pin Selection4
RPS(SEL4) Required Resistor 1% E96 Series 169 kW
Resistor

PS Pin Selection5
RPS(SEL5) Required Resistor 1% E96 Series 255 kW
Resistor

PS Pin Selection6
RPS(SEL6) Required Resistor 1% E96 Series 340 kW
Resistor

PS Pin Selection7
RPS(SEL7) Required Resistor 1% E96 Series 499 kW
Resistor
G1 and G2 Pins
G1, G2 Clamp Voltage VG1(CLMP) LSR2000C
BPS = 15 V 10.3 11.7 13.5 V
(Freq 0,1) VG2(CLMP) H001,H002

G1, G2 Clamp Voltage VG1(CLMP) LSR2000C

BPS = 15 V 5.0 6.0 7.0 V
(Freq 2,3) VG2(CLMP) H003,H004,H005

VG1(CLMP)(DROP) BPS = 15 V
G1, G2 BP Voltage Drop 0.65 1.1 1.5 V
VG2(CLMP)(DROP) See Note A

IG1(SOURCE)
G1, G2 Source Current BPS = 15 V, VG1 = VG2 = 0 V 0.65 1.1 1.5 A
IG2(SOURCE)

IG1(SINK)
G1, G2 Sink Current BPS = 15 V, VG1 = VG2 = VG1(CLMP) 1.6 2 2.2 A
IG2(SINK)

28
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 HiperLCS-2

Conditions
BPS = 12 V
Parameter Symbol Min Typ Max Units
TJ = 0 °C to 100 °C
(Unless Otherwise Specified)
Secondary-Side of Safety Isolation Barrier (cont.)
D1 and D2 Pin
D1, D2 Breakdown
BVD1D2 150 V
Voltage

Recommended external R between SR FET

D1, D2 External Resistor RD1D2(EXT) 200 1500 W
Drain and D1, D2 pin

D1, D2 Inverse Current ID1D2(INV) Allowed current out of D1, D2 when below GND -5 mA
D1, D2 SR On Threshold VD1D2ON(TH) See Note E -275 -250 -210 mV

D1, D2 SR Off Threshold VD1D2OFF(TH) See Note E 3 8.5 12.5 mV

D1, D2 SR Off Threshold

∆VD1D2OFF -2.6 0 2.6 mV
Matching

D1, D2 Ouput Bias

ID1D2OFF Bias Current Out of D1, D2 at VD1D2OFF(TH) -17 -13 -9 mA
Current ‒ Off
Secondary Control Over-Temperature
Secondary Control
SC(OT)(STOP) See Note A 123 130 137 °C
Over-Temperature Stop

Secondary Control
SC(OT)(START) See Note A 75 °C
Over-Temperature Start
Primary-Side of Safety Isolation Barrier
5VL Pin
5VL Power-Up
V5VL(UV+) C5VL = 1 mF / 10 V Ceramic 3 3.5 4 V
Threshold

5VL Power-Up
V5VL(HYST) C5VL = 1 mF / 10 V Ceramic 1.5 V
Hysteresis
FL Pin
FL - Logic 1 Output
VFL(1) IFL = 10 mA, 5VL = 5 V 4.55 4.7 4.929 V
Voltage

FL - Logic 0 Output
VFL(0) IFL = +10 mA 0.17 0.25 0.42 V
Voltage

NOTES:
A. Not tested parameter. Guaranteed by design.
B. In typical LLC application circuit.
C. Normally limited by internal circuitry.
D. Not tested parameter. Based on device characterization.
E. Production test limits. Observed operational threshold for SR MOSFET drain (D1, D2), also depends on chosen
D1, D2 resistors RD1D2(EXT) values.

29
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 InSOP-24C

0.50 Ref. 3 4 0.20 Ref.

2.71

www.power.com
3.35 Ref.
2.59
5 Lead Tips
DETAIL A
2X 24 13 0.15 C
0.10 C B

2.06 Ref. 0.29 Ref.

3.05 Ref.
7
HiperLCS-2

2
10.80 13.63 5.69 Ref.
4.70 Ref.

3.00 Ref.
0.28 Ref.
0.65 Ref. 0.65 Ref.
3.20 Ref. 3.20 Ref.

0.25 H
1 12 0.15 C 0.45 Ref.
12 Lead Tips 2
Gauge
Pin #1 I.D. 3 4 A 9.40 Plane
0.30
16X Seating Plane
0.75 0.20
2X 0.10 C A 0.76 C
0.25 M C A B 0° – 8° Ref. 0.15
0.81 0.00
0.51 Standoff
TOP VIEW BOTTOM VIEW

1.60 Max. 1.42 Ref.

Total Mounting Height 3
Detail A 0.30
17X 11.34
0.18
3.42 5.49 2.43

Seating 1 24
Plane CL
C
1.45 0.10 C
0.75 2.40
1.25 Coplanarity: 17 Leads
3.19
Body Thickness
4.80

SIDE VIEW END VIEW 1.65 3.30 6.75

7.50
8.25 CL 8.25

1.65

Notes:
1. Dimensioning and Tolerancing per ASME Y14.5M – 1994.
2.40
0.41
2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive
of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch
between the top and bottom of the plastic body. Maximum mold protrusion is 0.18 mm per side. 12 13
1.58 1.58
3. Dimensions noted are inclusive of plating thickness. 3.42 4.50 3.42

4. Does not include inter-lead flash or protrusions. Note: The PCB footprint shown is the minimum recommended layout for basic thermal, mechanical
and electrical interconnect, including package-to-PCB creepage. Modifications are expected, based on
5. Dimensions in millimeters. application-specific requirements, to add copper areas for improved thermal performance or reduce
for increased on-PCB creepage.
6. Datums A & B to be determined at Datum H.

7. Exposed pad size and location dimensions are for reference only. PCB PAD LAYOUT

30
POD_inSOP-24C_B_031417

Rev. E 07/23
PI-8294-051619
 InSOP-24D

3 4
0.50 [0.020] Ref. 0.20 [0.008] Ref.
2.71 0.107

www.power.com
3.35 [0.132] Ref. 2.59 0.102
5 Lead Tips
2X 24 13 0.15 [0.006] C
0.10 [0.004] C B

0.25 [0.010] H 0.45 [0.018]

Ref.
HiperLCS-2

2
Gauge
10.80 [0.425] 13.43 [0.529] Plane
Seating Plane
C
0° – 8°
0.25 0.010
0.81 0.032 0.10 0.004
0.51 0.020
Standoff
1 12 0.15 [0.006] C
12 Lead Tips 2
Pin #1 I.D. 3 4 A 9.40 [0.370]
DETAIL A
0.30 0.012 16X
0.75 [0.030] 0.20 0.008
2X 0.10 [0.004] C A
0.25 [0.010] M C A B

TOP VIEW BOTTOM VIEW 6.75 8.25

[0.266] [0.325]

4.80 7.50
[0.189] [0.295]
0.75
12.72
[0.030]
[0.501]

8.25
1.60 [0.063] Max. 1.32 [0.052] Ref. 2.81
[0.325]
Total Mounting Height [0.111]
0.41
Detail A [0.016]

Seating
Plane
C 3 1.58 1.58
0.30 0.012 [0.062] [0.062]
1.45 0.057
0.10 [0.004] C 0.18 0.007
1.25 0.049
Coplanarity: 17 Leads 17X
Body Thickness

SIDE VIEW END VIEW PCB PAD LAYOUT

Notes:
1. Dimensioning and Tolerancing per ASME Y14.5M – 1994.
2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash,
but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.18 [0.007] per side.

3. Dimensions noted are inclusive of plating thickness.

4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in millimeters [inches].

31
6. Datums A & B to be determined at Datum H. PI-8106-052620
POD-InSOP-24D Rev C

Rev. E 07/23
POD_inSOP-24D_C_052920
 HiperLCS-2

PACKAGE MARKING

InSOP-24C

LCS7265C C
01M7C151A D

A
1815 B

A. Power Integrations Registered Trademark

B. Assembly Date Code (last two digits of year followed by 2-digit work week)
C. Product Identification (Part #/Package Type)
D. Lot Identification Code
PI-9310-021121

Part Ordering Information

• HiperLCS Product Family

• LCS HB Series Number
• Package Identifier
C InSOP-24C
• Tape & Reel and Other Options
LCS 7265 C - TL TL Tape and Reel, 2 k pcs for C Package.

32
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 HiperLCS-2

PACKAGE MARKING

InSOP-24D

LSR2000C C
01M7C151A D

A
1815 B
E H001 F

A. Power Integrations Registered Trademark

B. Assembly Date Code (last two digits of year followed by 2-digit work week)
C. Product Identification (Part #/Package Type)
D. Lot Identification Code
E. Pin 1 Indicator
F. Features Code
PI-9311-021621

Part Ordering Information

• HiperLCS Product Family

• LCS SR Series Number
• Package Identifier
C InSOP-24D
• Features Code
• Tape & Reel and Other Options
LSR 2000 C - H001 - TL TL Tape & Reel, 2 k pcs per reel.

33
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 HiperLCS-2

Feature Code Frequency Range Nominal Frequency Burst Mode

H001 0 90 kHz See Table 6

H002 1 120 kHz See Table 6

H003 2 180 kHz See Table 6

H004 3 240 kHz See Table 6

H005 3 240 kHz <2%

MSL Table

Part Number MSL Rating

LCS7260C 3
LCS7262C 3
LCS7265C 3
LSR2000C 3

34
www.power.com Rev. E 07/23
 Revision Notes Date
B Production release. 03/21
C Updates. 03/22
D Updates including adding error codes. 11/22
E Added H005 codes. 07/23

For the latest updates, visit our website: www.power.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at www.power.com/ip.htm.
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POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

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failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.

Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperLCS, HiperPLC,
HiperPFS, HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI,
PI Expert, PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are
property of their respective companies. ©2022, Power Integrations, Inc.

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