VHDL

Very High Speed Integrated

Circuits
Hardware Description Language
DIGITAL SYSTEMS DESIGN
 • To describe VHDL language programming
• To describe CAD tools for digital system design
• To describe hardware description languages
• To provide a history of hardware description
languages
• To define VHDL
OBJECTIVES • To describe the VHDL programming structure
• To define ENTITY
• To define ARCHITECTURE
• To describe VHDL data types
• To describe VHDL operators
• To describe Subcircuit design
CAD TOOL–BASED
LOGIC DESIGN
• Digital integrated circuits perform highly
complex functions.
• Nearly impossible without CAD (computer-
aided design) tools:
• design entry
• simulation
• synthesis and optimization
• physical design
CAD TOOL–BASED LOGIC DESIGN
• Design entry:

Write, synthesize, optimize, and generate the circuit implementation.

CAD TOOL–BASED LOGIC DESIGN
• Simulation (functional/behavioral and timing):

For simulation, the user has to supply to the simulator “test vectors” for the inputs and
expected outputs.
CAD TOOL–BASED LOGIC DESIGN
• Synthesis :

A synthesis tool is used to translate the design described in a design entry method (usually, a program
in VHDL or Verilog) into a physically realizable circuit. The same tool is also used to optimize the
circuit.
CAD TOOL–BASED LOGIC DESIGN
• Place and Route (P&R) :

P&R, also known as the physical design phase, is where the gates are placed and interconnected (routing) to complete the
circuit.
 • An HDL (Language Description Language) is a
formal design tool

• Used to describe behaviour or structure (RTL or

gate level) of digital circuits (ICs) using a textual
approach.

What is HDL? • Using an HDL a designer can describe the operation

of a system at different levels of abstractions:
• What the system will do? (Behavior)
• How will the system do it? (Algorithmic)
• With what will do it (data flow and structural)
 Describe processes and events that
occur in a concurrent fashion

CHARACTERISTICS Allows a hierarchical structure of

OF AN HDL a design, combining modules
described by different abstractions.

Allows to model the concept of

TIME.
ADVANTAGES OF AN HDL
• SPECIFICATION TOOL:
• Used to describe the general specification of a system at both, hardware and software levels
• Used to describe hardware, at system, subsystem and componet levels,
• DESIGN TOOL
• Documentation
• Code reuse
• Parametrization
• Portability
• Techonology independent.
• SIMULATION TOOL
• Aviability of component models in vendor libraries
• Allows the generation of complex testbeches and test vectors.
What HLDs are available?
• Low Level: circuit architecture (DFFs, gates, logics ecuastions)
• PALASM, CUPL, ABEL

• Medium Level: hierachical design, iterative conditional (arithmetic

functions, FSM)
• AHDL (ALTERA Hardware Description Language)

• High Level: allows simulation, higher level of abstraction

• VHDL, VERILOG
WARNING:
Does it
works?
Verilog
• Standard IEEE 1364-1995
• Updated in Verilog-2001
• Used in the design and
verification of digital circuits
at the register-transfer level
(RTL) of abstraction
• Syntax similar to C.
• Design hierarchy
VHDL
• VHSIC Hardware Description Language
• VHSIC : Very High Speed Integrated Circuits
• IEEE standard 1076-1987
• Created by the USA’s Defense Department to document ASIC
design.
• Updated in 1993 (VHDL’93)
• Allows description at high level of abstraction (behavior) or at
low level (RTL and Gate level)
• Case Insensitive.
• 97 reserved keywords:
• abs, access, after, alias, all, and, architecture, array,
assert, attribute, begin, block, body,...,wait, when, while,
with, xnor, xor
Levels of abstraction
• Behavioral: details I/O function of the design. Does
not takes into the architecture, i.e. registers, gates,
etc.
• Algorithmic: describes actions to do, as in a SW
algorithm.
• Data Path: Sequential machine, registers and glue
logic, i.e. architecture
• Register Transfer Level (RTL): describes a network
of gates and registers interconnected.
• Gate level: describes a network of logic gates (logic
equations.
Example :
a
AND c
b
ENTITY example_1

e d

• Port IN can be read (signal_x <= portA_input). Cannot be

modiffied (portA_input <= signal_x)
• Port OUT can be assigned (portC_output <= signal_x).
Cannot be read (signal_x <= portC_output )
• Port BUFFER is an always open output, can be read and
assigned.
• Port INOUT is a bidirectional port (tri-state). Can be read
and modified.
Example :
a a
AND c c
AND
b b
ENTITY example_1

e d e d
ARCHITECTURE
Example: Gate Level Design
ONE-bit comparator

𝑒𝑞 𝑖0 · 𝑖1 𝑖0 · 𝑖1
Example: Gate Level Design
ONE-bit comparator
Example: Gate Level Design
ONE-bit comparator
-- Comment

-- Comment
Example: Gate Level Design
ONE-bit comparator

Calls std_logic_1164 package from ieee library.

ENTITY: Defines I/O ports

and parameters

ARCHITECTURE: Defines
the functionality of a
circuit.
Example: Gate Level Design
ONE-bit comparator

<name> : <IN/OUT> <type>;

SIGNAL <name> : <type> [:= <expression>];

Label:
Example: Gate Level Design
ONE-bit comparator

Designed Circuit

Quartus Generated Circuit

 • VHDL  strongly typed language.
• STD_LOGIC defined in the std_logic_1164
package.
• Values: ‘1’, ‘0’, ’Z’
STD_LOGIC • 'U'  "uninitialized" ; 'X'  "unknown“ (for
simulation)
type • ' - ' , 'H', 'L' 'W'  Out of scope of the course
• std_logic_vector used to define signals with
multiple bits.
• A : IN STD_LOGIC_VECTOR( 7 DOWNTO 0);
• B : OUT STD_LOGIC_VECTOR(0 TO 7);
LOGIC
OPERATORS
• Defined in std_logic_1164 package:
• NOT
• AND
• OR
• XOR
• Only work for STD_LOGIC_VECTOR y STD-LOGIC.
• For STD_LOGIC_VECTOR it works bit-to-bit.
• It is implemented using the Look-up tables of the
logic elements of the device.
LOGIC OPERATORS
RELATIONAL OPERATORS
 HIERARCHICAL DESIGN

• How to instantiate a component using

VHDL-93 format:

labelname: ENTITY work.entityName(architectureName)

GENERIC MAP (generic_association_list)
PORT MAP (port_association_list);

Image from: https://resources.altium.com/p/flat-vs-hierarchical-schematics-why-you-need-dynamic-schematic-compilation

EXAMPLE : TWO-bit comparator

Take the previous designed code for a oneBitEquality:

Pay attention
to the port
declaration
EXAMPLE : TWO-bit comparator
EXAMPLE : TWO-bit comparator

Vectors

Referring to an individual bit from a vector vectorName(i)

idem
EXAMPLE : TWO-bit comparator

ENTITY declaration in
OneBitEquality

Component instantiation
in twoBitEquality
Testbench
• Simulation is the ONLY tool for debugging complex digital
systems.
• Digital simulators are discrete event simulators:
• To model the states of inputs and outputs along time
looking for events that change such states
• A event can generate new events, either in now or in
the future.
• While no events occur, the system does not change.
Testbench
After a circuit is generated, it can be simulated to
verify the correctness of the circuit operation and
can be synthesized to a physical device.

We create a special program, known as a

testbench, to mimic a all possible conditions (input
test vectors).

Code generated for simulation usually is not

synthesizable
 • Testbench program must have an empty ENTITY, i.e. no
ports declared.
Testbench: Two Models • *DUT: Design Under Test
• *BIST: Built-In Self Test
 Testbench: PROCESS statement
• To facilitate system modeling, VHDL contains a number of sequential
statements, which are executed in sequence:
• A black box whose behavior is described by sequential statements.
• Encapsulated inside a PROCESS.
• A PROCESS itself is a concurrent statement.
[label:] PROCESS (sensitivity list)
[VARIABLE name TYPE [range] [:= initial_value;]]
BEGIN
(sequential code)
END PROCESS [label];

Note: The PROCESS statement will be discussed in depth further in the course. At this point the
statement is needed to generate test vectors in the creation of comprehensive testbenches.
Testbench: WAIT FOR and AFTER statements
• WAIT FOR time;  Only used inside a process

• WAIT FOR 200 ns;

• signal_name <= expression AFTER delay;

• q <= d AFTER 10 ns;

Modelling events: