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ARMCortex Interrupt

The document discusses the Nested Vectored Interrupt Controller (NVIC) which handles exceptions and interrupts in the ARM Cortex M4 microcontroller. It describes the NVIC's sequence of operations when an interrupt occurs, including pushing registers to the stack, running the interrupt service routine, and restoring registers. It also categorizes interrupts as hardware or software-related and as maskable or non-maskable.

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10 views

ARMCortex Interrupt

The document discusses the Nested Vectored Interrupt Controller (NVIC) which handles exceptions and interrupts in the ARM Cortex M4 microcontroller. It describes the NVIC's sequence of operations when an interrupt occurs, including pushing registers to the stack, running the interrupt service routine, and restoring registers. It also categorizes interrupts as hardware or software-related and as maskable or non-maskable.

Uploaded by

21l106
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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ARM Cortex M4

Dr. K. Vasanthamani
Nested Vectored Interrupt Controller
(NVIC)
• Control unit that is embedded inside the Cortex-M4 MCU
• Used to handle and pre-process all exceptions and interrupts
(maskable and unmaskable) during the normal running of
application codes
NVIC - Sequence of Operation
• 1. An exception or interrupt is first created by an interrupt source,
and an interrupt-service request is sent to the Cortex-M4 CPU.
• 2. CPU will determine whether to response or process the interrupt
request based on the mask register’s content and the interrupt
priority level.
• 3. If the interrupt request is accepted, the associated hardware will
provide interrupt-related information, such as the interrupt source
and related Interrupt Service Routine (ISR) entry point, in a Vector
Table format.
• 4. Before the control can be transferred to the ISR, all related
registers, including R0–R3, R12, LR, PSR, and PC, are pushed into
the stack to reserve their contents.
• During this protection process, all other interrupts or exceptions are masked
or disabled to avoid any data to be lost.
NVIC - Sequence of Operation
• 5. Then the control will be directed to the entry point (entry
address of the ISR) to run the ISR to perform the required
interrupt service.
• During this process, all other interrupts and exceptions are unmasked
or enabled to allow higher-level-priority interrupts or exceptions to be
requested and responded.
• 6. After the ISR is done and before the control can be
transferred back to the main program,
• (a) all other interrupts or exceptions are masked or disabled to avoid
any data to be lost and
• (b) all related registers protected in step 4, including the PC, will be
recovered by popping them back to the related registers.
NVIC - Sequence of Operation
• 7. Then the control can be directed to the main program to
continue executing the normal application codes based on the
old PC content.
• At this time, all interrupts and exceptions are unmasked or enabled to
allow any interrupt or exception to be requested and responded
NVIC - Properties
• The exception and interrupt can be categorized to hardware-related
exceptions/interrupts or software-related exceptions/interrupts.
• For example, the watchdog timer and voltage monitor belong to hardware-
related interrupts, but the divided-by-zero is a software-related exception.
• The interrupt requests can be divided into two categories: Maskable
IRQs and Non-Maskable Interrupt (NMI) request.
• If a mapping relationship between the exception numbers and
interrupt request numbers IRQs is made, all exception numbers
would be negative ( 1 to 14) since the interrupt request number
(IRQs) starts from 0
NVIC

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