Unit-3

Combinational Logic Design

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Combinational Logic Gates
CMOS Inverter (NOT) Gate

Figure (a) Symbol for inverter; (b) truth table of inverter; (c)
CMOS realization of inverter

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Two-input NAND Gate
To illustrate the design methodology, let us consider a simple example of a two-input NAND gate design. The
two-input NAND function is expressed by

Step 1: Take complement of Y

Step 2: Design the PDN

In this case, there is only one AND term. So there will be two nMOSFETs in series, as shown in Fig.
Step 3: Design the PUN

In PUN, there will be two pMOSFETs in parallel, as shown in Fig.

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Two-input NAND gate: (a) symbol; (b) truth table; (c) CMOS realization

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Two-Input NOR Gate

Pull-down network comprising nMOSFETs and Pull-up network comprising pMOSFETs.

Two-input NOR gate: (a) symbol; (b) truth table; (c) CMOS realization
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Design of Complex Logic Circuit

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AOI gate realization using CMOS logic OAI gate realization using CMOS logic
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MOS Logic Circuits with Depletion nMOS Loads

A two-input depletion-load NOR gate, its logic symbol, and the corresponding truth table.
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Calculation of VOH
When both input voltages VA and VB are lower than the corresponding driver threshold voltage, the driver
transistors are turned off and conduct no drain current. Consequently, the load device, which operates in the
linear region, also has zero drain current. In particular, its linear region equation becomes

Eq. 1

The solution of this equation gives VOH = VDD.

Calculation of VOL
To calculate the output low voltage VOL, we must consider three different cases, i.e., three
different input voltage combinations, which produce a conducting path from the output
node to the ground. These cases are

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For the first two cases, (i) and (ii), the NOR circuit reduces to a simple nMOS depletion load inverter. Assuming that
the threshold voltages of the two enhancement-type driver transistors are identical (VT0,A= VT0,B = VT0.), the driver-to-
load ratio of the corresponding inverter can be found as follows. In case (i), where the driver transistor A is on, the ratio
is
Eq. 2

In case (ii), where the driver transistor B is on, the ratio is

Eq. 3

The output low voltage level VOL in both cases is found as follows:
Eq. 4

Note that if the (WIL) ratios of both drivers are identical, i.e., (W/L)A =(WIL)B the output low voltage (VOL) values
calculated for case (i) and case (ii) will be identical.

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In case (iii), where both driver transistors are turned on, the saturated load current is the sum of the two linear-
mode driver currents.
Eq. 5

Eq. 6

Since the gate voltages of both driver transistors are equal (VA =VB =VOH), we can devise an equivalent driver-
to-load ratio for the NOR structure:

Eq. 7

Thus, the NOR gate with both of its inputs tied to a logic-high voltage is replaced with an nMOS depletion-load
inverter circuit with the driver-to-load ratio given by Eq. 7. The output voltage level in this case is

Eq. 8

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Generalized NOR Structure with Multiple Inputs
Note that the combined current ID in this circuit is supplied by the driver transistors which are turned on, i.e.,
transistors which have gate voltages higher than the threshold voltage VT0.

Generalized n-input NOR gate. Equivalent inverter circuit corresponding to the n-input NOR gate.
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the multiple-input NOR gate can also be reduced to an equivalent inverter, shown in Fig., for static analysis. The
(W/L) ratio of the driver transistor here is

The source terminals of all enhancement-type nMOS driver transistors in the NOR gate are connected to ground.
Thus, the drivers do not experience any substrate-bias effect. The depletion-type nMOS load transistor, however,
is subject to substrate-bias effect, since its source is connected to the output node, and its source-to-substrate
voltage is VSB= Vout.

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Transient Analysis of NOR Gate
Figure shows the two-input NOR (NOR2) gate with all of its relevant parasitic device capacitances. As in the
inverter case, we can combine the capacitances seen in Fig. into one lumped capacitance, connected between the
output node and the ground. The value of this combined load capacitance, Cload, can be found as

Parasitic device capacitances in the NOR2 gate and the lumped equivalent load capacitance. The gate-to-source
capacitances of the driver transistors are included in the load of the previous stages driving the inputs A and B.
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Two-Input NAND Gate

A two-input depletion-load NAND gate, its logic symbol, and the corresponding truth table. Notice the
substrate-bias effect for all nMOS transistors except one.

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Generalized NAND Structure with Multiple Inputs
N series-connected driver transistors, as shown in Fig. . Neglecting the substrate bias effect, and assuming that
the threshold voltages of all transistors are equal to V., the driver current ID in the linear region can be derived as
in Eq. whereas ID in saturation is taken as its extension.

Hence, the (WIL) ratio of the equivalent driver transistor is

If the series-connected transistors are identical, i.e., (W/L), =

(W/L) 2 =.. . = (WIL), the width-to-length ratio of the equivalent
transistor becomes

The generalized NAND structure and its inverter equivalent.

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Transient Analysis of NAND Gate
Assume, for example, that the input VA is equal to VOH and the other
input VB is switching from VOH to VOL. In this case, both the output
voltage Vout, and the internal node voltage Vx will rise, resulting in

Now consider another case where VB is equal to VOH and VA switches from
VOH to VOL. In this case, the output voltage Vout, will rise, but the internal
node voltage Vx, will remain low because the bottom driver transistor is on.
Thus, the lumped output capacitance is

Parasitic device capacitances in the NAND2 gate.

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 CMOS Logic Circuits
CMOS NOR2 (Two-Input NOR) Gate
The switching threshold of the CMOS inverter is equal
to VDD/2. Using the same parameters, the switching
threshold of the NOR2 gate is

A CMOS NOR2 gate and its complementary operation: Either the nMOS network
is on and the pMOS network is off, or the pMOS network is on and the nMOS network is off.
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The switching threshold voltage of the NOR2 gate can also be obtained by using the equivalent-inverter
approach. When both inputs are identical, the parallel-connected nMOS transistors can be represented by a
single nMOS transistor with 2kn. Similarly, the series-connected pMOS transistors are represented by a single
pMOS transistor with kP/2. The resulting equivalent CMOS inverter is shown in Fig.

For the equivalent inverter circuit, we obtain

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CMOS NAND2 (Two-Input NAND) Gate
The switching threshold for this gate is then found as

Parasitic device capacitances of the CMOS

equivalent with the lumped output load
capacitance. NOR2 circuit and the simplified

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Layout of Simple CMOS Logic Gates

Sample layout of the CMOS NOR2 gate. Sample layout of the CMOS NAND2 gate.

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Stick Diagram of CMOS NOR2 Gate

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Complex Logic Circuits
For the analysis and design of complex logic gates, we can
employ the equivalent inverter approach already used for the
simpler NOR and NAND gates. It can be shown for the circuit
in Fig. that, if all input variables are logic-high, the equivalent-
driver W/L ratio of the pull-down network consisting of five
nMOS transistors is

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A complex CMOS logic gate realizing the Boolean function

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Full-CMOS implementation of the XOR function.

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AOI and OAI Gates
The AND-OR-INVERT (AOI) gate, enables the sum-of-products realization of a Boolean
function in one logic stage. The pull-down net of the AOI gate consists of parallel branches of series-
connected nMOS driver transistors. The corresponding p-type pull-up network can simply be found
using the dual-graph concept.

The OR-AND-INVERT (OAI) gate, on the other hand, enables the product-of-sums realization of a
Boolean function in one logic stage. The pull-down net of the OAI gate consists of series branches of
parallel-connected nMOS driver transistors, while the corresponding p-type pull-up network can be
found using the dual-graph concept.

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An AND-OR-INVERT (AOI) gate and the corresponding pull-down net

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An OR-AND-INVERT (OAI) gate, and the corresponding pull-down net

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Ratioed Logic
Ratioed logic is an attempt to reduce the number of transistors required to implement a given logic function, at the
cost of reduced robustness and extra power dissipation

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Pseudo-nMOS Gates
The large area requirements of complex CMOS gates present
a problem in high-density designs, since two complementary
transistors, one nMOS and one pMOS, are needed for every
input. One possible approach to reduce the number of
transistors is to use a single pMOS transistor, with its gate
terminal connected to ground, as the load device.
The most significant disadvantage of using a pseudo-nMOS
gate instead of a full CMOS gate is the nonzero static power
dissipation, since the always-on pMOS load device conducts a
steady-state current when the output voltage is lower than
VDD. Also, the value of VOL and the noise margins are now
determined by the ratio of the pMOS load transconductance to
the pull-down or driver transconductance.

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CMOS Full-Adder Circuit
The sum_out and carry_out signals of the full adder are defined as the following two combinational Boolean
functions of the three input variables, A, B, and C.

Gate-level schematic of the one-bit full-adder circuit.

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Transistor-level schematic of the one-bit full-adder circuit.

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CMOS Transmission Gates (Pass Gates)

Four different representations of the CMOS transmission gate (TG).

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Bias conditions and operating regions of the CMOS transmission gate, shown as functions of the output voltage.

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Two-input multiplexor circuit implemented using two CMOS Eight-transistor CMOS TG implementation of the XOR
TGs. function.

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Six-transistor CMOS TG implementation of the XOR function. CMOS TG realization of a three-variable Boolean function.

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Pass-Transistor Logic
Pass-transistor logic attempts to reduce the number of transistors required to implement logic by allowing the primary
inputs to drive gate terminals as well as source/drain terminals.

Pass-transistor implementation of an
AND gate

pass-transistor gates cannot be cascaded by connecting the output of a pass gate to the gate input of another pass
transistor

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Complementary Pass-Transistor Logic (CPL)
• CPL is to use a pure nMOS pass-transistor network for the logic operations.
• All inputs are applied in complementary form
• The circuit also produces complementary outputs, to be used by subsequent CPL stages.
• Reduces the parasitic capacitances
• Increased process complexity

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CPL NAND and NOR Gate

Circuit diagram of (a) CPL NAND2 gate and (b) CPL NOR2 gate.

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CPL-based XOR gate

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CPL full adder

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How to Build Even Better Loads
It is possible to create a ratioed logic style that completely eliminates static currents and provides rail-
to-rail swing. Such a gate combines two concepts: differential logic and positive feedback. A
differential gate requires that each input is provided in complementary format, and produces
complementary outputs in turn. The feedback mechanism ensures that the load device is turned off
when not needed. A example of such a logic family, called Differential Cascode Voltage Switch Logic
(or DCVSL), is presented.

DCVSL logic gate

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In addition to the problem of increase complexity in design, this circuit style still has a power-dissipation
problem that is due to cross-over currents. During the transition, there is a period of time when PMOS and PDN
are turned on simultaneously, producing a short circuit path.

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Dynamic CMOS Design
An alternate logic style called dynamic logic is presented that obtains a similar result, while avoiding static
power consumption. With the addition of a clock input, it uses a sequence of precharge and conditional
evaluation phases.
Dynamic Logic: Basic Principles
The PDN (pull-down network) is constructed
exactly as in complementary CMOS. The
operation of this circuit is divided into two
major phases: precharge and evaluation, with
the mode of operation determined by the
clock signal CLK.

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Precharge
When CLK = 0, the output node Out is precharged to VDD by the PMOS transistor Mp. During that
time, the evaluate NMOS transistor Me is off, so that the pull-down path is disabled. The evaluation
FET eliminates any static power that would be consumed during the precharge period (this is, static
current would flow between the supplies if both the pulldown and the precharge device were turned
on simultaneously).
Evaluation
For CLK = 1, the precharge transistor Mp is off, and the evaluation transistor Me is turned on. The
output is conditionally discharged based on the input values and the pull-down topology. If the inputs
are such that the PDN conducts, then a low resistance path exists between Out and GND and the
output is discharged to GND. If the PDN is turned off, the precharged value remains stored on the
output capacitance CL, which is a combination of junction capacitances, the wiring capacitance, and
the input capacitance of the fan-out gates. During the evaluation phase, the only possible path
between the output node and a supply rail is to GND. Consequently, once Out is discharged, it cannot
be charged again till then next precharge operation. The inputs to the gate can therefore make at most
one transition during evaluation. Notice that the output can be in the high-impedance state during
the evaluation period if the pull-down network is turned off. This behavior is fundamentally different
from the static counterpart that always has a low resistance path between the output and one of the
power rails.

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As an example, consider the circuit shown in Figure b. During the precharge phase
(CLK=0), the output is precharged to VDD regardless of the input values since the
evaluation device is turned off. During evaluation (CLK=1), a conducting path is
created between Out and GND if (and only if) A·B+C is TRUE. Otherwise, the
output remains at the precharged state of VDD. The following function is thus
realized:

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A number of important properties can be derived for the dynamic logic gate:
• The logic function is implemented by the NMOS pull-down network. The construction of the PDN
proceeds just as it does for static CMOS.
• The number of transistors (for complex gates) is substantially lower than in the
static case: N + 2 versus 2N.

• It is non-ratioed. The sizing of the PMOS precharge device is not important for realizing proper
functionality of the gate. The size of the precharge device can be made large to improve the low-to-high
transition time (of course, at a cost to the high-to low transition time). There is however, a trade-off with
power dissipation since a larger precharge device directly increases clock-power dissipation.

• It only consumes dynamic power. Ideally, no static current path ever exists between VDD and GND. The
overall power dissipation, however, can be significantly higher compared to a static logic gate.

• The logic gates have faster switching speeds. There are two main reasons for this. The first (obvious)
reason is due to the reduced load capacitance attributed to the lower number of transistors per gate and the
single-transistor load per fan-in. Second, the dynamic gate does not have short circuit current, and all the
current provided by the pull-down devices goes towards discharging the load capacitance.

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Speed and Power Dissipation of Dynamic Logic
The main advantages of dynamic logic are increased speed and reduced implementation area. Fewer devices to
implement a given logic function implies that the overall load capacitance is much smaller.
After the precharge phase, the output is high. For a low input signal, no additional switching occurs. As a result,
tpLH = 0! The high-to-low transition, on the other hand, requires the discharging of the output capacitance
through the pull-down network. Therefore tpHL is proportional to CL and the current-sinking capabilities of the
pull-down network.
The presence of the evaluation transistor slows the gate somewhat, as it presents an extra series resistance.
Omitting this transistor, while functionally not forbidden, may result in static power dissipation and potentially a
performance loss.

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Issues in Dynamic Design
Charge Leakage
The operation of a dynamic gate relies on the dynamic storage of the output value on a capacitor. If the pull-down network is
off, the output should ideally remain at the precharged state of VDD during the evaluation phase. However, this charge
gradually leaks away due to leakage currents, eventually resulting in a malfunctioning of the gate. Figure a shows the sources
of leakage for the basic dynamic inverter circuit.

Leakage issues in dynamic circuits.

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Dynamic circuits therefore require a minimal clock rate, which is typically on the order of a few kHz. This
makes the usage of dynamic techniques unattractive for low performance products such as watches, or
processors that use conditional clocks.
Leakage is caused by the high impedance state of the output node during the evaluate mode, when the pull down
path is turned off. The leakage problem can be counteracted by reducing the output impedance on the output
node during evaluation. This is often done by adding a bleeder transistor as shown in Figure. The only function
of the bleeder—a pseudo-NMOS-like pull-up device—is to compensate for the charge lost due
to the pull-down leakage paths.

Static bleeders
compensates for the charge-
leakage

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Charge Sharing
During the precharge phase, the output node is precharged to VDD.
Assume that all inputs are set to 0 during precharge, and that the capacitance Ca is
discharged. Assume further that input B remains at 0 during evaluation, while input A
makes a 0 to 1 transition, turning transistor Ma on. The charge stored originally on
capacitor CL is redistributed over CL and Ca. This causes a drop in the output voltage,
which cannot be recovered due to the dynamic nature of the circuit.

The influence on the output voltage is readily calculated. Under the above assumptions,
the following initial conditions are valid: Vout(t = 0) = VDD and VX(t =0) = 0. Two possible
scenarios must be considered:

1. DVout < VTn — In this case, the final value of VX equals VDD – VTn(VX). Charge
conservation yields

Eq. 1

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2. DVout > VTn — Vout and VX reach the same value:

Eq. 2

Which of the above scenarios is valid is determined by the capacitance ratio. The boundary condition between
the two cases can be determined by setting DVout equal to VTn in Eq. 2, yielding

Overall, it is desirable to keep the value of DVout below |VTp|. The output of the dynamic gate might be connected
to a static inverter, in which case the low level of Vout would cause static power consumption. One major
concern is circuit malfunction if the output voltage is brought below the switching threshold of the gate it drives.

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Capacitive Coupling
The high impedance of the output node makes the circuit very sensitive to crosstalk effects. A wire routed over a
dynamic node may couple capacitively and destroy the state of the floating node. Another equally important
form of capacitive coupling is the backgate (or output-to-input) coupling.

Example demonstrating the effect of backgate coupling.

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Clock-Feedthrough
A special case of capacitive coupling is clock-feedthrough, an effect caused by the capacitive coupling between
the clock input of the precharge device and the dynamic output node. The coupling capacitance consists of the
gate-to-drain capacitance of the precharge device, and includes both the overlap and the channel capacitances.
This capacitive coupling causes the output of the dynamic node to rise above VDD on the low-to-high transition
of the clock, assuming that the pull-down network is turned off. Subsequently, the fast rising and falling edges of
the clock couple onto the signal node.

Clock feedthrough effect.

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Cascading Dynamic Gates
There is one major catch that complicates the design of dynamic circuits: straightforward cascading of dynamic
gates to create more complex structures does not work.

Cascade of dynamic n-type blocks

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Domino Logic

DOMINO CMOS logic

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Domino CMOS has the following properties:
 Since each dynamic gate has a static inverter, only non-inverting logic can be
implemented. Although there are ways to deal with this, as is discussed in a
subsequent section, this is major limiting factor, and pure Domino design has
become rare.

 Very high speeds can be achieved: only a rising edge delay exists, while tpHL
equals zero. The inverter can be sized to match the fan-out, which is already much
smaller than in the complimentary static CMOS case, as only a single gate
capacitance has to be accounted for per fan-out gate.

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Dealing with the Non-inverting Property of Domino Logic.
A major limitation in Domino logic is that only non-inverting logic can be implemented. This requirement has
limited the widespread use of pure Domino logic.

Effect of ripple precharge when the evaluation transistor is removed. The circuit also
exhibits static power dissipation.

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There are several ways to deal with the non-inverting logic requirement. Figure shows one approach to the
problem—reorganizing the logic using simple boolean transforms such as De Morgan’s Law. Unfortunately, this
sort of optimization is not always possible, and more general schemes may have to be used.

Restructuring logic to enable implementation using non-inverting Domino Logic.

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A general but expensive approach to solving the problem is the use of differential logic. Dual-rail Domino is
similar in concept to the DCVSL structure discussed earlier, but uses a precharged load instead of a static cross-
coupled PMOS load. Figure shows the circuit schematic of an AND/NAND differential logic gate.

Simple dual rail (differential) Domino logic gate.

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Optimization of Domino Logic Gates

Multiple output Domino

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Compound Domino logic uses complex static gates at the output of the dynamic gates.

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np-CMOS
The Domino logic has the disadvantage that each dynamic gate
requires an extra static inverter in the critical path to make the
circuit functional. np-CMOS, provides an alternate approach to
cascading dynamic logic by using two flavors (n-tree and p-
tree) of dynamic logic.

np-CMOS logic exploits the duality between n-tree and p-tree

logic gates to eliminate the cascading problem.

A disadvantage of the np-CMOS logic style is that

the p-tree blocks are slower than the n-tree modules, due to the
lower current drive of the PMOS transistors in the logic
network.

The np-CMOS logic circuit style

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How to Choose a Logic Style?

Each of the circuit styles has its advantages and disadvantages. Which one to select depends upon the primary
requirement: ease of design, robustness, area, speed, or power dissipation.
The static approach has the advantage of being robust in the presence of noise. This
makes the design process rather trouble-free and amenable to a high degree of automation.
This ease-of-design does not come for free: for complex gates with a large fan-in, complementary CMOS
becomes expensive in terms of area and performance. Alternative static logic styles have therefore been devised.
Pseudo-NMOS is simple and fast at the expense of a reduced noise margin and static power dissipation. Pass-
transistor logic is attractive for the implementation of a number of specific circuits, such as multiplexers and
XOR dominated logic such as adders.

Dynamic logic, on the other hand, makes it possible to implement fast and small complex gates. This comes at a
price. Parasitic effects such as charge sharing make the design process a precarious job. Charge leakage forces a
periodic refresh, which puts a lower bound on the operating frequency of the circuit.

The current trend is towards an increased use of complementary static CMOS. This tendency is inspired by the
increased use of design-automation tools at the logic design level. These tools emphasize optimization at the
logic rather than the circuit level and put a premium on robustness. Another argument is that static CMOS is
more amenable to voltage scaling than some of the other approaches.

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Designing Logic for Reduced Supply Voltages

Voltage Scaling (VDD/VT on delay and leakage)

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Reducing the threshold voltage, increases the subthreshold leakage current exponentially.

with S the slope factor of the device. The subthreshold leakage of an inverter is the current of the NMOS for Vin
= 0V and Vout = VDD (or the PMOS current for Vin = VDD and Vout = 0).
The exponential increase in inverter leakage for decreasing thresholds illustrated in Figure b.
In short-channel MOS transistors, the sub-threshold leakage current depends not only on the gate drive (VGS) and
the body bias (VBS), but also depends on the drain voltage (VDS). The threshold voltage of a short-channel MOS
transistor decreases with increasing VDS due to drain induced barrier lowering (DIBL).

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In an inverter with In = 0, the sub-threshold leakage of the inverter is set by the NMOS transistor with its VGS =
VBS = 0 V. In more complex CMOS gates, the leakage current depends upon the input vector. For example,
the sub-threshold leakage current of a two-input NAND gate is the least when A = B = 0. Under these
conditions, the intermediate node X settles to,

The NAND gate sub-threshold leakage is then set by the top-most NMOS transistor with VGS = VBS = -VX.
Clearly, the sub-threshold leakage under this condition is slightly smaller than that of the inverter. This reduction
in sub-threshold leakage due to stacked transistors is called the stack effect. Figure shows the leakage
components for a simple two input NAND gate.

Sub-threshold leakage reduction due to stack effect in a two-input NAND gate

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Transistor Sizing

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 Problems
Q1.

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Q2.

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Q3.

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