A B C D E

1 1

Blue Moutain KIWB1/B2 2

Schematics Document
Mobile Penryn uFCPGA with Intel
3

Cantiga_GM/PM+ICH9-M core logic 3

REV:2.0

4 4

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2009/03/16 Deciphered Date 2010/03/15 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4602P
Date: Wednesday, March 18, 2009 Sheet 1 of 53
A B C D E
 A B C D E

ZZZ1
Compal confidential POWER BD Slide Bar LED X 10 (B) RIGHT BD
File Name : Power on X1 USER-DEFINED (W) VOLUME UP X1
LED X1 (G) DOLBY (W) VOLUME DOWN X1
15.6W_PCB_LA4601P
:POWER LED X 3 MUTE X1
NOVO X1 WIRELESS LED (G) MUTE LED X1(G)
VRAM 64*16 Mobile Penryn BLUETOOTH LED (G)
1
DDR3*8 3G LED (G) 1
page20
uFCPGA-478 CPU Clock Gen. HDD LED (G) USB_Board
PCI-E X16 SLG8SP556VTR
NVidia N10M-GS1 USB CONN X 2
ICS9LPRS387AKLFT POWER ON (G) TV CONN X1
page5,6,7 page25
NVidia N10P-GE1 BATTERY CHARG(G/A)
page16~24 WIRELESS SWITCH (G)
H_A#(3..35) FSB ON/OFF
H_D#(0..63) 667/800/1066MHz
Double check ME
HDMI PS8101T PCI-E DDR3-800(1.5V)
CONN
page26 DDR3-SO-DIMM X2
page26
Intel Cantiga GMCH DDR3-1067(1.5V) BANK 0, 1, 2, 3 page 14,15

CRT cable PCBGA 1329 Dual Channel UP TO 8G

LVDS I/F
page28
page 8,9,10,11,12,13
SPK amplifier 2Channel Speaker
2
page36 page37 2
LVDS
Connector page27 DMI C-Line WOOFER amplifier 1Channel Speaker
page37
page37

PCI Express AZALIA Audio Codec

6*PCI-E BUS Realtek ALC272 HP X 1+
Mini card Slot 1
page31
Intel ICH9-M 12*USB2.0
page36
MIC_Ext X1 page37
None mBGA-676
PCI Express PCI BUS 2Channel MIC_Int
4*SATA serial page36
New Card CMOS Camera
Mini card Slot 2 page31 3.3V / 33 MHz page27,28,29,30
page41
page31

PCI Express BlueTooth CONN

LPC BUS page41
Mini card Slot 3
3
page31 USB CONN X1 3

page41

BCM5906/BCM5784M
EC
ENE KB926D New Card X1
SIM Card 10/100/1G LAN page38 page31
page32
page31 Realtek 5158E
M-PCIE CONN X 3 MS/MS
page31
pro/SD/SD
RJ45 CONN Int.KBD pro/mmc/XD page36
page33 page39

Touch Pad BIOS

page39
page40 REPEATER ESATA HDD AND USB CONN
page35 page35

HDD/ODD,SCL & T/L LED on MB SATA HDD CONN

4 CAPS and NUM on KBD page35 4

SATA ODD CONN

page35
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/03/16 Deciphered Date 2010/03/ Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4602P
Date: Wednesday, March 18, 2009 Sheet 2 of 53
A B C D E
 A B C D E

DDR3 Voltage Rails

+5VS
+3VS
+1.5VS
power
plane +1.1VS SMBUS, SPI and I2C Control Table
+VCCP
1 1
+5VALW +1.5V +CPU_CORE SERIAL NEW CLK CAP Mini Mini THERMAL THERMAL
SOURCE HDMI LVDS CRT HDCP EEPROM BATT SENSOR SENSOR
+B +VGA_CORE CARD GEN sensor CARD1 CARD2 (VGA) (CPU)
+3VALW +1.8VS
+0.75V
EC_SMB_CK1
EC_SMB_DA1
KB926 X X X X X X X X X X V X X
State
EC_SMB_CK2
EC_SMB_DA2
KB926 X X X X X X X V X X X V V
ICH_SMBCLK
ICH_SMBDAT ICH9 X X X X X V V X V V X X X
LVDS_SCL
LVDS_SDA Cantiga
X V X X X X X X X X X X X
S0
O O O O GMCH_CRT_CLK
GMCH_CRT_DAT Cantiga
X X V X X X X X X X X X X
HDMICLK_NB
S3
O O O X HDMIDAT_NB Cantiga
V X X X X X X X X X X X X
2
S5 S4/AC
O O X X
VGA_DDCCLK
VGA_DDCDATA VGA X X V X X X X X X X X X X 2

S5 S4/ Battery only

O X X X
VGA_LVDS_SCL
VGA_LVDS_DAT VGA X V X X X X X X X X X X X
VGA_HDMI_SCL
S5 S4/AC & Battery
don't exist X X X X VGA_HDMI_DAT VGA
V X X X X X X X X X X X X
HDCP_SMB_CK1
HDCP_SMB_DA1 VGA X X X X V X X X X X X X X
@ FUNCTION FSEL#SPICS#_SB
FRD#SPI_SO_SB
SPI_CLK_SB ICH9 X X X X V X X X X X X X X
FWR#SPI_SI_SB

100@ (100 LAN) FSEL#SPICS#

TVSW@ (TV POWER SW) 10M@ (N10M 40nm CHIPSET)

FRD#SPI_SO
SPI_CLK
FWR#SPI_SI
KB926 X X X X V X X X X X X X X
AO@ (ALWAYS ON SW) 10P@ (N10P 40nm CHIPSET)
MONO@ (MONO MIC) PM@ (VGA BOM)
3 3
X76@ (X76 BOM) 45@ (45 BOM)
GM@ (UMA BOM)
GM45@ (GM45 BOM)
GL40@ (GL40 BOM)
BT@ WITH BLUETOOTH GIGA@ (GIGA LAN)
3G@ WITH 3G NO_TVSW@ (NON TV POWER SW)
TV@ WITH TV NO_AO@ (NON ALWAY ON SW)
ARRAY@ (ARRAY MIC)
S512@ FOR X76 BOM
Q512@ FOR X76 BOM
4
S256@ FOR X76 BOM 4

Q256@ FOR X76 BOM

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/03/16 Deciphered Date 2010/03/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4601P
Date: Wednesday, March 18, 2009 Sheet 3 of 53
A B C D E
 A B C D E

VGA and DDR3 Voltage Rails (N10x GPIO) Performance Mode P0 TDP at Tj = 102 C* (DDR3)
FBVDDQ PCI Express I/O and I/O and Other
GPIO I/O ACTIVE Function Description GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.5V) (1.5V) (6) (1.8V) (1.05V) (3.3V)
GPIO0 N/A N/A Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)

GPIO1 IN - Hot plug detect for IFP link C N10P-GS

128bit 21.07 6.67 TBD TBD 18.25 17.34 2.06 3.09 4.09 6.14 850 0.89 75 0.14 63 0.07 55 0.18
1024MB
GPIO2 OUT H Panel Back-Light brightness(PWM capable) DDR3
1 1

GPIO3 OUT H Panel Power Enable N10P-GE

128bit 20.97 6.73 TBD TBD 19.17 17.25 2.03 3.05 4.09 6.14 840 0.88 75 0.14 63 0.07 55 0.18
1024MB
GPIO4 OUT H Panel Back-Light On/Off (PWM) DDR3

GPIO5 OUT - GPU VID0 N10P-LP

128bit 15.48 6.44 TBD TBD 13.95 11.86 1.90 2.85 3.99 5.99 810 0.85 75 0.14 63 0.07 55 0.18
1024MB
GPIO6 OUT - GPU VID1 DDR3

GPIO7 OUT - GPU VID2

Performance Mode P0 TDP at Tj = 102 C* (DDR3)
GPIO8 I/O L Thermal Catastrophic Overtemp
FBVDDQ PCI Express I/O and I/O and Other
GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
GPIO9 OUT L Thermal Alert (4) (1,5) /MCLK NVVDD (1.5V) (1.5V) (6) (1.8V) (1.05V) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)
GPIO10 OUT Memory VREF switch
N10M-GE
GPIO11 I/O L SLI raster sync 64bit 13.36 2.93 TBD TBD 11.89 10.70 0.66 0.99 2.16 3.24 792 0.83 75 0.14 63 0.07 100 0.33
512MB
DDR3
GPIO12 IN - AC power detect pin
N10M-GS
2
GPIO13 OUT - MEM_VID orPower supply control 64bit 14.29 3.10 TBD TBD 11.53 11.53 0.70 1.05 2.28 3.42 817 0.86 75 0.14 63 0.07 100 0.33 2
512MB
DDR3
GPIO14 OUT - Power supply control
N10M-LP
GPIO15 IN - Hot plug detect for IFP Link E 64bit 8.28 2.91 TBD TBD 6.60 5.61 0.62 0.93 2.20 3.3 782 0.82 75 0.14 63 0.07 100 0.33
512MB
DDR3
GPIO16 OUT - Programmable Fan Control

GPIO17 IN - The ramp time for any rail must be more than 40us
Power Sequence
GPIO18 IN -

GPIO19 IN - Hot plug detect for IFP Link D

GPIO20 IN - (+3VS) VDD33

GPIO21 IN - Hot plug detect for IFP link F
PEX_VDD can ramp up any time
GPIO22 IN - SLI swap ready signal
(1.1VS) PEX_VDD
GPIO23 I/O
tNVVDD
3 3

(+VGA_CORE) NVVDD
GPIO6 GPIO5 N10M-GS N10P-GS
GPU_VID1 GPU_VID0 VGA_CORE P-State tNV-IFPAB_IOVDD
0 0 0.8V 12
0 1 0.85V 12 IFPAB_IOVDD
1 1 0.9V 0, 10
tNV-FBVDDQ

(1.8VS) FBVDDQ

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/03/16 Deciphered Date 2010/03/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4602P
Date: Wednesday, March 18, 2009 Sheet 4 of 53
A B C D E
 5 4 3 2 1

XDP Reserve
+VCCP +3VS

H_IERR# R1 1 2 56_0402_5% XDP_DBRESET# R2 1 2 @ 1K_0402_5%

H_PROCHOT# R3 1 2 56_0402_5%
+VCCP

XDP_TDI R4 1 2 54.9_0402_1%
USE->68Ω,NOT USE-->56Ω
D XDP_TMS R5 1 2 54.9_0402_1% D
CONN@
JCPU1A XDP_TDO R6 1 2 @ 54.9_0402_1%
H_A#3 J4 H1 H_ADS#
<8> H_A#[3..16] A[3]# ADS# H_ADS# <8>

ADDR GROUP_0
H_A#4 L5 E2 H_BNR# XDP_TRST# R7 1 2 54.9_0402_1%
A[4]# BNR# H_BNR# <8>
H_A#5 L4 G5 H_BPRI#
A[5]# BPRI# H_BPRI# <8>
H_A#6 K5 XDP_TCK R8 1 2 54.9_0402_1%
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# <8>
H_A#8 N2 F21 H_DRDY#
A[8]# DRDY# H_DRDY# <8>
H_A#9 J1 E1 H_DBSY#
A[9]# DBSY# H_DBSY# <8>
H_A#10 N3
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# <8>
H_A#12 P2 A[12]#

CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR# H_INIT#
P4 A[14]# INIT# B3 H_INIT# <28>
H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# <8>
H_ADSTB#0 M1
<8> H_ADSTB#0 ADSTB[0]#
C1 H_RESET#
RESET# H_RESET# <8>
H_REQ#0 K3 F3 H_RS#0
<8> H_REQ#0 REQ[0]# RS[0]# H_RS#0 <8>
H_REQ#1 H2 F4 H_RS#1
<8> H_REQ#1 REQ[1]# RS[1]# H_RS#1 <8>
H_REQ#2 K2 G3 H_RS#2
<8> H_REQ#2 REQ[2]# RS[2]# H_RS#2 <8>
H_REQ#3 J3 G2 H_TRDY#
<8> H_REQ#3 REQ[3]# TRDY# H_TRDY# <8>
H_REQ#4 L1
<8> H_REQ#4 REQ[4]#
G6 H_HIT#
HIT# H_HIT# <8>
H_A#17 Y2 E4 H_HITM#
<8> H_A#[17..35] A[17]# HITM# H_HITM# <8>
H_A#18 U5
H_A#19 A[18]# XDP_BPM#0
R3 A[19]# BPM[0]# AD4
+3VS +3VS
ADDR GROUP_1

H_A#20 W6 AD3 XDP_BPM#1

C H_A#21 A[20]# BPM[1]# XDP_BPM#2 C
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4 XDP_BPM#3
A[22]# BPM[3]#

1
H_A#23 U1 AC2 XDP_BPM#4
XDP/ITP SIGNALS

A[23]# PRDY# 1
H_A#24 R4 AC1 XDP_BPM#5
H_A#25 A[24]# PREQ# XDP_TCK C1 U1 @ R9
T5 A[25]# TCK AC5
H_A#26 T3 AA6 XDP_TDI 0.1U_0402_16V4Z 10K_0402_5%
H_A#27 A[26]# TDI XDP_TDO 2
W2 AB3

2
H_A#28 A[27]# TDO XDP_TMS EC_SMB_CK2
W5 A[28]# TMS AB5 1 VDD SMCLK 8 EC_SMB_CK2 <16,38,42>
H_A#29 Y4 AB6 XDP_TRST#
H_A#30 A[29]# TRST# XDP_DBRESET# H_THERMDA EC_SMB_DA2
U2 A[30]# DBR# C20 XDP_DBRESET# <29> 2 DP SMDATA 7 EC_SMB_DA2 <16,38,42>
H_A#31 V4
H_A#32 A[31]# H_THERMDC
W3 A[32]# 1 2 3 DN ALERT# 6
H_A#33 AA4 THERMAL C2 2200P_0402_50V7K
H_A#34 A[33]# H_PROCHOT# THERM#
AB2 A[34]# 4 THERM# GND 5
H_A#35 AA3 D21
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA
<8> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC +3VS 1 2
H_A20M# THERMDC R10 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8
<28> H_A20M# A6 A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP#
<28> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <8,28>
H_IGNNE# C4
<28> H_IGNNE# IGNNE#

<28> H_STPCLK#
H_STPCLK# D5 STPCLK#
2nd Source: ADT7421ARMZ (SA00001UN00)
H_INTR C6 H CLK
<28> H_INTR LINT0
H_NMI B4 A22 CLK_CPU_BCLK
<28> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <23>
H_SMI# A3 A21 CLK_CPU_BCLK#
<28> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <23> Address:100_1100
M4 RSVD[01]
N5 RSVD[02] H_THERMDA, H_THERMDC routing together,
T2 RSVD[03]
B
V3 Trace width / Spacing = 10 / 10 mil +5VS B

B2
RSVD[04]
FAN1 Conn
RESERVED

RSVD[05] C3 1
RSVD pins on the CPU D2 RSVD[06] 2 10U_0805_10V4Z
should be left as NO D22 RSVD[07]
D3 RSVD[08]
CONNECT F6 U2 +5VS
RSVD[09]
1 VEN GND 8
+VCC_FAN1 2 7
VIN GND

1
+VCC_FAN1 3 6
EN_FAN1 R11 1 VO GND
<38> EN_FAN1 2 100_0402_5% 4 VSET GND 5 @
Penryn 1 D1
G990P11U_SO8 1SS355TE-17_SOD323-2
C4

2
2200P_0402_50V7K D2 1 2 @ BAS16_SOT23-3
2
FAN +5VS DROOP +3VS
C5 1 2 1U_0603_10V4Z

1
C6 1 2 0.1U_0402_16V4Z

R12 40mil
10K_0402_5% +VCC_FAN1 JP1
+VCC_FAN1 1

2
1
<38> FAN_SPEED1 2 2
1 3 3
C7 4
1000P_0402_50V7K GND
5 GND
2
A A
ME@E&T_3801-F03N-01R

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2008/03/25 Deciphered Date 2008/04/ Title
Penryn(1/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4602P
Date: W ednesday, March 18, 2009 Sheet 5 of 53
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE CONN@ +CPU_CORE

JCPU1C
CONN@ A7 AB20
JCPU1B VCC[001] VCC[068]
<8> H_D#[0..15] H_D#[32..47] <8> A9 VCC[002] VCC[069] AB7
H_D#0 E22 Y22 H_D#32 A10 AC7
H_D#1 D[0]# D[32]# H_D#33 VCC[003] VCC[070]
D F24 D[1]# D[33]# AB24 A12 VCC[004] VCC[071] AC9 D
H_D#2 E26 V24 H_D#34 A13 AC12
D[2]# D[34]# VCC[005] VCC[072]

DATA GRP 0
H_D#3 G22 V26 H_D#35 A15 AC13
D[3]# D[35]# VCC[006] VCC[073]

DATA GRP 2
H_D#4 F23 V23 H_D#36 A17 AC15
H_D#5 D[4]# D[36]# H_D#37 VCC[007] VCC[074]
G25 D[5]# D[37]# T22 A18 VCC[008] VCC[075] AC17
H_D#6 E25 U25 H_D#38 A20 AC18
H_D#7 D[6]# D[38]# H_D#39 VCC[009] VCC[076]
E23 D[7]# D[39]# U23 B7 VCC[010] VCC[077] AD7
H_D#8 K24 Y25 H_D#40 B9 AD9
H_D#9 D[8]# D[40]# H_D#41 VCC[011] VCC[078]
G24 D[9]# D[41]# W22 B10 VCC[012] VCC[079] AD10
H_D#10 J24 Y23 H_D#42 B12 AD12
H_D#11 D[10]# D[42]# H_D#43 VCC[013] VCC[080]
J23 D[11]# D[43]# W24 B14 VCC[014] VCC[081] AD14
H_D#12 H22 W25 H_D#44 B15 AD15
H_D#13 D[12]# D[44]# H_D#45 VCC[015] VCC[082]
F26 D[13]# D[45]# AA23 B17 VCC[016] VCC[083] AD17
H_D#14 K22 AA24 H_D#46 B18 AD18
H_D#15 D[14]# D[46]# H_D#47 VCC[017] VCC[084]
H23 D[15]# D[47]# AB25 B20 VCC[018] VCC[085] AE9
H_DSTBN#0 J26 Y26 H_DSTBN#2 C9 AE10
<8> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <8> VCC[019] VCC[086]
H_DSTBP#0 H26 AA26 H_DSTBP#2 C10 AE12
<8> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <8> VCC[020] VCC[087]
H_DINV#0 H25 U22 H_DINV#2 C12 AE13
<8> H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 <8> VCC[021] VCC[088]
C13 VCC[022] VCC[089] AE15
<8> H_D#[16..31] H_D#[48..63] <8> C15 VCC[023] VCC[090] AE17
H_D#16 N22 AE24 H_D#48 C17 AE18
H_D#17 D[16]# D[48]# H_D#49 VCC[024] VCC[091]
K25 D[17]# D[49]# AD24 C18 VCC[025] VCC[092] AE20
H_D#18 P26 AA21 H_D#50 D9 AF9
H_D#19 D[18]# D[50]# H_D#51 VCC[026] VCC[093]
R23 D[19]# D[51]# AB22 D10 VCC[027] VCC[094] AF10
H_D#20 L23 AB21 H_D#52 D12 AF12
D[20]# D[52]# VCC[028] VCC[095]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D14 AF14
D[21]# D[53]# VCC[029] VCC[096]

DATA GRP 3
H_D#22 L22 AD20 H_D#54 D15 AF15
H_D#23 D[22]# D[54]# H_D#55 VCC[030] VCC[097]
M23 D[23]# D[55]# AE22 D17 VCC[031] VCC[098] AF17
H_D#24 P25 AF23 H_D#56 D18 AF18
C H_D#25 D[24]# D[56]# H_D#57 VCC[032] VCC[099] +VCCP C
P23 D[25]# D[57]# AC25 E7 VCC[033] VCC[100] AF20
H_D#26 P22 AE21 H_D#58 E9
H_D#27 D[26]# D[58]# H_D#59 VCC[034]
T24 D[27]# D[59]# AD21 E10 VCC[035] VCCP[01] G21 R13 2 1 0_0402_5%
H_D#28 R24 AC22 H_D#60 E12 V6 R14 2 1 0_0402_5%
H_D#29 D[28]# D[60]# H_D#61 VCC[036] VCCP[02]
L25 D[29]# D[61]# AD23 E13 VCC[037] VCCP[03] J6
H_D#30 T25 AF22 H_D#62 E15 K6
H_D#31 D[30]# D[62]# H_D#63 VCC[038] VCCP[04]
N25 D[31]# D[63]# AC23 E17 VCC[039] VCCP[05] M6 For testing purpose only
H_DSTBN#1 L26 AE25 H_DSTBN#3 E18 J21
<8> H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 <8> VCC[040] VCCP[06]
H_DSTBP#1 M26 AF24 H_DSTBP#3 E20 K21
<8> H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 <8> VCC[041] VCCP[07]
H_DINV#1 N24 AC20 H_DINV#3 F7 M21
<8> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <8> VCC[042] VCCP[08]
F9 VCC[043] VCCP[09] N21
+CPU_GTLREF AD26 R26 COMP0 R15 1 2 27.4_0402_1% F10 N6
R16 GTLREF COMP[0] VCC[044] VCCP[10]
1 2 @ 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 R17 1 2 54.9_0402_1% F12 VCC[045] VCCP[11] R21
R18 1 2 @ 1K_0402_5% TEST2 D25 AA1 COMP2 R19 1 2 27.4_0402_1% F14 R6
T1 TEST3 TEST2 COMP[2] COMP3 R20 54.9_0402_1% VCC[046] VCCP[12]
C24 TEST3 COMP[3] Y1 1 2 F15 VCC[047] VCCP[13] T21
T2 TEST4 AF26 F17 T6 Near pin B26
T3 TEST5 TEST4 H_DPRSTP# VCC[048] VCCP[14]
AF1 TEST5 DPRSTP# E5 H_DPRSTP# <8,28,50> F18 VCC[049] VCCP[15] V21
T4 TEST6 A26 B5 H_DPSLP# F20 W21
TEST6 DPSLP# H_DPSLP# <28> VCC[050] VCCP[16]
T5 TEST7 C3 D24 H_DPW R# AA7 20mils
TEST7 DPWR# H_DPW R# <8> VCC[051]
CPU_BSEL0 B22 D6 H_PW RGOOD AA9 B26
<23> CPU_BSEL0 BSEL[0] PWRGOOD H_PW RGOOD <28> VCC[052] VCCA[01] +1.5VS
CPU_BSEL1 B23 D7 H_CPUSLP# AA10 C26

0.01U_0402_16V7K
<23> CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# <8> VCC[053] VCCA[02]
CPU_BSEL2 C21 AE6 H_PSI# AA12

10U_0805_10V4Z
<23> CPU_BSEL2 BSEL[2] PSI# H_PSI# <50> VCC[054]
AA13 VCC[055] VID[0] AD6 CPU_VID0 <50>
Penryn AA15 AF5 1 1
VCC[056] VID[1] CPU_VID1 <50>
Trace Close CPU < 0.5' AA17 VCC[057] VID[2] AE5 CPU_VID2 <50>

C8

C9
AA18 VCC[058] VID[3] AF4 CPU_VID3 <50>
AA20 VCC[059] VID[4] AE3 CPU_VID4 <50> 2 2
TRACE CLOSELY CPU < 0.5' AB9 VCC[060] VID[5] AF3 CPU_VID5 <50>
B Width=4 mil , AC10 VCC[061] VID[6] AE2 CPU_VID6 <50> B
Spacing: 15mil COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) AB10 VCC[062]
AB12
COMP1, COMP3 layout : Width 5mils and Space 25mils (55Ohms) VCC[063] VCCSENSE
(55Ohm) AB14 VCC[064] VCCSENSE AF7 VCCSENSE <50>
AB15 VCC[065]
AB17 VCC[066]
AB18 AE7 VSSSENSE
VCC[067] VSSSENSE VSSSENSE <50>
Penryn
.
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

+VCCP
FSB BCLK BSEL2 BSEL1 BSEL0 Length match within 25 mils. +CPU_CORE
1

The trace width/space/other is R22

100_0402_1%
533 133 0 0 1
R21 18/7/25. 1 2 VCCSENSE
1K_0402_1%
667 166 0 1 1 R23
2

Layout note: Z0=55 ohm +CPU_GTLREF 100_0402_1%

1 2 VSSSENSE
0.5" max for GTLREF.
800 200 0 1 0 Layout Note:
1

Route VCCSENSE and VSSSENSE traces at

R24 1067 266 0 0 0 27.4 Ohms with 50 mil spacing.
2K_0402_1%
Place PU and PD within 1 inch of CPU.
2

Length matched to within 25 mils.

A Close to CPU pin A

within 500mils.
Close to CPU pin AD26
within 500mils.
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (2/3)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B KIWB3/B4_LA4551P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, March 18, 2009 Sheet 6 of 53
5 4 3 2 1
 5 4 3 2 1

CONN@
JCPU1D
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
A16 VSS[005] VSS[086] R5
A19 VSS[006] VSS[087] R22
A23 VSS[007] VSS[088] R25
D AF2 VSS[008] VSS[089] T1 D
B6 VSS[009] VSS[090] T4
B8 VSS[010] VSS[091] T23
B11 VSS[011] VSS[092] T26
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24
B24 VSS[016] VSS[097] V2
C5 VSS[017] VSS[098] V5
C8 VSS[018] VSS[099] V22
C11 VSS[019] VSS[100] V25
+CPU_CORE
C14 VSS[020] VSS[101] W1
+CPU_CORE
C16 VSS[021] VSS[102] W4
C19 VSS[022] VSS[103] W23 10~15 vias for +CPU_CORE
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3
C25 VSS[025] VSS[106] Y6
D1 VSS[026] VSS[107] Y21 needed to update
D4 VSS[027] VSS[108] Y24 1 1 1 1 1 1
D8 AA2 1 2 @ @
VSS[028] VSS[109] C832 C834 C664 C833 C644 C647
D11 VSS[029] VSS[110] AA5
D13 AA8 + C10 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[030] VSS[111] 1200U_PFAF250E128MNTTE_2.5VM 2 2 2 2 2 2
D16 VSS[031] VSS[112] AA11
D19 VSS[032] VSS[113] AA14
3 4
D23 VSS[033] VSS[114] AA16
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
E6 VSS[036] VSS[117] AA25 10~15 vias for GND
C E8 AB1 C
VSS[037] VSS[118]
E11 VSS[038] VSS[119] AB4 SGA00003F10 1000uF
E14 AB8
E16
VSS[039] VSS[120]
AB11
be placed under the center of CPU +CPU_CORE
VSS[040] VSS[121]
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
E24 AB19
F5
VSS[043] VSS[124]
AB23
Middle Frequency Decoupling
VSS[044] VSS[125]
F8 VSS[045] VSS[126] AB26
F11 VSS[046] VSS[127] AC3
F13 VSS[047] VSS[128] AC6 1 1 1 1 1 1
F16 AC8 @ @ @
VSS[048] VSS[129] C818 C831 C817 C830 C803 C804
F19 VSS[049] VSS[130] AC11
F2 AC14 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[050] VSS[131] 2 2 2 2 2 2
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 VSS[053] VSS[134] AC21
G1 VSS[054] VSS[135] AC24
G23 VSS[055] VSS[136] AD2
G26 VSS[056] VSS[137] AD5
H3 VSS[057] VSS[138] AD8 Per PWR team request ,
H6 AD11
H21
VSS[058] VSS[139]
AD13
reserve 12 MLCC for +CPU_CORE
VSS[059] VSS[140]
H24 AD16
J2
VSS[060] VSS[141]
AD19
Reserved
VSS[061] VSS[142]
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25
J25 VSS[064] VSS[145] AE1
K1 AE4 +VCCP
B
K4
VSS[065]
VSS[066]
VSS[146]
VSS[147] AE8 FOR 3G ISSUE (SED) 20080826 B

K23 VSS[067] VSS[148] AE11

K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
L6 VSS[070] VSS[151] AE19
L21 AE23 C28 C29 C30 C31 C26 C27
VSS[071] VSS[152]
L24 VSS[072] VSS[153] AE26 22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J
M2 VSS[073] VSS[154] A2 @ @ @ @ @ @
M5 VSS[074] VSS[155] AF6
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
N26 AF21 +VCCP
VSS[080] VSS[161]
P3 VSS[081] VSS[162] A25
VSS[163] AF25
1
Penryn 1 1 1 1 1 1
C48 +
.
C46 C47 C49 C50 C51 C52 Place these inside socket cavity
220U_D2_4VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 on L8 (North side Secondary)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (3/3)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B KIW10/11_LA4142P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, March 18, 2009 Sheet 7 of 53
5 4 3 2 1
 5 4 3 2 1

U3B
H_A#[3..35] <5>
U3A T6 M36 AP24 M_CLK_DDR0 M_CLK_DDR0 <14>
H_A#3 T7 RSVD1 SA_CK_0 M_CLK_DDR1
A14 N36 AT21 M_CLK_DDR1 <14>
H_D#0 H_A#_3 H_A#4 +1.5V T8 RSVD2 SA_CK_1 M_CLK_DDR2
<6> H_D#[0..63] F2 C15 R33 AV24 M_CLK_DDR2 <15>
H_D#1 H_D#_0 H_A#_4 H_A#5 T9 RSVD3 SB_CK_0 M_CLK_DDR3
G8 F16 T33 AU20 M_CLK_DDR3 <15>
H_D#_1 H_A#_5 RSVD4 SB_CK_1

COMPENSATION
H_D#2 F8 H13 H_A#6 T10 AH9
H_D#_2 H_A#_6 RSVD5

1
H_D#3 E6 C18 H_A#7 T11 AH10 AR24 M_CLK_DDR#0
H_D#_3 H_A#_7 RSVD6 SA_CK#_0 M_CLK_DDR#0 <14>
H_D#4 G2 M16 H_A#8 T12 AH12 AR21 M_CLK_DDR#1
H_D#_4 H_A#_8 RSVD7 SA_CK#_1 M_CLK_DDR#1 <14>
H_D#5 H6 J13 H_A#9 R28 T13 AH13 AU24 M_CLK_DDR#2
H_D#_5 H_A#_9 RSVD8 SB_CK#_0 M_CLK_DDR#2 <15>
H_D#6 H2 P16 H_A#10 1K_0402_1% T14 K12 AV20 M_CLK_DDR#3
H_D#_6 H_A#_10 RSVD9 SB_CK#_1 M_CLK_DDR#3 <15>
H_D#7 F6 R16 H_A#11 T15 AL34

2
H_D#8 H_D#_7 H_A#_11 H_A#12 SMRCOMP_VOH T16 RSVD10 DDR_CKE0_DIMMA
D4 N17 AK34 BC28 DDR_CKE0_DIMMA <14>
H_D#9 H_D#_8 H_A#_12 H_A#13 T17 RSVD11 SA_CKE_0 DDR_CKE1_DIMMA
H3 M13 1 1 AN35 AY28 DDR_CKE1_DIMMA <14>

1
H_D#10 H_D#_9 H_A#_13 H_A#14 T18 RSVD12 SA_CKE_1 DDR_CKE2_DIMMB
M9 E17 AM35 AY36 DDR_CKE2_DIMMB <15>
H_D#11 H_D#_10 H_A#_14 H_A#15 C53 C54 T19 RSVD13 SB_CKE_0 DDR_CKE3_DIMMB
M11 P17 T24 BB36 DDR_CKE3_DIMMB <15>
H_D#12 H_D#_11 H_A#_15 H_A#16 2.2U_0603_6.3V4Z R25 RSVD14 SB_CKE_1
J1 F17 0.01U_0402_25V7K
H_D#13 H_D#_12 H_A#_16 H_A#17 2 2 3.01K_0402_1% DDR_CS0_DIMMA#
J2 G20 BA17 DDR_CS0_DIMMA# <14>
D
H_D#14 H_D#_13 H_A#_17 H_A#18 SA_CS#_0 DDR_CS1_DIMMA# D
N12 B19 AY16 DDR_CS1_DIMMA# <14>

2
H_D#15 H_D#_14 H_A#_18 H_A#19 T20 SA_CS#_1 DDR_CS2_DIMMB# +1.5V
J6 J16 B31 AV16 DDR_CS2_DIMMB# <15>
H_D#16 H_D#_15 H_A#_19 H_A#20 SMRCOMP_VOL T26 RSVD15 SB_CS#_0 DDR_CS3_DIMMB#
P2 E20 B2 AR13 DDR_CS3_DIMMB# <15>
H_D#_16 H_A#_20 RSVD16 SB_CS#_1

DDR CLK/ CONTROL/

H_D#17 L2 H16 H_A#21 T21 M1
H_D#_17 H_A#_21 RSVD17

1
RSVD
H_D#18 R2 J20 H_A#22 1 1 BD17 M_ODT0 M_ODT0 <14>
H_D#19 H_D#_18 H_A#_22 H_A#23 SA_ODT_0 M_ODT1
N9 L17 AY17 M_ODT1 <14>
H_D#20 H_D#_19 H_A#_23 H_A#24 C55 C56 R26 T22 SA_ODT_1 M_ODT2 R27
L6 A17 AY21 BF15 M_ODT2 <15>
H_D#21 H_D#_20 H_A#_24 H_A#25 0.01U_0402_25V7K 2.2U_0603_6.3V4Z 1K_0402_1% RSVD20 SB_ODT_O M_ODT3 80.6_0402_1%
M5
H_D#_21 H_A#_25
B17
2 2 SB_ODT_1
AY13 M_ODT3 <15> 20mil
H_D#22 J3 L16 H_A#26

2
H_D#23 H_D#_22 H_A#_26 H_A#27 SMRCOMP
N2
H_D#_23 H_A#_27
C21
SM_RCOMP
BG22 For Crestline: 20ohm
H_D#24 R1 J17 H_A#28 T23 BG23 BH21 SMRCOMP# 1 2 For Calero: 80.6ohm
H_D#25 H_D#_24 H_A#_28 H_A#29 T24 RSVD22 SM_RCOMP# R29 80.6_0402_1%
N5
H_D#_25 H_A#_29
H20 BF23
RSVD23 For Cantiga: 80.6ohm
H_D#26 N6 B18 H_A#30 T25 BH18 BF28 SMRCOMP_VOH
H_D#27 H_D#_26 H_A#_30 H_A#31 T27 RSVD24 SM_RCOMP_VOH SMRCOMP_VOL R30 0_0402_5%
P13 K17 BF18 BH28 1 2 1.5V_PGOOD <48>
H_D#28 H_D#_27 H_A#_31 H_A#32 RSVD25 SM_RCOMP_VOL R31
N8 B20 1 2 @ 12K_0402_5% DDR3_SM_PWROK
H_D#29 H_D#_28 H_A#_32 H_A#33 +DDR_MCH_REF
L7 F21 AV42
H_D#30 H_D#_29 H_A#_33 H_A#34 SM_VREF SM_PWROK R32
N10 K21 AR36 1 2 @ 10K_0402_5%
H_D#31 H_D#_30 H_A#_34 H_A#35 SM_PWROK SM_REXT R33 499_0402_1%
M3 L20 BF17 1 2
H_D#32 H_D#_31 H_A#_35 SM_REXT SM_DRAMRST#
Y3 BC36 SM_DRAMRST# <14,15>
H_D#33 H_D#_32 H_ADS# SM_DRAMRST#
AD14 H12 H_ADS# <5>
H_D#34 H_D#_33 H_ADS# H_ADSTB#0
H_D#35
Y6
H_D#_34 H_ADSTB#_0
B16
H_ADSTB#1
H_ADSTB#0 <5>
CLK_MCH_DREFCLK
DDR3
Y10 G17 H_ADSTB#1 <5> B38 CLK_MCH_DREFCLK <23>
H_D#36 H_D#_35 H_ADSTB#_1 H_BNR# DPLL_REF_CLK CLK_MCH_DREFCLK#
Y12 A9 H_BNR# <5> A38 CLK_MCH_DREFCLK# <23>
H_D#_36 H_BNR# DPLL_REF_CLK#
HOST

H_D#37 Y14 F11 H_BPRI# E41 MCH_SSCDREFCLK

H_D#_37 H_BPRI# H_BPRI# <5> DPLL_REF_SSCLK MCH_SSCDREFCLK <23>
H_D#38 Y7 G12 H_BR0# F41 MCH_SSCDREFCLK#
H_D#_38 H_BREQ# H_BR0# <5> DPLL_REF_SSCLK# MCH_SSCDREFCLK# <23>
H_D#39 H_DEFER#

CLK
W2 E9 H_DEFER# <5>
H_D#40 H_D#_39 H_DEFER# H_DBSY# CLK_MCH_3GPLL
AA8 B10 H_DBSY# <5> F43 CLK_MCH_3GPLL <23>
H_D#41 H_D#_40 H_DBSY# CLK_MCH_BCLK PEG_CLK CLK_MCH_3GPLL#
Y9 AH7 CLK_MCH_BCLK <23> E43 CLK_MCH_3GPLL# <23>
H_D#42 H_D#_41 HPLL_CLK CLK_MCH_BCLK# PEG_CLK#
AA13 AH6 CLK_MCH_BCLK# <23>
H_D#43 H_D#_42 HPLL_CLK# H_DPWR#
AA9 J11 H_DPWR# <6>
H_D#44 H_D#_43 H_DPWR# H_DRDY#
AA11 F9 H_DRDY# <5>
H_D#45 H_D#_44 H_DRDY# H_HIT# DMI_TXN0
AD11 H9 H_HIT# <5> AE41 DMI_TXN0 <29>
H_D#46 H_D#_45 H_HIT# H_HITM# DMI_RXN_0 DMI_TXN1
AD10 E12 H_HITM# <5> AE37 DMI_TXN1 <29>
H_D#47 H_D#_46 H_HITM# H_LOCK# DMI_RXN_1 DMI_TXN2
AD13 H11 H_LOCK# <5> AE47 DMI_TXN2 <29>
H_D#48 H_D#_47 H_LOCK# H_TRDY# DMI_RXN_2 DMI_TXN3
AE12 C9 H_TRDY# <5> AH39 DMI_TXN3 <29>
H_D#49 H_D#_48 H_TRDY# DMI_RXN_3
AE9
H_D#50 H_D#_49 DMI_TXP0
AA2 AE40 DMI_TXP0 <29>
H_D#51 H_D#_50 MCH_CLKSEL0 DMI_RXP_0 DMI_TXP1
C AD8 <23> MCH_CLKSEL0 T25 AE38 DMI_TXP1 <29>
C
H_D#52 H_D#_51 MCH_CLKSEL1 CFG_0 DMI_RXP_1 DMI_TXP2
AA3 <23> MCH_CLKSEL1 R25 AE48 DMI_TXP2 <29>
H_D#53 H_D#_52 H_DINV#0 MCH_CLKSEL2 CFG_1 DMI_RXP_2 DMI_TXP3
AD3 J8 H_DINV#0 <6> <23> MCH_CLKSEL2 P25 AH40 DMI_TXP3 <29>
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1 CFG_2 DMI_RXP_3
AD7 L3 H_DINV#1 <6> P20
H_D#55 H_D#_54 H_DINV#_1 H_DINV#2 CFG_3 DMI_RXN0
AE14 Y13 H_DINV#2 <6> P24 AE35 DMI_RXN0 <29>
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3 CFG5 CFG_4 DMI_TXN_0 DMI_RXN1

DMI
AF3 Y1 H_DINV#3 <6> CFG5 C25 AE43 DMI_RXN1 <29>
H_D#57 H_D#_56 H_DINV#_3 T28 CFG6 CFG_5 DMI_TXN_1 DMI_RXN2
AC1 N24 AE46 DMI_RXN2 <29>
H_D#58 H_D#_57 H_DSTBN#0 T29 CFG7 CFG_6 DMI_TXN_2 DMI_RXN3
AE3 L10 H_DSTBN#0 <6> M24 AH42 DMI_RXN3 <29>
H_D#_58 H_DSTBN#_0 CFG_7 DMI_TXN_3

CFG
H_D#59 AC3 M7 H_DSTBN#1 T30 CFG8 E21
H_D#_59 H_DSTBN#_1 H_DSTBN#1 <6> CFG_8
H_D#60 AE11 AA5 H_DSTBN#2 T31 CFG9 C23 AD35 DMI_RXP0
H_D#_60 H_DSTBN#_2 H_DSTBN#2 <6> CFG_9 DMI_TXP_0 DMI_RXP0 <29>
H_D#61 AE8 AE6 H_DSTBN#3 T32 CFG10 C24 AE44 DMI_RXP1
H_D#_61 H_DSTBN#_3 H_DSTBN#3 <6> CFG_10 DMI_TXP_1 DMI_RXP1 <29>
H_D#62 AG2 T33 CFG11 N21 AF46 DMI_RXP2
H_D#_62 CFG_11 DMI_TXP_2 DMI_RXP2 <29>
H_D#63 AD6 L9 H_DSTBP#0 T34 CFG12 P21 AH43 DMI_RXP3
H_D#_63 H_DSTBP#_0 H_DSTBP#0 <6> CFG_12 DMI_TXP_3 DMI_RXP3 <29>
M8 H_DSTBP#1 T35 CFG13 T21
H_DSTBP#_1 H_DSTBP#1 <6> CFG_13
AA6 H_DSTBP#2 +3VS T36 CFG14 R20
H_DSTBP#_2 H_DSTBP#2 <6> CFG_14
H_SWNG C5 AE5 H_DSTBP#3 T37 CFG15 M20
H_SWING H_DSTBP#_3 H_DSTBP#3 <6> CFG_15
H_RCOMP E3 T38 CFG16 L21
H_RCOMP H_REQ#0 T39 CFG17 CFG_16
B15 H_REQ#0 <5> H21
1

1
H_REQ#_0 H_REQ#1 T40 CFG18 CFG_17
K13 P29

GRAPHICS VID
H_REQ#_1 H_REQ#1 <5> CFG_18
F13 H_REQ#2 T41 CFG19 R28
H_REQ#_2 H_REQ#2 <5> CFG_19
B13 H_REQ#3 R34 R35 T42 CFG20 T28 B33
H_REQ#_3 H_REQ#3 <5> CFG_20 GFX_VID_0
<5> H_RESET# H_RESET# C12 B14 H_REQ#4 10K_0402_5% 10K_0402_5% B32 T43 PAD MCH_HDA_BCLK
H_CPURST# H_REQ#_4 H_REQ#4 <5> GFX_VID_1
<6> H_CPUSLP# H_CPUSLP# E11 G33 T44 PAD connect to power CPU_CORE 1
2

H_CPUSLP# H_RS#0 PM_EXTTS#0 GFX_VID_2 T45 PAD @

B6 H_RS#0 <5> F33
H_RS#_0 H_RS#1 PM_EXTTS#1 PM_BMBUSY# GFX_VID_3 T46 PAD C57
F12 H_RS#1 <5> <29> PM_BMBUSY# R29 E33
H_VREF H_RS#_1 H_RS#2 H_DPRSTP# PM_SYNC# GFX_VID_4 T47 PAD 10P_0402_50V8J
A11 C8 H_RS#2 <5> <6,28,50> H_DPRSTP# B7
H_AVREF H_RS#_2 PM_EXTTS#0 PM_DPRSTP# 2
B11 <14,15> PM_EXTTS#0 N33
H_DVREF PM_EXT_TS#_0

PM
PM_EXTTS#1 P32
PM_EXTTS#1 PM_EXT_TS#_1
GM45@CANTIGA ES_FCBGA1329 PM_POK_R AT40 C34 T48
PLT_RST#_R PWROK GFX_VR_EN
AT11
H_THERMTRIP# RSTIN# +VCCP
<5,28> H_THERMTRIP# T20
DPRSLPVR THERMTRIP#
<29,50> DPRSLPVR R32
DPRSLPVR
layout note: For AMT function

1
Route H_SCOMP and H_SCOMP# with trace width BG48 AH37 CL_CLK0 CL_CLK0 <29>
NC_1 CL_CLK CL_DATA0 R36
spacing and impedance (55 ohm) same as FSB data traces BF48
NC_2 CL_DATA
AH36 CL_DATA0 <29>

ME
BD48 AN36 1K_0402_1%
NC_3 CL_PWROK M_PWROK <29>
BC48 AJ35 CL_RST#
CL_RST# <29>

2
B NC_4 CL_RST# CL_VREF B
BH47 AH34
NC_5 CL_VREF
BG47
NC_6
BE47
Layout Note: R37 1 2 0_0402_5% PM_POK_R BH46
NC_7
N28
1
<29,38> ICH_POK NC_8 DDPC_CTRLCLK T49

NC
C58 R38
H_RCOMP / H_VREF / H_SWNG R39 1 2 @ 0_0402_5%
BF46
BG45
NC_9 DDPC_CTRLDATA
M28
G36 HDMICLK_NB
T50
0.1U_0402_16V4Z 499_0402_1%
<29,50> VGATE NC_10 SDVO_CTRLCLK HDMICLK_NB <24> 2
trace width and spacing is 10/20 R40
BH44
NC_11 SDVO_CTRLDATA
E36 HDMIDAT_NB HDMIDAT_NB <24>
<16,27,31,32> PLT_RST# 1 2 100_0402_5% PLT_RST#_R BH43 K36 MCH_CLKREQ#
MCH_CLKREQ# <23>
NC_12 CLKREQ#

MISC
BH6 H36 MCH_ICH_SYNC#
NC_13 ICH_SYNC# MCH_ICH_SYNC# <29>
BH5 TSATN# <38>
+VCCP +VCCP NC_14
BG4
NC_15 R41
BH3 B12 1 2 56_0402_5% +VCCP
NC_16 TSATN#
BF3
Layout Note:
1

+1.5V NC_17
BH2
NC_18
R42 R43
V_DDR_MCH_REF trace BG2
BE2
NC_19
B28 MCH_HDA_BCLK R44 1 2 GM@ 0_0402_5%
HDA_BITCLK_CODEC <28,36>
1

NC_20 HDA_BCLK
1K_0402_1% 221_0603_1% width and spacing is 20/20. R45
BG1
NC_21 HDA_RST#
B30 MCH_HDA_RST#
MCH_HDA_SDIN0_R
R46
R47
1 2 GM@
GM@
0_0402_5%
33_0402_5%
HDA_RST_CODEC# <28,36>
BF1 B29 1 2
2

NC_22 HDA_SDI HDA_SDIN0 <28>

H_VREF H_RCOMP H_SWNG 1K_0402_1% BD1 C29 MCH_HDA_SDOUT R48 1 2 GM@ 0_0402_5%
NC_23 HDA_SDO HDA_SDOUT_CODEC <28,36>
BC1 A28 MCH_HDA_SYNC R49 1 2 GM@ 0_0402_5%

HDA
HDA_SYNC_CODEC <28,36>
1

NC_24 HDA_SYNC
1 1 F1
2

+DDR_MCH_REF NC_25
A47
R50 C59 R51 R52 C60 NC_26
Notice: Please check HDA power rail to select HDA controller.
1

2K_0402_1% 0.1U_0402_16V4Z 24.9_0402_1% 100_0402_1% 0.1U_0402_16V4Z 1 GM45@CANTIGA ES_FCBGA1329

2 2 R53
2

C61 1K_0402_1%
0.1U_0402_16V4Z
2
2

within 100 mils from NB Near B3 pin

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(1/6)-GTL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C KIWB3/B4_LA4551P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 18, 2009 Sheet 8 of 53
5 4 3 2 1
 5 4 3 2 1

D D

DDR_A_BS[0..2] <14> <15> DDR_B_D[0..63]

U3D U3E
DDR_A_D0 AJ38 BD21 DDR_A_BS0 DDR_B_D0 AK47 BC16 DDR_B_BS0
<14> DDR_A_D[0..63] SA_DQ_0 SA_BS_0 SB_DQ_0 SB_BS_0 DDR_B_BS[0..2] <15>
DDR_A_D1 AJ41 BG18 DDR_A_BS1 DDR_B_D1 AH46 BB17 DDR_B_BS1
DDR_A_D2 SA_DQ_1 SA_BS_1 DDR_A_BS2 DDR_B_D2 SB_DQ_1 SB_BS_1 DDR_B_BS2
AN38 SA_DQ_2 SA_BS_2 AT25 AP47 SB_DQ_2 SB_BS_2 BB33
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_A_RAS# DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDR_A_RAS# <14> AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_A_CAS# DDR_B_D5 AJ48 AU17 DDR_B_RAS#
SA_DQ_5 SA_CAS# DDR_A_CAS# <14> SB_DQ_5 SB_RAS# DDR_B_RAS# <15>
DDR_A_D6 AM44 AY20 DDR_A_W E# DDR_B_D6 AM48 BG16 DDR_B_CAS#
SA_DQ_6 SA_WE# DDR_A_W E# <14> SB_DQ_6 SB_CAS# DDR_B_CAS# <15>
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14 DDR_B_W E#
SA_DQ_7 SB_DQ_7 SB_WE# DDR_B_W E# <15>
DDR_A_D8 AN43 DDR_B_D8 AU47
DDR_A_D9 SA_DQ_8 DDR_B_D9 SB_DQ_8
AN44 SA_DQ_9 AU46 SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
DDR_A_D11 SA_DQ_10 DDR_B_D11 SB_DQ_10
AT38 SA_DQ_11 AY48 SB_DQ_11
DDR_A_D12 AN41 DDR_B_D12 AT47
DDR_A_D13 SA_DQ_12 DDR_A_DM0 DDR_B_D13 SB_DQ_12
AN39 SA_DQ_13 SA_DM_0 AM37 DDR_A_DM[0..7] <14> AR47 SB_DQ_13
DDR_A_D14 AU44 AT41 DDR_A_DM1 DDR_B_D14 BA47
DDR_A_D15 SA_DQ_14 SA_DM_1 DDR_A_DM2 DDR_B_D15 SB_DQ_14 DDR_B_DM0
AU42 SA_DQ_15 SA_DM_2 AY41 BC47 SB_DQ_15 SB_DM_0 AM47 DDR_B_DM[0..7] <15>
DDR_A_D16 AV39 AU39 DDR_A_DM3 DDR_B_D16 BC46 AY47 DDR_B_DM1
DDR_A_D17 SA_DQ_16 SA_DM_3 DDR_A_DM4 DDR_B_D17 SB_DQ_16 SB_DM_1 DDR_B_DM2
AY44 SA_DQ_17 SA_DM_4 BB12 BC44 SB_DQ_17 SB_DM_2 BD40
DDR_A_D18 BA40 AY6 DDR_A_DM5 DDR_B_D18 BG43 BF35 DDR_B_DM3
C DDR_A_D19 SA_DQ_18 SA_DM_5 DDR_A_DM6 DDR_B_D19 SB_DQ_18 SB_DM_3 DDR_B_DM4 C
BD43 SA_DQ_19 SA_DM_6 AT7 BF43 SB_DQ_19 SB_DM_4 BG11
DDR_A_D20 AV41 AJ5 DDR_A_DM7 DDR_B_D20 BE45 BA3 DDR_B_DM5
DDR_A_D21 SA_DQ_20 SA_DM_7 DDR_B_D21 SB_DQ_20 SB_DM_5 DDR_B_DM6
AY43 BC41 AP1

B
SA_DQ_21 SB_DQ_21 SB_DM_6
A

DDR_A_D22 BB41 DDR_B_D22 BF40 AK2 DDR_B_DM7

DDR_A_D23 SA_DQ_22 DDR_A_DQS0 DDR_B_D23 SB_DQ_22 SB_DM_7
BC40 SA_DQ_23 SA_DQS_0 AJ44 DDR_A_DQS[0..7] <14> BF41 SB_DQ_23
DDR_A_D24 AY37 AT44 DDR_A_DQS1 DDR_B_D24 BG38
DDR_A_D25 SA_DQ_24 SA_DQS_1 DDR_A_DQS2 DDR_B_D25 SB_DQ_24 DDR_B_DQS0
BD38 SA_DQ_25 SA_DQS_2 BA43 BF38 SB_DQ_25 SB_DQS_0 AL47 DDR_B_DQS[0..7] <15>

MEMORY
DDR_A_D26 DDR_A_DQS3 DDR_B_D26 DDR_B_DQS1
MEMORY

AV37 SA_DQ_26 SA_DQS_3 BC37 BH35 SB_DQ_26 SB_DQS_1 AV48

DDR_A_D27 AT36 AW12 DDR_A_DQS4 DDR_B_D27 BG35 BG41 DDR_B_DQS2
DDR_A_D28 SA_DQ_27 SA_DQS_4 DDR_A_DQS5 DDR_B_D28 SB_DQ_27 SB_DQS_2 DDR_B_DQS3
AY38 SA_DQ_28 SA_DQS_5 BC8 BH40 SB_DQ_28 SB_DQS_3 BG37
DDR_A_D29 BB38 AU8 DDR_A_DQS6 DDR_B_D29 BG39 BH9 DDR_B_DQS4
DDR_A_D30 SA_DQ_29 SA_DQS_6 DDR_A_DQS7 DDR_B_D30 SB_DQ_29 SB_DQS_4 DDR_B_DQS5
AV36 SA_DQ_30 SA_DQS_7 AM7 BG34 SB_DQ_30 SB_DQS_5 BB2
DDR_A_D31 AW36 DDR_B_D31 BH34 AU1 DDR_B_DQS6
DDR_A_D32 SA_DQ_31 DDR_B_D32 SB_DQ_31 SB_DQS_6 DDR_B_DQS7
BD13 SA_DQ_32 BH14 SB_DQ_32 SB_DQS_7 AN6
DDR_A_D33 AU11 AJ43 DDR_A_DQS#0 DDR_B_D33 BG12
SA_DQ_33 SA_DQS#_0 DDR_A_DQS#[0..7] <14> SB_DQ_33
DDR_A_D34 BC11 AT43 DDR_A_DQS#1 DDR_B_D34 BH11
DDR_A_D35 SA_DQ_34 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D35 SB_DQ_34 DDR_B_DQS#0
BA12 BA44 BG8 AL46

SYSTEM
SA_DQ_35 SA_DQS#_2 SB_DQ_35 SB_DQS#_0 DDR_B_DQS#[0..7] <15>
SYSTEM

DDR_A_D36 AU13 BD37 DDR_A_DQS#3 DDR_B_D36 BH12 AV47 DDR_B_DQS#1

DDR_A_D37 SA_DQ_36 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D37 SB_DQ_36 SB_DQS#_1 DDR_B_DQS#2
AV13 SA_DQ_37 SA_DQS#_4 AY12 BF11 SB_DQ_37 SB_DQS#_2 BH41
DDR_A_D38 BD12 BD8 DDR_A_DQS#5 DDR_B_D38 BF8 BH37 DDR_B_DQS#3
DDR_A_D39 SA_DQ_38 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D39 SB_DQ_38 SB_DQS#_3 DDR_B_DQS#4
BC12 SA_DQ_39 SA_DQS#_6 AU9 BG7 SB_DQ_39 SB_DQS#_4 BG9
DDR_A_D40 BB9 AM8 DDR_A_DQS#7 DDR_B_D40 BC5 BC2 DDR_B_DQS#5
DDR_A_D41 SA_DQ_40 SA_DQS#_7 DDR_B_D41 SB_DQ_40 SB_DQS#_5 DDR_B_DQS#6
BA9 SA_DQ_41 BC6 SB_DQ_41 SB_DQS#_6 AT2
DDR_A_D42 AU10 DDR_B_D42 AY3 AN5 DDR_B_DQS#7
DDR_A_D43 SA_DQ_42 DDR_B_D43 SB_DQ_42 SB_DQS#_7
AV9 SA_DQ_43 AY1 SB_DQ_43
DDR_A_D44 BA11 BA21 DDR_A_MA0 DDR_B_D44 BF6
SA_DQ_44 SA_MA_0 DDR_A_MA[0..14] <14> SB_DQ_44
DDR_A_D45 BD9 BC24 DDR_A_MA1 DDR_B_D45 BF5 AV17 DDR_B_MA0 DDR_B_MA[0..14] <15>

DDR
SA_DQ_45 SA_MA_1 SB_DQ_45 SB_MA_0
DDR

DDR_A_D46 AY8 BG24 DDR_A_MA2 DDR_B_D46 BA1 BA25 DDR_B_MA1

DDR_A_D47 SA_DQ_46 SA_MA_2 DDR_A_MA3 DDR_B_D47 SB_DQ_46 SB_MA_1 DDR_B_MA2
BA6 SA_DQ_47 SA_MA_3 BH24 BD3 SB_DQ_47 SB_MA_2 BC25
B DDR_A_D48 DDR_A_MA4 DDR_B_D48 DDR_B_MA3 B
AV5 SA_DQ_48 SA_MA_4 BG25 AV2 SB_DQ_48 SB_MA_3 AU25
DDR_A_D49 AV7 BA24 DDR_A_MA5 DDR_B_D49 AU3 AW25 DDR_B_MA4
DDR_A_D50 SA_DQ_49 SA_MA_5 DDR_A_MA6 DDR_B_D50 SB_DQ_49 SB_MA_4 DDR_B_MA5
AT9 SA_DQ_50 SA_MA_6 BD24 AR3 SB_DQ_50 SB_MA_5 BB28
DDR_A_D51 AN8 BG27 DDR_A_MA7 DDR_B_D51 AN2 AU28 DDR_B_MA6
DDR_A_D52 SA_DQ_51 SA_MA_7 DDR_A_MA8 DDR_B_D52 SB_DQ_51 SB_MA_6 DDR_B_MA7
AU5 SA_DQ_52 SA_MA_8 BF25 AY2 SB_DQ_52 SB_MA_7 AW28
DDR_A_D53 AU6 AW24 DDR_A_MA9 DDR_B_D53 AV1 AT33 DDR_B_MA8
DDR_A_D54 SA_DQ_53 SA_MA_9 DDR_A_MA10 DDR_B_D54 SB_DQ_53 SB_MA_8 DDR_B_MA9
AT5 SA_DQ_54 SA_MA_10 BC21 AP3 SB_DQ_54 SB_MA_9 BD33
DDR_A_D55 AN10 BG26 DDR_A_MA11 DDR_B_D55 AR1 BB16 DDR_B_MA10
DDR_A_D56 SA_DQ_55 SA_MA_11 DDR_A_MA12 DDR_B_D56 SB_DQ_55 SB_MA_10 DDR_B_MA11
AM11 SA_DQ_56 SA_MA_12 BH26 AL1 SB_DQ_56 SB_MA_11 AW33
DDR_A_D57 AM5 BH17 DDR_A_MA13 DDR_B_D57 AL2 AY33 DDR_B_MA12
DDR_A_D58 SA_DQ_57 SA_MA_13 DDR_A_MA14 DDR_B_D58 SB_DQ_57 SB_MA_12 DDR_B_MA13
AJ9 SA_DQ_58 SA_MA_14 AY25 AJ1 SB_DQ_58 SB_MA_13 BH15
DDR_A_D59 AJ8 DDR_B_D59 AH1 AU33 DDR_B_MA14
DDR_A_D60 SA_DQ_59 DDR_B_D60 SB_DQ_59 SB_MA_14
AN12 SA_DQ_60 AM2 SB_DQ_60
DDR_A_D61 AM13 DDR_B_D61 AM3
DDR_A_D62 SA_DQ_61 DDR_B_D62 SB_DQ_61
AJ11 SA_DQ_62 AH3 SB_DQ_62
DDR_A_D63 AJ12 DDR_B_D63 AJ3
SA_DQ_63 SB_DQ_63
GM45@CANTIGA ES_FCBGA1329 GM45@CANTIGA ES_FCBGA1329

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH (2/6)-DDRII
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B KIWB3/B4_LA4551P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, March 18, 2009 Sheet 9 of 53
5 4 3 2 1
 5 4 3 2 1

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_N[0..15] <16>
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_P[0..15] <16>
+3VS PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_N[0..15] <16>
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_P[0..15] <16>
Strap Pin Table
1 2 LVDS_SCL CFG[2:0] FSB Freq select 000 = FSB 1066MHz
R54 2.2K_0402_5% 010 = FSB 800MHz
D 1 2 LVDS_SDA Place the resistor within 500mils 011 = FSB 667MHz D
R55 2.2K_0402_5%
(1.27mm)of the (G)MCH Others = Reserved
PEGCOMP trace width CFG[4:3] Reserved
U3C
and spacing is 20/25 mils. CFG5 (DMI select) 0 = DMI x 2
+VCC_PEG
L32 1 = DMI x 4
<25> GMCH_ENBKL
+3VS
GMCH_ENBKL
R56 1
T51
2 10K_0402_5%
G32
M32
L_BKLT_CTRL
L_BKLT_EN PEG_COMPI T37
T36 PEGCOMP R59 1 2 49.9_0402_1% CFG6
*
0 = The iTPM Host Interface is enable
R57 1 L_CTRL_CLK PEG_COMPO
2 10K_0402_5% M33 1 = The iTPM Host Interface is disable
<25> LVDS_SCL
<25> LVDS_SDA
LVDS_SCL
LVDS_SDA
K33
J33
L_CTRL_DATA
L_DDC_CLK
H44 PCIE_GTX_C_MRX_N0 Please check Power CFG7 (Intel Management 0 =(TLS)chiper suite with no confidentiality
*
GM_ENVDD L_DDC_DATA PEG_RX#_0 PCIE_GTX_C_MRX_N1
<25> GM_ENVDD M29 L_VDD_EN PEG_RX#_1 J46 source if want Engine Crypto strap) 1 =(TLS)chiper suite with confidentiality
L44 PCIE_GTX_C_MRX_N2
PEG_RX#_2 PCIE_GTX_C_MRX_N3 support IAMT
1 2 C44 LVDS_IBG PEG_RX#_3 L40 CFG8 Reserved
R58 2.37K_0402_1% B43 N41 PCIE_GTX_C_MRX_N4
LVDS_VBG PEG_RX#_4 PCIE_GTX_C_MRX_N5
For Cantiga:2.37kohm E37 LVDS_VREFH PEG_RX#_5 P48 CFG9 0 = Reverse Lane,15->0, 14->1
E38 N44 PCIE_GTX_C_MRX_N6 (PCIE Graphics Lane Reversal) 1 = Normal Operation,Lane Number in order
For Crestline:2.4kohm
For Calero: 1.5Kohm LVDS_ACLK# C41
LVDS_VREFL PEG_RX#_6
PEG_RX#_7 T43
U43
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_N8 CFG10 (PCIE Lookback enable) 0 = Enable
*
<25> LVDS_ACLK# LVDSA_CLK# PEG_RX#_8
LVDS_ACLK C40 Y43 PCIE_GTX_C_MRX_N9 1 = Disable
Note: All LVDS data
<25>
<25>
LVDS_ACLK
LVDS_BCLK#
LVDS_BCLK#
LVDS_BCLK
B37
A37
LVDSA_CLK
LVDSB_CLK#
PEG_RX#_9
PEG_RX#_10 Y48
Y36
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_N11 CFG11 Reserved
*
<25> LVDS_BCLK LVDSB_CLK PEG_RX#_11

LVDS
AA43 PCIE_GTX_C_MRX_N12
signals/and it's compliments LVDS_A0# PEG_RX#_12 PCIE_GTX_C_MRX_N13
should be routed <25> LVDS_A0# H47 LVDSA_DATA#_0 PEG_RX#_13 AD37 CFG[13:12] (XOR/ALLZ) 00 = Reserved
LVDS_A1# E46 AC47 PCIE_GTX_C_MRX_N14 01 = XOR Mode Enabled
<25> LVDS_A1# LVDSA_DATA#_1 PEG_RX#_14
Differentially <25> LVDS_A2#
LVDS_A2# G40 AD39 PCIE_GTX_C_MRX_N15 10 = All Z Mode Enabled
LVDSA_DATA#_2 PEG_RX#_15
A40 11 = Normal Operation(Default)
C LVDS_A0
T52

H48
LVDSA_DATA#_3
PEG_RX_0 H43
J44
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_P1 CFG[15:14] Reserved
* C
<25> LVDS_A0 LVDSA_DATA_0 PEG_RX_1
LVDS_A1 D45 L43 PCIE_GTX_C_MRX_P2
<25> LVDS_A1 LVDSA_DATA_1 PEG_RX_2

GRAPHICS
LVDS_A2 F40 L41 PCIE_GTX_C_MRX_P3 CFG16 (FSB Dynamic ODT) 0 = Disabled
<25> LVDS_A2 LVDSA_DATA_2 PEG_RX_3
B40 N40 PCIE_GTX_C_MRX_P4 1 = Enabled
LVDS_B0#
T53

A41
LVDSA_DATA_3 PEG_RX_4
PEG_RX_5 P47
N43
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P6 CFG[18:17] Reserved
*
<25> LVDS_B0# LVDSB_DATA#_0 PEG_RX_6
LVDS_B1# H38 T42 PCIE_GTX_C_MRX_P7
<25> LVDS_B1# LVDSB_DATA#_1 PEG_RX_7
LVDS_B2# G37 U42 PCIE_GTX_C_MRX_P8 CFG19 (DMI Lane Reversal) 0 = Normal Operation
<25> LVDS_B2#
T54 J37
LVDSB_DATA#_2
LVDSB_DATA#_3
PEG_RX_8
PEG_RX_9 Y42
W47
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_P10
(Lane number in Order)
1 = Reverse Lane
*
LVDS_B0 PEG_RX_10 PCIE_GTX_C_MRX_P11
<25> LVDS_B0 B42 LVDSB_DATA_0 PEG_RX_11 Y37
LVDS_B1 G38 AA42 PCIE_GTX_C_MRX_P12 CFG20 (PCIE/SDVO concurrent) 0 = Only PCIE or SDVO is operational.
<25> LVDS_B1
<25> LVDS_B2
LVDS_B2
T55
F37
K37
LVDSB_DATA_1
LVDSB_DATA_2
PEG_RX_12
PEG_RX_13 AD36
AC48
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_P14
1 = PCIE/SDVO are operating simu. *
LVDSB_DATA_3 PEG_RX_14

PCI-EXPRESS
AD40 PCIE_GTX_C_MRX_P15
PEG_RX_15 CLOSE TO MCH
J41 PCIE_MTX_GRX_N0 C62 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N0
PEG_TX#_0 PCIE_MTX_GRX_N1 C63 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N1
PEG_TX#_1 M46 1 2
R60 1 2 GM@ 75_0402_5% TVA_DAC F25 M47 PCIE_MTX_GRX_N2 C64 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N2
R61 TVA_DAC PEG_TX#_2
1 2 GM@ 75_0402_5% TVB_DAC H25 TVB_DAC PEG_TX#_3 M40 PCIE_MTX_GRX_N3 C65 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N3
R62 1 2 GM@ 75_0402_5% TVC_DAC K25 M42 PCIE_MTX_GRX_N4 C66 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N4
TVC_DAC PEG_TX#_4 PCIE_MTX_GRX_N5 C67 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N5
PEG_TX#_5 R48 1 2
TV

H24 N38 PCIE_MTX_GRX_N6 C68 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N6

TV_RTN PEG_TX#_6 PCIE_MTX_GRX_N7 C69 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N7
T40 1 2
Layout Note: Place 150 Ω termination PEG_TX#_7
U37 PCIE_MTX_GRX_N8 C70 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N8
PEG_TX#_8 PCIE_MTX_GRX_N9 C71 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N9
resistors close to GMCH C31
PEG_TX#_9 U40
Y40 PCIE_MTX_GRX_N10 C72
1
1
2
2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N10
R63 TV_DCONSEL_0 PEG_TX#_10
1 2 GM@ 150_0402_1% GMCH_CRT_R E32 TV_DCONSEL_1 PEG_TX#_11 AA46 PCIE_MTX_GRX_N11 C73 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N11
R64 1 2 GM@ 150_0402_1% GMCH_CRT_G AA37 PCIE_MTX_GRX_N12 C74 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N12
B R65 PEG_TX#_12 B
1 2 GM@ 150_0402_1% GMCH_CRT_B
PEG_TX#_13 AA40 PCIE_MTX_GRX_N13 C75 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N13
AD43 PCIE_MTX_GRX_N14 C76 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N14
PEG_TX#_14 PCIE_MTX_GRX_N15 C77 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N15
PEG_TX#_15 AC46 1 2

GMCH_CRT_B E28 J42 PCIE_MTX_GRX_P0 C78 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P0

<26> GMCH_CRT_B CRT_BLUE PEG_TX_0
L46 PCIE_MTX_GRX_P1 C79 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P1
GMCH_CRT_G PEG_TX_1 PCIE_MTX_GRX_P2 C80 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P2
<26> GMCH_CRT_G G28 CRT_GREEN PEG_TX_2 M48 1 2
M39 PCIE_MTX_GRX_P3 C81 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P3
PEG_TX_3
VGA

GMCH_CRT_R J28 M43 PCIE_MTX_GRX_P4 C82 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P4

<26> GMCH_CRT_R CRT_RED PEG_TX_4
R47 PCIE_MTX_GRX_P5 C83 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P5
PEG_TX_5 PCIE_MTX_GRX_P6 C84 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P6
G29 CRT_IRTN PEG_TX_6 N37 1 2
T39 PCIE_MTX_GRX_P7 C85 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P7
GMCH_CRT_CLK H32 PEG_TX_7 PCIE_MTX_GRX_P8 C86 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P8
<26> GMCH_CRT_CLK CRT_DDC_CLK PEG_TX_8 U36 1 2
<26> GMCH_CRT_DATA GMCH_CRT_DATA J32 U39 PCIE_MTX_GRX_P9 C87 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P9
R66 CRT_DDC_DATA PEG_TX_9 PCIE_MTX_GRX_P10 C88 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P10
<26> GMCH_CRT_HSYNC J29 CRT_HSYNC PEG_TX_10 Y39 1 2
GM@ 30_0402_1% E29 Y46 PCIE_MTX_GRX_P11 C89 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P11
CRT_TVO_IREF PEG_TX_11 PCIE_MTX_GRX_P12 C90 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P12
AA36 1 2
20mil PEG_TX_12
AA39 PCIE_MTX_GRX_P13 C91 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P13
R67 GM@ 30_0402_1% PEG_TX_13 PCIE_MTX_GRX_P14 C92 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P14
<26> GMCH_CRT_VSYNC L29 CRT_VSYNC PEG_TX_14 AD42 1 2
AD46 PCIE_MTX_GRX_P15 C93 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P15
PEG_TX_15
1

change R64,R65 from 33ohm to 30ohm @ @

R68 R69 GM45@CANTIGA ES_FCBGA1329 PCIE_MTX_GRX_P3 C94 1 2 GM@ 0.1U_0402_10V7K TMDS_B_CLK <24>
by checklist2.0 & CRB1.0 05/08/08 0_0402_5% 0_0402_5% R70 PCIE_MTX_GRX_N3 C95 1 2 GM@ 0.1U_0402_10V7K TMDS_B_CLK# <24>
1.02K_0402_1% PCIE_MTX_GRX_P2 C96 1 2 GM@ 0.1U_0402_10V7K TMDS_B_DATA0 <24>
PCIE_MTX_GRX_N2 C97 1 2 GM@ 0.1U_0402_10V7K TMDS_B_DATA0# <24>
2

PCIE_MTX_GRX_P1 C98 1 2 GM@ 0.1U_0402_10V7K TMDS_B_DATA1 <24>

PCIE_MTX_GRX_N1 C99 1 2 GM@ 0.1U_0402_10V7K TMDS_B_DATA1# <24>
A
PCIE_MTX_GRX_P0 C100 1 2 GM@ 0.1U_0402_10V7K TMDS_B_DATA2 <24> A
PCIE_MTX_GRX_N0 C101 1 2 GM@ 0.1U_0402_10V7K TMDS_B_DATA2# <24>

For Cantiga:1.02kohm PCIE_GTX_C_MRX_P3 R71 1 2 GM@ 0_0402_5% TMDS_B_HPD# <24>

For Crestline:1.3kohm
For Calero: 255ohm
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2008/03/25 Deciphered Date 2008/04/ Title
Cantiga(3/6)-VGA/LVDS/TV
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB3/B4_LA4551P
Date: W ednesday, March 18, 2009 Sheet 10 of 53
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS_DAC_CRT
R72
1 2
+VCCP
VCC_AXF: 321.35mA

0.022U_0402_16V7K
0_0603_5%
(10UF*1, 1UF*1)

0.1U_0402_16V4Z
GM@ U3H
+1.05VS_DPLLA
1 1 1 R73 +VCCP
VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1) +V1.05VS_AXF

C102

C103
GM@ GM@ C838 U13 1 2 +VCCP
VTT_1

4.7U_0805_10V4Z

0.1U_0402_16V4Z
@ +3VS_DAC_CRT B27 T13 1
2 2 2 VCCA_CRT_DAC_1 VTT_2

220U_D2_4VM

10U_0805_10V4Z
A26 U12 1 MCK3225151YZF 1210 1 2
VCCA_CRT_DAC_2 VTT_3

10U_0805_10V4Z

1U_0603_10V4Z
T12 +
VTT_4 1 1
GM@

C106
C104

C105
VCCA_DAC_BG: 2.68mA (0.1UF*1, 0.01UF*1) U11 R75
VTT_5

C107
22U_0805_6.3VA T11 @ 1 1 0_0603_5%
VTT_6 2 2

C108

C109
CRT
+3VS_DAC_BG A25 U10
VCCA_DAC_BG VTT_7 2 2
T10
+3VS +3VS_DAC_BG VTT_8 GM@ GM@
D B25 VSSA_DAC_BG VTT_9 U9 D
T9 2 2
VTT_10
1R74 2 VTT_11 U8 +1.05VS_DPLLA
0.022U_0402_16V7K
0_0603_5% T8 VCC_SM_CK: 119.85mA
VTT_12 +1.05VS_DPLLB: 64.8mA
0.1U_0402_16V4Z

10U_0805_10V4Z

4.7U_0805_10V4Z
VTT
GM@ F47 U7
+1.05VS_DPLLA VCCA_DPLLA VTT_13 (470UF*1, 0.1UF*1) (10UF*1, 0.1UF*1)

C113
1 1 GM@ 1 T7 1 1
VTT_14
C112

+1.05VS_DPLLB L48 VCCA_DPLLB VTT_15 U6 +1.5V_SM_CK

+1.05VS_DPLLB
C110

C111

C114
GM@ GM@ T6 +1.5V
VTT_16 R76

PLL
AD1 U5 R77

0.47U_0402_6.3V6K
2 2 2 +1.05VS_HPLL VCCA_HPLL VTT_17 2 2
VTT_18 T5 1 2 +VCCP 1 2

0.1U_0402_16V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z
+1.05VS_MPLL AE1 V3 0_0805_5%
VCCA_MPLL VTT_19

10U_0805_10V4Z
U3 MCK3225151YZF 1210 1
+1.8V_TXLVDS VTT_20

C117
V2 1 1 1
VTT_21 GM@

C115

C118
A PEG A LVDS
J48 U2
VCCA_LVDS VTT_22

C116
1 T2
1000P_0402_50V7K VTT_23 2
J47 VSSA_LVDS VTT_24 V1
C120 U1 2 2 2
C102 C110 VTT_25 GM@ GM@
2
+1.5VS_PEG_BG: 0.414mA AD48 VCCA_PEG_BG
(0.1UF*1) +1.5VS_PEG_BG
R78 20 mils
+1.05VS_HPLL
+1.5VS 2 1 AA48
VCCA_PEG_PLL +1.05VS_HPLL: 24mA
0_0402_5% 0_0402_5% 0_0603_5% +1.05VS_PEGPLL
PM@ PM@ R79 (4.7UF*1, 0.1UF*1) +1.5VS_TVDAC +1.5VS
1 R80
C122 2 1 +VCCP
BLM18PG121SN1D_0603 2 1
0.1U_0402_16V4Z 0_0603_5%
2 POWER

0.022U_0402_16V7K

0.1U_0402_16V4Z

10U_0805_10V4Z
AR20 1 1 C126 GM@
VCCA_SM_1 C123 C124
AP20 1 1 1
+1.05VS_A_SM VCCA_SM_2
AN20 VCCA_SM_3
+VCCP

C126

C127

C128
R81 AR17 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z
VCCA_SM_4 2 2

A SM
1 2 AP17 VCCA_SM_5 2 2 2
VCCD_TVDAC: 58.696mA
VCCA_SM:720mA 1 0_0805_5% AN17 B22
VCCA_SM_6 VCC_AXF_1 +V1.05VS_AXF (0.1UF*1, 0.01UF*1)

AXF
(22UF*2, 4.7UF*1, 1UF*1) 1 1 1 AT16
VCCA_SM_7 VCC_AXF_2
B21 0_0402_5%
+ C129 4.7U_0805_10V4Z C131 AR16 A21
C132 C130 VCCA_SM_8 VCC_AXF_3 PM@ GM@ GM@ GM@
AP16
220U_D2_4VY_R15M 10U_0805_10V4Z 1U_0603_10V4Z VCCA_SM_9
C C
2 2 2 2

VCC_SM_CK_1 BF21 +1.5V_SM_CK +1.05VS_MPLL +1.8V_TXLVDS

SM CK
+1.05VS_A_SM_CK VCC_SM_CK_2 BH20 1.05VS_MPLL: 139.2mA 40 mils
VCCA_SM_CK: 220mA R82 VCC_SM_CK_3 BG20 (22UF*1, 0.1UF*1) R84
BF20 R83
(22UF*1, 2.2UF*1, 0.1UF*1) 2 1 AP28
VCC_SM_CK_4
2 1 1000P_0402_50V7K 2 1
VCCA_SM_CK_1 +VCCP +1.8V
1U_0402_6.3V4Z

1U_0603_10V4Z

0_0603_5% AN28 BLM18PG121SN1D_0603 0_0603_5%

VCCA_SM_CK_2
10U_0805_10V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z
AP25 C140 GM@ +1.8V_TXLVDS: 118.8mA
VCCA_SM_CK_3
1 1 1 1 AN25 1 1 1 1
VCCA_SM_CK_4 +1.8V_TXLVDS (22UF*1, 1000PF*1)
C133

C137

C141
AN24 K47 C135 C139 C140
VCCA_SM_CK_5 VCC_TX_LVDS
C134

A CK
GM@ GM@
C138

AM28
VCCA_SM_CK_NCTF_1 +3VS_HV 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z
AM26
2 2 2 2 VCCA_SM_CK_NCTF_2 2 2 2 2

0.1U_0402_16V4Z
AM25
VCCA_SM_CK_NCTF_3
AL25
VCCA_SM_CK_NCTF_4 VCC_HV_1
C35 1 0_0402_5%
AM24 B35 PM@
VCCA_SM_CK_NCTF_5 VCC_HV_2

C142
HV
AL24 A35
VCCA_SM_CK_NCTF_6 VCC_HV_3
AM23
VCCA_SM_CK_NCTF_7 2
AL23
VCCA_SM_CK_NCTF_8 +VCC_PEG
+3VS_TVDAC: 40mA VCC_PEG_1
V48 +VCCP
(0.1UF*1, 0.01UF*1 for VCC_PEG_2
U48
+1.05VS_PEGPLL
+1.5VS_PEG_PLL: 50mA +VCC_PEG

PEG
V47
GM@ each DAC) VCC_PEG_3
U47
(0.1UF*1)
+3VS R85 +3VS_TVDAC VCC_PEG_4 L1 R166 1
+3VS_TVDAC B24 VCCA_TV_DAC_1 VCC_PEG_5 U46 2
1 2 A24 1 2 +VCCP
VCCA_TV_DAC_2

10U_0805_10V4Z
TV BLM18PG121SN1D_0603 1 0_1206_5%

0.1U_0402_16V4Z

220U_D2_4VM
0_0603_5% 1

C143

C148
+
1 1 1 1

C146
C144 C145 VCC_HDA: 50mA +1.5VS A32 AH48 +VCC_DMI C147
VCC_HDA VCC_DMI_1
HDA

0.022U_0402_16V7K 0.1U_0402_16V4Z AF48

(0.1UF*1) VCC_DMI_2 2 2
DMI
AH47 VCC_DMI: 456mA 2.2U_0603_6.3V4Z
2 2 VCC_DMI_3 2 2
AG47
C144 GM@ GM@ VCC_DMI_4 (0.1UF*1) 0316 add
+1.5VS_TVDAC M25
VCCD_TVDAC
D TV/CRT

B +1.5VS_QDAC L28 VCCD_QDAC 20mils B

+VCCP
0_0402_5% +1.05VS_HPLL AF1
VCCD_HPLL
PM@ A8 +VCC_DMI
VTTLF1 R86
+1.05VS_PEGPLL AA47 L1
VCCD_PEG_PLL VTTLF2 +VCCP_D
VTTLF

AB2 2 1
VTTLF3 0_0805_5%

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

1U_0603_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z
+1.8V_LVDS M38 1 1 1
VCCD_LVDS_1
LVDS

L37 D3 @ R87 @ R88 1 1 1

VCCD_LVDS_2
C150

C151

C152

C153

C154

C155
+VCCP 2 1 2 1 2 1 +3VS_HV
10_0402_5% 0_0402_5%
2 2 2 CH751H-40PT_SOD323-2
GM45@ CANTIGA ES_FCBGA1329 2 2 2
+3VS
U3
0316 add

PM
PM@

U3

VCCD_QDAC: 48.363mA 1.8V_LVDS: 60.311111mA

+1.5VS_QDAC (0.1UF*1, 0.01UF*1) +1.8V_LVDS (1UF*1) GL40
GL40@
R89
R90
2 1 +1.5VS
1U_0402_6.3V4Z

10U_0805_10V4Z

0_0603_5% 2 1 +1.8V
0.1U_0402_16V4Z

10U_0805_10V4Z

0_0603_5%
1U_0603_10V4Z

1 1 1 1 1 GM@
C160
C156

C157

C158

C159

A A
GM@
2 2 2 2 2 GM@
GM@
GM@ C160

0_0603_5%
PM@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline GMCH (4/6)-VCC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom KIWB3/B4_LA4551P 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 17, 2009 Sheet 11 of 53
5 4 3 2 1
 5 4 3 2 1

U3F
+AXG_CORE

Check : power
1782mA VCC_AXG_NTCF_1
W28
AP33 VCC_SM_1 VCC_AXG_NCTF_2 V28
AN33 W26 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
VCC_SM_2 VCC_AXG_NCTF_3
+1.5V BH32 V26
VCC_SM_3 VCC_AXG_NCTF_4
BG32
VCC_SM_4 VCC_AXG_NCTF_5
W25 1 C164 1 C165 1 C166

10U_0805_10V4Z

0.01U_0402_16V7K
BF32 VCC_SM_5 VCC_AXG_NCTF_6 V25

220U_D2_4VM_R15
+VCCP BD32 W24
1 VCC_SM_6 VCC_AXG_NCTF_7
U3G 1 2 BC32 V24 GM@ GM@ GM@
VCC_SM_7 VCC_AXG_NCTF_8 2 2 2

C168

C162

C163
D + BB32 W23 D
VCC_SM_8 VCC_AXG_NCTF_9

VCC
AG34 VCC_1 BA32 VCC_SM_9 VCC_AXG_NCTF_10 V23
AC34 AY32 AM21 0.22U_0402_10V4Z
VCC_2 2 2 1 VCC_SM_10 VCC_AXG_NCTF_11
AB34 AW32 AL21
VCC_3 VCC_SM_11 VCC_AXG_NCTF_12
AA34 AV32 AK21
VCC_4 VCC_SM_12 VCC_AXG_NCTF_13
Y34 VCC_5 AU32 VCC_SM_13 VCC_AXG_NCTF_14 W21
V34 AT32 V21 C166

VCC CORE

SM
VCC_6 VCC_SM_14 VCC_AXG_NCTF_15
U34 VCC_7 AR32 VCC_SM_15 VCC_AXG_NCTF_16 U21
AM33 VCC_8 AP32 VCC_SM_16 VCC_AXG_NCTF_17 AM20
AK33 AN32 AK20
VCC_9 VCC_SM_17 VCC_AXG_NCTF_18
AJ33 VCC_10 BH31 VCC_SM_18 VCC_AXG_NCTF_19 W20
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z

AG33 BG31 U20

VCC_11 VCC_SM_19 VCC_AXG_NCTF_20
10U_0805_10V4Z

AF33 VCC_12 BF31 VCC_SM_20 VCC_AXG_NCTF_21 AM19 0_0603_5%

1 1 1 1 BG30 AL19 PM@
VCC_SM_21 VCC_AXG_NCTF_22
C170

C171

C172

BH29 AK19
VCC_SM_22 VCC_AXG_NCTF_23
C167

BG29 AJ19
VCC_SM_23 VCC_AXG_NCTF_24
AE33 VCC_13 BF29 VCC_SM_24 VCC_AXG_NCTF_25 AH19
2 2 2 2 AC33 BD29 AG19
VCC_14 VCC_SM_25 VCC_AXG_NCTF_26
AA33 VCC_15 BC29 VCC_SM_26 VCC_AXG_NCTF_27 AF19
Y33 BB29 AE19
VCC_16 VCC_SM_27 VCC_AXG_NCTF_28
W33 BA29 AB19
VCC_17 VCC_SM_28 VCC_AXG_NCTF_29

POWER
V33 AY29 AA19
VCC_18 VCC_SM_29 VCC_AXG_NCTF_30

GFX NCTF
U33 VCC_19 AW29 VCC_SM_30 VCC_AXG_NCTF_31 Y19
AH28 VCC_20 AV29 VCC_SM_31 VCC_AXG_NCTF_32 W19
AF28 AU29 V19
VCC_21 VCC_SM_32 VCC_AXG_NCTF_33
AC28 VCC_22 AT29 VCC_SM_33 VCC_AXG_NCTF_34 U19
AA28 AR29 AM17
VCC_23 VCC_SM_34 VCC_AXG_NCTF_35
AJ26 AP29 AK17
VCC_24 VCC_SM_35 VCC_AXG_NCTF_36
AG26 VCC_25 VCC_AXG_NCTF_37 AH17
AE26 VCC_26 VCC_AXG_NCTF_38 AG17
AC26 AF17
VCC_27 +VCCP VCC_AXG_NCTF_39
C
AH25
VCC_28 +VCCP
GM@ +AXG_CORE
BA36
VCC_SM_36/NC VCC_AXG_NCTF_40
AE17
C
AG25 VCC_29 BB24 VCC_SM_37/NC VCC_AXG_NCTF_41 AC17

VCC
AF25 @ BD16 AB17
VCC_30 J1 VCC_SM_38/NC VCC_AXG_NCTF_42
AG24 AM32 BB21 Y17
VCC_31 VCC_NCTF_1 VCC_SM_39/NC VCC_AXG_NCTF_43
AJ23 VCC_32 VCC_NCTF_2 AL32 1 1 2 2 AW16 VCC_SM_40/NC VCC_AXG_NCTF_44 W17
AH23 VCC_33 VCC_NCTF_3 AK32 AW13 VCC_SM_41/NC VCC_AXG_NCTF_45 V17
AF23 AJ32 AT13 AM16
VCC_34 VCC_NCTF_4 JUMP_43X118 VCC_SM_42/NC VCC_AXG_NCTF_46
T32 VCC_35 VCC_NCTF_5 AH32 VCC_AXG_NCTF_47 AL16
AG32 AK16

POWER
VCC_NCTF_6 VCC_AXG_NCTF_48
VCC_NCTF_7 AE32 VCC_AXG_NCTF_49 AJ16
AC32 AH16
VCC_NCTF_8 VCC_AXG_NCTF_50
VCC_NCTF_9 AA32 VCC_AXG_NCTF_51 AG16
Y32 AF16
VCC_NCTF_10 VCC_AXG_NCTF_52
VCC_NCTF_11 W32 Y26 VCC_AXG_1 VCC_AXG_NCTF_53 AE16
U32 AE25 AC16
VCC_NCTF_12 VCC_AXG_2 VCC_AXG_NCTF_54
AM30 AB25 AB16
VCC_NCTF_13 +AXG_CORE VCC_AXG_3 VCC_AXG_NCTF_55
AL30 AA25 AA16
VCC_NCTF_14 VCC_AXG_4 VCC_AXG_NCTF_56
AK30 AE24 Y16
VCC_NCTF_15 10U_0805_10V4Z 0.1U_0402_16V4Z VCC_AXG_5 VCC_AXG_NCTF_57
AH30 AC24 W16
VCC_NCTF_16 VCC_AXG_6 VCC_AXG_NCTF_58
AG30 AA24 V16
VCC_NCTF_17 VCC_AXG_7 VCC_AXG_NCTF_59
VCC_NCTF_18 AF30 1 Y24 VCC_AXG_8 VCC_AXG_NCTF_60 U16
AE30 GM@ 1 GM@ GM@ 1 GM@ 1 GM@ 1 AE23
VCC_NCTF_19 C173 C174 + C175 C176 C177 VCC_AXG_9
AC30 AC23
NCTF

VCC_NCTF_20 VCC_AXG_10
AB30 AB23
VCC_NCTF_21 1U_0603_10V4Z VCC_AXG_11
AA30 AA23
VCC_NCTF_22 2 2 2 2 2 VCC_AXG_12
Y30 AJ21
VCC_NCTF_23 VCC_AXG_13
W30 AG21
VCC_NCTF_24 220U_D2_4VM_R15 10U_0805_10V4Z VCC_AXG_14
VCC_NCTF_25 V30 AE21 VCC_AXG_15
U30 AC21
VCC_NCTF_26 VCC_AXG_16
VCC

AL29 AA21
VCC_NCTF_27 VCC_AXG_17
AK29 Y21
VCC_NCTF_28 VCC_AXG_18

VCC
AJ29 AH20
VCC_NCTF_29 VCC_AXG_19
AH29 AF20
B VCC_NCTF_30 C176 VCC_AXG_20 B
VCC_NCTF_31 AG29 AE20 VCC_AXG_21
VCC_NCTF_32 AE29 AC20 VCC_AXG_22
AC29 AB20
VCC_NCTF_33 VCC_AXG_23
AA29 AA20

GFX
VCC_NCTF_34 VCC_AXG_24
Y29 T17
VCC_NCTF_35 VCC_AXG_25
W29 T16
VCC_NCTF_36 VCC_AXG_26
VCC_NCTF_37
V29 0_0805_5% AM15
VCC_AXG_27
AL28 PM@ AL15
VCC_NCTF_38 VCC_AXG_28
AK28 AE15
VCC_NCTF_39 VCC_AXG_29
VCC_NCTF_40 AL26 AJ15 VCC_AXG_30
VCC_NCTF_41 AK26 AH15 VCC_AXG_31
AK25 AG15
VCC_NCTF_42 VCC_AXG_32
VCC_NCTF_43 AK24 AF15 VCC_AXG_33
AK23 AB15
VCC_NCTF_44 VCC_AXG_34
AA15 VCC_AXG_35
Y15
VCC_AXG_36
V15
VCC_AXG_37
U15
VCC_AXG_38
AN14
VCC_AXG_39
AM14
VCC_AXG_40
U14 AV44 VCCSM_LF1

VCC SM LF
VCC_AXG_41 VCC_SM_LF1
T14 VCC_AXG_42 VCC_SM_LF2 BA37 VCCSM_LF2
AM40 VCCSM_LF3
VCC_SM_LF3
GM45@ CANTIGA ES_FCBGA1329
VCC_SM_LF4 AV21 VCCSM_LF4
AY5 VCCSM_LF5
VCC_SM_LF5
T56 AJ14 AM10 VCCSM_LF6
VCC_AXG_SENSE VCC_SM_LF6
T57 AH14 VSS_AXG_SENSE VCC_SM_LF7 BB13 VCCSM_LF7

C179 0.1U_0402_16V4Z

C180 0.1U_0402_16V4Z

C181 0.22U_0402_10V4Z

C182 0.22U_0402_10V4Z

C183 0.47U_0402_6.3V6K

C184 1U_0402_6.3V4Z

C185 1U_0402_6.3V4Z
1 1 1 1 1 1 1

2 2 2 2 2 2 2
A A
GM45@ CANTIGA ES_FCBGA1329

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline GMCH (5/6)-VCC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom KIWB3/B4_LA4551P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 18, 2009 Sheet 12 of 53
5 4 3 2 1
 5 4 3 2 1

U3I U3J

AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8

AR48 AE36 L12 Y8
VSS_2 VSS_101 VSS_200 VSS_298
AL48 P36 AW21 L8
VSS_3 VSS_102 VSS_201 VSS_299
BB47 L36 AU21 E8
VSS_4 VSS_103 VSS_202 VSS_300
AW47 J36 AP21 B8
VSS_5 VSS_104 VSS_203 VSS_301
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
AJ47 VSS_7 VSS_106 B36 AH21 VSS_205 VSS_303 AU7
AF47 AH35 AF21 AN7
VSS_8 VSS_107 VSS_206 VSS_304
AD47 AA35 AB21 AJ7
VSS_9 VSS_108 VSS_207 VSS_305
AB47 VSS_10 VSS_109 Y35 R21 VSS_208 VSS_306 AE7
Y47 VSS_11 VSS_110 U35 M21 VSS_209 VSS_307 AA7
T47 VSS_12 VSS_111 T35 J21 VSS_210 VSS_308 N7
D D
N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
L47 VSS_14 VSS_113 AM34 BC20 VSS_212 VSS_310 BG6
G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6
BD46 AF34 AW20 AV6
VSS_16 VSS_115 VSS_214 VSS_312
BA46 AE34 AT20 AT6
VSS_17 VSS_116 VSS_215 VSS_313
AY46 VSS_18 VSS_117 W34 AJ20 VSS_216 VSS_314 AM6
AV46 B34 AG20 M6
VSS_19 VSS_118 VSS_217 VSS_315
AR46 VSS_20 VSS_119 A34 Y20 VSS_218 VSS_316 C6
AM46 VSS_21 VSS_120 BG33 N20 VSS_219 VSS_317 BA5
V46 BC33 K20 AH5
VSS_22 VSS_121 VSS_220 VSS_318
R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5
P46 AV33 C20 Y5
VSS_24 VSS_123 VSS_222 VSS_320
H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
F46 AL33 BG19 J5
VSS_26 VSS_125 VSS_224 VSS_322
BF44 AH33 A18 H5
VSS_27 VSS_126 VSS_225 VSS_323
AH44 AB33 BG17 F5
VSS_28 VSS_127 VSS_226 VSS_324
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
AA44 L33 AW17
VSS_30 VSS_129 VSS_228
Y44 VSS_31 VSS_130 H33 AT17 VSS_229 VSS_327 BC3
U44 N32 R17 AV3
VSS_32 VSS_131 VSS_230 VSS_328
T44 K32 M17 AL3
VSS_33 VSS_132 VSS_231 VSS_329
M44 F32 H17 R3
VSS_34 VSS_133 VSS_232 VSS_330
F44
BC43
VSS_35
VSS_36
VSS_134
VSS_135
C32
A31
C17 VSS_233 VSS VSS_331
VSS_332
P3
F3
AV43 AN29 BA16 BA2
VSS_37 VSS_136 VSS_235 VSS_333
AU43 VSS_38 VSS_137 T29 VSS_334 AW2
AM43 N29 AU16 AU2
VSS_39 VSS_138 VSS_237 VSS_335
J43 K29 AN16 AR2
VSS_40 VSS_139 VSS_238 VSS_336
C43 VSS_41 VSS_140 H29 N16 VSS_239 VSS_337 AP2
BG42
AY42
VSS_42
VSS_43
VSS VSS_141
VSS_142
F29
A29
K16
G16
VSS_240
VSS_241
VSS_338
VSS_339
AJ2
AH2
AT42 BG28 E16 AF2
C VSS_44 VSS_143 VSS_242 VSS_340 C
AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
AJ42 BA28 AC15 AD2
VSS_46 VSS_145 VSS_244 VSS_342
AE42 AV28 W15 AC2
VSS_47 VSS_146 VSS_245 VSS_343
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
BD41 AJ28 AA14 K2
VSS_50 VSS_149 VSS_248 VSS_346
AU41 VSS_51 VSS_150 AG28 C14 VSS_249 VSS_347 AM1
AM41 AE28 BG13 AA1
VSS_52 VSS_151 VSS_250 VSS_348
AH41 VSS_53 VSS_152 AB28 BC13 VSS_251 VSS_349 P1
AD41 Y28 BA13 H1
VSS_54 VSS_153 VSS_252 VSS_350
AA41 VSS_55 VSS_154 P28
Y41 K28 U24
VSS_56 VSS_155 VSS_351
U41 VSS_57 VSS_156 H28 AN13 VSS_255 VSS_352 U28
T41 F28 AJ13 U25
VSS_58 VSS_157 VSS_256 VSS_353
M41 C28 AE13 U29
VSS_59 VSS_158 VSS_257 VSS_354
G41 BF26 N13
VSS_60 VSS_159 VSS_258
B41 AH26 L13 AF32
VSS_61 VSS_160 VSS_259 VSS_NCTF_1
BG40 AF26 G13 AB32
VSS_62 VSS_161 VSS_260 VSS_NCTF_2
BB40 AB26 E13 V32
VSS_63 VSS_162 VSS_261 VSS_NCTF_3
AV40 VSS_64 VSS_163 AA26 BF12 VSS_262 VSS_NCTF_4 AJ30
AN40 C26 AV12 AM29
VSS_65 VSS_164 VSS_263 VSS_NCTF_5
H40 B26 AT12 AF29
VSS_66 VSS_165 VSS_264 VSS_NCTF_6
E40 BH25 AM12 AB29
VSS_67 VSS_166 VSS_265 VSS_NCTF_7
AT39 BD25 AA12 U26

VSS NCTF
VSS_68 VSS_167 VSS_266 VSS_NCTF_8
AM39 BB25 J12 U23
VSS_69 VSS_168 VSS_267 VSS_NCTF_9
AJ39 AV25 A12 AL20
VSS_70 VSS_169 VSS_268 VSS_NCTF_10
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_11 V20
N39 AJ25 BB11 AC19
VSS_72 VSS_171 VSS_270 VSS_NCTF_12
L39 AC25 AY11 AL17
VSS_73 VSS_172 VSS_271 VSS_NCTF_13
B39 Y25 AN11 AJ17
VSS_74 VSS_173 VSS_272 VSS_NCTF_14
BH38 N25 AH11 AA17
VSS_75 VSS_174 VSS_273 VSS_NCTF_15
BC38 L25 U17
B VSS_76 VSS_175 VSS_NCTF_16 B
BA38 VSS_77 VSS_176 J25 Y11 VSS_275
AU38 VSS_78 VSS_177 G25 N11 VSS_276
AH38 E25 G11 BH48
VSS_79 VSS_178 VSS_277 VSS_SCB_1
AD38 VSS_80 VSS_179 BF24 C11 VSS_278 VSS_SCB_2 BH1
AA38 AD12 BG10 A48
VSS_81 VSS_180 VSS_279 VSS_SCB_3
Y38 AY24 AV10 C1
VSS SCB

VSS_82 VSS_181 VSS_280 VSS_SCB_4

U38 AT24 AT10 A3
VSS_83 VSS_182 VSS_281 VSS_SCB_5
T38 AJ24 AJ10
VSS_84 VSS_183 VSS_282
J38 AH24 AE10
VSS_85 VSS_184 VSS_283
F38 VSS_86 VSS_185 AF24 AA10 VSS_284
C38 VSS_87 VSS_186 AB24 M10 VSS_285
BF37 R24 BF9 E1
VSS_88 VSS_187 VSS_286 NC_26
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_27 D2
AW37 K24 AN9 C3
VSS_90 VSS_189 VSS_288 NC_28
AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_29 B4
AN37 G24 AD9 A5
VSS_92 VSS_191 VSS_290 NC_30
AJ37 F24 G9 A6
VSS_93 VSS_192 VSS_291 NC_31
H37 E24 B9 A43
VSS_94 VSS_193 VSS_292 NC_32
C37 BH23 BH8 A44
VSS_95 VSS_194 VSS_293 NC_33
BG36 AG23 BB8 B45
VSS_96 VSS_195 VSS_294 NC_34
BD36 Y23 AV8 C46
NC

VSS_97 VSS_196 VSS_295 NC_35

AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_36 D47
AU36 A23 B47
VSS_99 VSS_198 NC_37
VSS_199 AJ6 NC_38 A46
F48
GM45@CANTIGA ES_FCBGA1329 NC_39
E48
NC_40
NC_41 C48
B48
NC_42

GM45@CANTIGA ES_FCBGA1329
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH (6/6)-GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom KIWB3/B4_LA4551P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 18, 2009 Sheet 13 of 53
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V

+V_DDR3_DIMM_REF
<9> DDR_A_DQS#[0..7]

<9> DDR_A_D[0..63] JP2

1 2
+1.5V VREF_DQ VSS1 DDR_A_D4
<9> DDR_A_DM[0..7] 3 4
DDR_A_D0 VSS2 DQ4 DDR_A_D5
5 DQ0 DQ5 6
DDR_A_D1 7 8
<9> DDR_A_DQS[0..7] DQ1 VSS3

1
9 10 DDR_A_DQS#0
R91 DDR_A_DM0 VSS4 DQS#0 DDR_A_DQS0
<9> DDR_A_MA[0..14] 11 12
100_0402_1% DM0 DQS0
13 VSS5 VSS6 14
+V_DDR3_DIMM_REF DDR_A_D2 15 16 DDR_A_D6
DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 18

2
D +V_DDR3_DIMM_REF DQ3 DQ7 D
<15> +V_DDR3_DIMM_REF 19 VSS7 VSS8 20
DDR_A_D8 21 22 DDR_A_D12
DQ8 DQ12

1
0.1U_0402_16V4Z
DDR_A_D9 23 24 DDR_A_D13
R92 DQ9 DQ13
1 25 26
DDR_A_DQS#1 VSS9 VSS10 DDR_A_DM1
27 28
DQS#1 DM1

C186
100_0402_1% DDR_A_DQS1 29 30 SM_DRAMRST#
DQS1 RESET# SM_DRAMRST# <8,15>
31 32

2
2 DDR_A_D10 VSS11 VSS12 DDR_A_D14
33 DQ10 DQ14 34
DDR_A_D11 35 36 DDR_A_D15
DQ11 DQ15
37 38
DDR_A_D16 VSS13 VSS14 DDR_A_D20
39 DQ16 DQ20 40
DDR_A_D17 41 42 DDR_A_D21
DQ17 DQ21
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2
47 48
+1.5V DQS2 VSS17 DDR_A_D22
49 50
FOR 3G ISSUE (SED) 20080826 DDR_A_D18 51
VSS18
DQ18
DQ22
DQ23 52 DDR_A_D23
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 60
C14 C15 C16 C17 C18 C19 DQ25 VSS21 DDR_A_DQS#3
61 62
DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J 63 DM3 DQS3 64
@ @ @ @ @ @ 65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 72
VSS25 VSS26

Layout Note: DDR_CKE0_DIMMA DDR_CKE1_DIMMA

<8> DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA <8>
Place near JP2 CKE0 CKE1
75 76
C VDD1 VDD2 C
77 NC1 A15 78
DDR_A_BS2 79 80 DDR_A_MA14
<9> DDR_A_BS2 BA2 A14
Layout Note: Place these 4 Caps near Command 81
VDD3 VDD4
82
DDR_A_MA12 83 84 DDR_A_MA11
and Control signals of DIMMA DDR_A_MA9 85
A12/BC# A11
86 DDR_A_MA7
A9 A7
87 88
+1.5V DDR_A_MA8 VDD5 VDD6 DDR_A_MA6
89 A8 A6 90
DDR_A_MA5 91 92 DDR_A_MA4
A5 A4
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
A3 A2
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1 1 1 1 1 1 1 1 1 1 99 100
VDD9 VDD10
C193

C194

C195

C196
C187

C188

C189

C190

C191

C192

+ C197 M_CLK_DDR0 101 102 M_CLK_DDR1

470U_D2_2.5VM_R15 <8> M_CLK_DDR0 M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1 M_CLK_DDR1 <8>
103 104 M_CLK_DDR#1 <8>
<8> M_CLK_DDR#0 CK0# CK1#
@ 105 106
2 2 2 2 2 2 2 2 2 2 2 DDR_A_MA10 VDD11 VDD12 DDR_A_BS1
107 108 DDR_A_BS1 <9>
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
<9> DDR_A_BS0 109 110 DDR_A_RAS# <9>
BA0 RAS#
111 112
DDR_A_WE# VDD13 VDD14 DDR_CS0_DIMMA#
113 114 DDR_CS0_DIMMA# <8>
<9> DDR_A_WE# DDR_A_CAS# WE# S0# M_ODT0
<9> DDR_A_CAS# 115 CAS# ODT0 116 M_ODT0 <8>
117 118
DDR_A_MA13 VDD15 VDD16 M_ODT1 +V_DDR3_DIMM_REF
119 120 M_ODT1 <8>
DDR_CS1_DIMMA# A13 ODT1
121 122
<8> DDR_CS1_DIMMA# S1# NC2 R95
123 124
VDD17 VDD18 DDR_VREF_CA_DIMMA
125 126 1 2
NCTEST VREF_CA
127 128
DDR_A_D32 VSS27 VSS28 DDR_A_D36 0_0402_5%
Layout Note: DDR_A_D33
129 DQ32 DQ36 130
DDR_A_D37
131 132
Place near JP2.203 & JP2.204 DQ33 DQ37
133 134
VSS29 VSS30

2.2U_0805_16V4Z

0.1U_0402_16V4Z
DDR_A_DQS#4 135 136 DDR_A_DM4
DDR_A_DQS4 DQS#4 DM4
137 138 1 1
DQS4 VSS31 DDR_A_D38
139 140
VSS32 DQ38

C198

C199
B DDR_A_D34 DDR_A_D39 B
141 DQ34 DQ39 142
+0.75V DDR_A_D35 143 144
DQ35 VSS33 DDR_A_D44 2 2
145 146
DDR_A_D40 VSS34 DQ44 DDR_A_D45
147 DQ40 DQ45 148
DDR_A_D41 149 150
DQ41 VSS35
1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

10U_0805_6.3V6M

151 152 DDR_A_DQS#5

DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 154
DM5 DQS5
2 2 2 2 1 155 156
DDR_A_D42 VSS37 VSS38 DDR_A_D46
157 158
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
1 1 1 1 2
C200

C201

C202

C203

C204

DDR_A_D48 163 164 DDR_A_D52

DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 168
DDR_A_DQS#6 VSS41 VSS42 DDR_A_DM6
169 DQS#6 DM6 170
DDR_A_DQS6 171 172
DQS6 VSS43 DDR_A_D54
173 174
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 176
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_A_D60
179 180
DDR_A_D56 VSS46 DQ60 DDR_A_D61
181 182
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 DM7 DQS7 188
189 190
DDR_A_D58 VSS49 VSS50 DDR_A_D62
191 192
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
1 R96 2 195 196
10K_0402_5% VSS51 VSS52 PM_EXTTS#0_1
197 198 PM_EXTTS#0 <8,15>
SA0 EVENT# CLK_SMBDATA
+3VS 199 200 CLK_SMBDATA <15,23>
VDDSPD SDA CLK_SMBCLK
201 202 CLK_SMBCLK <15,23>
SA1 SCL
2.2U_0603_6.3V4Z

1 1 203 VTT1 VTT2 204 +0.75V

1
10K_0402_5%

A A
0.1U_0402_16V4Z

C206
C205 205 206
G1 G2
R97

2 2 FOX _AS0A626-U2RN-7F_RV +0.75V DDR3 SO-DIMM A

REVERSE
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4601P
Date: Monday, April 27, 2009 Sheet 14 of 53
5 4 3 2 1
 5 4 3 2 1

<9> DDR_B_DQS#[0..7] +1.5V +1.5V

<9> DDR_B_D[0..63]
+V_DDR3_DIMM_REF

<9> DDR_B_DM[0..7] JP3

<9> DDR_B_DQS[0..7] <14> +V_DDR3_DIMM_REF 1 2
VREF_DQ VSS1 DDR_B_D4
3 VSS2 DQ4 4
DDR_B_D0 5 6 DDR_B_D5
<9> DDR_B_MA[0..14] DQ0 DQ5
DDR_B_D1 7 8
DQ1 VSS3 DDR_B_DQS#0
9 10
DDR_B_DM0 VSS4 DQS#0 DDR_B_DQS0
11 DM0 DQS0 12
13 VSS5 VSS6 14
Layout Note: DDR_B_D2 15 16 DDR_B_D6
D DDR_B_D3 DQ2 DQ6 DDR_B_D7 D
17 DQ3 DQ7 18
Place near JP3 19 20
DDR_B_D8 VSS7 VSS8 DDR_B_D12
21 DQ8 DQ12 22
Layout Note: Place these 4 Caps near Command DDR_B_D9 23 24 DDR_B_D13
DQ9 DQ13
and Control signals of DIMMA 25 26
DDR_B_DQS#1 VSS9 VSS10 DDR_B_DM1
27 DQS#1 DM1 28
DDR_B_DQS1 29 30 SM_DRAMRST#
+1.5V DQS1 RESET# SM_DRAMRST# <8,14>
31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 36
DQ11 DQ15
37 VSS13 VSS14 38

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_D16 39 40 DDR_B_D20
DQ16 DQ20
10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 DDR_B_D17 41 42 DDR_B_D21
DQ17 DQ21

C213

C214

C215

C216
C207

C208

C209

C210

C211

C212
43 44
+ C217 DDR_B_DQS#2 VSS15 VSS16 DDR_B_DM2
45 46
470U_D2_2.5VM_R15 DDR_B_DQS2 DQS#2 DM2
47 48
2 2 2 2 2 2 2 2 2 2 DQS2 VSS17 DDR_B_D22
@ 49 50
2 DDR_B_D18 VSS18 DQ22 DDR_B_D23
51 52
DDR_B_D19 DQ18 DQ23
53 DQ19 VSS19 54
55 56 DDR_B_D28
DDR_B_D24 VSS20 DQ28 DDR_B_D29
57 58
DDR_B_D25 DQ24 DQ29
59 60
DQ25 VSS21 DDR_B_DQS#3
61 VSS22 DQS#3 62
DDR_B_DM3 63 64 DDR_B_DQS3
DM3 DQS3
65 66
DDR_B_D26 VSS23 VSS24 DDR_B_D30
67 DQ26 DQ30 68
+1.5V DDR_B_D27 69 70 DDR_B_D31
FOR 3G ISSUE (SED) 20080826 71
DQ27
VSS25
DQ31
VSS26
72

DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
C <8> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <8> C
C22 C23 C24 C25 C20 C21 75 76
VDD1 VDD2
22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J 77 78
DDR_B_BS2 NC1 A15 DDR_B_MA14
@ @ @ @ @ @ <9> DDR_B_BS2 79 80
BA2 A14
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 86
A9 A7
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 94
DDR_B_MA3 VDD7 VDD8 DDR_B_MA2
Layout Note: DDR_B_MA1
95 A3 A2 96
DDR_B_MA0
97 98
Place near JP3.203 & JP3.204 A1 A0
99 VDD9 VDD10 100
M_CLK_DDR2 101 102 M_CLK_DDR3
<8> M_CLK_DDR2 M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3 M_CLK_DDR3 <8>
103 104 M_CLK_DDR#3 <8>
<8> M_CLK_DDR#2 CK0# CK1#
105 106
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
107 108 DDR_B_BS1 <9>
+0.75V DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
<9> DDR_B_BS0 109 110 DDR_B_RAS# <9>
BA0 RAS#
111 112
DDR_B_WE# VDD13 VDD14 DDR_CS2_DIMMB#
113 WE# S0# 114 DDR_CS2_DIMMB# <8>
<9> DDR_B_WE# DDR_B_CAS# M_ODT2
<9> DDR_B_CAS# 115 116 M_ODT2 <8>
CAS# ODT0
1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

10U_0805_6.3V6M

117 118
DDR_B_MA13 VDD15 VDD16 M_ODT3 +V_DDR3_DIMM_REF
119 120 M_ODT3 <8>
DDR_CS3_DIMMB# A13 ODT1
2 2 2 2 1 121 122
<8> DDR_CS3_DIMMB# S1# NC2 R98
123 124
VDD17 VDD18 DDR_VREF_CA_DIMMB
125 126 1 2 0_0402_5%
NCTEST VREF_CA
127 VSS27 VSS28 128
1 1 1 1 2
C218

C219

C220

C221

C222

DDR_B_D32 129 130 DDR_B_D36

DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 132
DQ33 DQ37
133 134
VSS29 VSS30

2.2U_0805_16V4Z

0.1U_0402_16V4Z
DDR_B_DQS#4 135 136 DDR_B_DM4
DDR_B_DQS4 DQS#4 DM4
137 138 1 1
B DQS4 VSS31 DDR_B_D38 B
139 VSS32 DQ38 140

C223

C224
DDR_B_D34 141 142 DDR_B_D39
DDR_B_D35 DQ34 DQ39
143 144
DQ35 VSS33 DDR_B_D44 2 2
145 VSS34 DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 150
DQ41 VSS35 DDR_B_DQS#5
151 152
DDR_B_DM5 VSS36 DQS#5 DDR_B_DQS5
153 154
DM5 DQS5
155 156
DDR_B_D42 VSS37 VSS38 DDR_B_D46
157 DQ42 DQ46 158
DDR_B_D43 159 160 DDR_B_D47
DQ43 DQ47
161 162
DDR_B_D48 VSS39 VSS40 DDR_B_D52
163 DQ48 DQ52 164
DDR_B_D49 165 166 DDR_B_D53
DQ49 DQ53
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS#6 DM6
171 172
DQS6 VSS43 DDR_B_D54
173 174
DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 176
DDR_B_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_B_D60
179 180
DDR_B_D56 VSS46 DQ60 DDR_B_D61
181 DQ56 DQ61 182
DDR_B_D57 183 184
DQ57 VSS47 DDR_B_DQS#7
185 VSS48 DQS#7 186
DDR_B_DM7 187 188 DDR_B_DQS7
DM7 DQS7
189 190
DDR_B_D58 VSS49 VSS50 DDR_B_D62
191 DQ58 DQ62 192
DDR_B_D59 193 194 DDR_B_D63
1 R99 2 195
DQ59
VSS51
DQ63
VSS52
196 same with intel DDR3 CRB connection
10K_0402_5% 197 198 PM_EXTTS#0_1
SA0 EVENT# PM_EXTTS#0 <8,14>
199 200 CLK_SMBDATA
+3VS VDDSPD SDA CLK_SMBCLK CLK_SMBDATA <14,23>
201 SA1 SCL 202 CLK_SMBCLK <14,23>
A A
0.1U_0402_16V4Z

1 2 203 204
1
R100
10K_0402_5% 205
VTT1 VTT2
206
+0.75V
DDR3 SO-DIMM B
2
C225 G1 G2
FOX_AS0A626-UARN-7F _RV +0.75V
REVERSE

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4601P
Date: Monday, April 27, 2009 Sheet 15 of 53
5 4 3 2 1
 5 4 3 2 1

U50A

PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P0 AP17 Part 1 of 7 K1

<10> PCIE_MTX_C_GRX_N[0..15] PEX_RX0 GPIO0
PCIE_MTX_C_GRX_N0 AN17 K2 HDMI_DETECT_VGA <24>
PCIE_MTX_C_GRX_P[0..15] PCIE_MTX_C_GRX_P1 PEX_RX0_N GPIO1 NV_INVTPWM
<10> PCIE_MTX_C_GRX_P[0..15] AN19 K3 PAD T84
PCIE_MTX_C_GRX_N1 PEX_RX1 GPIO2 VGA_ENVDD
AP19 H3 VGA_ENVDD <25>
PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_P2 PEX_RX1_N GPIO3 VGA_ENBKL
<10> PCIE_GTX_C_MRX_N[0..15] AR19 H2 @
VGA_ENBKL <25>
PCIE_MTX_C_GRX_N2 PEX_RX2 GPIO4 GPU_VID0
AR20 H1 GPU_VID0 <49>
PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P3 PEX_RX2_N GPIO5 GPU_VID1
<10> PCIE_GTX_C_MRX_P[0..15] AP20 H4 GPU_VID1 <49>
PCIE_MTX_C_GRX_N3 PEX_RX3 GPIO6
AN20 H5
PCIE_MTX_C_GRX_P4 PEX_RX3_N GPIO7
AN22 H6

1
PCIE_MTX_C_GRX_N4 PEX_RX4 GPIO8
AP22 J7
PCIE_MTX_C_GRX_P5 PEX_RX4_N GPIO9 PM@ PM@
AR22 K4
PCIE_MTX_C_GRX_N5 PEX_RX5 GPIO10 R1066 R1067
AR23 K5 1 2
PCIE_MTX_C_GRX_P6 PEX_RX5_N GPIO11 R1068 PM@ 10K_0402_5%
AP23 H7

GPIO
PCIE_MTX_C_GRX_N6 PEX_RX6 GPIO12 10K_0402_5% 10K_0402_5%
AN23 J4

2
PCIE_MTX_C_GRX_P7 PEX_RX6_N GPIO13
AN25 J6 1 2
PCIE_MTX_C_GRX_N7 PEX_RX7 GPIO14 R1069 PM@ 10K_0402_5%
AP25 L1
D
PCIE_MTX_C_GRX_P8 PEX_RX7_N GPIO15 D
AR25 L2
PCIE_MTX_C_GRX_N8 PEX_RX8 GPIO16
AR26 L4 PAD T85
PCIE_MTX_C_GRX_P9 PEX_RX8_N GPIO17
AP26 M4
PCIE_MTX_C_GRX_N9 PEX_RX9 GPIO18
AN26 L7 @
PCIE_MTX_C_GRX_P10 PEX_RX9_N GPIO19
AN28
PEX_RX10 GPIO20
L5 GPIO6 GPIO5 N10M-GS N10P-GS
PCIE_MTX_C_GRX_N10 AP28 K6
PCIE_MTX_C_GRX_P11 PEX_RX10_N GPIO21
AR28
PEX_RX11 GPIO22
L6 GPU_VID1 GPU_VID0 VGA_CORE P-State
PCIE_MTX_C_GRX_N11 AR29 M6
PCIE_MTX_C_GRX_P12 PEX_RX11_N GPIO23
AP29
PEX_RX12 0 0 0.8V 12
PCIE_MTX_C_GRX_N12 AN29
PCIE_MTX_C_GRX_P13 PEX_RX12_N
AN31
PEX_RX13 MIOA_D0
N1 0 1 0.85V 12
PCIE_MTX_C_GRX_N13 AP31 P4
PCIE_MTX_C_GRX_P14 PEX_RX13_N MIOA_D1
AR31
PEX_RX14 MIOA_D2
P1 1 1 0.9V 0, 10
PCIE_MTX_C_GRX_N14 AR32 P2
PCIE_MTX_C_GRX_P15 PEX_RX14_N MIOA_D3
AR34 P3
PCIE_MTX_C_GRX_N15 PEX_RX15 MIOA_D4
AP34 T3
PEX_RX15_N MIOA_D5
T2
MIOA_D6
T1

PCI EXPRESS
PCIE_GTX_C_MRX_P0 C226 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_P0 MIOA_D7
1 2 AL17 U4
PCIE_GTX_C_MRX_N0 C227 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_N0 PEX_TX0 MIOA_D8
1 2 AM17 U1
PCIE_GTX_C_MRX_P1 C228 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_P1 PEX_TX0_N MIOA_D9
1 2 AM18 U2
PCIE_GTX_C_MRX_N1 C230 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_N1 PEX_TX1 MIOA_D10
1 2 AM19 U3
PCIE_GTX_C_MRX_P2 C231 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_P2 PEX_TX1_N MIOA_D11
1 2 AL19 R6
PCIE_GTX_C_MRX_N2 C232 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_N2 PEX_TX2 MIOA_D12
1 2 AK19 T6

DVO
PCIE_GTX_C_MRX_P3 C233 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_P3 PEX_TX2_N MIOA_D13
1 2 AL20 N6
PCIE_GTX_C_MRX_N3 C234 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_N3 PEX_TX3 MIOA_D14
1 2 AM20
PCIE_GTX_C_MRX_P4 C235 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_P4 PEX_TX3_N
1 2 AM21 Y1
PCIE_GTX_C_MRX_N4 C236 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_N4 PEX_TX4 MIOB_D0
1 2 AM22 Y2
PCIE_GTX_C_MRX_P5 C237 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_P5 PEX_TX4_N MIOB_D1
1 2 AL22 Y3
PCIE_GTX_C_MRX_N5 C238 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_N5 PEX_TX5 MIOB_D2
1 2 AK22 AB3
PCIE_GTX_C_MRX_P6 C239 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_P6 PEX_TX5_N MIOB_D3
1 2 AL23 AB2
PCIE_GTX_C_MRX_N6 C240 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_N6 PEX_TX6 MIOB_D4
1 2 AM23 AB1
PCIE_GTX_C_MRX_P7 C241 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_P7 PEX_TX6_N MIOB_D5
1 2 AM24 AC4
PCIE_GTX_C_MRX_N7 C242 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_N7 PEX_TX7 MIOB_D6
1 2 AM25 AC1
PCIE_GTX_C_MRX_P8 C243 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_P8 PEX_TX7_N MIOB_D7
1 2 AL25 AC2
PCIE_GTX_C_MRX_N8 C248 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_N8 PEX_TX8 MIOB_D8
1 2 AK25 AC3
PCIE_GTX_C_MRX_P9 C249 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_P9 PEX_TX8_N MIOB_D9
1 2 AL26 AE3
PCIE_GTX_C_MRX_N9 C250 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_N9 PEX_TX9 MIOBD_10
C 1 2 AM26 AE2 C
+VCCP +PLLVDD PCIE_GTX_C_MRX_P10 C251 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_P10 PEX_TX9_N MIOB_D11
1 2 AM27 U6
L508 MBK1608121YZF_0603 PCIE_GTX_C_MRX_N10 C252 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_N10 PEX_TX10 MIOB_D12
1 2 AM28 W6
1U_0603_10V4Z PCIE_GTX_C_MRX_P11 C253 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_P11 PEX_TX10_N MIOB_D13
1 2 1 2 AL28 Y6
PM@ PCIE_GTX_C_MRX_N11 C254 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_N11 PEX_TX11 MIOB_D14
1 2 AK28
PM@ PM@ PM@ PCIE_GTX_C_MRX_P12 C255 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_P12 PEX_TX11_N
1 2 AK29 N3
C1155 C1156 C1157 PCIE_GTX_C_MRX_N12 C256 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_N12 PEX_TX12 MIOA_HSYNC
1 2 AL29 L3
PCIE_GTX_C_MRX_P13 C257 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_P13 PEX_TX12_N MIOA_VSYNC
NEAR GPU PCIE_GTX_C_MRX_N13
1 2
PCIE_GTX_MRX_N13
AM29
PEX_TX13
C258 1 2 PM@ 0.1U_0402_16V7K AM30 W1
1U_0603_10V4Z 1U_0603_10V4Z PCIE_GTX_C_MRX_P14 C259 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_P14 PEX_TX13_N MIOB_HSYNC
1 2 AM31 W2
PCIE_GTX_C_MRX_N14 C260 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_N14 PEX_TX14 MIOB_VSYNC
1 2 AM32
PCIE_GTX_C_MRX_P15 C262 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_P15 PEX_TX14_N
1 2 AN32 N2
PM@ PEX_TX15 MIOA_DE
1 PM@ PCIE_GTX_C_MRX_N15 C263 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_MRX_N15 AP32
PEX_TX15_N MIOA_CTL3
P5
C1158 C1159 N5
0.1U_0402_16V4Z MIOA_VREF
4700P_0402_16V7K +3VS
2 UNDER GPU MIOB_DE
Y5
<23> CLK_PCIE_VGA AR16 W3
PEX_REFCLK MIOB_CTL3
<23> CLK_PCIE_VGA# AR17 AF1
PEX_REFCLK_N MIOB_VREF
2 1 AR13
10K_0402_5% PM@ R1079 PEX_CLKREQ_N 10K_0402_5%
N4 2 PM@ 1 R1081
MIOA_CLKIN
AJ17 R4
PEX_TSTCLK_OUT MIOA_CLKOUT
1 2 AJ18
R1082 @ 200_0402_5% PEX_TSTCLK_OUT_N 10K_0402_5%
AE1 2 PM@ 1 R1083
MIOB_CLKIN
V4
+VCCP +SP_PLLVDD PLT_RST# MIOB_CLKOUT
<8,27,31,32> PLT_RST# AM16
L510 PM@ PEX_RST_N
2 1 AG21 T4
1

1U_0603_10V4Z 4700P_0402_16V7K R1084 PM@ 2.49K_0402_1% PEX_TERMP MIOA_CLKOUT_N

1 2 W4
MBK1608121YZF_0603 R1085 MIOB_CLKOUT_N
1
PM@ PM@ PM@ 10K_0402_5% U5
C1164 C1165 C1166 @ MIOACAL_PD_VDDQ
AE9 T5
+PLLVDD PLLVDD 60mA MIOACAL_PU_GND
2

2 AF9 AA7
0.1U_0402_16V4Z
+SP_PLLVDD SP_PLLVDD 45mA MIOBCAL_PD_VDDQ
AA6
MIOBCAL_PU_GND
AD9
VID_PLLVDD 45mA

CLK
XTALIN B1
CRT OUT
XTALIN XTALOUT XTAL_IN VGA_CRT_R VGA_CRT_R R1086 1 PM@
B2 AM15 VGA_CRT_R <26> 2 150_0402_1%
XTAL_OUT DACA_RED VGA_CRT_G VGA_CRT_G R1087 1 PM@
AM14 VGA_CRT_G <26> 2 150_0402_1%
B
Y9 XTAL_OUTBUFF DACA_GREEN VGA_CRT_B VGA_CRT_B R1088 1 PM@
B
D1 AL14 VGA_CRT_B <26> 2 150_0402_1%
XTALOUT XTAL_SSIN XTAL_OUTBUFF DACA_BLUE
4 3 D2
GND OUT XTAL_SSIN VGA_HSYNC +DACA_VDD
AM13 VGA_HSYNC <26>
DACA_HSYNC VGA_VSYNC +3VS
1 2 1 AL13 VGA_VSYNC <26>
IN GND PM@ DACA_VSYNC PM@
1
PM@ C1167 EC_SMB_CK2 E2 AJ12 +DACA_VDD 470P_0402_50V7K 1 2
<5,38,42> EC_SMB_CK2 I2CS_SCL DACA_VDD
C1168 27MHZ_16PF_X7T027000BG1H-V 20P_0402_50V8 PULL UP BY EC SIDE EC_SMB_DA2 E1 AK12 DACA_VREF 1 1 2 L509 MBK1608121YZF_0603
20P_0402_50V8 2 <5,38,42> EC_SMB_DA2 I2CS_SDA DACA_VREF DACA_RSET PM@ PM@ PM@

DACs
AK13
2 VGA_LVDS_SCL_C DACA_RSET C1160 C1161 C1162
PM@ E3 1
VGA_LVDS_SDA_C I2CC_SCL PM@ PM@ 4.7U_0603_6.3V6M
+3VS PULL UP BY VGA SIDE E4
I2CC_SDA DACB_RED
AK4
R1093 C1163 2 2 1
AL4
R1092 PM@ 2.2K_0402_5% VGA_HDMI_SCL_R DACB_GREEN 124_0402_1% 0.1U_0402_16V4Z 4700P_0402_16V7K
G3 AJ4
PM@ VGA_HDMI_SDA_R I2CB_SCL DACB_BLUE 2
G2

I2C
+3VS I2CB_SDA
1 R1091 2.2K_0402_5% AM1
PM@ VGA_DDCCLK_C DACB_HSYNC
G1 AM2
1

C1121 VGA_DDCDATA_C I2CA_SCL DACB_VSYNC

PULL UP BY RGB SIDE G4
0.1U_0402_16V4Z @ PM@ PM@ I2CA_SDA +DACB_VDD R1094 2 PM@
AG7 1 10K_0402_5%
2 R1072 R1071 R1070 HDCP_I2CH_SCL DACB_VDD
F6 AK6
U51 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5% HDCP_I2CH_SDA I2CH_SCL DACB_VREF DACB_RSET R793 1
G6 AH7 2 10K_0402_5%
I2CH_SDA DACB_RSET @
1 8
2

A0 VCC
2 7
A1 WP HDCP_I2CH_SCL
3 6
A2 SCL HDCP_I2CH_SDA N10P-GS-A1_BGA969
4 5
GND SDA 10M@
1

AT24C16AN-10SU-2.7_SO8
PM@ PM@ @
R1074 R1073 External Spread Spectrum OSC_OUT R1075 1 2 @ 22_0402_5% XTAL_OUTBUFF
100K_0402_1% 2.2K_0402_5%

1
PM@
2

U52 R1077
1 6 10K_0402_5%
REFOUT VSS
2 5 OSC_SPREAD

2
XOUT MODOUT
PM@ OSC_OUT 3 4 +3VS
MBK1608121YZF_0603 2 L517 VGA_DDCCLK_C XIN/CLKIN VDD OSC_SPREAD R1179 1 XTAL_SSIN
<26> VGA_DDCCLK 1 1 2 @ 22_0402_5%
<26> VGA_DDCDATA MBK1608121YZF_0603 2 L518
1 VGA_DDCDATA_C @

1
A PM@ @ ASM3P2872AF-06OR_TSOT-23-6 C1147 A
PM@ 0.1U_0402_16V4Z PM@
MBK1608121YZF_0603 2 L519
1 VGA_LVDS_SCL_C 2 R1178
<25> VGA_LVDS_SCL
<25> VGA_LVDS_SDA MBK1608121YZF_0603 2 L520
1 VGA_LVDS_SDA_C 10K_0402_5%
PM@

2
1
C247
1
C246
1
C245
1
C244 If External Spread Spectrum not stuff then stuff resistor
PM@ PM@ PM@ PM@
12P_0402_50V8J 12P_0402_50V8J R110 R109
2 2 2 2
12P_0402_50V8J
2.2K_0402_5%
12P_0402_50V8J PM@
2.2K_0402_5%
PM@
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2008/03/25 Deciphered Date 2008/04/ Title

+3VS
N10x-GS PCIE,LVDS,GPIO,CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NIWBA_LA5371P
Date: Wednesday, March 18, 2009 Sheet 16 of 53
5 4 3 2 1
 5 4 3 2 1

FBA_CMD[0..30]
FBA_CMD[0..30] <21>
FBA_DQM[0..7] FBC_CMD[0..30]
FBA_DQM[0..7] <21> FBC_CMD[0..30] <22>
FBA_DQS[0..7] FBC_DQM[0..7]
FBA_DQS[0..7] <21> FBC_DQM[0..7] <22>
FBA_DQS#[0..7] FBC_DQS[0..7]
FBA_DQS#[0..7] <21> FBC_DQS[0..7] <22>
FBA_D[0..63] FBC_DQS#[0..7]
FBA_D[0..63] <21> FBC_DQS#[0..7] <22>
UPDATE 0216 FBC_D[0..63] UPDATE 0216
FBC_D[0..63] <22>
U50B
R1095 10K_0402_5% U50C R1100 10K_0402_5%
Part 2 of 7 V32 FBA_CMD0 FBA_CMD7 1 2 PM@ FBC_CMD7 1 2 PM@
D FBA_D0 FBA_CMD0 FBA_CMD1 Part 3 of 7 D
L32 FBA_D0 FBA_CMD1 W31
FBA_D1 N33 U31 FBA_CMD2 FBC_D0 B13 C17 FBC_CMD0
FBA_D2 FBA_D1 FBA_CMD2 FBA_CMD3 R1101 10K_0402_5% FBC_D1 FBC_D0 FBC_CMD0 FBC_CMD1 R1102 10K_0402_5%
L33 FBA_D2 FBA_CMD3 Y32 D13 FBC_D1 FBC_CMD1 B19
FBA_D3 N34 AB35 FBA_CMD4 FBA_CMD15 1 2 PM@ FBC_D2 A13 D18 FBC_CMD2 FBC_CMD15 1 2 PM@
FBA_D4 FBA_D3 FBA_CMD4 FBA_CMD5 FBC_D3 FBC_D2 FBC_CMD2 FBC_CMD3
N35 AB34 A14 F21
FBA_D5 FBA_D4 FBA_CMD5 FBA_CMD6 FBC_D4 FBC_D3 FBC_CMD3 FBC_CMD4
P35 FBA_D5 FBA_CMD6 W35 C16 FBC_D4 FBC_CMD4 A23
FBA_D6 P33 W33 FBA_CMD7 R1096 10K_0402_5% FBC_D5 B16 D21 FBC_CMD5 R1097 10K_0402_5%
FBA_D7 FBA_D6 FBA_CMD7 FBA_CMD8 FBA_CMD18 FBC_D6 FBC_D5 FBC_CMD5 FBC_CMD6 FBC_CMD18
P34 FBA_D7 FBA_CMD8 W30 1 2 PM@ A17 FBC_D6 FBC_CMD6 B23 1 2 PM@
FBA_D8 K35 T34 FBA_CMD9 FBC_D7 D16 E20 FBC_CMD7
FBA_D9 FBA_D8 FBA_CMD9 FBA_CMD10 FBC_D8 FBC_D7 FBC_CMD7 FBC_CMD8
K33 T35 C13 G21
FBA_D10 FBA_D9 FBA_CMD10 FBA_CMD11 R1098 10K_0402_5% FBC_D9 FBC_D8 FBC_CMD8 FBC_CMD9 R1103 10K_0402_5%
K34 FBA_D10 FBA_CMD11 AB31 B11 FBC_D9 FBC_CMD9 F20
FBA_D11 H33 Y30 FBA_CMD12 FBA_CMD28 1 2 PM@ FBC_D10 C11 F19 FBC_CMD10 FBC_CMD28 1 2 PM@
FBA_D12 FBA_D11 FBA_CMD12 FBA_CMD13 FBC_D11 FBC_D10 FBC_CMD10 FBC_CMD11
G34 FBA_D12 FBA_CMD13 Y34 A11 FBC_D11 FBC_CMD11 F23
FBA_D13 G33 W32 FBA_CMD14 FBC_D12 C10 A22 FBC_CMD12
FBA_D14 FBA_D13 FBA_CMD14 FBA_CMD15 R1099 10K_0402_5% FBC_D13 FBC_D12 FBC_CMD12 FBC_CMD13 R1104 10K_0402_5%
E34 AA30 C8 C22
FBA_D15 FBA_D14 FBA_CMD15 FBA_CMD16 FBA_CMD30 FBC_D14 FBC_D13 FBC_CMD13 FBC_CMD14 FBC_CMD30
E33 AA32 1 2 PM@ B8 B17 1 2 PM@
FBA_D16 FBA_D15 FBA_CMD16 FBA_CMD17 FBC_D15 FBC_D14 FBC_CMD14 FBC_CMD15
G31 FBA_D16 FBA_CMD17 Y33 A8 FBC_D15 FBC_CMD15 F24
FBA_D17 F30 U32 FBA_CMD18 FBC_D16 E8 C25 FBC_CMD16
FBA_D18 FBA_D17 FBA_CMD18 FBA_CMD19 FBC_D17 FBC_D16 FBC_CMD16 FBC_CMD17
G30 FBA_D18 FBA_CMD19 Y31 F8 FBC_D17 FBC_CMD17 E22
FBA_D19 G32 U34 FBA_CMD20 FBC_D18 F10 C20 FBC_CMD18
FBA_D20 FBA_D19 FBA_CMD20 FBA_CMD21 FBC_D19 FBC_D18 FBC_CMD18 FBC_CMD19
K30 Y35 F9 B22
FBA_D21 FBA_D20 FBA_CMD21 FBA_CMD22 FBC_D20 FBC_D19 FBC_CMD19 FBC_CMD20
K32 W34 F12 A19
FBA_D22 FBA_D21 FBA_CMD22 FBA_CMD23 FBC_D21 FBC_D20 FBC_CMD20 FBC_CMD21
H30 FBA_D22 FBA_CMD23 V30 D8 FBC_D21 FBC_CMD21 D22
FBA_D23 K31 U35 FBA_CMD24 FBC_D22 D11 D20 FBC_CMD22
FBA_D24 FBA_D23 FBA_CMD24 FBA_CMD25 FBC_D23 FBC_D22 FBC_CMD22 FBC_CMD23
L31 U30 E11 E19
FBA_D25 FBA_D24 FBA_CMD25 FBA_CMD26 FBC_D24 FBC_D23 FBC_CMD23 FBC_CMD24
L30 FBA_D25 FBA_CMD26 U33 D12 FBC_D24 FBC_CMD24 D19
FBA_D26 M32 AB30 FBA_CMD27 FBC_D25 E13 F18 FBC_CMD25

MEMORY INTERFACE
FBA_D27 FBA_D26 FBA_CMD27 FBA_CMD28 FBC_D26 FBC_D25 FBC_CMD25 FBC_CMD26
N30 AB33 F13 C19

MEMORY INTERFACE C
FBA_D28 FBA_D27 FBA_CMD28 FBA_CMD29 FBC_D27 FBC_D26 FBC_CMD26 FBC_CMD27
M30 FBA_D28 FBA_CMD29 T33 F14 FBC_D27 FBC_CMD27 F22
FBA_D29 P31 W29 FBA_CMD30 FBC_D28 F15 C23 FBC_CMD28
FBA_D30 FBA_D29 FBA_CMD30 FBC_D29 FBC_D28 FBC_CMD28 FBC_CMD29
R32 E16 B20
FBA_D31 FBA_D30 FBC_D30 FBC_D29 FBC_CMD29 FBC_CMD30
R30 F16 A20
C FBA_D32 FBA_D31 FBC_D31 FBC_D30 FBC_CMD30 C
AG30 FBA_D32 F17 FBC_D31
FBA_D33 AG32 P32 FBA_DQM0 FBC_D32 D29
FBA_D34 FBA_D33 FBA_DQM0 FBA_DQM1 FBC_D33 FBC_D32
AH31 H34 F27
FBA_D35 FBA_D34 FBA_DQM1 FBA_DQM2 FBC_D34 FBC_D33 FBC_DQM0
AF31 FBA_D35 FBA_DQM2 J30 F28 FBC_D34 FBC_DQM0 A16
FBA_D36 AF30 P30 FBA_DQM3 FBC_D35 E28 D10 FBC_DQM1
FBA_D37 FBA_D36 FBA_DQM3 FBA_DQM4 FBC_D36 FBC_D35 FBC_DQM1 FBC_DQM2
AE30 AF32 D26 F11
FBA_D38 FBA_D37 FBA_DQM4 FBA_DQM5 FBC_D37 FBC_D36 FBC_DQM2 FBC_DQM3
AC32 FBA_D38 FBA_DQM5 AL32 F25 FBC_D37 FBC_DQM3 D15
FBA_D39 AD30 AL34 FBA_DQM6 FBC_D38 D24 D27 FBC_DQM4
FBA_D40 FBA_D39 FBA_DQM6 FBA_DQM7 FBC_D39 FBC_D38 FBC_DQM4 FBC_DQM5
AN33 FBA_D40 FBA_DQM7 AF35 E25 FBC_D39 FBC_DQM5 D34
FBA_D41 AL31 FBC_D40 E32 A34 FBC_DQM6
FBA_D41 FBC_D40 FBC_DQM6
A

FBA_D42 AM33 FBC_D41 F32 D28 FBC_DQM7

FBA_D43 FBA_D42 FBC_D42 FBC_D41 FBC_DQM7
AL33 D33
FBA_D44 FBA_D43 FBA_DQS#0 FBC_D43 FBC_D42
AK30 FBA_D44 FBA_DQS_RN0 L35 E31 FBC_D43
FBA_D45 AK32 G35 FBA_DQS#1 FBC_D44 C33 B14 FBC_DQS#0
FBA_D46 FBA_D45 FBA_DQS_RN1 FBA_DQS#2 FBC_D45 FBC_D44 FBC_DQS_RN0 FBC_DQS#1
AJ30 H31 F29 B10
FBA_D47 FBA_D46 FBA_DQS_RN2 FBA_DQS#3 FBC_D46 FBC_D45 FBC_DQS_RN1 FBC_DQS#2
AH30 N32 D30 D9
FBA_D48 FBA_D47 FBA_DQS_RN3 FBA_DQS#4 FBC_D47 FBC_D46 FBC_DQS_RN2 FBC_DQS#3
AH33 AD32 E29 E14
FBA_D49 FBA_D48 FBA_DQS_RN4 FBA_DQS#5 FBC_D48 FBC_D47 FBC_DQS_RN3 FBC_DQS#4
AH35 AJ31 B29 F26
FBA_D50 FBA_D49 FBA_DQS_RN5 FBA_DQS#6 FBC_D49 FBC_D48 FBC_DQS_RN4 FBC_DQS#5
AH34 AJ35 C31 D31
FBA_D51 FBA_D50 FBA_DQS_RN6 FBA_DQS#7 FBC_D50 FBC_D49 FBC_DQS_RN5 FBC_DQS#6
AH32 FBA_D51 FBA_DQS_RN7 AC34 C29 FBC_D50 FBC_DQS_RN6 A31
FBA_D52 AJ33 FBC_D51 B31 A26 FBC_DQS#7
FBA_D53 FBA_D52 FBC_D52 FBC_D51 FBC_DQS_RN7
AL35 C32
FBA_D54 FBA_D53 FBC_D53 FBC_D52
AM34 B32
FBA_D55 FBA_D54 FBA_DQS0 FBC_D54 FBC_D53
AM35 L34 B35
FBA_D56 FBA_D55 FBA_DQS_WP0 FBA_DQS1 FBC_D55 FBC_D54 FBC_DQS0
AF33 H35 B34 C14
FBA_D57 FBA_D56 FBA_DQS_WP1 FBA_DQS2 FBC_D56 FBC_D55 FBC_DQS_WP0 FBC_DQS1
AE32 J32 A29 A10
FBA_D58 FBA_D57 FBA_DQS_WP2 FBA_DQS3 FBC_D57 FBC_D56 FBC_DQS_WP1 FBC_DQS2
AF34 FBA_D58 FBA_DQS_WP3 N31 B28 FBC_D57 FBC_DQS_WP2 E10
FBA_D59 AE35 AE31 FBA_DQS4 FBC_D58 A28 D14 FBC_DQS3
FBA_D60 FBA_D59 FBA_DQS_WP4 FBA_DQS5 FBC_D59 FBC_D58 FBC_DQS_WP3 FBC_DQS4
AE34 AJ32 C28 E26
FBA_D61 FBA_D60 FBA_DQS_WP5 FBA_DQS6 FBC_D60 FBC_D59 FBC_DQS_WP4 FBC_DQS5
AE33 AJ34 C26 D32
+1.5VRAM FBA_D62 FBA_D61 FBA_DQS_WP6 FBA_DQS7 FBC_D61 FBC_D60 FBC_DQS_WP5 FBC_DQS6
AB32 AC33 D25 A32
FBA_D63 FBA_D62 FBA_DQS_WP7 FBC_D62 FBC_D61 FBC_DQS_WP6 FBC_DQS7
AC35 B25 B26
B FBA_D63 FBC_D63 FBC_D62 FBC_DQS_WP7 B
A25 FBC_D63
UNDER GPU +FB_PLLVDD
R1105 +FB_PLLVDD AG27 +1.5VRAM
1K_0402_5% FB_DLLAVDD FBA_CLK0 PM@ FBC_CLK0
AF27 FB_PLLAVDD FBA_CLK0 T32 FBA_CLK0 <21> K27 FBCAL_PD_VDDQ FBC_CLK0 E17 FBC_CLK0 <22>
@ 10MIL T31 FBA_CLK0# R1106 60.4_0402_1% D17 FBC_CLK0#
FBA_CLK0_N FBA_CLK0# <21> FBC_CLK0_N FBC_CLK0# <22>
2 PM@ 1 L27
+FB_VREF +FB_VREF R1107 40.2_0402_1% FBCAL_PU_GND FBC_CLK1
J27 D23 FBC_CLK1 <22>
FB_VREF FBA_CLK1 FBC_CLK1 FBC_CLK1#
AC31 FBA_CLK1 <21> 2 PM@ 1 M27 E23 FBC_CLK1# <22>
PM@ 2 FBA_CLK1 FBA_CLK1# R1108 40.2_0402_1% FBCAL_TERM_GND FBC_CLK1_N
1 +1.5VRAM 1 T30 AC30 FBA_CLK1# <21>
R1109 R1110 10K_0402_5% FBA_DEBUG FBA_CLK1_N
G19 2 PM@ 1 +1.5VRAM
1K_0402_5% C1169 FBC_DEBUG R1111 10K_0402_5%
@ 0.01U_0402_16V7K
2 @
N10P-GS-A1_BGA969 N10P-GS-A1_BGA969
10M@ 10M@
Place Components Close to BGA

Memory/PKG FBVDDQ FBCAL_PU_GND FBCAL_PD_VDDQ FBCAL_TERM_GND

+VCCP +FB_PLLVDD DDR3 +1.5VS 40.2 ohm 60.4 ohm 40.2 ohm
L511PM@ MBK1608121YZF_0603
1 2 GDDR3 +1.8VS 40.2 ohm 60.4 ohm 40.2 ohm
1
1 PM@ PM@
C1172 PM@ C1170 C1171 Must be used 1% resister for driver calibration
4.7U 6.3V K X5R 0603 1U_0603_10V4Z 0.1U_0402_16V4Z
2
2
A A

NEAR GPU UNDER GPU

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N10x-GS Memory
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NIWBA_LA5371P
Date: Wednesday, March 18, 2009 Sheet 17 of 53
5 4 3 2 1
 5 4 3 2 1

U50D

Part 4 of 7
VGA_LVDS_ACLK AM11 A2
<25> VGA_LVDS_ACLK VGA_LVDS_ACLK# IFPA_TXC NC_0
<25> VGA_LVDS_ACLK# AM12 A7
VGA_LVDS_A0 IFPA_TXC_N NC_1
<25> VGA_LVDS_A0 AM8 IFPA_TXD0 NC_2 B7
VGA_LVDS_A0# AL8 C5
<25> VGA_LVDS_A0# IFPA_TXD0_N NC_3
VGA_LVDS_A1 AM10 C7
D <25> VGA_LVDS_A1 IFPA_TXD1 NC_4 D
VGA_LVDS_A1# AM9 D5
<25> VGA_LVDS_A1# VGA_LVDS_A2 IFPA_TXD1_N NC_5
<25> VGA_LVDS_A2 AK10 IFPA_TXD2 NC_6 D6
VGA_LVDS_A2# AL10 D7
<25> VGA_LVDS_A2# IFPA_TXD2_N NC_7
AK11 E5
IFPA_TXD3 NC_8
AL11 E7
IFPA_TXD3_N NC_9
NC_10 F4
G5
VGA_LVDS_BCLK NC_11
<25> VGA_LVDS_BCLK AP13 IFPB_TXC NC_12 G11
VGA_LVDS_BCLK# AN13 G12
<25> VGA_LVDS_BCLK# IFPB_TXC_N NC_13
VGA_LVDS_B0 AN8 G14
<25> VGA_LVDS_B0 VGA_LVDS_B0# IFPB_TXD4 NC_14
<25> VGA_LVDS_B0# AP8 IFPB_TXD4_N NC_15 G15
VGA_LVDS_B1 AP10 G27
<25> VGA_LVDS_B1 VGA_LVDS_B1# IFPB_TXD5 NC_16
<25> VGA_LVDS_B1# AN10 IFPB_TXD5_N NC_17 G28
VGA_LVDS_B2 AR11 G24
<25> VGA_LVDS_B2 VGA_LVDS_B2# IFPB_TXD6 NC_18
<25> VGA_LVDS_B2# AR10 G25
IFPB_TXD6_N NC_19
AN11 H32
IFPB_TXD7 NC_20
AP11 IFPB_TXD7_N NC_21 J18
J19
NC_22

NC
NC_23 J25
<24> VGA_HDMI_TX2+ VGA_HDMI_TX2+ AM7 J26
VGA_HDMI_TX2- IFPC_L0 NC_24
<24> VGA_HDMI_TX2- AM6 L29
VGA_HDMI_TX1+ IFPC_L0_N NC_25
<24> VGA_HDMI_TX1+ AL5 M7
VGA_HDMI_TX1- IFPC_L1 NC_26
<24> VGA_HDMI_TX1- AM5 IFPC_L1_N NC_27 M29
VGA_HDMI_TX0+ AM3 P6
<24> VGA_HDMI_TX0+ IFPC_L2 NC_28
VGA_HDMI_TX0- AM4 P29
<24> VGA_HDMI_TX0- IFPC_L2_N NC_29
<24> VGA_HDMI_CLK+ VGA_HDMI_CLK+ AP1 R29
VGA_HDMI_CLK- IFPC_L3 NC_30
<24> VGA_HDMI_CLK- AR2 U7
IFPC_L3_N NC_31
V6
NC_32
NC_33 Y4
AR8 IFPD_L0 NC_34 AA4
AR7 AB4
IFPD_L0_N NC_35
AP7 AB7
C IFPD_L1 NC_36 C
AN7 IFPD_L1_N NC_37 AC5

LVDS/TMDS
AN5 AD6
IFPD_L2 NC_38
AP5 AD29
IFPD_L2_N NC_39
AR5 IFPD_L3 NC_40 AE29
AR4 IFPD_L3_N NC_41 AF6
AG6
NC_42
NC_43 AG20
AH6 AG29
IFPE_L0 NC_44
AH5 IFPE_L0_N NC_45 AH29
AH4 AJ5
IFPE_L1 NC_46
AG4 IFPE_L1_N NC_47 AK15
+3VS AF4 AL7
IFPE_L2 NC_48
AF5 IFPE_L2_N
AE6
IFPE_L3
AE5
IFPE_L3_N
1

D35 1 PM@ 2 +VGASENSE <49>

R1113 VDD_SENSE_0 R1112 0_0402_5%
AL2 P7
IFPF_L0 VDD_SENSE_1
4.7K_0402_5% AL3 AD20
PM@ IFPF_L0_N VDD_SENSE_2
AJ3 IFPF_L1
2

AJ2
2

Q63A IFPF_L1_N
AJ1
IFPF_L2
<24> VGA_HDMI_SCL 6 1 AH1 AD19 1 PM@ 2
IFPF_L2_N GND_SENSE_0 R1114 0_0402_5%
AH2 E35
2N7002DW-T/R7_SOT363-6 IFPF_L3 GND_SENSE_1 +3VS
AH3 R7
PM@ IFPF_L3_N GND_SENSE_2

1
@
IFPC_AUX AP2 R1115
IFPC_AUX_N IFPC_AUX_I2CW_SCL 10K_0402_5%
AN3
IFPC_AUX_I2CW_SDA_N TEST

2
PM@
B 2N7002DW-T/R7_SOT363-6 AP4 AP35 TESTMODE B
IFPD_AUX_I2CX_SCL TESTMODE JTAG_TCK
<24> VGA_HDMI_SDA 3 4 AN4 IFPD_AUX_I2CX_SDA_N JTAG_TCK AP14 PAD T86
AN14
JTAG_TDI

1
Q63B AN16 JTAG_TDO
JTAG_TDO PAD T87
AE4 AR14 PM@
5

IFPE_AUX_I2CY_SCL JTAG_TMS
1

AD4 AP16 JTAG_TRST_N PM@ 1K_0402_5% R1117

R1118 IFPE_AUX_I2CY_SDA_N JTAG_TRST_N R1116 10K_0402_5%
4.7K_0402_5%

2
PM@ AF3
IFPF_AUX_I2CZ_SCL
AF2 SERIAL
2

IFPF_AUX_I2CZ_SDA_N
C3
ROM_CS_N ROM_SI
ROM_SI D3 ROM_SI <20>
+3VS C4 ROM_SO
ROM_SO ROM_SO <20>
D4 ROM_SCLK
ROM_SCLK ROM_SCLK <20>

5V PULL UP IN CONNECTER SIDE GENERAL SPDIF_IN

A5 PAD T88
NC/SPDIF
T89 PAD A4
R1120 10K_0402_5% BUFRST_N
N9 1 PM@ 2
MULTI_STRAP_REF0_GND
+3VS 1 PM@ 2 AB5 CEC
R1119 40.2K_0402_1%
<24> HDMI_CEC 2 1 HDMI_CEC_R M9 1 PM@ 2
R722 @ 0_0402_5% STRAP0 MULTI_STRAP_REF1_GND R1121 40.2K_0402_1%
<20> STRAP0 W5 STRAP0
<20> STRAP1 STRAP1 W7 B5 PAD
STRAP1 THERMDP T90
<20> STRAP2 STRAP2 V7 B4 PAD
STRAP2 THERMDN T91

N10P-GS-A1_BGA969
10M@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N10P/N10M LVDS,HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NIWBA_LA5371P
Date: Wednesday, March 18, 2009 Sheet 18 of 53
5 4 3 2 1
 5 4 3 2 1

+VGA_CORE U50G
+VGA_CORE
AB11 P21
VDD_0 Part 7 of 7 VDD_56
AB13 P23
PM@ PM@ PM@ PM@ PM@ VDD_1 VDD_57
AB15 P25
C1181 C1174 C1182 C1175 C1183 VDD_2 VDD_58
AB17 R11
4700P_0402_16V7K .015U_0402_16V7K .015U_0402_16V7K .022U_0402_16V7 .022U_0402_16V7 VDD_3 VDD_59
AB19 R12
VDD_4 VDD_60
AB21 R13
AB23
VDD_5 22.28A VDD_61
R14
VDD_6 VDD_62
AB25 R15
VDD_7 VDD_63
AC11 R16
VDD_8 VDD_64
AC12 R17
PM@ PM@ PM@ PM@ PM@ PM@ VDD_9 VDD_65
AC13 R18
C1184 C1176 C1177 C1178 C1179 C1180 VDD_10 VDD_66
AC14 R19
0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K VDD_11 VDD_67
AC15 R20
VDD_12 VDD_68
AC16 R21
D VDD_13 VDD_69 D
AC17 R22
VDD_14 VDD_70
AC18 R23
VDD_15 VDD_71
AC19 R24
VDD_16 VDD_72
AC20 R25
PM@ VDD_17 VDD_73
AC21 T12
C1185 C1186 C1187 C1188 C1189 VDD_18 VDD_74
AC22 T14
.022U_0402_16V7 .022U_0402_16V7 .022U_0402_16V7 .022U_0402_16V7 0.1U_0402_10V7K VDD_19 VDD_75
AC23 T16
VDD_20 VDD_76

POWER
AC24 T18
VDD_21 VDD_77
AC25 T20
VDD_22 VDD_78
AD12 T22
VDD_23 VDD_79
AD14 T24
VDD_24 VDD_80
1 AD16 V11
PM@ PM@ PM@ VDD_25 VDD_81
AD18 V13
C1190 C1191 C1192 VDD_26 VDD_82
AD22 V15
0.22U_0603_10V7K 0.22U_0603_10V7K 0.1U_0402_16V4Z VDD_27 VDD_83
AD24 V17
2 VDD_28 VDD_84
L11 V19
VDD_29 VDD_85
UNDER GPU L12
VDD_30 VDD_86
V21
L13 V23
VDD_31 VDD_87
L14 V25
VDD_32 VDD_88
L15 W11
VDD_33 VDD_89
L16 W12
VDD_34 VDD_90
L17 W13
VDD_35 VDD_91
L18 W14
VDD_36 VDD_92
L19 W15
VDD_37 VDD_93
L20 W16
VDD_38 VDD_94
L21 W17
VDD_39 VDD_95
L22 W18
VDD_40 VDD_96
L23 W19
VDD_41 VDD_97
L24 W20
VDD_42 VDD_98 +VCCP
L25 W21
PM@ 220mA M12
VDD_43 VDD_99
W22
+IFPAB_PLLVDD VDD_44 VDD_100
+VCCP 1 2 M14 W23
MBK1608121YZF_0603 L512 VDD_45 VDD_101
1 1 1 1 M16 W24 1 1 1 1
PM@ PM@ PM@ PM@ PM@ VDD_46 VDD_102 PM@ PM@ PM@ PM@ PM@ PM@
M18 W25
C1193 C1194 C1195 C1196 C1197 VDD_47 VDD_103 C1198 C1199 C1200 C1201 C1202 C1203
M20 Y12
4.7U 6.3V K X5R 0603 1U_0603_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4700P_0402_25V7K VDD_48 VDD_104 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V6K 1U_0402_6.3V6K
M22 Y14
2 2 2 2 VDD_49 VDD_105 2 2 2 2
M24 Y16
VDD_50 VDD_106
C P11 Y18 C
VDD_51 VDD_107
P13
VDD_52 VDD_108
Y20 UNDER GPU (0-150 Mil)
P15 Y22
VDD_53 VDD_109
P17 Y24
VDD_54 VDD_110
P19
VDD_55

220mA
+IFPD_PLLVDD 10M@ 1 1 1 1 1 1
N10P-GS-A1_BGA969 PM@ PM@ PM@ PM@ PM@ PM@
PM@ L513 U50E C1204 C1205 C1206 C1207 C1208 C1209
1 2 +IFPC_PLLVDD +1.5VRAM 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
+3VS
MBK1608121YZF_0603 1 1 1 1 Part 5 of 7 2A 2 2 2 2 2 2
PM@ PM@ PM@ PM@ PM@ PM@ J23 AG11
C1210 C1213 C1214 C1211 C1215 C1216 220mA J24
FBVDDQ_0 PEX_IOVDDQ_0
AG12 NEAR GPU (0-750 Mil)
4.7U 6.3V K X5R 0603 1U_0603_10V4Z 1U_0603_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z FBVDDQ_1 PEX_IOVDDQ_1
J29 AG13
2 2 2 2 FBVDDQ_2 PEX_IOVDDQ_2
AA27 AG15
FBVDDQ_3 PEX_IOVDDQ_3
AA29 AG16
FBVDDQ_4 PEX_IOVDDQ_4
AA31 AG17
FBVDDQ_5 PEX_IOVDDQ_5
AB27 AG18
FBVDDQ_6 PEX_IOVDDQ_6
AB29 AG22
FBVDDQ_7 PEX_IOVDDQ_7
AC27 AG23
150mA AD27
FBVDDQ_8 PEX_IOVDDQ_8
AG24
FBVDDQ_9 PEX_IOVDDQ_9
AE27 AG25
+IFPA_IOVDD FBVDDQ_10 PEX_IOVDDQ_10 +VCCP
AJ28 AG26
PM@ FBVDDQ_11 PEX_IOVDDQ_11
B18 AJ14
+IFPB_IOVDD FBVDDQ_12 PEX_IOVDDQ_12 PM@
+1.8VS 1 2 E21 AJ15 2 1
L514 FBVDDQ_13 PEX_IOVDDQ_13 L515
1 1 1 G17 AJ19 1 1
MBK1608121YZF_0603 PM@ PM@ PM@ PM@ FBVDDQ_14 PEX_IOVDDQ_14 PM@ PM@ PM@ PM@ PM@ PM@ MBK1608121YZF_0603
G18 AJ21
C1212 C1217 C1218 C1219 150mA G22
FBVDDQ_15 PEX_IOVDDQ_15
AJ22 C1220 C1221 C1222 C1223 C1224 C1225
4.7U 6.3V K X5R 0603 1U_0603_10V4Z 0.1U_0402_16V4Z 4700P_0402_25V7K FBVDDQ_16 PEX_IOVDDQ_16 0.1U_0402_16V4Z 1U_0402_6.3V6K 1U_0603_10V4Z 1U_0603_10V4Z 1U_0603_10V4Z 4.7U 6.3V K X5R 0603
G8 AJ24
2 2 2 FBVDDQ_17 PEX_IOVDDQ_17 2 2
G9 AJ25
FBVDDQ_18 PEX_IOVDDQ_18
H29 AJ27
FBVDDQ_19 PEX_IOVDDQ_19

POWER
J14
FBVDDQ_20 PEX_IOVDDQ_20
AK18 UNDER GPU NEAR GPU
J15 AK20
285mA J16
FBVDDQ_21 PEX_IOVDDQ_21
AK23
+IFPC_IOVDD FBVDDQ_22 PEX_IOVDDQ_22
J17 AK26
B
PM@ FBVDDQ_23 PEX_IOVDDQ_23 B
J20 AL16
+IFPD_IOVDD FBVDDQ_24 PEX_IOVDDQ_24
+VCCP 1 2 J21
L516 FBVDDQ_25 +3VS
1 1 1 J22
MBK1608121YZF_0603 PM@ PM@ PM@ PM@ FBVDDQ_26
N27
C1226 C1227 C1228 C1229 285mA P27
FBVDDQ_27
AK16
4.7U 6.3V K X5R 0603 1U_0603_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z FBVDDQ_28 PEX_IOVDD_0
R27 AK17
2 2 2 FBVDDQ_29 PEX_IOVDD_1 PM@ PM@ PM@
T27 AK21
FBVDDQ_30 PEX_IOVDD_2 C1230 C1231 C1232
U27 AK24
FBVDDQ_31 PEX_IOVDD_3 0.01U_0402_16V7K 0.1U_0402_10V7K 1U_0603_10V4Z
U29 AK27
FBVDDQ_32 PEX_IOVDD_4
V27
FBVDDQ_33
V29
FBVDDQ_34
V34
FBVDDQ_35 150mA UNDER GPU NEAR GPU
W27 AG14
FBVDDQ_36 PEX_PLLVDD
Y27
FBVDDQ_37
120mA
+1.5VRAM +IFPAB_PLLVDD
UNDER GPU +IFPAB_RSET
AK9
IFPAB_PLLVDD PEX_SVDD_3V3_0
AG19
+3VS
1 2 AJ11 F7
R1122 @ 1K_0402_5% IFPAB_RSET PEX_SVDD_3V3_1

PM@ PM@ PM@ PM@ +IFPA_IOVDD AG9

C1237 C1238 C1239 C1240 +IFPB_IOVDD IFPA_IOVDD PM@ PM@ PM@ PM@
AG10 J10
0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K IFPB_IOVDD VDD33_0 C1233 C1234 C1235 C1236
J11
VDD33_1 0.1U_0402_10V7K 0.1U_0402_10V7K 1U_0603_10V4Z 1U_0603_10V4Z
J12
+IFPC_PLLVDD VDD33_2
AJ9 J13
PM@ 1 +IFPC_RSET IFPC_PLLVDD VDD33_3
2 AK7 J9
R1123 1K_0402_5% IFPC_RSET VDD33_4
+IFPC_IOVDD
UNDER GPU NEAR GPU
1 1 1 AJ8
PM@ PM@ PM@ IFPC_IOVDD
C1241 C1242 C1243 P9 +3VS
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +IFPD_PLLVDD MIOA_VDDQ_0
AC6 R9
2 2 2 +IFPD_RSET IFPD_PLLVDD MIOA_VDDQ_1 PM@
AB6 T9
10K_0402_5% IFPD_RSET MIOA_VDDQ_2 C1244
U9
MIOA_VDDQ_3 0.1U_0402_10V7K
2 1 R1180 +IFPD_IOVDD AK8
@ IFPD_IOVDD
10K_0402_5% AA9
PM@ 1 R1124 +IFPEF_PLLVDD MIOB_VDDQ_0
2 AJ6 AB9
IFPEF_PLLVDD MIOB_VDDQ_1 PM@
A AL1 W9 A
10K_0402_5% IFPEF_RSET MIOB_VDDQ_2 C1245
Y9
MIOB_VDDQ_3 0.1U_0402_10V7K
2 PM@ 1 R1125 +IFPE_IOVDD AE7
IFPE_IOVDD
2 PM@ 1 R1126 +IFPF_IOVDD AD7
IFPF_IOVDD
10K_0402_5%

10M@
N10P-GS-A1_BGA969

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N10x-GS POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NIWBA_LA5371P
Date: Wednesday, April 22, 2009 Sheet 19 of 53
5 4 3 2 1
 5 4 3 2 1

+3VS
U50F

B3 Part 6 of 7
GND_0

1
B6 GND_1 GND_97 V18
B9 V20 PM@ @ PM@ @ @ @
GND_2 GND_98 R1127 R1128 R1129 R1130 R1131 R1132
B12 GND_3 GND_99 V22
B15 V24 10K_0402_1% 10K_0402_1% 45.3K_0402_1% 15K_0402_1% 2K_0402_5% 4.99K_0402_1%
GND_4 GND_100
B21 V31

2
GND_5 GND_101 STRAP2
B24 GND_6 GND_102 Y11 <18> STRAP2
B27 Y13 STRAP1
GND_7 GND_103 <18> STRAP1
B30 Y15 STRAP0
GND_8 GND_104 <18> STRAP0
B33 Y17 ROM_SCLK
GND_9 GND_105 <18> ROM_SCLK
D C2 Y19 ROM_SI D
GND_10 GND_106 <18> ROM_SI
C34 Y21 ROM_SO
GND_11 GND_107 <18> ROM_SO
E6 GND_12 GND_108 Y23

1
E9 GND_13 GND_109 Y25
E12 AA2 @ PM@ @ PM@ X76@ PM@
GND_14 GND_110 R1133 R1134 R1135 R1136 R1137 R1138
E15 GND_15 GND_111 AA5
E18 AA11 10K_0402_1% 10K_0402_1% 10K_0402_1% 15K_0402_1% 20K_0402_1% 10K_0402_1%
GND_16 GND_112
E24 AA12

2
GND_17 GND_113
E27 GND_18 GND_114 AA13
E30 GND_19 GND_115 AA14
F2 AA15 X2
GND_20 GND_116
F31 GND_21 GND_117 AA16
F34 GND_22 GND_118 AA17
F5 AA18 S1024@
GND_23 GND_119
J2 AA19
J5
GND_24
GND_25
GND_120
GND_121 AA20 GB1 Family GPU Strap Qptions GPU DEVID RAM_CFG GPU DEVID
J31 GND_26 GND_122 AA21 X76_S1024
J34 GND_27 GND_123 AA22
K9 GND_28 GND_124 AA23 GPU FB Memory ROM_SO ROM_SCLK ROM_SI STRAP2 STRAP1 STRAP0
L9 GND_29 GND_125 AA24
M2 GND_30 GND_126 AA25
M5 AA34 X3
GND_31 GND_127
M11 GND_32 GND_128 AB12 Samsung 64Mx16 PD 10K PD 15K PD 20K PU 10K PD 10K PU 45K
M13 GND_33 GND_129 AB14
M15 AB16 H1024@
GND_34 GND_130
M17 GND_35 GND_131 AB18
M19 GND_36 GND_132 AB20
M21 GND_37 GND_133 AB22 X76_H1024 N10P-GS
M23 GND_38 GND_134 AB24 Hynix 64Mx16 PD 10K PD 15K PD 15K PU 10K PD 10K PU 45K
C M25 AC9 (0xA34) C
GND_39 GND_135
M31 GND_40 GND_136 AD2
M34 AD5 X4
GND_41 GND_137
GND

N11 GND_42 GND_138 AD11

N12 GND_43 GND_139 AD13
N13 AD15 S512@
GND_44 GND_140
N14 GND_45 GND_141 AD17
N15 GND_46 GND_142 AD21
N16 GND_47 GND_143 AD23 X76_S512
N17 GND_48 GND_144 AD25
N18 GND_49 GND_145 AD31
N19 GND_50 GND_146 AD34
N20 GND_51 GND_147 AE11
N21 AE12 X5
GND_52 GND_148
N22 GND_53 GND_149 AE13 GPU FB Memory ROM_SO ROM_SCLK ROM_SI STRAP2 STRAP1 STRAP0
N23 GND_54 GND_150 AE14
N24 AE15 H512@
GND_55 GND_151
N25 GND_56 GND_152 AE16
P12 GND_57 GND_153 AE17 Samsung 64Mx16 PD 10K PD 15K PD 20K PU 10K PD 10K PU 45K
P14 GND_58 GND_154 AE18 X76_H512
P16 GND_59 GND_155 AE19
P18 GND_60 GND_156 AE20
P20 GND_61 GND_157 AE21
P22 AE22 U50
P24
GND_62 GND_158
AE23
N10M-GS Hynix 64Mx16 PD 10K PD 15K PD 15K PU 10K PD 10K PU 45K
GND_63 GND_159
R2 GND_64 GND_160 AE24 (0xA74)
R5 GND_65 GND_161 AE25
R31 GND_66 GND_162 AG2
R34 GND_67 GND_163 AG5
B B
T11 GND_68 GND_164 AG31 N10P-GS
T13 AG34 10P@
GND_69 GND_165
T15 GND_70 GND_166 AK2
T17 GND_71 GND_167 AK5
T19 GND_72 GND_168 AK14
T21 GND_73 GND_169 AK31
T23 GND_74 GND_170 AK34
T25 GND_75 GND_171 AL6
U11 GND_76 GND_172 AL9
U12 GND_77 GND_173 AL12
U13 GND_78 GND_174 AL15
U14 GND_79 GND_175 AL18
U15 GND_80 GND_176 AL21
U16 GND_81 GND_177 AL24
U17 GND_82 GND_178 AL27
U18 GND_83 GND_179 AL30
U19 GND_84 GND_180 AN2
U20 GND_85 GND_181 AN34
U21 GND_86 GND_182 AP3
U22 GND_87 GND_183 AP6
U23 GND_88 GND_184 AP9
U24 GND_89 GND_185 AP12
U25 GND_90 GND_186 AP15
V2 GND_91 GND_187 AP18
V5 GND_92 GND_188 AP21
V9 GND_93 GND_189 AP24
V12 GND_94 GND_190 AP27
V14 GND_95 GND_191 AP30
A V16 GND_96 GND_192 AP33 A

N10P-GS-A1_BGA969
10M@
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2008/03/25 Deciphered Date 2008/04/ Title
N10x-GS GND & STRAP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NIWBA_LA5371P
Date: Wednesday, March 18, 2009 Sheet 20 of 53
5 4 3 2 1
 5 4 3 2 1

N10x 40nm DDR3 MAPPING

NVIDIA COCUMENT FOR DA-3978-001
U54 U55 U56 U57

FBA_CMD[0..30] VREFC_A1 M9 E4 FBA_D5 VREFC_A2 M9 E4 FBA_D19 VREFC_A3 M9 E4 FBA_D32 VREFC_A4 M9 E4 FBA_D60

<17> FBA_CMD[0..30] VREFD_Q1 VREFCA DQL0 FBA_D1 VREFD_Q2 VREFCA DQL0 FBA_D22 VREFD_Q3 VREFCA DQL0 FBA_D33 VREFD_Q4 VREFCA DQL0 FBA_D59
H2 F8 H2 F8 H2 F8 H2 F8
FBA_DQM[0..7] VREFDQ DQL1 FBA_D7 VREFDQ DQL1 FBA_D18 VREFDQ DQL1 FBA_D34 VREFDQ DQL1 FBA_D61
<17> FBA_DQM[0..7] F3 F3 F3 F3
FBA_CMD19 DQL2 FBA_D0 FBA_CMD19 DQL2 FBA_D23 FBA_CMD19 DQL2 FBA_D35 FBA_CMD19 DQL2 FBA_D63
N4 F9 N4 F9 N4 F9 N4 F9
FBA_DQS[0..7] FBA_CMD25 A0 DQL3 FBA_D6 FBA_CMD25 A0 DQL3 FBA_D17 FBA_CMD25 A0 DQL3 FBA_D36 FBA_CMD25 A0 DQL3 FBA_D56
<17> FBA_DQS[0..7] P8 H4 P8 H4 P8 H4 P8 H4
FBA_CMD22 A1 DQL4 FBA_D2 FBA_CMD22 A1 DQL4 FBA_D21 FBA_CMD4 A1 DQL4 FBA_D37 FBA_CMD4 A1 DQL4 FBA_D58
P4 H9 P4 H9 P4 H9 P4 H9
FBA_DQS#[0..7] FBA_CMD24 A2 DQL5 FBA_D3 FBA_CMD24 A2 DQL5 FBA_D16 FBA_CMD6 A2 DQL5 FBA_D38 FBA_CMD6 A2 DQL5 FBA_D57
<17> FBA_DQS#[0..7] N3 G3 N3 G3 N3 G3 N3 G3
FBA_CMD0 A3 DQL6 FBA_D4 FBA_CMD0 A3 DQL6 FBA_D20 FBA_CMD5 A3 DQL6 FBA_D39 FBA_CMD5 A3 DQL6 FBA_D62
P9 H8 P9 H8 P9 H8 P9 H8
FBA_D[0..63] FBA_CMD2 A4 DQL7 FBA_CMD2 A4 DQL7 FBA_CMD13 A4 DQL7 FBA_CMD13 A4 DQL7
<17> FBA_D[0..63] P3 P3 P3 P3
FBA_CMD21 A5 FBA_CMD21 A5 FBA_CMD21 A5 FBA_CMD21 A5
R9 R9 R9 R9
D
FBA_CMD16 A6 FBA_D13 FBA_CMD16 A6 FBA_D31 FBA_CMD16 A6 FBA_D40 FBA_CMD16 A6 FBA_D48 D
R3 D8 R3 D8 R3 D8 R3 D8
FBA_CMD23 A7 DQU0 FBA_D9 FBA_CMD23 A7 DQU0 FBA_D28 FBA_CMD23 A7 DQU0 FBA_D45 FBA_CMD23 A7 DQU0 FBA_D52
T9 C4 T9 C4 T9 C4 T9 C4
FBA_CMD20 A8 DQU1 FBA_D14 FBA_CMD20 A8 DQU1 FBA_D29 FBA_CMD20 A8 DQU1 FBA_D41 FBA_CMD20 A8 DQU1 FBA_D51
R4 C9 R4 C9 R4 C9 R4 C9
FBA_CMD17 A9 DQU2 FBA_D11 FBA_CMD17 A9 DQU2 FBA_D25 FBA_CMD17 A9 DQU2 FBA_D46 FBA_CMD17 A9 DQU2 FBA_D54
L8 C3 L8 C3 L8 C3 L8 C3
FBA_CMD9 A10/AP DQU3 FBA_D12 FBA_CMD9 A10/AP DQU3 FBA_D27 FBA_CMD9 A10/AP DQU3 FBA_D43 FBA_CMD9 A10/AP DQU3 FBA_D49
R8 A8 R8 A8 R8 A8 R8 A8
FBA_CMD14 A11 DQU4 FBA_D8 FBA_CMD14 A11 DQU4 FBA_D24 FBA_CMD14 A11 DQU4 FBA_D47 FBA_CMD14 A11 DQU4 FBA_D55
N8 A3 N8 A3 N8 A3 N8 A3
FBA_CMD26 A12 DQU5 FBA_D15 FBA_CMD26 A12 DQU5 FBA_D30 FBA_CMD26 A12 DQU5 FBA_D42 FBA_CMD26 A12 DQU5 FBA_D50
T4 B9 T4 B9 T4 B9 T4 B9
A13 DQU6 FBA_D10 A13 DQU6 FBA_D26 A13 DQU6 FBA_D44 A13 DQU6 FBA_D53
T8 A4 T8 A4 T8 A4 T8 A4
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M8 M8 M8 M8
A15/BA3 +1.5VRAM A15/BA3 +1.5VRAM A15/BA3 +1.5VRAM A15/BA3 +1.5VRAM

FBA_CMD12 M3 B3 FBA_CMD12 M3 B3 FBA_CMD12 M3 B3 FBA_CMD12 M3 B3

FBA_CMD3 BA0 VDD FBA_CMD3 BA0 VDD FBA_CMD3 BA0 VDD FBA_CMD3 BA0 VDD
N9 D10 N9 D10 N9 D10 N9 D10
FBA_CMD27 BA1 VDD FBA_CMD27 BA1 VDD FBA_CMD27 BA1 VDD FBA_CMD27 BA1 VDD
M4 G8 M4 G8 M4 G8 M4 G8
BA2 VDD BA2 VDD BA2 VDD BA2 VDD
K3 K3 K3 K3
VDD VDD VDD VDD
K9 K9 K9 K9
VDD VDD VDD VDD
N2 N2 N2 N2
VDD FBA_CLK0 VDD VDD FBA_CLK1 VDD
<17> FBA_CLK0 J8 N10 J8 N10 <17> FBA_CLK1 J8 N10 J8 N10
CK VDD FBA_CLK0# CK VDD CK VDD FBA_CLK1# CK VDD
<17> FBA_CLK0# K8 R2 K8 R2 <17> FBA_CLK1# K8 R2 K8 R2
FBA_CMD18 CK VDD FBA_CMD18 CK VDD CK VDD FBA_CMD7 CK VDD
K10 R10 K10 R10 K10 R10 K10 R10
CKE/CKE0 VDD +1.5VRAM CKE/CKE0 VDD +1.5VRAM FBA_CMD7 CKE/CKE0 VDD +1.5VRAM CKE/CKE0 VDD +1.5VRAM

FBA_CMD30 K2 A2 FBA_CMD30 K2 A2 FBA_CMD28 K2 A2 FBA_CMD28 K2 A2

FBA_CMD29 ODT/ODT0 VDDQ FBA_CMD29 ODT/ODT0 VDDQ FBA_CMD8 ODT/ODT0 VDDQ FBA_CMD8 ODT/ODT0 VDDQ
L3 A9 L3 A9 L3 A9 L3 A9
FBA_CMD1 CS VDDQ FBA_CMD1 CS VDDQ FBA_CMD1 CS VDDQ FBA_CMD1 CS VDDQ
J4 C2 J4 C2 J4 C2 J4 C2
FBA_CMD10 RAS VDDQ FBA_CMD10 RAS VDDQ FBA_CMD10 RAS VDDQ FBA_CMD10 RAS VDDQ
K4 C10 K4 C10 K4 C10 K4 C10
FBA_CMD11 CAS VDDQ FBA_CMD11 CAS VDDQ FBA_CMD11 CAS VDDQ FBA_CMD11 CAS VDDQ
L4 D3 L4 D3 L4 D3 L4 D3
WE VDDQ WE VDDQ WE VDDQ WE VDDQ
E10 E10 E10 E10
VDDQ VDDQ VDDQ VDDQ
F2 F2 F2 F2
FBA_DQS0 VDDQ FBA_DQS2 VDDQ FBA_DQS4 VDDQ FBA_DQS7 VDDQ
F4 H3 F4 H3 F4 H3 F4 H3
FBA_DQS1 DQSL VDDQ FBA_DQS3 DQSL VDDQ FBA_DQS5 DQSL VDDQ FBA_DQS6 DQSL VDDQ
C8 H10 C8 H10 C8 H10 C8 H10
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

FBA_DQM0 E8 A10 FBA_DQM2 E8 A10 FBA_DQM4 E8 A10 FBA_DQM7 E8 A10

FBA_DQM1 DML VSS FBA_DQM3 DML VSS FBA_DQM5 DML VSS FBA_DQM6 DML VSS
D4 B4 D4 B4 D4 B4 D4 B4
DMU VSS DMU VSS DMU VSS DMU VSS
E2 E2 E2 E2
VSS VSS VSS VSS
G9 G9 G9 G9
FBA_DQS#0 VSS FBA_DQS#2 VSS FBA_DQS#4 VSS FBA_DQS#7 VSS
C G4 J3 G4 J3 G4 J3 G4 J3 C
FBA_DQS#1 DQSL VSS FBA_DQS#3 DQSL VSS FBA_DQS#5 DQSL VSS FBA_DQS#6 DQSL VSS
B8 J9 B8 J9 B8 J9 B8 J9
DQSU VSS DQSU VSS DQSU VSS DQSU VSS
M2 M2 M2 M2
VSS VSS VSS VSS
M10 M10 M10 M10
VSS VSS VSS VSS
P2 P2 P2 P2
FBA_CMD15 VSS FBA_CMD15 VSS FBA_CMD15 VSS FBA_CMD15 VSS
T3 P10 T3 P10 T3 P10 T3 P10
RESET VSS RESET VSS RESET VSS RESET VSS
T2 T2 T2 T2
VSS VSS VSS VSS
L9 T10 L9 T10 L9 T10 L9 T10
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
PM@ J2 B2 PM@ J2 B2 PM@ J2 B2 PM@ J2 B2
R1140 NC/ODT1 VSSQ R1141 NC/ODT1 VSSQ R1142 NC/ODT1 VSSQ R1143 NC/ODT1 VSSQ
L2 B10 L2 B10 L2 B10 L2 B10
FBA_CLK0 NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
240_0402_1% J10 D2 240_0402_1% J10 D2 240_0402_1% J10 D2 240_0402_1% J10 D2
2

NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ

L10 D9 L10 D9 L10 D9 L10 D9
PM@ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E3 E3 E3 E3
2

2
R1139 VSSQ VSSQ VSSQ VSSQ
A1 E9 A1 E9 A1 E9 A1 E9
243_0402_1% NC VSSQ NC VSSQ NC VSSQ NC VSSQ
A11 F10 A11 F10 A11 F10 A11 F10
FBA_CLK0# NC VSSQ NC VSSQ NC VSSQ NC VSSQ
T1 G2 T1 G2 T1 G2 T1 G2
1

NC VSSQ NC VSSQ NC VSSQ NC VSSQ

T11 G10 T11 G10 T11 G10 T11 G10
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
FBA_CLK1 100-BALL 100-BALL 100-BALL 100-BALL
1

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3

PM@ K4B1G1646D-HCF8_FBGA100
R1144 K4B1G1646D-HCF8_FBGA100 K4B1G1646D-HCF8_FBGA100 K4B1G1646D-HCF8_FBGA100
243_0402_1% @
FBA_CLK1# @ @ @
2

+1.5VRAM
B 1 1 1 1 1 1 B
PM@ PM@ PM@ PM@ PM@ PM@ +1.5VRAM VREFD_Q3 +1.5VRAM VREFD_Q4
C1246 C1247 C1248 C1249 C1250 C1251
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M

1
2 2 2 2 2 2 PM@ VREFC_A3 PM@ VREFC_A4
R1145 R1146
1.33K_0402_1% 1.33K_0402_1%
VREFC_A1 VREFD_Q2
1U_0402_6.3V4Z

2
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
+1.5VRAM 10MIL VREFD_Q1
10MIL VREFC_A2
1 PM@ 1 PM@ 1 PM@ 1 PM@ 1 PM@ 1 PM@ 1 PM@ 1 PM@ 1 PM@ 1 PM@

1
C1254

C1255

C1256

C1257

C1258

C1259

C1260

C1261

C1262

C1263

PM@ 1 PM@ 1
R1147 PM@ R1148 PM@
1.33K_0402_1% C1252 1.33K_0402_1% C1253
2 2 2 2 2 2 2 2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 2

2
1U_0402_6.3V4Z 1U_0402_6.3V4Z

+1.5VRAM
1U_0402_6.3V4Z 1U_0402_6.3V4Z
+1.5VRAM 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1
PM@
+
1 PM@ 1 PM@ 1 PM@ 1 PM@ 1 PM@ 1 PM@ 1 PM@ 1 PM@ 1 PM@ 1 PM@ C1264
C1265

C1266

C1267

C1268

C1269

C1270

C1271

C1272

C1273

C1274

220U_D2_4VM_R15
2
2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z 1U_0402_6.3V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM DDRA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NIWBA_LA5371P
Date: Wednesday, April 22, 2009 Sheet 21 of 53
5 4 3 2 1
 5 4 3 2 1

+3VSM_CK505 +3VS
FSC FSB FSA CPU SRC PCI REF DOT_96 USB
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz +3VS R178 1 2 0_0805_5%
1 1 1 1 1 1 1

0 0 0 266 100 33.3 14.318 96.0 48.0 C441 C442 C443 C444 C445 C446 C447 R235 1 2 0_0402_5% @ @
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R179 R180
2 2 2 2 2 2 2 2.2K_0402_5% 2.2K_0402_5%
0 0 1 133 100 33.3 14.318 96.0 48.0 2N7002DW-T/R7_SOT363-6
+1.5VS R181 1 2 @ 0_0805_5% <29,31> ICH_SMBDATA 6 1 CLK_SMBDATA
+VDD_CK505
0 1 0 200 100 33.3 14.318 96.0 48.0 @ Q1A
+VCCP R182 1 2 0_0805_5%

2
1 1 1 1 1 1 1 +3VS
D D
0 1 1 166 100 33.3 14.318 96.0 48.0

5
C448 C449 C450 C451 C452 C453 C454
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z @ Q1B
2 2 2 2 2 2 2 CLK_SMBCLK
1 0 0 333 100 33.3 14.318 96.0 48.0 <29,31> ICH_SMBCLK 3 4

2N7002DW-T/R7_SOT363-6
1 0 1 100 100 33.3 14.318 96.0 48.0 SA000020K00 (Silego : SLG8SP556VTR ) R234 1 2 0_0402_5%

1 1 0 400 100 33.3 14.318 96.0 48.0 SA000020H10 (ICS : ICS9LPRS387BKLFT)

+3VSM_CK505 U16
1 1 1 Reserved 9 CLK_SMBDATA
SDA CLK_SMBDATA <14,15>
55
VDD_SRC CLK_SMBCLK
10
SCL CLK_SMBCLK <14,15>
6
VDD_REF
+VCCP 12 71 CLK_CPU_BCLK
VDD_PCI CPU_0 CLK_CPU_BCLK <5>
72 70 CLK_CPU_BCLK#
CLK_CPU_BCLK# <5>
2

VDD_CPU CPU_0#
@ CLK_48M_CR C853 @ 22P_0402_50V8J 19 68 CLK_MCH_BCLK
VDD_48 CPU_1 CLK_MCH_BCLK <8>
R183
56_0402_5% CLK_48M_ICH C854 @ 22P_0402_50V8J 27 67 CLK_MCH_BCLK#
+VDD_CK505 VDD_PLL3 CPU_1# CLK_MCH_BCLK# <8>
1

FSA R184 2 1 2.2K_0402_5% R185 1 2 1K_0402_5% CLK_14M_ICH C855 @ 22P_0402_50V8J

MCH_CLKSEL0 <8>
66 24 R_CLK_DOT R186 1 2 GM@ 0_0402_5%
VDD_CPU_IO SRC_0/DOT_96 CLK_MCH_DREFCLK <8>
R187 1 2 0_0402_5% CLK_14M_SIO C856 @ 22P_0402_50V8J R188 1 2 PM@ 0_0402_5%
<6> CPU_BSEL0 CLK_PCIE_VGA <16>
31 25 R_CLK_DOT# R189 1 2 GM@ 0_0402_5%
CLK_MCH_DREFCLK# <8>
1

VDD_PLL3_IO SRC_0#/DOT_96# R191 PM@ 0_0402_5%

1 2 CLK_PCIE_VGA# <16>
@ 62
C R190 FOR 3G ISSUE (SED) VDD_SRC_IO
LCDCLK/27M
28 MCH_SSCDREFCLK <8>
C
1K_0402_5% 52
VDD_SRC_IO
29 MCH_SSCDREFCLK# <8> SRC PORT LIST
2

LCDCLK#/27M_SS
23
VDD_IO

CLK_48M_CR 1
R192
2 12_0402_5%
38
VDD_SRC_IO SRC_2
32 CLK_MCH_3GPLL
CLK_MCH_3GPLL <8> PORT DEVICE
+VCCP <34> CLK_48M_CR 33 CLK_MCH_3GPLL#
SRC_2# CLK_MCH_3GPLL# <8>
CLK_48M_ICH 1
R193
2 12_0402_5% FSA 20
SRC0 MCH_DREFCLK
1

<29> CLK_48M_ICH USB_0/FS_A CLK_PCIE_EXP

@ FSB 2
SRC_3
35 CLK_PCIE_EXP <31> SRC2 MCH_3GPLL
R194 R195 FS_B/TEST_MODE CLK_PCIE_EXP#
1K_0402_5% CLK_14M_ICH 1 2 33_0402_5% FSC 7
SRC_3#
36 CLK_PCIE_EXP# <31> SRC3 PCIE_EXP#
<29> CLK_14M_ICH REF_0/FS_C/TEST_
SRC4 PCIE_WLAN2
2

FSB R196 1 2 1K_0402_5% CLK_14M_SIO 1 R197 2 @ 33_0402_5% 8 39 CLK_PCIE_WLAN2

MCH_CLKSEL1 <8><39> CLK_14M_SIO REF_1 SRC_4 CLK_PCIE_WLAN2 <31>

<6> CPU_BSEL1
R198 1 2 0_0402_5% 40 CLK_PCIE_WLAN2#
CLK_PCIE_WLAN2# <31>
SRC6 PCIE_WLAN
CK_PWRGD SRC_4#
1
SRC7 PCIE_WLAN1
1

<29> CK_PWRGD CKPWRGD/PD#

@ CLK_PCIE_WLAN
R199
11
NC SRC_6
57 CLK_PCIE_WLAN <31> SRC8
0_0402_5% CLK_PCIE_WLAN#
SRC_6#
56 CLK_PCIE_WLAN# <31> SRC9 PCIE_LAN
2

PM_STP_CPU#
<29> H_STP_CPU#
53
CPU_STOP#
61 CLK_PCIE_WLAN1
CLK_PCIE_WLAN1 <31>
SRC10 PCIE_ICH
PM_STP_PCI# SRC_7
<29> H_STP_PCI#
54
PCI_STOP#
60 CLK_PCIE_WLAN1#
CLK_PCIE_WLAN1# <31>
SRC11 PCIE_SATA
+VCCP SRC_7#
CLK_XTAL_IN 5
XTAL_IN
64
1

CLK_XTAL_OUT SRC_8/CPU_ITP +3VS

4
B @ XTAL_OUT B
63
R200 SRC_8#/CPU_ITP# SATA_CLKREQ#_R R201 10K_0402_5%
2 1
1K_0402_5% EXP_CLKREQ# R202 2 1 10K_0402_5%
13 44 CLK_PCIE_LAN WLAN_CLKREQ1# R203 2 1 10K_0402_5%
CLK_PCIE_LAN <32>
2

R204 1 PCI_1 SRC_9

FSC 2 10K_0402_5% R205 1 2 1K_0402_5% MCH_CLKSEL2 <8>
MCH_CLKREQ#_R R206 2 1 10K_0402_5%
R207 1 2 @ 33_0402_5% PCI2_TME 14 45 CLK_PCIE_LAN# CLKREQ_LAN# R208 2 1 10K_0402_5%
<39> CLK_PCI_DB PCI_2 SRC_9# CLK_PCIE_LAN# <32>
R209 1 2 0_0402_5% WLAN_CLKREQ# R210 2 1 10K_0402_5%
<6> CPU_BSEL2
15 WLAN_CLKREQ2# R211 2 1 10K_0402_5%
1

PCI_3 CLK_PCIE_ICH
50 CLK_PCIE_ICH <29>
@ R213 1 33_0402_5% PCI4_SEL SRC_10
2 16
R212
<38> CLK_PCI_LPC PCI_4/SEL_LCDCL
51 CLK_PCIE_ICH# REQ PORT LIST
SRC_10# CLK_PCIE_ICH# <29>
0_0402_5% R214 1 2 33_0402_5% ITP_EN 17
<27> CLK_PCI_ICH PCIF_5/ITP_EN
PORT DEVICE
2

48 CLK_PCIE_SATA
SRC_11 CLK_PCIE_SATA <28>
18
VSS_PCI SRC_11#
47 CLK_PCIE_SATA#
CLK_PCIE_SATA# <28> REQ_3# PCIE_EXP#
3
VSS_REF REQ_4# PCIE_WLAN2
+3VS +3VS +3VS EXP_CLKREQ#
22
VSS_48 CLKREQ_3#
37 EXP_CLKREQ# <31> REQ_6# PCIE_WLAN
WLAN_CLKREQ2#
26 41 WLAN_CLKREQ2# <31> REQ_7# PCIE_WLAN1
1

VSS_IO CLKREQ_4#
@ PM@ WLAN_CLKREQ#
R215 R216 R217
69
VSS_CPU CLKREQ_6#
58 WLAN_CLKREQ# <31> REQ_9# PCIE_LAN
10K_0402_5% 10K_0402_5% 10K_0402_5% WLAN_CLKREQ1#
30
VSS_PLL3 CLKREQ_7#
65 WLAN_CLKREQ1# <31> REQ_10#
2

ITP_EN PCI4_SEL PCI2_TME C455 22P_0402_50V8J CLK_XTAL_IN CLKREQ_LAN#

34
VSS_SRC CLKREQ_9#
43 CLKREQ_LAN# <32> REQ_11# PCIE_SATA
1

GM@ @ Y2
59
VSS_SRC SLKREQ_10#
49 REQ_A# MCH_3GPLL
R218 R219 R220 14.31818MHZ_16PF_DSX840GA 42 46 SATA_CLKREQ#_R R221 1 2 0_0402_5%
A VSS_SRC CLKREQ_11# SATA_CLKREQ# <29> A
10K_0402_5% 10K_0402_5% 10K_0402_5%
2

C456 22P_0402_50V8J CLK_XTAL_OUT 73 21 MCH_CLKREQ#_R R222 1 2 0_0402_5% MCH_CLKREQ# <8>

2

VSS USB_1/CLKREQ_A#

Routing the trace at least 10mil SLG8SP556VTR_QFN72_10X10

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# Security Classification Compal Secret Data Compal Electronics,Ltd.
For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96# Issued Date 2008/03/25 Deciphered Date 2008/04/ Title
Pin28/29 : LCDCLK / LCDCLK# Clock Generator CK505
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1 = Pin24/25 : SRC_0 / SRC_0# Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
Pin28/29 : 27M/27M_SS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB3/B4_LA4551P
Date: Wednesday, March 18, 2009 Sheet 23 of 53
5 4 3 2 1
 5 4 3 2 1

+3VS
P/N:SA00002D700 (8101T) FOR 7318C PIN6 PULL DOWN 1.2Kohm
P/N:SA00001U900 (CH7318A) PIN7 PULL DOWN 7.5Kohm

1
@
R223 U17
0_0402_5% PIN7 PULL UP 20Kohm

2
25 +3VS +3VS
OE#

1
D
+3VS 2 D
VCC

1
@ HDMICLK_R 28 11 1 1 1 1
R224 SCL_SINK VCC GM@ GM@ GM@ GM@ R615
VCC 15
1

0_0402_5% HDMIDAT_R 29 21 C457 C458 C459 C460 20K_0402_1%

R225 SDA_SINK VCC 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z @
26

2
VCC 2 2 2 2 TMDS_B_HPD#
4.7K_0402_5% 33

1 2
HDMI_DETECT VCC
GM@ 30 HPD_SINK VCC 40
46
2

VCC R614
32 DDC_EN +3VS 7.5K_0402_1%
1

+3VS 4.7K_0402_5% +3VS @

@ R227 1 2 @ 34 R228 1 2 GM@ 4.7K_0402_5%
PC1 4

2
R226 R229 1 CFG0
2 @ 35 CFG1 3
PC0 internal
R230 1 2 @ 4.7K_0402_5%
0_0402_5% 4.7K_0402_5% pull down

1
internal pull down
2

6 R231 1 2 GM@ 499_0402_1% GM@ GM@

REXT

2
R232 R233
R612 R613 7 TMDS_B_HPD# 2.2K_0402_5% 2.2K_0402_5%
HPD# TMDS_B_HPD# <10>
4.7K_0402_5% 4.7K_0402_5%

2
@ @ SDA 8 HDMIDAT_NB <8>

1
SCL 9 HDMICLK_NB <8>

10 C461 1 2 PM@ 0.1U_0402_16V7K HDMI_CLK-

RT_EN# <18> VGA_HDMI_CLK-
C462 1 2 PM@ 0.1U_0402_16V7K HDMI_CLK+
<18> VGA_HDMI_CLK+
48 13 HDMI_CLK+ C463 1 2 PM@ 0.1U_0402_16V7K HDMI_TX0-
<10> TMDS_B_CLK IN_D4+ OUT_D4+ <18> VGA_HDMI_TX0-
47 14 HDMI_CLK- C464 1 2 PM@ 0.1U_0402_16V7K HDMI_TX0+
C
<10> TMDS_B_CLK# IN_D4- OUT_D4- <18> VGA_HDMI_TX0+ C
45 16 HDMI_TX0+ C465 1 2 PM@ 0.1U_0402_16V7K HDMI_TX1-
<10> TMDS_B_DATA0 IN_D3+ OUT_D3+ <18> VGA_HDMI_TX1-
44 17 HDMI_TX0- C466 1 2 PM@ 0.1U_0402_16V7K HDMI_TX1+
<10> TMDS_B_DATA0# IN_D3- OUT_D3- <18> VGA_HDMI_TX1+
42 19 HDMI_TX1+ C467 1 2 PM@ 0.1U_0402_16V7K HDMI_TX2-
<10> TMDS_B_DATA1 IN_D2+ OUT_D2+ <18> VGA_HDMI_TX2-
41 20 HDMI_TX1- C468 1 2 PM@ 0.1U_0402_16V7K HDMI_TX2+
<10> TMDS_B_DATA1# IN_D2- OUT_D2- <18> VGA_HDMI_TX2+

<10> TMDS_B_DATA2 39 22 HDMI_TX2+ PM@ MBK1608121YZF_0603

IN_D1+ OUT_D1+ HDMI_TX2- L15 1 HDMIDAT_R
38 23 2
TMDS pull down (500ohm) resistors G9x only <10> TMDS_B_DATA2# IN_D1- OUT_D1- <18> VGA_HDMI_SDA
<18> VGA_HDMI_SCL L16 1 MBK1608121YZF_0603
2 HDMICLK_R
PM@
HDMI_CLK+_CONN 1 2
R236 PM@ 499_0402_1% 1 1 1
HDMI_CLK-_CONN GND C469 C470
1 2 GND 5
R237 PM@ 499_0402_1% 12
HDMI_TX0+_CONN GND PM@ PM@
1 2 GND 18
R238 PM@ 499_0402_1% 2 2
GND 24
HDMI_TX0-_CONN 1 2 27 12P_0402_50V8J 12P_0402_50V8J
R239 PM@ 499_0402_1% GND
GND 31
HDMI_TX1+_CONN 1 2 36
R240 PM@ 499_0402_1% GND
GND 37
1

HDMI_TX1-_CONN D +5VS
1 2 GND 43
R241 PM@ 499_0402_1% 2 +3VS 49
HDMI_TX2+_CONN G PAD
1 2
R242 PM@ 499_0402_1% S PM@ GM@ PS8101TQFN48G_QFN48_7X7
3

2
HDMI_TX2-_CONN 1 2 Q2
R243 PM@ 499_0402_1% 2N7002W -T/R7_SOT323-3
+5VS @ R244 D4
B
NEAR CONNECT 0_0805_5% RB491D_SC59-3
B

1
3

2
L17 R249 +5VS_HDMI
HDMI_CLK+ 1 2 HDMI_CLK+_CONN <16> HDMI_DETECT_VGA HDMI_DETECT_VGA 1 2
1 2 PM@ 1K_0402_1% 1 C471
1

0.1U_0402_16V4Z

2
HDMI_CLK- 4 3 HDMI_CLK-_CONN @ PM@
4 3 D6 R250 @

1
W CM-2012-900T_4P RB751V_SOD323 10K_0402_1% D5 R245 R246 2 <18> HDMI_CEC
BAT54S-7-F_SOT23-3 2.2K_0402_5% 2.2K_0402_5%
2

L18

1
HDMI_TX0+ 1 2 HDMI_TX0+_CONN HDMI_DETECT 1 2
1 2 R247 GM@ 0_0402_5% JHDMI
18 +5V
HDMI_TX0- 4 3 HDMI_TX0-_CONN HDMIDAT_R 16 13
4 3 HDMI_CLK+ SDA CEC
1 R825 2 1 2 C857 HDMI_CLK- 1 2 1 2 HDMICLK_R 15 SCL Reserved 14
W CM-2012-900T_4P 68_0402_5% L19 FBMA-L10-160808-121LMT_2P R248 PM@ 0_0402_5% 19
@ 0.5P_0402_50V8 PM@ HP_DET
@ PM@ GND 2
L20 C472 HDMI_CLK-_CONN 12 5
HDMI_TX1+ HDMI_TX1+_CONN HDMI_TX0+ CK- GND
1 1 2 2 1 R826 2 1 2 C858 HDMI_TX0- 330P_0402_50V7K HDMI_CLK+_CONN 10 CK+ GND 8
68_0402_5% HDMI_TX0-_CONN 9 11
@ 0.5P_0402_50V8 HDMI_TX0+_CONN D0- GND
@ 7 D0+ GND 20
HDMI_TX1- 4 3 HDMI_TX1-_CONN +5VS +5VS HDMI_TX1-_CONN 6 21
4 3 HDMI_TX1+ D1- GND
1 R827 2 1 2 C859 HDMI_TX1- HDMI_TX1+_CONN 4 D1+ GND 22
W CM-2012-900T_4P 68_0402_5% 3 3 HDMI_TX2-_CONN 3 23
@ 0.5P_0402_50V8 HDMI_TX2+_CONN D2- GND
@ 1 D2+ DDC/CEC_GND 17
L21 1 HDMIDAT_R 1 HDMICLK_R
HDMI_TX2+ 1 2 HDMI_TX2+_CONN HDMI_TX2+ 1 R828 2 1 2 C860 HDMI_TX2-
1 2 68_0402_5% @ @ SUYIN_100042MR019S153ZL
2 2
A @ @ 0.5P_0402_50V8 D7 D8 A
HDMI_TX2- 4 3 HDMI_TX2-_CONN BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3
4 3
W CM-2012-900T_4P

HDMI_CLK+ R251 1 @ 2 0_0402_5% HDMI_CLK+_CONN

HDMI_CLK- R252 1 @ 2 0_0402_5% HDMI_CLK-_CONN
HDMI_TX0+ R253 1 @ 2 0_0402_5% HDMI_TX0+_CONN Security Classification Compal Secret Data Compal Electronics,Ltd.
HDMI_TX0- R254 1 @ 2 0_0402_5% HDMI_TX0-_CONN 2008/03/25 2008/04/ Title
Issued Date Deciphered Date
HDMI_TX1+ R255 1 @ 2 0_0402_5% HDMI_TX1+_CONN
HDMI_TX1- R256 1 @ 2 0_0402_5% HDMI_TX1-_CONN Level Shiftter_PS8101T
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI_TX2+ R257 1 @ 2 0_0402_5% HDMI_TX2+_CONN Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
HDMI_TX2- R258 1 @ 2 0_0402_5% HDMI_TX2-_CONN Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4601P
Date: W ednesday, March 18, 2009 Sheet 24 of 53
5 4 3 2 1
 5 4 3 2 1

+3VS
LCD POWER CIRCUIT

1
INVT_PWM
R259
+LCDVDD +5VALW DAC_BRIG
4.7K_0402_5%
+3VS D9 DISPOFF#

2
W=60mils BKOFF# 1 2 DISPOFF#
<38> BKOFF#

1
R790 R791 CH751H-40PT_SOD323-2 1 @ 1 @ 1 @
150_0603_1% 100K_0402_5% 1 2 1 ENBKL C475 C476 C477
<10> GMCH_ENBKL ENBKL <38>
C478 R260 GM@ 0_0402_5%
<16> VGA_ENBKL 2 1 470P_0402_50V7K

2
4.7U_0805_10V4Z R261 PM@ 0_0402_5% 2 2 2

2
1

3
D D R792 220K_0402_5%
S
2 R262 470P_0402_50V7K 470P_0402_50V7K D
G
2 1 2 2 100K_0402_1%
Q5 G
2N7002_SOT23 S SI2301BDS-T1-E3_SOT23-3

1
1
DTC124EK 1 change from 10K to 100K
C11 Q6 D 5/8 by checklist For EMI
W=60mils

OUT

1
GM@ 0.1U_0402_16V4Z
R263 1 2 0_0402_5% 2 2 +LCDVDD +LCDVDD_CONN
<10> GM_ENVDD IN Q4 L23

GND
DTC124EKAT146_SC59-3 1 2

1
FBMA-L11-201209-221LMA30T_0805
R265 1 2 0_0402_5%

3
<16> VGA_ENVDD
R264 @ 1 1
PM@ 100K_0402_5% C473 C474
B+

2
4.7U_0805_10V4Z 0.1U_0402_16V4Z +LEDVDD L22
2 2 1 2
FBMA-L11-201209-221LMA30T_0805

1 1
C837
UMA LCD/PANEL BD. Conn. VGA LCD/PANEL BD. Conn.
680P_0402_50V7K C479
4.7U_0805_25V6-K
JLVDS1 +LEDVDD @ 2 2
1 2 +LEDVDD JLVDS2
1 2 +LEDVDD
+LCDVDD_CONN (60 MIL) 3
3 4
4 +LCDVDD_CONN 1
1 2
2
5
5 6
6 (60 MIL) 3
3 4
4 +LCDVDD_CONN
7 8 +LCDVDD_CONN 5 6
+3VS 7 8 +3VS 5 6
9 10 LVDS_B2# 7 8
9 10 LVDS_B2# <10> +3VS 7 8 +3VS
11 12 LVDS_B2 9 10 VGA_LVDS_B2#
11 12 LVDS_BCLK# LVDS_B2 <10> 9 10 VGA_LVDS_B2 VGA_LVDS_B2# <18>
<38> INVT_PWM 13 14 LVDS_BCLK# <10> 11 12 VGA_LVDS_B2 <18>
C DISPOFF# 13 14 LVDS_BCLK 11 12 VGA_LVDS_BCLK# C
15 15 16 16 LVDS_BCLK <10> <38> INVT_PWM 13 13 14 14 VGA_LVDS_BCLK# <18>
17 18 LVDS_B1# @ DISPOFF# 15 16 VGA_LVDS_BCLK
<38> DAC_BRIG 17 18 LVDS_B1# <10> 680P_0402_50V7K 1 15 16 VGA_LVDS_BCLK <18>
19 20 LVDS_B1 17 18 VGA_LVDS_B1#
19 20 LVDS_B1 <10> C836 <38> DAC_BRIG 17 18 VGA_LVDS_B1# <18>
21 22 LVDS_A0# 19 20 VGA_LVDS_B1
21 22 LVDS_A0 LVDS_A0# <10> 19 20 VGA_LVDS_A0# VGA_LVDS_B1 <18>
23 23 24 24 21 21 22 22
LVDS_B0 LVDS_A0 <10> 2 VGA_LVDS_A0 VGA_LVDS_A0# <18>
25 26 LVDS_B0 <10> 23 24
25 26 LVDS_B0# 23 24 VGA_LVDS_B0 VGA_LVDS_A0 <18>
27 27 28 28 LVDS_B0# <10> 25 25 26 26
LVDS_A1 VGA_LVDS_B0# VGA_LVDS_B0 <18>
29 30 LVDS_A1 <10> 27 28
29 30 LVDS_A1# 27 28 VGA_LVDS_A1 VGA_LVDS_B0# <18>
31 31 32 32 LVDS_A1# <10> 29 29 30 30 VGA_LVDS_A1 <18>
33 34 LVDS_A2# 31 32 VGA_LVDS_A1#
33 34 LVDS_A2 LVDS_A2# <10> 31 32 VGA_LVDS_A2# VGA_LVDS_A1# <18>
35 35 36 36 LVDS_A2 <10> 33 33 34 34 VGA_LVDS_A2# <18>
LVDS_SCL 37 38 LVDS_ACLK# 35 36 VGA_LVDS_A2
<10> LVDS_SCL 37 38 LVDS_ACLK# <10> 35 36 VGA_LVDS_A2 <18>
LVDS_SDA 39 40 LVDS_ACLK VGA_LVDS_SCL 37 38 VGA_LVDS_ACLK#
<10> LVDS_SDA 39 40 LVDS_ACLK <10> <16> VGA_LVDS_SCL VGA_LVDS_SDA 37 38 VGA_LVDS_ACLK VGA_LVDS_ACLK# <18>
<16> VGA_LVDS_SDA 39 40 VGA_LVDS_ACLK <18>
39 40
41 42
GND GND
41 42
ACES_87142-4041 GND GND
ACES_87142-4041

+LEDVDD

JLVDS4
JLVDS3 1
1
1 1 2 2 G1 41
2
2 G1
41 400mA 3
3 G2
42
3 42 4 43
3 G2 +LEDVDD 4 G3
4 43 +LEDVDD 5 44
+LEDVDD 4 G3 5 G4
5 44 6 45
5 G4 6 G5
6 45 7 46
B 6 G5 7 G6 B
7 7 G6 46 +LCDVDD_CONN (60 MIL) 8 8
+LCDVDD_CONN (60 MIL) 8 8 9 9
9 10
9 10
10 10 +3VS 11 11
+3VS 11 <38> INVT_PWM 12
11 DISPOFF# 12
<38> INVT_PWM 12 13
DISPOFF# 12 DAC_BRIG 13
13 <38> DAC_BRIG 14
DAC_BRIG 13 VGA_LVDS_SCL 14
<38> DAC_BRIG 14 <16> VGA_LVDS_SCL 15
LVDS_SCL 14 VGA_LVDS_SDA 15
<10> LVDS_SCL 15 <16> VGA_LVDS_SDA 16
LVDS_SDA 15 16
<10> LVDS_SDA 16 16 17 17
17 VGA_LVDS_B2# 18
17 <18> VGA_LVDS_B2# 18
LVDS_B2# 18 VGA_LVDS_B2 19
<10> LVDS_B2# 18 <18> VGA_LVDS_B2 19
LVDS_B2 19 20
<10> LVDS_B2 19 20
20 VGA_LVDS_BCLK# 21
20 <18> VGA_LVDS_BCLK# 21
LVDS_BCLK# 21 VGA_LVDS_BCLK 22
<10> LVDS_BCLK# LVDS_BCLK 21 <18> VGA_LVDS_BCLK 22
<10> LVDS_BCLK 22 23
22 VGA_LVDS_B1# 23
23 <18> VGA_LVDS_B1# 24
LVDS_B1# 23 VGA_LVDS_B1 24
<10> LVDS_B1# 24 <18> VGA_LVDS_B1 25
LVDS_B1 24 25
<10> LVDS_B1 25 26
25 VGA_LVDS_A0# 26
26 <18> VGA_LVDS_A0# 27
LVDS_A0# 26 VGA_LVDS_A0 27
<10> LVDS_A0# 27 <18> VGA_LVDS_A0 28
LVDS_A0 27 28
<10> LVDS_A0 28 28 29 29
29 VGA_LVDS_B0 30
29 <18> VGA_LVDS_B0 30
LVDS_B0 30 VGA_LVDS_B0# 31
<10> LVDS_B0 30 <18> VGA_LVDS_B0# 31
<10> LVDS_B0# LVDS_B0# 31 32
31 VGA_LVDS_A1 32
32 <18> VGA_LVDS_A1 33
LVDS_A1 32 VGA_LVDS_A1# 33
<10> LVDS_A1 33 33 <18> VGA_LVDS_A1# 34 34
LVDS_A1# 34 35
<10> LVDS_A1# 34 35
35 VGA_LVDS_A2# 36
35 <18> VGA_LVDS_A2# 36
LVDS_A2# 36 VGA_LVDS_A2 37
<10> LVDS_A2# 36 <18> VGA_LVDS_A2 37
LVDS_A2 37 38
<10> LVDS_A2 37 38
38 VGA_LVDS_ACLK# 39
A LVDS_ACLK# 38 <18> VGA_LVDS_ACLK# VGA_LVDS_ACLK 39 A
<10> LVDS_ACLK# 39 <18> VGA_LVDS_ACLK 40
LVDS_ACLK 39 40
<10> LVDS_ACLK 40 40 IPEX_20143-040E-20F
IPEX_20143-040E-20F

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS & DVI Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4601P
Date: Wednesday, March 18, 2009 Sheet 25 of 53
5 4 3 2 1
 A B C D E

CLOSE TO CHIPSET CLOSE TO CONN FCM1608CF-121T03_2P

R266 1 2 PM@ 0_0402_5% CRT_R_1 L24 1 2 RED
<16> VGA_CRT_R
R267 GM@ 0_0402_5%
<10> GMCH_CRT_R
FCM1608CF-121T03_2P
1 R268 1 2 PM@ 0_0402_5% CRT_G_1 L25 1 2 GREEN 1
<16> VGA_CRT_G
R269 1 2 GM@ 0_0402_5%
<10> GMCH_CRT_G
FCM1608CF-121T03_2P
R270 1 2 PM@ 0_0402_5% CRT_B_1 L26 1 2 BLUE
<16> VGA_CRT_B
R271 1 2 GM@ 0_0402_5%
<10> GMCH_CRT_B

1
1 1 1 1 1
R272 R273 R274 C481 C483 C484 C485 C486
150_0402_1% 150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J
2 2 2 2 2
CRT Connector

2
+5VS +5VS +5VS +CRT_VCC
+5VS
D10
3 3 3 UPDATE FOR PVT
2 1
1 BLUE 1 GREEN 1 RED 1
RB491D_SC59-3
2 2 2 C480
@ @ @
D11 D12 D13 W=40mils 2
0.1U_0402_16V4Z

BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3

+5VS +5VS

+CRT_VCC 3
2 JVGA_HS 1 JVGA_VS 2
1

1
2
C487 R275 @ JCRT1
0.1U_0402_16V4Z 1K_0402_5% D15 1
2 BAT54S-7-F_SOT23-3 RED 1
<BOM Structure> 2 2
3

2
FCM1608CF-121T03_2P GREEN 3
4 4
R276 1 2 PM@ 0_0402_5% CRT_HSYNC_1 L27 1 2 JVGA_HS 5
<16> VGA_HSYNC 5
BLUE 6
FCM1608CF-121T03_2P 6
<10> GMCH_CRT_HSYNC 7 7
L28 1 2 JVGA_VS JVGA_VS 8 8
1 1 9 9
@ JVGA_HS 10
C488 @ C489 CRT_DDC_DAT 10
11 11
+CRT_VCC 10P_0402_50V8J 10P_0402_50V8J CRT_DDC_CLK 12
2 2 12

1 13 GND1
14 GND2
Place closed to chipset C490
0.1U_0402_16V4Z ACES_87213-1200G
2 ME@
5

1
OE#
P

R277 1 2 PM@ 0_0402_5% 2 4 CRT_VSYNC_1

<16> VGA_VSYNC A Y
G

U20
<10> GMCH_CRT_VSYNC
SN74AHCT1G125DCKR_SC70-5
3

3 3

2.2K
+3VS

+CRT_VCC
2.2K
1

+3VS
1

R278 R279
2.2K_0402_5% 2.2K_0402_5%
R282
2

<16> VGA_DDCDATA 2.2K_0402_5%

2

4 3 CRT_DDC_DAT
<10> GMCH_CRT_DATA

Q30B
2

2N7002DW -T/R7_SOT363-6
R284 1 2 GM@ 0_0402_5% 1 6 CRT_DDC_CLK
<10> GMCH_CRT_CLK
1 1
<16> VGA_DDCCLK R285 1 2 PM@ 0_0402_5% @ @
Q30A C491 C492
2N7002DW -T/R7_SOT363-6 100P_0402_50V8J 68P_0402_50V8K
2 2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TV-OUT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4601P
Date: W ednesday, March 18, 2009 Sheet 26 of 53
A B C D E
 5 4 3 2 1

+3VS

R313
GATEA20 2 1
+RTCVCC 10K_0402_5%

R314 330K_0402_1% C494 1 2 ICH_RTCX1 R315

1 2 LAN100_SLP 10P_0402_50V8J KB_RST# 2 1

1
R316 1M_0402_5% Y3 10K_0402_5%
1 2 SM_INTRUDER# 2 NC IN 1
32.768KHZ_12.5P_1TJS125BJ2A251 R317 +VCCP
R318 330K_0402_1% 3 4 10M_0402_5%
D NC OUT D
1 2 ICH_INTVRMEN R319 @

2
LPC_AD[0..3] <38,39> H_DPRSTP#
U21A 2 1
C23 K5 LPC_AD0
C496 1 ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1 56_0402_5%
2 C24 K4
10P_0402_50V8J RTCX2 FWH1/LAD1 LPC_AD2 R321 @
L6
ICH_RTCRST# FWH2/LAD2 LPC_AD3 H_DPSLP#
+RTCVCC 1 2 A25 RTCRST# FWH3/LAD3 K2 2 1
+RTCVCC R320 20K_0402_5% ICH_SRTCRST# F20
SM_INTRUDER# SRTCRST# LPC_FRAME# 56_0402_5%
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# <38,39>

RTC

LPC
CLRP1
ICH_INTVRMEN B22 J3 LPC_DRQ0#
+RTCBATT LAN100_SLP INTVRMEN LDRQ0# LPC_DRQ0# <39>
R322 2 1 A22 J1 +VCCP
LAN100_SLP LDRQ1#/GPIO23
1 2
E25 N7 GATEA20
2MM GLAN_CLK A20GATE GATEA20 <38>

1
2 100_0603_1% AJ27 H_A20M#
A20M# H_A20M# <5>
C495 1 2 C13
LAN_RSTSYNC
C497 1U_0603_10V4Z AJ25 H_DPRSTP_R# R323 2 1 0_0402_5% H_DPRSTP#
H_DPRSTP# <6,8,50>
R324
0.1U_0402_16V4Z DPRSTP# H_DPSLP# 56_0402_5%
F14 LAN_RXD0 DPSLP# AE23 H_DPSLP# <6>
1
close to RAM door G13

2
LAN_RXD1 H_FERR#_S R325 1
D14 LAN_RXD2 FERR# AJ26 2 56_0402_5% H_FERR# <5>

LAN / GLAN
D13 AD22 H_PWRGOOD
LAN_TXD_0 CPUPWRGD H_PWRGOOD <6>
D12
LAN_TXD_1 H_IGNNE#
E13 LAN_TXD_2 IGNNE# AF25 H_IGNNE# <5>
+1.5VS B10 AE22 H_INIT#
GPIO56 INIT# H_INIT# <5> +VCCP
AG25 H_INTR

CPU
GLAN_COMP INTR KB_RST# H_INTR <5>
1 2 B28 L3 KB_RST# <38>
R326 24.9_0402_1% GLAN_COMPI RCIN#
B27
GLAN_COMPO

1
1 2 HDA_BITCLK_R AF23 H_NMI
<8,36> HDA_BITCLK_CODEC NMI H_NMI <5>
R327 33_0402_5% AF6 AF24 H_SMI#
HDA_SYNC_R HDA_BIT_CLK SMI# H_SMI# <5>
1 2 AH4 R328
<8,36> HDA_SYNC_CODEC HDA_SYNC H_STPCLK#
R329 33_0402_5% AH27 56_0402_5%
C HDA_RST_R# STPCLK# H_STPCLK# <5> C
1 2 AE7

2
<8,36> HDA_RST_CODEC# HDA_RST# THRMTRIP_ICH# H_THERMTRIP#
R330 33_0402_5% AG26 R331 1 2 54.9_0402_1%
THRMTRIP# H_THERMTRIP# <5,8>
<8> HDA_SDIN0 AF4
HDA_SDIN0
HDA_SDIN1 AG4 HDA_SDIN1 TP12 AG27
<36> HDA_SDIN2 AH3 HDA_SDIN2
AE5

IHDA
HDA_SDIN3 SATA_DTX_C_IRX_N4 0.01U_0402_16V7K C826 SATA_DTX_IRX_N4_CONN
SATA4RXN AH11 2 1 SATA_DTX_IRX_N4_CONN <35>
1 2 HDA_SDOUT_R AG5 AJ11 SATA_DTX_C_IRX_P4 0.01U_0402_16V7K 2 1 C827 SATA_DTX_IRX_P4_CONN
<8,36> HDA_SDOUT_CODEC HDA_SDOUT SATA4RXP SATA_DTX_IRX_P4_CONN <35>
R333 33_0402_5% AG12 SATA_ITX_C_DRX_N4 0.01U_0402_16V7K 2 1 C824 SATA_ITX_DRX_N4_CONN
SATA4TXN SATA_ITX_DRX_N4_CONN <35>
AG7 AF12 SATA_ITX_C_DRX_P4 0.01U_0402_16V7K 2 1 C825 SATA_ITX_DRX_P4_CONN
HDA_DOCK_EN#/GPIO33 SATA4TXP SATA_ITX_DRX_P4_CONN <35>
+3VS 1 2 AE8 HDA_DOCK_RST#/GPIO34
R335 10K_0402_5%
<42> DRIVE_LED#
DRIVE_LED# 2 1 SATA_LED# AG8 SATALED#
NEAR U42
RB751V_SOD323 D16 AH9 R336 1 2 @ 1K_0402_5%
SATA_DTX_C_IRX_N0 SATA5RXN R337 1
<35> SATA_DTX_C_IRX_N0 AJ16 AJ9 2 @ 1K_0402_5%
SATA_DTX_C_IRX_P0 SATA0RXN SATA5RXP
HDD <35> SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0 C498 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_N0
AH16
AF17
SATA0RXP SATA5TXN
AE10
AF10
<35> SATA_ITX_DRX_N0 SATA0TXN SATA5TXP
<35> SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 C499 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P0 AG17
SATA0TXP CLK_PCIE_SATA#
AH18 CLK_PCIE_SATA# <23>
SATA_CLKN

SATA
SATA_DTX_C_IRX_N1 AH13 AJ18 CLK_PCIE_SATA
<35> SATA_DTX_C_IRX_N1 SATA1RXN SATA_CLKP CLK_PCIE_SATA <23>
SATA_DTX_C_IRX_P1 AJ13 AJ7
<35> SATA_DTX_C_IRX_P1 SATA1RXP SATARBIAS#
SATA_ITX_DRX_N1 C500 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_N1 SATARBIAS R338 1 2 24.9_0402_1%
ODD <35> SATA_ITX_DRX_N1 SATA_ITX_DRX_P1 C501 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P1
AG14
SATA1TXN SATARBIAS
AH7
<35> SATA_ITX_DRX_P1 AF14
SATA1TXP 10mils width less than 500mils

ICH9-M ES_FCBGA676

B
SATA PORT LIST B

Need check
PORT DEVICE
+3VS
XOR Chain Entrance Strap 0 HDD
2

ICH_TP3 HDA_SDOUT Description 1 ODD

R339
1K_0402_5% 0 0 RSVD 2 X
@
0 1 Enter XOR Chain 3 X
1

HDA_SDOUT_R
1 0 Normal Operation 4 ESATA
1 1 Set PCIE port config bit 1 5 X

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(2/4)-LAN,IDELPC,RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom JITR1_LA-4141P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 18, 2009 Sheet 28 of 53
5 4 3 2 1
 5 4 3 2 1

+3VS

SERIRQ
+3VALW
PCI_CLKRUN#
+3VS
GPIO38 +3VALW

EC_THERM#
CLK_48M_ICH CLK_14M_ICH

OCP# <23,31> ICH_SMBCLK

D <23,31> ICH_SMBDATA D
LINKALERT#
ME__EC_CLK1
PM_BMBUSY# ME__EC_DATA1
CLK_14M_ICH
+3VS CLK_14M_ICH <23> +3VALW
GPIO39 ICH_RI# CLK_48M_ICH
CLK_48M_ICH <23>
GPIO48 ICH_SUSCLK
XDP_DBRESET#
<5> XDP_DBRESET#
SLP_S3#
SLP_S3# <38>
PM_BMBUSY# SLP_S4#
+3VALW <8> PM_BMBUSY# SLP_S4# <38>
SLP_S5#
SLP_S5# <38>
LID_OUT#
<38> EC_LID_OUT#
LINKALERT# S4_STATE#
H_STP_PCI# M_PWROK
<23> H_STP_PCI#
CL_RST# R_STP_CPU# ICH_POK M_PWROK
<23> H_STP_CPU# ICH_POK <8,38>
XDP_DBRESET# PCI_CLKRUN# DPRSLPVR
DPRSLPVR <8,50>
ICH_RI# ICH_PCIE_WAKE# ICH_LOW_BAT#
<31,32> ICH_PCIE_WAKE#
SERIRQ
<38,39> SERIRQ
ICH_PCIE_WAKE# EC_THERM# PBTN_OUT#
<38> EC_THERM# PBTN_OUT# <38>
ICH_LOW_BAT# VRMPWRGD
<8,50> VGATE
LID_OUT# SST_CTL EC_RSMRST#R EC_RSMRST#R

WOL_EN OCP# CK_PWRGD_R CK_PWRGD

OCP# CK_PWRGD <23>
<31,38> CPUSB#
GPIO7 M_PWROK
M_PWROK <8>
EC_SMI# +3VS
+3VS <38> EC_SMI# VGATE <8,50>
EC_SCI#
<38> EC_SCI#
GPIO13
GPIO7 GPIO17
CL_CLK0 <8>
GPIO18
CL_CLK1
GPIO13 GPIO20
GPIO22
CL_DATA0 <8>
GPIO17 GPIO27
CL_DATA1
C C
GPIO18 SATA_CLKREQ# CL_VREF0_ICH
<23> SATA_CLKREQ#
GPIO38 CL_VREF1_ICH +3VALW
GPIO20 GPIO39
GPIO48 CL_RST#
CL_RST# <8>
GPIO22 GPIO49
GPIO57
SB_INT_FLASH_SEL <40>
SB_SPKR ACIN
+3VS <36> SB_SPKR ACIN <38,44,46>
MCH_ICH_SYNC# GPIO14
<8> MCH_ICH_SYNC#
ICH_RSVD +3VALW
SB_SPKR
WOL_EN

GPIO57

DPRSLPVR

ICH_RSVD

POK <47>

EC_RSMRST#R
+3VALW <38> EC_RSMRST#
PCIE_RXN1 DMI_RXN0 DMI_RXN0 <8>
<31> PCIE_RXN1
PCIE_RXP1 DMI_RXP0 DMI_RXP0 <8>
<31> PCIE_RXP1
USB_OC#6 <31> PCIE_TXN1 PCIE_C_TXN1 DMI_TXN0 DMI_TXN0 <8> +3VALW
USB_OC#1 <31> PCIE_TXP1 PCIE_C_TXP1 DMI_TXP0 DMI_TXP0 <8>
USB_OC#2
USB_OC#4 DMI_RXN1 DMI_RXN1 <8>
DMI_RXP1 DMI_RXP1 <8>
DMI_TXN1 DMI_TXN1 <8>
DMI_TXP1 DMI_TXP1 <8>
USB_OC#5 PCIE_RXN3 DMI_RXN2 DMI_RXN2 <8>
<31> PCIE_RXN3
USB_OC#7 PCIE_RXP3 DMI_RXP2 DMI_RXP2 <8>
<31> PCIE_RXP3
USB_OC#9 <31> PCIE_TXN3 PCIE_C_TXN3 DMI_TXN2 DMI_TXN2 <8>
USB_OC#0 <31> PCIE_TXP3 PCIE_C_TXP3 DMI_TXP2 DMI_TXP2 <8>
B B
PCIE_RXN4 DMI_RXN3 DMI_RXN3 <8>
<31> PCIE_RXN4
PCIE_RXP4 DMI_RXP3 DMI_RXP3 <8>
<31> PCIE_RXP4
<31> PCIE_TXN4 PCIE_C_TXN4 DMI_TXN3 DMI_TXN3 <8>
USB_OC#8 <31> PCIE_TXP4 PCIE_C_TXP4 DMI_TXP3 DMI_TXP3 <8>
USB_OC#3
USB_OC#10 PCIE_RXN5 CLK_PCIE_ICH#
<31> PCIE_RXN5 CLK_PCIE_ICH# <23>
USB_OC#11 PCIE_RXP5 CLK_PCIE_ICH
<31> PCIE_RXP5 CLK_PCIE_ICH <23>
<31> PCIE_TXN5 PCIE_C_TXN5
<31> PCIE_TXP5 PCIE_C_TXP5
DMI_IRCOMP +1.5VS
PCIE_IRX_PTX_N6
<32> PCIE_IRX_PTX_N6
PCIE_IRX_PTX_P6 USB20_N0
<32> PCIE_IRX_PTX_P6 USB20_N0 <35>
<32> PCIE_ITX_C_PRX_N6 PCIE_ITX_PRX_N6 USB20_P0
USB20_P0 <35>
<32> PCIE_ITX_C_PRX_P6 PCIE_ITX_PRX_P6 USB20_N1
USB20_N1
USB20_P1
USB20_P1
USB20_N2
+3VS USB20_N2 <41>
USB20_P2
USB20_P2 <41>
SB_SPI_CS#1 USB20_N3
<27> SB_SPI_CS#1 USB20_N3 <31>
USB20_P3
USB20_P3 <31>
USB20_N4
USB20_N4 <41>
USB20_P4
USB20_P4 <41>
USB20_N5
USB20_N5
USB_OC#0 USB20_P5
<35> USB_OC#0 USB20_P5
USB_OC#1 USB20_N6
USB20_N6 <41>
VRMPWRGD USB_OC#2 USB20_P6
USB20_P6 <41>
USB_OC#3 USB20_N7
USB20_N7 <34>
USB_OC#4 USB20_P7
<41> USB_OC#4 USB20_P7 <34>
USB_OC#5 USB20_N8
<50> CLK_ENABLE# USB20_N8 <31>
USB_OC#6 USB20_P8
USB20_P8 <31>
USB_OC#7 USB20_N9
USB20_N9 <31>
USB_OC#8 USB20_P9
USB20_P9 <31>
USB_OC#9 USB20_N10
USB20_N10 <31>
USB_OC#10 USB20_P10
USB20_P10 <31>
USB_OC#11 USB20_N11
<41> USB_OC#11 USB20_N11 <41>
USB20_P11
USB20_P11 <41>
USBRBIAS
A A

Security Classification Compal Secret Data

Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(3/4)-USB,GPIO,PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sheet of
5 4 3 2 1
2008/10/15
5 4 3 2 1

+VCCP
20 mils
+RTCVCC
ICH_V5REF_RUN

1 1
ICH_V5REF_SUS C518 C521 0.1U_0402_16V4Z

0.1U_0402_16V4Z
2 2

+5VS +3VS

D D
0.01U_0402_16V7K +1.5VS

1 1
C519 C522 10U_0805_6.3V6M

ICH_V5REF_RUN 2 2
20 mils
+VCCP

+5VALW +3VALW

+VCCP

+3VS
ICH_V5REF_SUS +3VS (DMI)
20 mils +3VS (SATA)
1
C530

1U_0603_10V4Z
2
C C
+3VS
40 mils
+1.5VS +3VS +1.5VS

+1.5VS

+1.5VS

VCCSUS1_5_ICH_1

VCCSUS1_5_ICH_2 1 2 +3VALW
R409
0_0402_5%
PM@
+1.5VS

+3VALW
B B

+1.5VS

+3VALW

+1.5VS
+1.5VS
1
C551
0.1U_0402_16V4Z
2

VCC_LAN1_05_INT_ICH_1
+3VS VCC_LAN1_05_INT_ICH_2 VCCCL1_05_ICH
close to AC7

+3VS
A A

+1.5VS 1
C554
(10UF*1, 2.2UF*1) 2
10U_0805_10V4Z
KIWB3/B4_LA4551P
+1.5VS +3VS
Security Classification Compal Secret Data m434[(0)-3.11
Compal El
Electronics,
-0 330115Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(4/4)-POWER&GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom JITR1_LA-4141P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 18, 2009 Sheet 30 of 53
5 4 3 2 1
 A B C D E

+1.5VS_TV +3VS_TV

Mini-Express Card for 3G Or TV Tuner +5VALW

+3VALW +3V_WWAN

+3VS

Mini-Express Card(Slot 1-TV TUNNER) 4.0mm high

+3VS_TV USB20_N3_R
<29> USB20_N3
+1.5VS_TV USB20_P3_R
<29> USB20_P3
+3VS +3VS_TV
SUSP AO_3G#
<43,48,49> SUSP <38> AO_3G#
<23> WLAN_CLKREQ# WLAN_CLKREQ#

<23> CLK_PCIE_WLAN#
1 <23> CLK_PCIE_WLAN 1

TV_RST#
+3V_WWAN +3VS
<29> PCIE_RXN5
<29> PCIE_RXP5
PLT_RST# <8,16,27,32>
Mini-Exp3(e)8.680405 -62.16
CS,
Td[(M)-0.993546(i)3.642[(M(-)-2)106(E)6.18218(
INC.
, IN C. )13.0cm BT/R7 3+3V_WWAN
Tf0 0.99672
aMPAL
-1 -0 572
ELECTRONI
<29> PCIE_TXN5
<29,32> ICH_PCIE_WAKE# ICH_PCIE_WAKE#
<29> PCIE_TXP5 +1.5VS
<41> BT_ACTIVE BT_ACTIVE
+3VS_TV USB20_N9 <29>
<41> WLAN_ACTIVE WLAN_ACTIVE
USB20_P9 <29>
<23> WLAN_CLKREQ2# WLAN_CLKREQ2# +UIM_PWR
UIM_DATA
UIM_CLK
<23> CLK_PCIE_WLAN2#
UIM_RST
<23> CLK_PCIE_WLAN2
UIM_VPP
EC_TX_P80_DATA
<38,39> EC_TX_P80_DATA 3G_OFF# <38>
EC_RX_P80_CLK
<38,39> EC_RX_P80_CLK WL_OFF# <38>
PLT_RST# <8,16,27,32>
<29> PCIE_RXN1 +3V_WWAN
<29> PCIE_RXP1 +3VS

ICH_SMBCLK <23,29>
<29> PCIE_TXN1 ICH_SMBDATA <23,29>
<29> PCIE_TXP1
USB20_N3_R
+3V_WWAN USB20_P3_R

+3VS +1.5VS 3G_LED# 3G_LED# <42>

+5VS +1.5VS

EC_TX_P80_DATA
<38,39> EC_TX_P80_DATA
EC_RX_P80_CLK
<38,39> EC_RX_P80_CLK

2 2

+3VS_TV +1.5VS_TV

<38> TV_POWER_SW

+3VALW

UIM_DATA +UIM_PWR

+3VS
SYSON
<38,43,48,49> SYSON
AO_SYSON

+3VS
AO_NEWCARD
<38> AO_NEWCARD
+3VS +3VALW +UIM_PWR
UIM_VPP UIM_RST
ICH_PCIE_WAKE# +1.5VS AO_SUSP# UIM_DATA UIM_CLK
<29,32> ICH_PCIE_WAKE#
<41> BT_ACTIVE BT_ACTIVE SUSP#
<38,43,48,49> SUSP#
<41> WLAN_ACTIVE WLAN_ACTIVE
<23> WLAN_CLKREQ1# WLAN_CLKREQ1#

<23> CLK_PCIE_WLAN1#
<23> CLK_PCIE_WLAN1

3G_OFF# <38>
WL_OFF# <38>
PLT_RST# <8,16,27,32>
+3VALW +UIM_PWR
<29> PCIE_RXN3
<29> PCIE_RXP3 +3VS
3 3
ICH_SMBCLK <23,29>
<29> PCIE_TXN3 ICH_SMBDATA <23,29>
<29> PCIE_TXP3
+3VS USB20_N8 <29>
USB20_P8 <29>

WLAN_LED# +3VS
WLAN_LED# <42>

<23,29> ICH_SMBCLK
EC_TX_P80_DATA
<38,39> EC_TX_P80_DATA
EC_RX_P80_CLK USB20_N10_R <23,29> ICH_SMBDATA
<38,39> EC_RX_P80_CLK <29> USB20_N10
USB20_N10_R
USB20_P10_R USB20_P10_R
<29> USB20_P10
2005/09/27 modified. CPUSB#
<29,38> CPUSB#
SUSP
Base on OPTION GTM351E Datasheet Rev0.1 <43,48,49> SUSP

Vcc 3.3V +/- 8%

Peak Icc 2750mA +1.5VS_CARD1
with max supply droop 50mA +5VALW
<29,32> ICH_PCIE_WAKE#
Average Icc 1000mA +3VALW_CARD1
+1.5VS_CARD1 PERST#
+3VS_CARD1

+1.5VS <23> EXP_CLKREQ#

CPUSB#
+1.5VS +1.5VS_CARD1
<23> CLK_PCIE_EXP#
<38,45> EC_SMB_CK1 <23> CLK_PCIE_EXP

+3VS_CARD1 <29> PCIE_RXN4

+3VALW <29> PCIE_RXP4
+3VS AO_NEWCARD
+3VS_CARD1 <38> AO_NEWCARD
+3VALW_CARD1 <29> PCIE_TXN4
<29> PCIE_TXP4
+3VS +3VALW
4 <38,45> EC_SMB_DA1 4
PLT_RST#
<8,16,27,32> PLT_RST#
AO_SYSON PERST#

AO_SUSP#

+3VALW +3VALW_CARD1
CPUSB#
+3VALW <29,38> CPUSB#
Security Classification
2007/10/15
Compal Secret Data
2008/10/15 Title
Compal Electronics, Inc.
Issued
Iss
d(ECCCI
Date E EDeciphered Date E E E E E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/3G/FeliCa/BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS JITR1_LA-4141P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 18, 2009 Sheet 31 of 53
A B C D E
 5 4 3 2 1

+3VALW
L29 @
1 2
MBK3216260YZF_2P +1.2V_LAN
+3V_LAN
+5VALW

S
1 3 1 1 1 1 1 1
2 2 1
C574 C575 C576 C577 C578 C579
Q33 C581 C582 C583 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

G
2
AO3414_SOT23-3 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2
1 1 2

1
Layout Notice : 1.2V filter. Place as close chip as possible.

1
D
D D
EN_WOL 2 Q34 C585
<38> EN_WOL
G 2N7002_SOT23 0.1U_0603_25V7K Layout Notice : Place as close chip as possible.
S 2 +2.5V12_LAN

3
+3V_LAN

1
+3V_LAN +2.5V12_LAN R772
0_0402_5%
EMI 20080826 100@

2
1

R440 R441 C32

56
61
15
19

38
52
68
6
0_0805_5% 0_0805_5% 1 2 U24
GIGA@ 100@

DC
DC
DC
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
1000P_0402_50V7K +LAN_BIASVDD
2

36 +3V_LAN
R444 1 GIGA@ 2 0_0402_5% BIASVDDH
+2.5V12_LAN 5
R442 1 100@ VDDC_IO +XTALVDD
2 0_0402_5% 55 C588 1 2 0.1U_0402_16V4Z
L30 VDDC_IO
+1.2V_LAN 13
VDDC
1 2 +LAN_BIASVDD 20 23
MBK1608601YZF_2P VDDC XTALVDDH
1 34

1
VDDC
60
C586 VDDC
0.1U_0402_16V4Z R443
2 4.7K_0402_5% U23
+LAN_AVDD 8 1

2
L31 LAN_WP VCC A0
7 2
LAN_AVDDH LAN_CLK WP A1
1 2 +XTALVDD 48 6 3
MBK1608601YZF_2P AVDDH AVDDH_LAN_TRD1N LAN_DATA SCL NC
2 42 5 4
AVDDH SDA GND
C587 AT24C02_SO8
0.1U_0402_16V4Z
1 39
+AVDDL AVDDL
L32 45
AVDDL
1 2 +LAN_AVDD 51
MBK1608601YZF_2P AVDDL R4461 100@ 0_0402_5% LAN_RX1-
C 2 C
0.01U_0402_16V7K

LAN_RX1- <33>
0.047U_0402_16V4Z

0.047U_0402_16V4Z

1 1 1
49 LAN_TX3- AVDDH_LAN_TRD1N R4471 GIGA@ 2 0_0402_5% LAN_AVDDH
TRD3_N LAN_TX3- <33>
C589 C590 C591 50 LAN_TX3+
TRD3_P LAN_TX3+ <33>
35 R4481 100@ 2 0_0402_5% LAN_RX1+
2 2 2 +GPHY_PLLVDD GPHY_PLLVDDL
47 LAN_TX2-
TRD2_N LAN_TX2- <33>
46 LAN_TX2+ LAN_TRD1N_TRD1P R4491 GIGA@ 2 0_0402_5% LAN_RX1-
EMI 20080826 TRD2_P LAN_TX2+ <33> LAN_RX1- <33>
+1.2V_LAN 43 LAN_TRD1N_TRD1P
TRD1_N
TRD1_P
44 LAN_RX1+
LAN_RX1+ <33>
C35 EMI 20080826
L33 +PCIE_PLLVDD 30 1 2
PCIE_PLLVDDL LAN_TX0-
1 2 +AVDDL 1 2 27 41 LAN_TX0- <33>
MBK1608601YZF_2P R450GIGA@ 0_0402_5% PCIE_PLLVDDL TRD0_N LAN_TX0+ 1000P_0402_50V7K
1 1 40 LAN_TX0+ <33>
TRD0_P
C592 C593 2 R484 2 1 330_0402_5% LINKLED# <33>
1U_0603_10V4Z 0.1U_0402_16V4Z LINKLED#
1 1 2
C34 2 2 SPD100LED# R453 1
67 2 0_0402_5%
SPD1000LED# R454 1 GIGA@
1 2 +PCIE_VDD 33 66 2 0_0402_5%
PCIE_VDDL TRAFFICLED# R455 100@ 0_0402_5%
1 2 24
1000P_0402_50V7K R456GIGA@ 0_0402_5% PCIE_VDDL
8 ACTIVITY# <33>
GPIO2
1 2
L34 R457100@ 0_0402_5% GPIO2 R458 1 2 @ 4.7K_0402_5%
1 2 +GPHY_PLLVDD
MBK1608601YZF_2P 1 1 9 R459 1 2 @ 0_0402_5% +3V_LAN
UART_MODE LAN_WP R460 1 0_0402_5%
7 2
C594 C595 C596 0.1U_0402_16V7K PCIE_IRX_C_PTX_P6 GPIO1_SERIALDI R461 1 GIGA@ 2 0_0402_5%
<29> PCIE_IRX_PTX_P6 26 4
4.7U_0805_10V4Z 0.1U_0402_16V4Z C597 0.1U_0402_16V7K PCIE_IRX_C_PTX_N6 PCIE_TXD_P GPIO0_SERIALDO GIGA@
<29> PCIE_IRX_PTX_N6 25
2 2 PCIE_TXD_N
<29> PCIE_ITX_C_PRX_P6 31
PCIE_RXD_P
<29> PCIE_ITX_C_PRX_N6 32
R462 1 PCIE_RXD_N
<29,31> ICH_PCIE_WAKE# 2 @ 0_0402_5% 12
WAKE#
<38> LAN_WAKE# 10
PERST# LAN_CLK R463
<23> CLK_PCIE_LAN 29 65 1 2 4.7K_0402_5%
L35 PCIE_REFCLK_P SCLK_EECLK SI
<23> CLK_PCIE_LAN# 28 63 1 2
PCIE_REFCLK_N SI LAN_DATA R464 4.7K_0402_5%
1 2 +PCIE_PLLVDD 64
MBK1608601YZF_2P SO_EEDATA CS#
1 1 62 1 2
CS# R465 4.7K_0402_5%
C598 C599 PLT_RST#
<8,16,27,31> PLT_RST#
4.7U_0805_10V4Z 0.1U_0402_16V4Z
B 2 2 B

59 R466 1 2 @ 0_0402_5% PCI_CBE#3 <27>

R468 1 VMAIN_PRSNT ENERGY_DET
+3VS 2 1K_0402_5%
+3V_LAN
+3V_LAN R467 1 2 1K_0402_5% 54
VMAIN_PRSNT VAUX_PRSNT
+PCIE_VDD 53
R469 1 VMAIN_PRSNT +2.5V12_LAN
1 1 2 @ 0_0402_5% 3
LOW_PWR

4
C600 C601 R470 1 GIGA@ 2 4.7K_0402_5% 58 17 R471 1 2 0_0402_5% @ Q35
1U_0603_10V4Z 0.1U_0402_16V4Z R472 1 GIGA@ 2 4.7K_0402_5% TEST1 VDDC_IO GIGA@ MBT35200MT1G_TSOP6
57
2 2 TEST2
XTALO 22 18 CTL25 3
XTALI XTALO REGOUT12_IO
21
Layout Notice : Filter place as close XTALI
R473 1 2 1K_0402_5% +3V_LAN
chip as possible. Notice : 4.7u 6.3V capactor Thickness 1.25mm 37

1
2
5
6
100@ RDAC
R474 1.24K_0402_1%
1 2 1
GIGA@
C602

3
0.1U_0402_16V4Z
2
14 CTL12 1
REGCTL12
+1.2V_LAN +2.5V12_LAN

0.1U_0402_16V4Z

10U_0805_10V4Z
Q36

2
4
MMJT9435T1G_SOT223 1 1
1

C840

C839
11 @
<23> CLKREQ_LAN# CLK_REQ# C603
10U_0805_10V4Z 2 2
GND

16 2
SUPER_IDDQ
BCM5784MKMLG B0_QFN68_10X10
69

1
R475
A 0_0402_5% A

2
R477 1 2 200_0402_1% XTALO

XTALI
Y4
1 2
1 1
25MHZ_20P
C604 C605

2
27P_0402_50V8J
2
27P_0402_50V8J
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2008/03/25 Deciphered Date 2008/04/ Title
Broadcom LAN BCM5784M/5906M
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4601P
Date: Wednesday, March 18, 2009 Sheet 32 of 53
5 4 3 2 1
 5 4 3 2 1

0513 : CARD_3V3 旁旁該該 100K change to 4.7u CAP==>該該

0521 : change C79 form 4.7u to 0.1u, add R47 100K ohm, JREAD1
SDDAT4_XDWP#_MSD7 33 23 SDDAT5_XDD0_MSD6
change C526 form 1u to 4.7u SDDAT1_XDD3_MSD1 8
xD-WP
xD-D3
SD-DAT5
SD-DAT0 14 SDDAT0_XDD6_MSD0
SDDAT7_XDD2_MSD2 9 25 SD_CMD
xD-D2 SD-CMD SDDAT3_XDWE#
SD-DAT3 29
SDDAT6_XDD7_MSD3 24 12 XDD4_SDDAT1
SDDAT4_XDWP#_MSD7 MS-DATA3 SD-DAT1
27 SD-DAT4
SDDAT2_XDRE# 30 XDPWR_SDPWR_MSPWR
SDCD SD-DAT2 MS-SCLK
1 SD-CD MS-SCLK 26
SDWP 2 13 XDD5_MSBS
SD-WP MS-BS MS_INS#
MS-INS 22
SDDAT5_XDD0_MSD6 32 28
XDD5_MSBS xD-D0 MS-VCC SDDAT1_XDD3_MSD1
D 6 xD-D5 MS-DATA1 15 D
2 1 XDPWR_SDPWR_MSPWR XDD4_SDDAT1 7 19 SDDAT7_XDD2_MSD2
R489 0_0402_5% SDDAT0_XDD6_MSD0 xD-D4 MS-DATA2 SDDAT0_XDD6_MSD0
5 xD-D6 MS-DATA0 17
SDDAT3_XDWE# 34 xD-WE SD-CLK
1 2 3 xD-VCC SD-CLK 20
C618 0.1U_0402_16V4Z SDDAT6_XDD7_MSD3 4 18 SDDAT6_XDD7_MSD3
xD-D7 SD-DAT6
1 C619 XDCE# 37 xD-CE SD-DAT7 16 SDDAT7_XDD2_MSD2
4.7U_0603_6.3V6K U25 SDDAT2_XDRE# 38 21
xD-RE SD-VCC

2
1 SDCLK_XDD1_MSCLK 10
R490 C620 XDCLE xD-D1
1 AV_PLL 36 xD-CLE 7IN1-GND 31
2 0.1U_0402_16V4Z XDALE
3 NC 35 xD-ALE 7IN1-GND 11
7 XD_RDY 39
XDPWR_SDPWR_MSPWR NC 2 XDCD xD-R/B
9 40

1
CARD_3V3 C621 1U_0603_16V4Z xD-CD
11 D3V3
33 10 1 2 100K_0402_5% 41
D3V3 VREG GND
MS_D4 22 GND 42
NC 30
+3VS R491 1 @ 2 0_0603_5% 3V3_IN 8 TAITW_R015-A10-LM_NR
RST# 3V3_IN ME@
44 RST#
R492 1 2 0_0603_5% 1 MODE SEL 45
C622 XTLO MODE_SEL XDCLE
+3VALW 47 XTLO XD_CLE_SP19 43
0.1U_0402_16V4Z XTLI 48 42 XDCE#
XTLI XD_CE#_SP18 XDALE
XD_ALE_SP17 41
2 USB20_N7 SDDAT2_XDRE# R493
<29> USB20_N7 4 DM SD_DAT2/XD_RE#_SP16 40
USB20_P7 5 39 SDDAT3_XDWE# 2 1 MS-SCLK
<29> USB20_P7 DP SD_DAT3/XD_WE#_SP15
14 38 XD_RDY 0_0402_5%
GPIO0 XD_RDY_SP14 SDDAT4_XDWP#_MSD7
SD_DAT4/XD_WP#/MS_D7_SP13 37
35 SDDAT5_XDD0_MSD6 R494
SD_DAT5/XD_D0/MS_D6_SP12 SDCLK_XDD1_MSCLK SD-CLK
keep supply 3.3V to 3V3_IN when S3 SD_CLK/XD_D1/MS_CLK_SP11 34
31 SDDAT6_XDD7_MSD3
2 1
0_0402_5%
SD_DAT6/XD_D7/MS_D3_SP10 MS_INS#
MS_INS#_SP9 29
28 SDDAT7_XDD2_MSD2 CLK_48M_CR MS-SCLK SD-CLK
SD_DAT7/XD_D2/MS_D2_SP8 SDDAT0_XDD6_MSD0
SD_DAT0/XD_D6/MS_D0_SP7 27
SDDAT1_XDD3_MSD1
Vender suggesttion SD_DAT1/XD_D3/MS_D1_SP6 26

2
25 XDD5_MSBS
C XD_D5_SP5 XDD4_SDDAT1 R663 R665 R664 C
XD_D4/SD_DAT1_SP4 23
21 SDCD 33_0402_5% 33_0402_5% 33_0402_5%
SD_CD#_SP3 SDWP
SD_WP_SP2 20 @ @ @
19 XDCD

1
XD_CD#_SP1
2

EEDI 18
R495 C805 C807 C806
100K_0402_5% 2 13 XTAL_CTR 2 1 3V3_IN 22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J
RREF XTAL_CTR R496 @ @ @
MS_D5 24
12
1

RST# DGND 0_0603_5%

32 DGND EEDO 15
EECS 16
1 6 AGND EESK 17
46 36 SD_CMD
AGND SD_CMD
C623
1U_0402_6.3V4Z
MSCLK and SDCLK 該該該該該該該該EMI
2
RTS5158E-GR_LQFP48_7X7
solution使使, (但但但但RTS5158E側).
2

<BOM Structure>
R497 R498
6.19K_0402_1% 0_0402_5%
將SD_DAT1 連連連RTS5158E的pin23
1

B B

CLK_48M_CR R499 1 2 0_0603_5%

<23> CLK_48M_CR

C624
MODE SEL
1 2 XTLI

6P_0402_50V8D
1

@
1
1

C625 @
R500
47P_0402_50V8J 10K_0402_5%
2 @ Y5
2

12MHZ_16P_6X12000012
C626 @

1 2 XTLO

6P_0402_50V8D
@
0521_C503 and R436 should be open

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1394+3 in 1 Card
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-3691P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 18, 2009 Sheet 34 of 53
5 4 3 2 1
 A B C D E F G H

SATA HDD Conn.

JHDD
1
SATA_ITX_DRX_P0 GND
2
<28> SATA_ITX_DRX_P0
<28> SATA_ITX_DRX_N0
SATA_ITX_DRX_N0 3
4
A+
A-
SATA ODD Conn.
SATA_DTX_C_IRX_N0 C634 1 SATA_DTX_IRX_N0 GND
2 0.01U_0402_16V7K 5 B-
1 <28> SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 C633 1 SATA_DTX_IRX_P0 1
<28> SATA_DTX_C_IRX_P0 2 0.01U_0402_16V7K 6 B+ JODD
7 GND
1
SATA_ITX_DRX_P1 GND
8 <28> SATA_ITX_DRX_P1 2
V33 SATA_ITX_DRX_N1 A+
+3VS 9 V33 <28> SATA_ITX_DRX_N1 3 A-
10 4
V33 SATA_DTX_C_IRX_N1 C635 1 SATA_DTX_IRX_N1 GND
11 GND 2 0.01U_0402_16V7K 5 B-
<28> SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 C636 1 SATA_DTX_IRX_P1
12 GND 2 0.01U_0402_16V7K 6 B+
<28> SATA_DTX_C_IRX_P1
13 7
GND GND
14 V5
+5VS 15
V5
16 V5 8 DP
17 +5VS 9
GND +5V
18 10
Reserved +5V
19 11
GND MD
20 V12 12 GND
21 23 13
+5VS +3VS V12 GND GND
22 V12 GND 24
CONN need change to new CONN OCTEK_SLS-13SB1G_RV
FOX_LD2122H-S43_NR ME@
1 1 1 1 1 1
@ ME@
C627 C628 C629 C630 C631 C632
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2

2 2

+USB_VCCB

+USB_VCCB
W=80mils
1
+ C733
1
C734
ESATA and USB Conn.
150U_D2_6.3VM 470P_0402_50V7K
2 2
JESATA
1 USB
USB20_N0 VBUS
<29> USB20_N0 2
USB20_P0 D-
<29> USB20_P0 3 D+
4

5
GND
A+ = RXP
SATA_ITX_DRX_P4_CONN GND
6
3
<28> SATA_ITX_DRX_P4_CONN
<28> SATA_ITX_DRX_N4_CONN
SATA_ITX_DRX_N4_CONN 7
8
A+
A-
ESATA A- = RXN 3
SATA_DTX_IRX_N4_CONN GND
<28> SATA_DTX_IRX_N4_CONN 9 B-
SATA_DTX_IRX_P4_CONN 10
<28> SATA_DTX_IRX_P4_CONN B+
11 GND
12
13
GND
B- = TXN
GND
14
15
GND
GND
B+ = TXP
TYCO_1759576-1
ME@

+5VALW

+USB_VCCB
U34
1 8
C732 0.1U_0402_16V4Z GND OUT
2 IN OUT 7
2 1 3 6
USB_ON 4 IN OUT
<38,41> USB_ON EN OC# 5 USB_OC#0 <29>
G545A1P1U_SO8

1
C735
@ 1000P_0402_50V7K
2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4601P
Date: Wednesday, March 18, 2009 Sheet 35 of 53
A B C D E F G H
 5 4 3 2 1

+5VS
HDA_RST_CODEC#

+5VDDA_CODEC HDA_SYNC_CODEC +3VS +3VDD_CODEC +5VDDA_CODEC

HDA_SDOUT_CODEC

BITCLK

D D

+5VDDA_CODEC +3VDD_CODEC
+MIC1_VREFO_L

+IOVDD_CODEC

INT_MIC_L
GNDA MIC_INTL MIC_INTR
C_LINE_OUTL LINE_OUTL

C_LINE_OUTR LINE_OUTR

INT_MIC_L MIC_INTL MIC_INL

GNDA
INT_MIC_R MIC_INTR MIC_INR

SPDIF_OUT <37>

C MIC_EXTL_C C
<37> EXT_MIC_L HP_OUTL <37>
MIC_EXTR_C
<37> EXT_MIC_R HP_OUTR <37>

PC_BEEP MONO_OUT
MONO_OUT <37>

BITCLK
<8,28> HDA_BITCLK_CODEC
HDA_SDOUT_CODEC
<8,28> HDA_SDOUT_CODEC
INT_MIC_R
<28> HDA_SDIN2
GNDA
HDA_RST_CODEC#
<8,28> HDA_RST_CODEC#
HDA_SYNC_CODEC
<8,28> HDA_SYNC_CODEC +MIC1_VREFO_L

+MIC2_VREFO
GNDA
<38> GPO_AUD

<37> MIC_JD SENSEA

<37> PLUG_IN SENSEB

<38> EAPD

B B

+5VAMP

+3VS AMP_OFF# EC_MUTE#

EC_MUTE# <37,38>
GAIN0
SPK_L1- SPK_L1- <37>
GAIN1
SPK_R1- SPK_R1- <37>
SPK_L2+ SPK_L2+ <37>
LINE_OUTL LIN SPK_R2+ SPK_R2+ <37> +5VAMP +5VAMP

LINE_OUTR RIN

PC_BEEP1 PC_BEEP

A <38> BEEP# GAIN0 GAIN1 A

<29> SB_SPKR

5 4 3 2 1
 5 4 3 2 1

Audio Jack
EMI 20080826
L49
D EXT_MIC_L 1 2 EXT_MIC_L-2 D
<36> EXT_MIC_L
FBMA-L10-160808-121LMT_2P
1 1
C669 @ C670
47P_0402_50V8J 10P_0402_50V8J
2 2
SubWoofer Conn. GNDA GNDA
Audio Jack
Speaker Connector L50 MIC IN
EXT_MIC_R 1 2 EXT_MIC_R-2
<36> EXT_MIC_R
FBMA-L10-160808-121LMT_2P
EMI 20080826 20mil JSPK1 1 1
W OOFER- L43 1 2 FBMA-L11-160808-121LMA30T W O- 1
W OOFER+ L44 FBMA-L11-160808-121LMA30T W O+ 1 C671 @ C672 JMIC1
1 2 2 2
SPK_R1- L45 1 2 FBMA-L11-160808-121LMA30T SPK_R1-_CONN 3 47P_0402_50V8J 10P_0402_50V8J 1
<36> SPK_R1- 3 2 2
SPK_R2+ L46 1 2 FBMA-L11-160808-121LMA30T SPK_R2+_CONN 4 2
<36> SPK_R2+ 4
SPK_L1- L47 1 2 FBMA-L11-160808-121LMA30T SPK_L1-_CONN 5 7
<36> SPK_L1- 5 G1
SPK_L2+ L48 1 2 FBMA-L11-160808-121LMA30T SPK_L2+_CONN 6 8 GNDA GNDA 3
<36> SPK_L2+ 6 G2
ACES_87213-0600G <36> MIC_JD MIC_JD 4

1 GNDA 5

10P_0402_50V8J C673
@
2
6 G
C GNDA C
SINGA_2SJ-0960-C02
220P_0402_50V7K 220P_0402_50V7K ME@

2
C674 C675 Headphone

1
@ R537 @ R538
1K_0402_5% 1K_0402_5%

2
GNDA
EMI 20080826 JHP1
6
HP_OUTR L51 1 2 PR-OUT 1
<36> HP_OUTR
FBMA-L10-160808-121LMT_2P
HP_OUTL L52 1 2 PL-OUT 4
<36> HP_OUTL
FBMA-L10-160808-121LMT_2P
5

<36> PLUG_IN PLUG_IN 7

+5VS 3
SPDIF_OUT 8
<36> SPDIF_OUT
1
C677 2

1
0.1U_0402_16V4Z
2 C676 SINGA_2SJ1533-000111
B B
220P_0402_50V7K

2
33K_0402_5%
1 2 +3VALW
R620
G1442 SubWoofer Amplifier 1500P_0402_50V7K ONLY FOR 15.6W
2

1 2
1nd = APA3011 (SA00001JM00) R621
C762 10K_0402_5%
2nd = TPA6211 (SA621110010 ) +5VAMP W=40mil @
0.01U_0402_16V7K
1

1 2 U39
6 1 AMP_OFF# 2 1 R622 EC_MUTE#
VDD SHUTDOWN# EC_MUTE# <36,38>
C760 0_0402_5%
W IN1 3 5 W OOFER+
C759 R618 IN+ Vo+
68K_0402_5%
MONO_OUT 1 2 1 2 1 2 W IN2 4 8 W OOFER-
<36> MONO_OUT IN- Vo-
0.018U_0603_50V7J 8.45K_0402_1% R619 2 2 7
BYPASS GND
C761
2.2U_0603_6.3V4Z APA3011XA-TRL_MSOP8
A 1 A

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2008/03/25 Deciphered Date 2008/04/ Title
AMP,Audio speaker CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4601P
Date: W ednesday, March 18, 2009 Sheet 37 of 53
5 4 3 2 1
 +3VALW
+EC_AVCC
1 1

0.1U_0402_16V4Z
C680

1000P_0402_50V7K
C685
L38
+3VALW +EC_AVCC
FBM-11-160808-601-T_0603
2 2

ECAGND

0_0402_5%
1 2
R779
INVT_PWM
<28> GATEA20 KB_RST#_EC BEEP# INVT_PWM <25>
<28> KB_RST# BEEP# <36>
<29,39> SERIRQ ACOFF NOVO# <42>
<28,39> LPC_FRAME# LPC_AD3 ACOFF <46>
<28,39> LPC_AD3
LPC_AD2
<28,39> LPC_AD2 LPC_AD1 BATT_TEMP
<28,39> LPC_AD1 LPC_AD0 BATT_OVP BATT_TEMP <45>
<28,39> LPC_AD0 BATT_OVP <46>
2 1 ADP_I <46>
@ C687 22P_0402_50V8J CPUSB#
<23> CLK_PCI_LPC CPUSB# <29,31>
<27,39> PCI_RST# EC_RST# TSATN#_EC R542 1
+3VALW 2 @ 0_0603_5% TSATN# <8>
EC_SCI# +5VS
<29> EC_SCI#
2 <42> PWR_LED_SC# GPO_AUD <36>
DAC_BRIG TP_CLK
DAC_BRIG <25>
C686 EN_FAN1
EN_FAN1 <5>
0.1U_0402_16V4Z IREF TP_DATA R545 1 2 4.7K_0402_5%
1 KSI0 IREF <46>
+3VALW
KSI1 CHGVADJ <46> BATT_OVP 1 2
KSI2 EC_MUTE# R546 1 2 @ 10K_0402_5% C688 100P_0402_50V8J
KSI3 BATT_TEMP 1 2
<39,42> KSI3 EC_MUTE# <36,37>
KSI4 USB_ON USB_ON C689 100P_0402_50V8J
<39> KSI4 KSI5 AO_3G# USB_ON <35,41> ACIN
KSI6 TP_LOCK# AO_3G# <31>
KSO[0..15] KSI7 TP_CLK TP_LOCK# <40>
<39> KSO[0..15] TP_CLK <39>
KSO0 TP_DATA
KSI[0..7] KSO1 TP_DATA <39>
<39,42> KSI[0..7] KSO2
KSO3
KSO4 KB926 SPI STRAP PIN
KSO5 EN_WOL <32>
+3VALW
BATT_SEL_EC <46>
KSO6
CMOS_OFF# <41>
KSO7
KSO1 KSO8 +3VS
KSO9 FRD#SPI_SO
FRD#SPI_SO <40>
KSO2 KSO10 FWR#SPI_SI
KSO11 SPI_CLK FWR#SPI_SI <40>
KSO12 FSEL#SPICS# SPI_CLK <40>
ENE UPDATE 10/21 KSO13 FSEL#SPICS# <40>
KSO14
KSO15 RCIRRX
RCIRRX <42>
KSO16 I2C_INT I2C_INT
<42> KSO16 I2C_INT <42>
KSO17
<42> KSO17 CHARGE_LED0# FSTCHG <46>
CAPS_LED# CHARGE_LED0# <40>
+3VALW
EC_SMB_CK1 CHARGE_LED1# CAPS_LED# <39>
<31,45> EC_SMB_CK1 CHARGE_LED1# <40>
EC_SMB_DA1
<31,45> EC_SMB_DA1 PWR_LED# <40>
2

EC_SMB_CK2 SYSON
<5,16,42> EC_SMB_CK2 EC_SMB_DA2 SYSON <31,43,48,49>
R550
<5,16,42> EC_SMB_DA2 ACIN VR_ON <50>
10K_0402_5%
ACIN <29,44,46>
1

<29> SLP_S3# EC_LID_OUT# EC_RSMRST# <29>

<29> SLP_S5# EC_SMI# EC_ON EC_LID_OUT# <29>
<29> EC_SMI# EC_ON <42>
LID_SW# MUTE_LED
<32> LAN_WAKE# <39> LID_SW# MUTE_LED# <42>
1 2 ICH_POK_EC ICH_POK
+3VALW ICH_POK <8,29>
+3VALW R552 4.7K_0402_5% BKOFF#
EC_PME# BKOFF# <25>
WL_OFF# <31> 1 2 +3VS
R555 0_0402_5%
<39> KILL_SW# FAN_SPEED1 WIRELESS_LED# TV_POWER_SW <31> @
<5> FAN_SPEED1 WIRELESS_LED# <40>
<27> PCI_PME# <31> 3G_OFF#
EC_TX_P80_DATA
<31,39> EC_TX_P80_DATA EC_RX_P80_CLK
<31,39> EC_RX_P80_CLK SLP_S4# <29>
<42> ON/OFF# AO_NEWCARD ENBKL <25>
+3VALW EAPD <36>
<31> AO_NEWCARD EC_THERM#
<39> NUM_LED# EC_THERM# <29>
SUSP#
PBTN_OUT# SUSP# <31,43,48,49>
PBTN_OUT# <29>
BT_OFF# <41>
XCLKI
+3VALW XCLKO
1
1 2 FRD#SPI_SO SUSP#
R557 @ 100K_0402_1% C691
1U_0603_10V4Z
1 2 FSEL#SPICS# 2
R558 @ 100K_0402_1%
ENE ISSUE CHANGE FROM 4.7uF TO 1uF
ECAGND

1 2 KSO17
R559 @ 10K_0402_5%
20080606

+5VALW +3VALW needed to update to D2 version

EC_SMB_CK1 EC_SMB_CK1 SA00001J570
EC_SMB_DA1 EC_SMB_DA1

+3VS

R562 XCLKO
2.2K_0402_5%
X1
2 NC IN 1
EC_SMB_CK2
EC_SMB_DA2 3 4
NC OUT
1
@ 32.768KHZ_12.5P_1TJS125BJ2A251 XCLKI
C694
100P_0402_50V8J
Security Classification Compal Secret Data Compal Electronics, Inc.
2 Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom JITR1_LA-4141P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 18, 2009 Sheet 38 of 53
 5 4 3 2 1

INT_KBD Conn. JP13 EC DEBUG PORT

KSI[0..7] KSI1 1
KSI[0..7] <38,42> 1
KSI7 2
KSO[0..15] KSI6 2
D KSO[0..15] <38> 3 3 D
KSO9 4
KSI4 4 JP14
5 5
KSI5 6 +3VALW 1
KSO2 C697 1 6 1
2 @ 100P_0402_50V8J KSO1 C698 1 2 @ 100P_0402_50V8J KSO0 7 7 <31,38> EC_TX_P80_DATA
EC_TX_P80_DATA 2 2
KSI2 8 EC_RX_P80_CLK 3
8 <31,38> EC_RX_P80_CLK 3
KSO15 C699 1 2 @ 100P_0402_50V8J KSO7 C700 1 2 @ 100P_0402_50V8J KSI3 9 4
KSO5 9 4
10 10
KSO6 C701 1 2 @ 100P_0402_50V8J KSI2 C702 1 2 @ 100P_0402_50V8J KSO1 11 ACES_85205-0400
KSI0 11
12 12 ME@
KSO8 C703 1 2 @ 100P_0402_50V8J KSO5 C704 1 2 @ 100P_0402_50V8J KSO2 13
KSO4 13
14 14
KSO13 C705 1 2 @ 100P_0402_50V8J KSI3 C706 1 2 @ 100P_0402_50V8J KSO7 15
KSO8 15
16 16
KSO12 C707 1 2 @ 100P_0402_50V8J KSO14 C708 1 2 @ 100P_0402_50V8J KSO6 17
KSO3 17
18 18
KSO11 C709 1 2 @ 100P_0402_50V8J KSI7 C710 1 2 @ 100P_0402_50V8J KSO12 19
KSO13 19
20 20
KSO10 C711 1 2 @ 100P_0402_50V8J KSI6 C712 1 2 @ 100P_0402_50V8J KSO14 21
KSO11 21
22 22
KSO3 C713 1 2 @ 100P_0402_50V8J KSI5 C714 1 2 @ 100P_0402_50V8J +5VS KSO10 23

KSO4 C715 1 2 @ 100P_0402_50V8J KSI4 C716 1 2 @ 100P_0402_50V8J 470_0402_5% 2

KSO15
1 R770
24
25
23
24 Lid Switch
470_0402_5% R771 25
2 1 26 26
KSI0 C717 1 2 @ 100P_0402_50V8J KSO9 C718 1 2 @ 100P_0402_50V8J <38> NUM_LED# 27 27
<38> CAPS_LED# 28 28
KSO0 C719 1 2 @ 100P_0402_50V8J KSI1 C720 1 2 @ 100P_0402_50V8J 29 31
29 G1 +VCC_LID R566 1
30 30 G2 32 +3VALW 1 2 2 100K_0402_5%
R565 0_0402_5%
C
CONN PIN define need double check ACES_85201-3005N C

2
A3212ELHLT-T_SOT23W -3

VDD
1
OUTPUT 3 LID_SW # <38>
C721
To TP/B Conn. +5VS 0.1U_0402_16V4Z 2

GND
2
C722
U30 10P_0402_50V8J

1
C723 1

0.1U_0402_16V4Z
JP15
4 4
TP_CLK 3
<38> TP_CLK 3
TP_DATA 2
<38> TP_DATA 2
1 1 1 1
@ @
C724 C725 E&T_6905-E04N-00R
2
100P_0402_50V8J
2
100P_0402_50V8J ME@ Kill Switch
CONN PIN define need double check
+3VALW
R632
100K_0402_5% LSSM12-P-V-T-R_3P
2 1 3 3
B B

<38> KILL_SW # 2 2
KILL_SW#
1 1

SW 2

FOR LPC SIO DEBUG PORT

JP16
1 1 +5VS
2 2
3 3 +3VS
4 4
5 5
6 6 CLK_14M_SIO <23>
7 LPC_AD0
7 LPC_AD0 <28,38>
8 LPC_AD1
8 LPC_AD1 <28,38>
9 LPC_AD2
9 LPC_AD2 <28,38>
10 LPC_AD3
10 LPC_AD3 <28,38>
11 LPC_FRAME#
11 LPC_FRAME# <28,38>
12 LPC_DRQ0#
12 LPC_DRQ0# <28>
13 PCI_RST#
13 PCI_RST# <27,38>
14 14 2 1
15 CLK_PCI_DB CLK_PCI_DB <23> R567 10K_0402_5%
15 SERIRQ
A 16 16 SERIRQ <29,38> @ A
17 17
18 18
19 19
20 20

ACES_85201-2005
ME@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB /SW /LPC Debug Conn.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4601P
Date: W ednesday, March 18, 2009 Sheet 39 of 53
5 4 3 2 1
 FOR EC 16M SPI ROM

+3VALW
20mils
1

1
C726
0.1U_0402_16V4Z R812
2 10K_0402_5%

2
U31
INT_SPI_CS# 1 8
FRD#SPI_SO R568 1 SPI_SO CS# VCC
<38> FRD#SPI_SO 2 15_0402_5% 2 SO HOLD# 7
3 6 SPI_CLK_R R569 1 2 15_0402_5% SPI_CLK SPI_CLK_R
WP# SCLK SPI_SI FWR#SPI_SI SPI_CLK <38>
4 5 R570 1 2 15_0402_5%
GND SI FWR#SPI_SI <38>

2
MX25L1605AM2C-12G_SO8 R571
33_0402_5% 47_0402_5% 3G@
R832

1
+3VALW
1
C727 C861 3G@
68P_0402_50V8J
INPUT 22P_0402_50V8J
2
OUTPUT
A B Y

5
@ U32 @ R572
1 INT_FLASH_EN# 100K_0402_5% 1 2 EMI 3G

P
INT_SPI_CS# R573 1 INB
L L L 2 15_0402_5% 4 O
2 FSEL#SPICS#
INA FSEL#SPICS# <38>

G
H L H MC74VHC1G32DFT2G_SC70-5~D

3
L H H
R574 1 2 0_0402_5%
H H H

+3VALW
JP17
FSEL#SPICS# 1 2
SPI_SO 1 2 INT_FLASH_EN#
3 4
3 4 SPI_CLK_R
<29> SB_INT_FLASH_SEL 5 6
5 6 SPI_SI FD1 FD2 FD3 FD4
7 8
7 8
1 1 1 1
ME@ E&T_2941-G08N-00E~D

LED H1 H2 H3 H4 H5 H6
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
SC500005B00,If=5mA,Vf=2.7V~3.15V,R=460~390ohm

1
WHITE LED1
<38> PWR_LED# 1 2 R624 1 2 470_0402_5% +5VALW
H7 H8 H9 H10 H11 H12
12-21SYGCS530-E1S155TR8_W HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
+5VALW
WHITE BATT_CHG_LED#
CHARGE_LED0# R625 1 2 470_0402_5%
<38> CHARGE_LED0#
2 H15 H16 H17 H18 H19 H20 H21
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
CHARGE_LED1# R626 1 2 470_0402_5% 3

1
<38> CHARGE_LED1#

AMBER BATT_LOW_LED# LED7 12-22-S2ST3D-C30-2C_WHI-ORG

H22 H23 H24 H25 H26
LED4 HOLEA HOLEA HOLEA HOLEA HOLEA

<38> TP_LOCK# 1 2 R577 1 2 750_0402_5% +5VS

1
19-213A-T1D-CP2Q2HY-3T_WHITE
WHITE
H27 H28
HOLEA HOLEA

LED5

1
<38> WIRELESS_LED# 1 2 R627 1 2 470_0402_5% +5VALW
12-21SYGCS530-E1S155TR8_W
WHITE

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED/EC SPI ROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4601P
Date: Wednesday, March 18, 2009 Sheet 40 of 53
 A B C D E

+5VALW

+USB_VCCA

+USB_VCCA +USB_VCCA

USB20_P4
<29> USB20_P4
1 USB20_N4 1
<29> USB20_N4

<35,38> USB_ON USB_ON USB20_N11

USB_OC#4 <29> <29> USB20_N11
USB20_P11
<29> USB20_P11
USB_OC#11 <29>

2 2

+5VS

+5VS
3 3

+3VS +3VS_BT
<38> BT_OFF#
CMOS1

<42> BT_LED#
<29> USB20_N2 USB20_N2
<38> CMOS_OFF#
<29> USB20_P2 USB20_P2

<29> USB20_N6 USB20_N6

<29> USB20_P6 USB20_P6
<31> BT_ACTIVE BT_ACTIVE
<31> WLAN_ACTIVE WLAN_ACTIVE
BTON_LED

4 4

Security Classification Compal Secret Data

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI

Date: Sheet of
A B C D E
 Power Bottom Board Conn. 6 pin Bottom Board Conn. 6 pin
+5VS
+3VALW +5VALW
CIR

1
2

1
R781
R581 R780 750_0402_5%
100_0603_5% 750_0402_5%
@

2
JP25

2
JP23 1
R582 MUTE_LED# 1
1 1 <38> MUTE_LED# 2 2
<38> RCIRRX RCIRRX 1 2 PW R_LED_SC# 2 KSO16 3
<38> PW R_LED_SC# 2 <38> KSO16 3
3 KSI2 4
3 <38,39> KSI2 4
33_0402_5% 1 NOVO_BTN# 4 KSO17 5
4 <38> KSO17 5
ON/OFFBTN# 5 KSI3 6
5 <38,39> KSI3 6
6 6 7 GND
C739 7 8
22P_0402_50V8J 2 GND GND
8 GND ACES_85201-06051
IR1 ACES_85201-06051 ME@
+3VALW 1 ME@
Vout
1 2 2 VCC
R583 100_0603_5% 1
3 NOVO_BTN# ON/OFFBTN#
C740 GND KSI2 KSO16 KSI3 KSO17

2
4 GND

2
4.7U_0805_10V4Z 2 D29
IRM-V538/TR1_3P PJSOT24C 3P C/A SOT-23 D30 D33
PJDLC05_SOT23-3 PJDLC05_SOT23-3

1
ON/OFF switchSW 1

1
@
1 3
KEY MATRIX
Power Button BTN FUNCTION
2 4
SMT1-05_4P IN OUT
MUTE BTN KSO17 KSI3
6
5

+3VALW

TOP Side 2 1 DOWN KSO17 KSI2

2

2MM J2 UP KSO16 KSI2

2 1 R584
Bottom Side 100K_0402_5%
D26
2MM J3
1

3 ON/OFF#
ON/OFF# <38>
ON/OFFBTN# 1
2 51_ON#
51_ON# <44> IDEAPAD BOARD 2PIN
DAN202UT106_SC70-3
1

2
C741 D27
1000P_0402_50V7K RLZTE1120A LL34
1 @ @
2
1

D
EC_ON 2 ACES_87213-0200
<38> EC_ON
G 4
R769 G2
Q44 S 3
3

G1
2

2N7002_SOT23-3 +5VS 1 2 2
R587 2
1 1
10K_0402_5% 100_0603_5% JP26
1

+3VALW
Slide Board Conn. 10 pin
2

R589
100K_0402_5%
JP24
D28 DRIVE_LED# 470_0402_5% 2 1 R773 1
1

NOVO# <28> DRIVE_LED# BT_LED# 470_0402_5% R774 1

<38> NOVO# 2 <41> BT_LED# 2 1 2 2
1 NOVO_BTN# <31> W LAN_LED# W LAN_LED# 470_0402_5% 2 1 R775 3
51_ON# 3G_LED# 470_0402_5% R776 3
<44> 51_ON# 3 <31> 3G_LED# 2 1 4 4
+5VS 5 5
R631 1 2 0_0402_5% I2C_INT_R 6
DAN202UT106_SC70-3 <38> I2C_INT 6
7 7
R586 1 2 0_0402_5% R_SMB_DA2 8
<5,16,38> EC_SMB_DA2 8
R585 1 2 0_0402_5% R_SMB_CK2 9
<5,16,38> EC_SMB_CK2 9
10 10
11 GND
12 GND
ACES_85201-1005N

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2008/03/25 Deciphered Date 2008/04/ Title
Audio Jack & SW connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4601P
Date: W ednesday, March 18, 2009 Sheet 42 of 53
 A B C D E

+5VALW TO +5VS +3VALW TO +3VS +1.8V to +1.8VS

+5VALW +5VS +3VALW +3VS
U35 U36
8 D S 1 8 D S 1
1 7 D S 2 1 1 1 7 D S 2 1 1

1
6 D S 3 6 D S 3
C742 5 C743 C744 C745 C746 C747 +1.8V +1.8VS
10U_0805_10V4Z D G 4 10U_0805_10V4Z 1U_0603_10V4Z R590
5
10U_0805_10V4Z D G 4 10U_0805_10V4Z 1U_0603_10V4Z R591 J4
1 2 2 2 2 2 2 1
SI4800BDY-T1-E3_SO8 470_0603_5% SI4800BDY-T1-E3_SO8 470_0603_5% 1 2
1 2

1
1 2

1 2
B+ B+ JUMP_43X118
D D R592
2 SUSP 2 SUSP 470_0603_5%

1
G G

1 2
S Q46 S Q47

3
R593 2N7002_SOT23 R594 2N7002_SOT23 D
20K_0402_5% 47K_0402_5% 2 SUSP
G

2
5VS_GATE S Q48

3
2

2
1 1 2N7002_SOT23
1

1
D R598 D R599
SUSP 2 Q49 0_0402_5% C751 SUSP 2 Q50 0_0402_5% C752
G 2N7002_SOT23 0.1U_0603_25V7K G 2N7002_SOT23 0.1U_0603_25V7K
S @ 2 S @ 2
3

1
+1.5V to +1.5VS
+1.5V +1.5VS
U38
8 D
S 1
2 1 7 2 1 1 2
D S

1
6 D
C754 S 3 C755 C756 +1.8V +1.5V +VCCP +0.75V
5 D 4
10U_0805_10V4Z G 10U_0805_10V4Z 1U_0603_10V4Z R601
2 2
SI4800BDY-T1-E3_SO8 2 470_0603_5%

1
2
R602 R603 R604 R605
1
+5VALW D 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
2 SUSP @

1 2

1 2

1 2

1 2
G
2

Q52 D D D D
S
3

R606 2N7002_SOT23 2 SYSON# 2 SYSON# 2 SUSP 2 SYSON#

47K_0402_5% G G G G
S Q53 S Q54 S Q55 S Q56

3
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23
1

1.5VS_GATE @
2

Q57 1 1
1

D R608
SUSP 2 0_0402_5% C757 C758
G @ 0.1U_0603_25V7K
2N7002_SOT23S @ 2 2
3

0.1U_0603_25V7K

3 3

RTCVREF +5VALW
+5VALW
1

@
R609 R610
10K_0402_5% 100K_0402_5% R611
100K_0402_5%
2

SUSP
<31,48,49> SUSP
2

SYSON#
<48,49> SYSON#
Q58 Q59
1

DTC124EKAT146_SC59-3 DTC124EKAT146_SC59-3
OUT

OUT

2 SYSON 2
<31,38,48,49> SUSP# IN <31,38,48,49> SYSON IN
GND

GND
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4601P
Date: Monday, April 27, 2009 Sheet 43 of 53
A B C D E
 A B C D

1
DC030006J00 VIN PR102
1

1M_0402_1%
JDCIN 1 2
@ 4602-Q04C-09R 4P P2.5 PF101 PL101 VINDE-2 VIN
7A_24VDC_429007.W RML SMB3025500YA_2P VS
1 APDIN 1 2 APDIN1 1 2 VIN
1

2 2

1
1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
3 3
PR103 PR105

0.1U_0603_50V7K

0.1U_0603_50V7K
<BOM Structure>
1

1
4 82.5K_0402_1% 10K_0402_1%
4
1 2 ACIN <29,38,46>
PR106

8
PC112

PC101

PC102

PC113

PC103

PC104
215K_0402_1%
VINDE-1 1 2 3

P
+ PACIN

1000P_0603_50V7K
1

2 Structure>
O PACIN
VINDE-3 2 -

G
1
PU102A

24.9K_0402_1%

0.1U_0402_16V7K

RLZ4.3B_LL34
1

1
LM393DG_SO8

4
PC106

PR107

PC107
<BOM

PD102
2
2
PR109

2
10K_0402_5%
2 1 RTCVREF 3.3V

2 2

Vin Detector

High 18.135 17.566 17.011

Low 14.866 14.355 14.063

SP093MX0000 VIN

2
PD103
LL4148_LL34-2

PD101

1
LL4148_LL34-2 51ON-1
BATT+ 2 1

1
PR110 PR111
PQ101 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3
PR101

2
200_0603_5%
CHGRTCP 1 2 51ON-2 3 1
VS
3 3

0.22U_0603_25V7K
1

1
PC108
PR112 PC109
100K_0402_1% 0.1U_0603_25V7K

2
PR113

2
22K_0402_1%
1 2 51ON-3
<42> 51_ON#

RTC Battery
- JRTC + RTCVREF

1
2 1 PR114
+RTCBATT +CHGRTC PU101 200_0603_5%
PR115 PR116
PD104 560_0603_5% 560_0603_5% 3.3V

2
@ MAXEL_ML1220T10 1 2 1 2RTCVREF-1
1 2 CHGRTCIN

RB751V-40TE17_SOD323-2

1
PC111
PC110 1U_0805_25V4Z
10U_0603_6.3V6M

2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/05/21 Deciphered Date 2009/05/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, March 18, 2009 Sheet 44 of 53
A B C D
 A B C D

24751_PVCC
PQ301 PQ302 B+
FDS6675BZ_SO8 FDS6675BZ_SO8
8 1 1 8 PR302
VIN 7 2 2 7 0.015_1206_1%
6 3 3 6 PJ301
5 5 B+_IN
1 4 2 1 CHG_B+
2 1

1
2

2
@ JUMP_43X118 PR303

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
2 3

4
PR301 PC332 PC302 100K_0402_5%

2
3.3_1210_5% 1000P_0402_50V7K 0.01U_0402_25V7K

CHGEN#
0.01U_0402_25V7K

1
PC303

PC304

PC305
0.01U_0402_25V7K

2
2

100K_0402_5%
PC307

2 1

1
2

5
6
7
8

3
2
1
1 1

PC301

PC306
0.1U_0402_16V7K PU301 PC310

BK-1
2 0.1U_0603_25V7K PQ304

0.1U_0603_25V7K

0.1U_0603_25V7K
1 2 1 28 1

1
PR305 CHGEN PVCC FDS6675BZ_SO8

1
/BATDRV

PR304
3.3_1210_5% PR307 4

PC308

PC309
2.2_0402_5%
27 24751_BTST-1
1 2 4
1 1

2
BTST

2
BK-2
PC311 PR306
2.2U_0805_25V6K 340K_0402_1% 24751_ACN
@ 2 26 24751_HIDRV PQ303
24751_ACP 3 ACN HIDRV AO4466_SO8
2

3
2
1

5
6
7
8
ACP PR308

1
24751_ACDRV# 4 25 24751_PH PL202 0.02_1206_1%
ACDET 5 ACDRV PH 10U_LF919AS-100M-P3_4.5A_20%
ACDET BATT+
2 124751_BTST
1 2 1 224751_SW -1 1 4
PD301

10U_1206_25V6M

10U_1206_25V6M
5
6
7
8
PC312

10U_1206_25V6M
REGN
LL4148_LL34-2 0.1U_0603_25V7K 2 3
2

1
PR311

PC314
PR310 75K_0402_1%
54.9K_0402_1%

PC331

PC313
PR309 24751_VREF 1 2 ACSET 6 PR312
340K_0402_1% ACSET 4.7_1206_5%
24

2
REGN

127K_0402_1%
4
1

2
1

1
PC316

24751_SNB
1

PR313
1U_0603_10V6K
PC315 PQ305

2
@ 0.01U_0402_25V7K AO4466_SO8

3
2
1
1 224751_ACOP
7 ACOP

1
PC317 23 24751_LODRV
0.47U_0603_16V7K LODRV 24751_VREF
CP setting PC318

2
2

PR314 22 820P_0603_50V7K
PGND

2
54.9K_0402_1% 24751_OVPSET 8 PC319
2 OVPSET PR315 0.1U_0402_16V7K 2

CP Point Setting @ 49.9K_0402_1% 1 2

9 21 ACOFF ACOFF <38>
1

AGND LEARN PQ310

90W adapter

1
Vacset=3.3*(127K/(75K+127K))=2.075V @ SSM3K7002FU_SC70-3
CP Point=(Vacset/Vvdac)*(0.1/PR302)=4.19A PR332 PC320 PC321

1
24751_VREF CELLS D @ 0_0402_5% 0.1U_0603_25V7K @0.1U_0603_25V7K
20

2
CELLS
65W adapter 2BAT_SEL
2 1 BATT_SEL_HW <45>
Vacset=3.3*(115K/(150K+115K))=1.432V 10 PR334 G
PQ306 PR337 VREF 0_0402_5%
CP Point=(Vacset/Vvdac)*(0.1/PR302)=2.89A

1U_0603_10V6K
S

3
3

AO3413_SOT23-3 @ 0_0402_5% 2 1 BATT_SEL_EC <38>

2
1

PC322
2 1 PR333
Input OVP : 22.3V PR316 19 24751_SRP @ 0_0402_5%
100K_0402_5% SRP
+EC_AVCC
2

ACIN detect : 17.26V 1 2 2 1 2 11 18 24751_SRN

PR336 VDAC SRN
Fsw : 300KHz 0_0402_5% 17
BAT

1
VADJ 12 VADJ PC323
1

24751_VREF ACSET 0.1U_0603_25V7K

2
TP 29
24751_VREF 24751_OCP-3 24751_ACGOOD#
1 2 13 ACGOOD ICHG setting
1

PC324 RTCVREF 24751_VREF

PR318 PR319
200K_0402_5% 0.1U_0603_25V7K SRSET
SRSET 16 2 1 IREF <38>
1

/BATDRV

100K_0402_5%

100K_0402_5%
14 BATDRV 54.9K_0402_1%
1

1
D
2

PR317

PR335
PR320 24751_OCP-2 2 PQ307 PR322
100K_0402_5% G SSM3K7002FU_SC70-3 15 IADAPT
1 2 180K_0402_1% PC325
IADAPT @0.01U_0402_25V7K
S
2

2
1

D BQ24751ARHDR_QFN28_5X5 PR321

2
3 3
ACOFF 1 2 24751_OCP-1 2 PQ308 10_0603_5% @ ACIN <29,38,44>
G SSM3K7002FU_SC70-3 REGN
1

1
PC326 D
S
3

0.1U_0402_16V7K PC327 24751_ACGOOD# 2

PR323 100P_0402_50V8J G PQ311

2
1

340K_0402_1% ADP_I IREF

<38> Current S @ SSM3K7002FU_SC70-3

3
PR324
2

@ 0_0402_5%
VMB2 PR326 2.842V 3.3A
210K_0402_1%
2

VADJ
499K_0402_1% 340K_0402_1%

<38> CHGVADJ 1 2
1

VS
PR327

CHGVADJ Pre Cell

1000P_0402_50V7K
1

499K_0402_1%
1
PR328
0.01U_0402_25V7K

24751_VREF
PC328

3.3V 4.35V
OVP-1 2

2
1

PC329

2
1

2
0V 4V
PR329

PR325
2

100K_0402_5%
"CHGVADJ" connect to EC DA pin
2

1
8

PR330
10K_0402_5% 3 OVP-2 CHGEN#
P

+
<38> BATT_OVP 2 1 1 0

1
D
2
G

-
105K_0402_1%

PQ309
A/D <38> FSTCHG 2
1

PU302A G SSM3K7002FU_SC70-3
LI-3S :13.5V----BATT-OVP=1.5V
0.01U_0402_25V7K
4

1
PR331

LM358DR_SO8 S

3
PC330

4
BATT-OVP=0.1112*BATT+ 4
2
2

OVP-3 5
P

+
7 0
6 Security Classification Compal Secret Data Compal Electronics, Inc.
G

-
PU302B 2008/05/21 2009/05/21 Title
Issued Date Deciphered Date
4

LM358DR_SO8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
OVP-4 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, March 18, 2009 Sheet 46 of 53
A B C D
 5 4 3 2 1

ISL6237_B+
ISL6237_B+
B+

2200P_0402_50V7K
D D

1
PC406
VL

2
3/5V_VCC
3/5V_VIN
+5VALWP

+3VALWP

UG3 HG5

BST3A-1 BST3A BST5A BST5A-1

5V_SNB
3V_SNB
SW 3 SW 5

LG3 LG5

C FB3 C

VL
FB5
2VREF_ISL6237

5V_SKIP
VL

VS POK <29>
EN_LDO-1 EN_LDO

3/5V_EN1 ILM1

3/5V_EN2 ILIM2

B VL B

3/5V_NC

3/5V_TON
2VREF_ISL6237

MAINPW ON <45>

+3VALWP +3VALW
2VREF_ISL6237

+5VALWP +5VALW

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2008/05/21 2009/05/21 Title
Issued Date Deciphered Date 3VALW/5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 18, 2009 Sheet 47 of 53
5 4 3 2 1
 5 4 3 2 1

PJ501
1.5V_IN 2 1 B+
2 1
@ JUMP_43X79

5
6
7
8

680P_0402_50V7K

330P_0402_50V7K

470P_0402_50V7K
10U_1206_25V6M
1

1
PC533

PC501

PC544

PC545
PR501

2
240K_0402_1% 4
1.5V_TON 1 2
D D
PR518
0_0402_5% PQ501
1 2 1.5V_EN BST_1.5V 1 2BST_1.5V-1
1 2 AO4466_SO8
<31,38,43,49> SYSON

3
2
1
PR519 PC525
2.2_0603_5% 0.1U_0603_25V7K

1
PL501

15

14
1
PC526 2.2UH_PCMC063T-2R2MN_8A_20%
@0.1U_0402_16V7K 1 2

EN_PSV

TP

VBST
+1.5VP

1
2 13 UG_1.5V
TON DRVH
PR521 3 12 SW _1.5V PR520
VOUT LL

5
6
7
8
422_0603_1% 4.7_1206_5%

10U_0603_6.3V6M
220U_6.3VM_R15
1
+5VALW 1 2 1.5V_V5FILT 4 11 1.5V_TRIP
1 2 +5VALW

1 1.5V_SNB 2
V5FILT TRIP

1
+

PC527
PR522
1.5V_FB

AO4712_SO8
5 10 23.7K_0402_1%
VFB V5DRV

PC528
2
1
LG_1.5V 2
1 2 6 PGOOD DRVL 9 4

PGND

PQ506
PC529

GND
1U_0603_10V6K PC530 PR533

1
@ 47P_0402_50V8J 100K_0402_1%
1 2 PC543 PC531 PC532

3
2
1
@0.1U_0402_16V7K PU501 4.7U_0805_6.3V6K 470P_0603_50V7K

2
TPS51117RGYR_QFN14_3.5x3.5
1.5V_PGOOD <8>
PR523
31.6K_0402_1%
1 2

1
C PR524 C
30.1K_0402_1%
PJ506
2 VCCP_IN 2 2 1 1 B+

@
JUMP_43X79

5
6
7
8

220P_0402_50V7K

680P_0402_50V7K

820P_0603_50V7K
10U_1206_25V6M
1

1
PC534

PC546

PC547

PC548
PR525

2
240K_0402_1% 4
VCCP_TON 1 2
PR526 PR527
PC535
100K_0402_1% 2.2_0603_5% PQ507
1 2 VCCP_EN BST_VCCP1 2BST_VCCP-1
1 2 AO4466_SO8
<31,38,43,49> SUSP#

3
2
1
0.1U_0603_25V7K
1

PL502

15

14
1
PC536 1.8UH_SIL104R-1R8PF_9.5A_30%
0.22U_0402_6.3V6K 1 2

EN_PSV

TP

VBST
+VCCPP
2

1
2 13 UG_VCCP
TON DRVH
PR529 3 12 SW _VCCP PR528
VOUT LL

5
6
7
8
422_0603_1% 4.7_1206_5%

10U_0603_6.3V6M
220U_6.3VM_R15

<BOM Structure>
1
+5VS 1 2 VCCP_V5FILT 4 11 VCCP_TRIP
1 2 +5VS

2
V5FILT TRIP

1
+

PC537
AO4712_SO8
PR530

VCCP_SNB
VCCP_FB 5 10 23.7K_0402_1%
VFB V5DRV

PC538
2
1

PQ508
6 9 LG_VCCP 4
PGOOD DRVL

PGND
B PC539 GND B
1U_0603_10V6K PC540
2

1
@

47P_0402_50V8J
1 2 PC541 PC542
7

3
2
1
PU503 4.7U_0805_6.3V6K 680P_0603_50V7K

2
TPS51117RGYR_QFN14_3.5x3.5

PR531
13.7K_0402_1%
1 2
1

PR532
+1.5V 31.6K_0402_1%
2
1

PJ502
1

@ JUMP_43X79
2

PJ504
PU502 2 1
+1.5VP +1.5V
2

0.75V_IN 2 1
1 VIN VCNTL 6 +3VALW
@ JUMP_43X118
2 GND NC 5
1

PC519
1

4.7U_0805_6.3V6K 3 7 PC520
PR515 VREF NC 1U_0402_6.3V6K
2

1K_0402_1% 4 8 PJ503 PJ505

VOUT NC
A
+VCCPP 2 2 1 1 +VCCP +0.75VP 2 2 1 1 +0.75V A
PR534 9
2

0_0402_5% TP @ JUMP_43X118 @ JUMP_43X79

1 2 0.75V_REF APL5331KAC-TRL_SO8
<31,43,49> SUSP
1

PR516 +0.75VP
1

@ 0_0402_5% D PR517
1 20.75V_EN 2 1K_0402_1% PC521
<43,49> SYSON# Security Classification Compal Secret Data Compal Electronics, Inc.
1

G 0.1U_0402_16V7K
2
1

S PQ505 PC523
Issued Date 2008/05/21 Deciphered Date 2009/05/21 Title
3

PC522 SSM3K7002FU_SC70-3 10U_0603_6.3V6M

1.5V/VCCP/0.75V
2

@ 0.1U_0402_16V7K
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, March 18, 2009 Sheet 48 of 53
5 4 3 2 1
 5 4 3 2 1

1.8V_IN B+
PR617
100K_0402_1%

330P_0402_50V7K
<31,38,43,48> SUSP# 1 2

1
1.8V_TON +VGA_COREP +VGA_CORE

PC602
2
1.8V_EN BST_1.8V BST_1.8V-1
<31,38,43,48> SYSON

15

14
D D

1
PU601

EN_PSV

TP

VBST
+1.5VRAMP
2 13 UG_1.8V
TON DRVH
+1.1VSP +1.1VS
3 12 SW _1.8V
VOUT LL

10U_0603_6.3V6M
+1.8V_VCC 1.8V_V5FILT 4 11 1.8V_TRIP
V5FILT TRIP

PC606
1.8V_SNB
1.8V_FB 5 10 +1.8V_VCC
VFB V5DRV
+1.5VRAMP +1.5VRAM

2
6 9 LG_1.8V
PGOOD DRVL

PGND
GND

1
TPS51117RGYR_QFN14_3.5x3.5 PC610

8
4.7U_0805_6.3V6K +1.8VP +1.8V

2
VGA_IN B+

UG_VGA
C BST_VGA BST_VGA-1 C

1 2 +5VS
+VGA_PVCC +VGA_VCC PD601
@ 1SS355_SOD323-2

+VGA_PVCC PL602
0.88UH_PCMB103E-R88MS_20A_20%
SW _VGA 1 2 +VGA_COREP

+5VS

5
6
7
8
VGA_FCCM

SI4634DY-T1-E3_SO8

VGA_SNB

0_0402_5%
PQ605
VGA_EN ISEN_VGA 4
<31,38,43,48> SUSP#

PR615
2
@

3
2
1
FSET_VGA
COMP_VGA

VGA_FB

LG_VGA
B B
+VGASENSE <18>
COMP_VGA-1

+5VALW +1.8V_VCC
GVID1-2 +1.8VS

GVID1-1 2 1 +5VS
<16> GPU_VID1 PR634
2.37K_0402_1%
+3VS

1.1V_IN +5VS LDO_1.8V_IN +1.8V_VCC

GVID0-2

GVID0-1
<16> GPU_VID0

1
1

PR623
PR621 1K_0402_1%
10K_0402_5%

2
2

1.1V_REF LDO_1.8V_REF
<31,43,48> SUSP

+1.1VSP +1.8VP
GPIO6 GPIO5 <31,43,48> SUSP
1.1V_EN LDO_1.8V_EN
A GPU_VID1 GPU_VID0 VGA_CORE A

1
NB10M-GS1 PC631
0 0
(Remove PR620) 0.92V 0.1U_0402_16V7K
1 0 2

GPIO6 GPIO5 Security Classification Compal Secret Data Compal Electronics, Inc.
GPU_VID1 GPU_VID0 VGA_CORE
Issued Date 2008/05/21 Deciphered Date 2009/05/21 Title
NB10P-GE1 0 0 0.9V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE/1.8V/1.1V
1 0 1.1V AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, March 18, 2009 Sheet 49 of 53
5 4 3 2 1
 5 4 3 2 1

<38>
VR_ON
+3VS

1.91K_0402_1%
1
10K_0402_1%
1.91K_0402_1%
1

1
D D

PR866
PR830

PR831

2
@
<8,29> VGATE

2
@

<29> CLK_ENABLE# 1 2

<8,29>
+CPU_B+

DPRSLPVR
PR832 PL801
@ 0_0402_5% +3VS +5VS HCB4532KF-800T90_1812
1 2 B+

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
0_0402_5%

1CPU_VREF 0_0402_5%
1

1
PC808

PC804

PC809

220U_25V_M
+

PR834

PR865
PC806
330P_0402_50V7K

PC805
2

2
2

0_0402_5%

0_0402_5%
@

5
0_0402_5%

0_0402_5%
124K_0402_1%

2
1

1
4

CPU_DPRSLPVR
PQ801

CPU_CLK_EN#
CPU_VR_ON 2

1
CPU_TRIPSEL
CPU_OSRSEL

CPU_TONSEL

PR837

PR838
SI7686DP-T1-E3_SO8

CPU_V5FILT

CPU_ISLEW
PL802

2
PR833

PR835

PR836
2 1 0.36UH_PCMC104T-R36MN1R17_30A_20%

3
2
1
PC824 1 4 +CPU_CORE
1U_0402_6.3V6K

5
6
7
8

5
6
7
8

1
CPU_CSP1-1
2 3
+5VS PR819

SI4634DY-T1-E3_SO8

SI4634DY-T1-E3_SO8

1
C 4.7_1206_5% C

17.8K_0402_1%
41

40

39

38

37

36

35

34

33

32

31

PR801
1CPU1_SNB
2
CPU_VREF
1 2
GND

V5FILT

ISLEW

OSRSEL

TONSEL

TRIPSEL

PWRMON

VR_ON

CLK_EN#

DPRSLPVR

PGOOD

2
PR839 PD801 4 4 PR840

PQ802

PQ803
4.02K_0402_1% 1SS355_SOD323-2 69.8K_0402_1%

2
1 2CPU_DROOP 1 30 UGATE_CPU1 1 2
PC825 68P_0402_50V8J DROOP DRVH1

1
CPU_CSP1 2 1 1 2CPU_VREF 2 29 BOOT_CPU1
1 PR841 2BOOT_CPU1-1
1 2 PC815

3
2
1

3
2
1
VREF VBST
PR861 470_0402_1% PC826 0.22U_0603_10V7K 2.2_0603_5% PC827 680P_0402_50V7K 1 2CPU_SN-1
1 2

2
2

3 28 PHASE_CPU1 0.22U_0603_10V7K PR842 PH801

GND LL1

CPU_CSN1
CPU_CSP1
PC836 28.7K_0402_1% 100K_0603_1%_TH11-4H104FT
100P_0402_50V8J 1 2 CPU_CSP1-2 4 27 LGATE_CPU1 +CPU_B+ 1 2
1

CPU_CSN1 2 PC828 33P_0402_50V8J CSP1 DRVL1 PC829

1 +5VS

5
PR862 470_0402_1% 2 CPU_CSN1-1 0.033U_0402_16V7K

10U_1206_25V6M

10U_1206_25V6M
1 5 CSN1 V5IN 26 1 2

1
CPU_CSN2 2 1 PC830 33P_0402_50V8J PC831 10U_0603_6.3V6M

PC817

PC818
PR863 470_0402_1% 1 2 CPU_CSN2-1 6 CSN2
PU801
PGND 25
2

PC832 33P_0402_50V8J TPS51620RHAR_QFN40_6X6

2
PC837 1 2 CPU_CSP2-2 7 CSP2 DRVL2 24 LGATE_CPU2
100P_0402_50V8J PC833 33P_0402_50V8J 4
1

CPU_CSP2 2 1 CPU_GNDSNS 8 23 PHASE_CPU2

PR864 470_0402_1% GNDSNS LL2 PQ804
CPU_VSNS 9 22 BOOT_CPU2
1 PR846 2BOOT_CPU2-1
1 2 SI7686DP-T1-E3_SO8 PL803
VSNS VBST2 2.2_0603_5% PC834 0.36UH_PCMC104T-R36MN1R17_30A_20%

3
2
1
CPU_THERM UGATE_CPU2 0.22U_0603_10V7K
DPRSTP#

10 THERM DRVH2 21 1 4
1

VR_TT#

1
0_0402_5%

0_0402_5%

1 2 CPU_CSP2-1
2 3
VID6

VID5

VID4

VID3

VID2

VID1

VID0
PSI#

+5VS

5
6
7
8

5
6
7
8
PD802

SI4634DY-T1-E3_SO8

SI4634DY-T1-E3_SO8
1

1
PR844

PR845

1SS355_SOD323-2 PR829

17.8K_0402_1%
PR848
4.7_1206_5%
2

11

12

13

14

15

16

17

18

19

20

1CPU2_SNB
PR849

2
20K_0402_1% PR850
1CPU_DPRSTP#

B 4 4 69.8K_0402_1% B
2

2
VID6

VID5

VID4

VID3

VID2

VID1

VID0
PSI#

PQ805

PQ806
1 2
1

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

1 2CPU_SN-2
1 2

3
2
1

3
2
1
PC823 PR851 PH803

2
1

CPU_CSN2
CPU_CSP2
PR843 PR847 680P_0402_50V7K 28.7K_0402_1% 100K_0603_1%_TH11-4H104FT
100_0402_1% 100_0402_1% 1 2
2

PC835
0.033U_0402_16V7K
PR852

PR853

PR854

PR855

PR856

PR857

PR858

PR859

PR860
2

1
<6>

<6>
VSSSENSE

+CPU_CORE
VCCSENSE

<6>

<6>

<6>

<6>

<6>

<6>

<6>

<6>
<6,8,28>
H_PSI#
H_DPRSTP#

CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/05/21 Deciphered Date 2009/05/21 Title
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 18, 2009 Sheet 50 of 53
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Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Reason for change PG# Modify List Date Phase
Change PU301 Pin 11 VDAC source form
D
1 Improve charge output current accuracy. P46 24751_VRFE to +EC_AVCC. 20080725 DVT D

Change PR801, PR848 from 15.4k_0402_1% to 17.8k_0402_1%

2 Improve CPU_CORE transient response. P50 Change PR840, PR850 from 196k_0402_1% to 69.8k_0402_1% 20080804 DVT
Change PC829, PC835 from 0.022u to 0.033u.

3 Adjust loadline. P50 Change PR839 from 5.76k_0402_1% to 4.02k_0402_1% 20080804 DVT

Add PC633, PC634 10u_0603_6.3V_V6M.

4 Reduce VGA_CORE ripple. P49 Add PC619 330u_2.5V_R9M 20080804 DVT

5 Improve VGA_CORE efficiency at heavy load. P49 Add PD601 20080804 DVT

Adjust 0.75V power sequence. P48 Add PR534. 20080813 DVT

6
C C
P48 Change PR525 from 0 to 27K. PR526 from 0 to 100k.
7 Adjust power sequence.
Add 0.1u_0402 at PC630 0.22u_0402 at PC536. 20080813 DVT
P49

Change PQ603 from SI4686 to SI7686DP.

Change PQ604, PQ605 from FDMS670 to SI4634DY.
8 For customer upgrade VGA to N10X. P49 20080813 DVT
Change PL602 from 1u to .88u.
Change PC615 from 220u ESR15 to 330u ESR9.

9 Reserve OSR to reduce overshoot. P50 Add PR865 20080813 DVT

10 Improve VGA CORE driver ability for upgrade P49 Change PU602 VGA CORE solution from TPS51117 to ISL6269A
VGA chip from N9X to N10X. 20080823 DVT

Change PR403, PR405, PR519, PR527, PR603, PR611, PR841, PR846 to 2.2ohm at BOM.
Change PR402, PR404, PR520, PR528, PR604, PR612, PR819, PR829 to 4.7ohm at BOM.
Change PC414, PC415 to 330p_0402_50V at BOM.
P47
Change PC542, PC608, PC618, PC815, PC823 680P_0603_50V7K at BOM.
B
P48 Change PC532 to 470P-0603_50V7K. 20080826 DVT B
Reduce power board band.
11 P49 Add PC546 220P_0402_50V7K.
P50 Add PC405, PC544, PC602, PC617, PC806 330P_0402_50V7K.
Add PC545 470P_0402_50V7K.
Add PC533, PC547 680P_0402_50V7K.

12 Change 1.8V sequence the same with 1.8VS. P49 Add PR617, PR631, PR637. 20080902 DVT

13 For solve charger unstable. P46 Add PC331 10u_1206_25V6M 20080902 DVT

14 Adjust power sequence. Change PR617, PR632 to 100k_0402_1%. 20080905 DVT

P49 Add PC604, PC631 to 0.1u_0402.

15 Reduce power board band. P46 Add PC332 1000P_0402_50V7K 20081013 PVT

Reserve VDAC power connect to

16 24751_VREF and EC_AVCC P46 Add PR336, PR337 0_0402_5% 20081015 PVT

A
17 Reduce power board band. P44 Add PC112, PC113 0.1U_0603_50V7K 20081022 PVT A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
<Doc>
Date: W ednesday, March 18, 2009 Sheet 51 of 53
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 5 4 3 2 1

NO DATE PAGE MODIFICATION LIST PURPOSE

------------------------------------------------------------------------------------------------------------- DVT
1 P11 change R166 package from 0805 to 1206 VOLTAGE DRAP
2 P16 ADD R788 (MEM_VREF PULL DOWN) GPIO STATUS
3 P29 REMOVE D17 REMOVE AC IN CONTROL OF SW
D 4 P42 add D29,D30,D33 EMI REQUEST D

5 P36 add R789 FOR MONO

6 P42 CHANGE R781 FROM 300 TO 560 MEET LED SPEC
7 P19 ADD C843 ADD 220uF FOR VGA CORE
8 P25 change LCD power circuit G5243 ISSUE
9 P42 modify JP26 pin define MEET IDEAPAD SPEC
10 P18 remove R135 CHECK NV SPEC
11 P16 ADD R793,R795,R796 FOR N10x 40nm
12 P19 ADD R794 FOR N10x 40nm
13 P7 STUFF C832,C834,C833,C647,C818,C817,C803 POWER REQUEST
14 P19 ADD C844,C845,C846,C847,C848,C849,C850,C851,C852 NV REQUEST
15 P35 CHANGE U42 POWER FROM 1.8V TO 1.8VS UPDATE
C 16 P43 ADD J4 1.8V CONNECT TO 1.8VS C

17 P14 CHANGE FROM 0.75V TO 0.75VS DDR3 POWER

18 P15 CHANGE FROM 0.75V TO 0.75VS DDR3 POWER
19 P43 CHANGE FROM 0.75V TO 0.75VS DDR3 POWER
20 P37 HP_OUTR TO SWAP HP_OUTL HP_OUTR TO SWAP HP_OUTL
21 P36 CHANGE C646,C646 FROM 0.1uF TO 0.01uF AUDIO TEAM TO REQUEST THE HPF OF 600Hz
22 P37 CHANGE C760 FROM 1nF TO 10nF AUDIO TEAM TO REQUEST THE LPF OF 600Hz
23 P37 CHANGE R619 FROM 47Kohm TO 68Kohm AUDIO TEAM TO REQUEST THE LPF OF 600Hz
24 P43 DELETE 5VS_GATE , R596,R597,R607 DELETE 5VS_GATE
25 P40 SWAP LED7 SWAP LED7
26 P40,P42 CHANGE LED POWER FROM 3V TO 5V USE WHITE LED
27 P35 REMOVE U42 REMOVE ESATA REDRIVER
B 28 P31,P38 ADD AO FUNCTION ADD AO FUNCTION B

29 P38 CHANGE R560,R561 FROM 4.7K TO 2.2K I2C BUS

30 P38 ADD R810,R811 I2C BUS POWER
31 P43 CHANGE U37,U38 POWER FROM B+ TO +5VALW CHANGE MOSFET VDS
32 P40 TO MODIFY ALL LED SYMBOL MODIFY COLOR TO WHITE
33 P40 MODIFY R627,R624,R577 FROM 300 TO 453OHM MODIFY COLOR TO WHITE
34 P23 ADD C853,C854,C855,C856 FOR 3G ISSUE (SED)
35 P7,P14,P15 ADD C14~C31 FOR 3G ISSUE (SED)
36 P32 C32,C33,C34,C35 EMI
37 P37 DEL R616,R617,R765,R766,R764,R767, EMI
R534,R536,R539,R540
38 P37 ADD L43,L44,L45,L46,L47,L48,L49,L50,L51,L52 EMI
A
39 P19 REMOVE C843 CHANGE TO POWER SIDE A

40 P31 ADD TV POWER SW FUNCTION ADD TV POWER SW FUNCTION

41 P5 CHANGE R1 FROM 49.9 TO 56 OHM FOLLOW INTEL CHECK LIST 2.0 Title
Compal Electronics, Inc.
42 P5 CHANGE R3 FROM 56 TO 68 OHM FOLLOW INTEL CHECK LIST 2.0 HW PIR
43 P8 CHANGE R45 R53 FROM 10K TO 1K OHM FOLLOW INTEL CHECK LIST 2.0 Size
B
Document Number
KIWB1/B2_LA4602P
Rev
1.0
44 P8 REMOVE "DDR3_SM_PWROK" CHANGE TO GPO_AUD Date: Wednesday, March 18, 2009 Sheet 52 of 53
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 5 4 3 2 1

NO DATE PAGE MODIFICATION LIST PURPOSE

------------------------------------------------------------------------------------------------------------- DVT
45 P11 CHANGE R79 R83 SIZE FROM 0805 TO 0603 COST DOWN
46 P16 ADD R813 ,R735,R793,R818,R816,R819,R817 FOR N10x 40nm
47 P19 DELETE L10,C316,C315,C312 FOR N10x 40nm
48 P19 DELETE L10,C316,C315,C312 FOR N10x 40nm
D D
49 P21,P22 CHANGE C781,C782,C800,C801 FROM 0.01UF TO 0.1 UF FOR N10x 40nm
50 P31 ADD R824 FOR 3G CARD
51 P36 ADD GPO_AUD FOR MUTE ISSUE
52 P38 CHANGE R562,R563 FROM 4.7K TO 2.2K OHM FOR SM BUS ISSUE (PULL UP)
53 P43 ADD C757 FOR POWER SEQUENCE
NO DATE PAGE MODIFICATION LIST PURPOSE
------------------------------------------------------------------------------------------------------------- PVT
1 P43 CHANGE R606,R595 FROM 150K TO 47K POWER SEQUENCE
P43 REMOVE C757 POWER SEQUENCE
2
3 P26 ADD POLY FUSE(F1) CRT PIN ISSUE
4 P24 ADD R825,R826,R827,R828,C857,C858,C859,C860 EMI SOLUTION OF HDMI
5 P40 CHANGE LED SYSBOL UPDATE FOOTPRINT
C C
6 P31 CHANGE R801 SIZE FROM 0603 TO 0805 NON-TV SW
7 P5 CHANGE R3 FROM 68 TO 56 OHM INTEL CHECK LIST 2.0
8 P36 ADD R829 REQUEST OF EMI
9 P28 CHANGE C494,C496 FROM 15pF TO 10pF RTC ADJUSTMENT
10 P32 CHANGE C693,C696 FROM 15pF TO 18pF RTC ADJUSTMENT
11 P38 CHANGE C605 FROM 27pF TO 33pF RTC ADJUSTMENT
12 P35,P41 CHANGE C728,C733 SYMBOL UPDATE FOOTPRINT
13 P38 ADD R830,R831 ENE ISSUE
14 P40 ADD R832,C861 3G REQUEST
15 P41 ADD C862,C863 MOSFET SW OF OVERSHOOT
NO DATE PAGE MODIFICATION LIST PURPOSE
B ------------------------------------------------------------------------------------------------------------- PRE MP B
1 P16,P18 ADD R834,R835,R836,R837,R838,R839,Q12A,Q12B FOR N10x 40nm
2 P16,P18 CONNECT AUX PIN FOR HDMI (AP2,AN3) FOR N10x 40nm
3 P42 R587 PULL DOWN FOR POWER ON/ OFF
4 P40 SWAP CHARGE_LED0# AND CHARGE_LED1# LED ISSUE
5 P37 CHANGE C758 FROM 1U TO 18N AUDIO TEAM REQUEST
6 P37 CHANGE R618 FROM 18KOHM TO 8.45K AUDIO TEAM REQUEST
7 P40 CHANGE R832 FROM 0 TO 47 OHM SED 3G TEAM REQUEST
8 P40 CHANGE C861 FROM 12P TO 68P SED 3G TEAM REQUEST
9 P36 CHANGE C645,C646 FROM .01U TO 3300P AUDIO TEAM REQUEST
10 P36 CHANGE R587 FROM 4.7K TO 10K ohm FOR POWER ON/ OFF
11 P42 CHANGE R769 TYPE FROM 0402 TO 0603
A
NO DATE PAGE MODIFICATION LIST PURPOSE A

------------------------------------------------------------------------------------------------------------- Upgrade
1 P16~P22 Modify nVIDIA N10x(40nm) and VRAM FOR N10x 40nm Compal Electronics, Inc.
Title

HW PIR
Size Document Number Rev
B KIWB1/B2_LA4602P 1.0

Date: Wednesday, March 18, 2009 Sheet 53 of 53

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