Digital Logic Design

BY

MUHIDIN M. (MSc.)
3/6/2023 1
 Chapter 2
LOGIC GATES
Lesson One

Main Logic Gates

At the end of this lesson, you should be able to
oList main logic gates
oDefine each main logic gates
oConstruct with their corresponding symbols
oProduce truth tables for each main logic gates
oImplement electrical circuit of main logic gates
oMention one application area of each logic gate

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 Chapter 2
LOGIC GATES
Lesson One
Logic gates
oAre the electronic device that produces a result based on two or more input values.
oTheir input and output values are logical values True (1) and False (0)
oAre a basic building block of a computer
oE.g. Integrated circuits (ICs) contain collections of gates suited to a particular purpose.
oMade up of transistors
oThey have no memory
oValues of output only depends on current values of input
oDivided into
 Main (basic) logic gates (NOT, AND & OR)
 Derived (combined) logic gates (NAND, NOR) and
 Exclusive logic gates (XOR, XNOR)

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 Chapter 2
LOGIC GATES
Lesson One
MAIN LOGIC GATES  Its operation is represented by a prime
or overbar
o NOT Gate  i.e.𝑦 = 𝑥 ′ (read as “NOT x equalto y”)
 An inverter  Meaning that y is what x is not
 Complements input and gives opposite  Its truth table is
output x y
 Always takes on input and gives one 0 1
output 1 0
 Symbolized by or
 Boolean expression: 𝑦 = 𝑥ҧ = 𝑥 ′
 Logic Gate:

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 Chapter 2
LOGIC GATES
Lesson One
MAIN LOGIC GATES
oNOT Timing Diagram for waveform inputs oNOT Gate Application
 Used to find 1’s complement
• Timing diagram shows how two or more  E.g. 8-bit binary number is complemented as
wave forms related in time

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 Chapter 2
LOGIC GATES
Lesson One
MAIN LOGIC GATES  Collector is connected to power supply (logical 1)
o NOT Gate implementation
 Emitter is connected to the ground (logical 0)

 If the input is set to 1, the transistor is in the ON

state and will pass the current through the ground
 In this case the output voltage of the gate is 0.

 If the input is set to 0, the transistor is in the OFF

state and it blocks passage of the current to the
ground.

 Instead the current is transmitted to the output line,

producing an output of 1.

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 Chapter 2
LOGIC GATES
Lesson One
MAIN LOGIC GATES  Truth table
x y z
oAND Gate 0 0 0
 Its operation is represented by a dot or
absence of an operator. 0 1 0
 i.e. 𝑥. 𝑦 = 𝑧 𝑜𝑟 𝑥𝑦 = 𝑧 (read as “x AND 1 0 0
y is equalto z”) 1 1 1
 Interpreted to mean that
• 𝑧 = 1 𝑖𝑓 𝑜𝑛𝑙𝑦 𝑥 = 1 & 𝑦 = 1;  Boolean expression: 𝑧 = 𝑥. 𝑦 = 𝑥𝑦
• 𝑜𝑡ℎ𝑒𝑟𝑤𝑖𝑠𝑒 𝑧 = 0
 Logic Gate:
 Can have two or more inputs
 Used logical multiplication

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 Chapter 2
LOGIC GATES
Lesson One
MAIN LOGIC GATES
oAND Timing Diagram for waveform inputs
oAND Gate
 Total number of possible combinations
of binary inputs to gate is given by:
 𝑁 = 2𝑛 ,
 𝑁 = 𝑝𝑜𝑠𝑠𝑖𝑏𝑙𝑒 𝑖𝑛𝑝𝑢𝑡 𝑐𝑜𝑚𝑏𝑖𝑛𝑎𝑡𝑖𝑜𝑛𝑠
 𝑛 = 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑖𝑛𝑝𝑢𝑡 𝑣𝑎𝑟𝑖𝑎𝑏𝑙𝑒𝑠
 E.g for two input variables: 𝑁 = 22 = 4
 for three input variables: 𝑁 = 23 = 8

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 Chapter 2
LOGIC GATES
Lesson One
MAIN LOGIC GATES
oAND Gate Application oAND gate Implementation
oE.g. Seat Belt Alarm System

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 Chapter 2
LOGIC GATES
Lesson One
MAIN LOGIC GATES  Its truth table is
x y z
oOR Gate 0 0 0
 Its operation is represented by a plus
sign. 0 1 1
 i.e 𝑥 + 𝑦 = 𝑧 (read as “x OR y is equalto 1 0 1
z”) 1 1 1
 Interpreted to mean that
 Boolean expression: 𝑧 = 𝑥 + 𝑦
• 𝑧 = 1 𝑖𝑓 𝑥 = 1 𝑜𝑟 𝑦 = 1 𝑜𝑟
 Logic Gate:
𝑖𝑓 𝑏𝑜𝑡ℎ 𝑥 𝑎𝑛𝑑 𝑦 𝑎𝑟𝑒 1;
• 𝑖𝑓 𝑏𝑜𝑡ℎ 𝑥 𝑎𝑛𝑑 𝑦 𝑎𝑟𝑒 0, 𝑡ℎ𝑒𝑛 𝑧 = 0

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 Chapter 2
LOGIC GATES
Lesson One
MAIN LOGIC GATES oOR application
 E.g. intrusion detection and alarm system (for
oOR Timing Diagram for waveform inputs home with two windows & one door)

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 Chapter 2
LOGIC GATES
Lesson One
MAIN LOGIC GATES

OR
Gate
Implementation
(Electrical ckt)

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 Chapter 2
LOGIC GATES
Lesson Two

Derived(combined) and Exclusive Logic Gates

At the end of this lesson, you should be able to
oList derived (combined) and exclusive logic gates
oDefine each derived (combined) and exclusive logic gates
oConstruct with their corresponding symbols
oProduce truth tables for each derived (combined) and exclusive logic gates
oImplement electrical circuit of derived (combined) and exclusive logic gates
oMention one application area of each logic gate

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 Chapter 2
LOGIC GATES
Lesson Two
Derived(combined) Logic Gates
oComplex gates that are made up of two or more basic gates
oSave the space

oThey are
 NAND
 NOR

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 Chapter 2
LOGIC GATES
Lesson Two
Derived(combined) LOGIC GATES oTruth Table
X Y Z
oNAND Gate 0 0 1
 It is a contraction of NOT-AND 0 1 1
 Same with AND gate except the output 1 0 1
is inverted. 1 1 0
oBoolean Expression :𝑧 = (𝑥. 𝑦)′ = 𝑥 ′ + 𝑦′
 It is a universal gate oLogic gate:
 it can be used in combination to perform
the AND, OR & NOT operations.
o ≡
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 Chapter 2
LOGIC GATES
Lesson Two
Derived(combined) LOGIC GATES oNAND Gate Application

oNAND Timing Diagram for waveform inputs

oIf tank A and tank B are above one-quarter

full, the LED is on.

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 Chapter 2
LOGIC GATES
Lesson Two
Derived(combined) LOGIC GATES Collector line of transistor 1 is connected to
 NAND Gate Implementation power supply (logical 1)
Emitter line of transistor 2 is connected to the
ground (logical 0)
If both input lines, input-1 & input-2, are set to
1, then both transistors are in the ON state and
the output will be connected to the ground,
resulting in a value of 0 on the output line.
If either (or both) input-1 or input-2 is 0, the
corresponding transistor is in the OFF state and
does not allow the current to pass, resulting in a
1 on the output line.
Thus the output of this gate is the opposite of
AND& represented a gate called NAND
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 Chapter 2
LOGIC GATES
Lesson Two
Derived(combined) LOGIC GATES oTruth Table
X Y Z
oNOR Gate 0 0 1
 It is a contraction of NOT-OR 0 1 0
 Same with OR gate except the output is
1 0 0
inverted.
1 1 0
 It can also be used as a universal gate oBoolean Expression :𝑧 = (𝑥 + 𝑦)′ = 𝑥 ′ . 𝑦′
 it can be used in combination to perform oLogic gate:
the AND, OR & NOT operations.

o ≡
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 Chapter 2
LOGIC GATES
Lesson Two
Derived(combined) LOGIC GATES oNOR Gate Application
 E.g. aircraft’s monitoring system.
oNOR Timing Diagram for waveform inputs

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 Chapter 2
LOGIC GATES
Lesson Two
Derived(combined) LOGIC GATES
oNOR Implementation  If either or both of the lines input-1 & input-2
are set to 1, then the corresponding transistor is
in the ON state & the output is connected to
the ground, producing an output value of 0.

 Only if both input lines are 0, effectively

shutting off both transistors, will the output
line contain a 1.

 Again, this is the exact opposite of the

definition of OR and is called NOR gate.

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 Chapter 2
LOGIC GATES
Lesson Two
Exclusive Gates oTruth Table
 Often treated as basic gates x y z
 Have their own unique symbols 0 0 0
 They are XOR & XNOR
0 1 1
1 0 1
o Exclusive – OR (XOR) Gate 1 1 0
 Has arbitrary inputs
 Its output is 1 if and only if one input is 1 oBoolean Expression :𝒛 = 𝒙⨁𝒚 = 𝐱 ′ 𝐲 + 𝐱𝐲′
and others are 0; otherwise, the output is 0. oLogic gate:

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 Chapter 2
LOGIC GATES
Lesson Two
Exclusive Gates
oXOR Gate Application  If one circuit fails, their outputs are different.
 Used to check failures of two identical  Then, output of XOR opposes the output of
circuits operating in parallel. the failed circuit.
 As long as both are operating properly, the
outputs of both circuits are always the same.  So XOR is used as failure indicator

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 Chapter 2
LOGIC GATES
Lesson Two
Exclusive – NOR (XNOR) Gate oTruth Table
x y z
 Has arbitrary inputs 0 0 1
0 1 0
 Its output is 1 if and only if the inputs are
of the same values 1 0 0
1 1 1
 i.e. all are 1 or all are 0; otherwise, the oBoolean Expression :𝒛 = 𝒙⨁𝒚 ′ = 𝒙′ 𝒚′ + 𝒙𝒚
output is 0. oLogic gate:

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 Chapter 2
LOGIC GATES
Lesson Two
Exclusive Gate Timing Diagram

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 Chapter 2
LOGIC GATES
Lesson Two
Exercise

Give one application area of

Each logic gates other than
examples given in this ppt.
Study rectangular shape of
each Gates. The End!
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