Timing and Control
• Timing for all registers in the basic computer is controlled by
a master clock generator.
• Clock pulses are applied to all flip-flops and registers in the
system, including the flip-flops and registers in the control
unit.
• Clock pulses do not change the state of a register unless the
register is enabled by a control signal.
• Two major types of control organization.
• Hardwired organization
• Microprogrammed organization
• Hardwired Organization
• The control logic is implemented with gates, flip-flops, decoders
and other digital circuits.
• It has the advantage that it can be optimized to produce a fast
mode of operation.
• The sequence of the operation carried out by this machine is
determined by the wiring of the logic elements and hence named
as “hardwired”.
• Requires changes in the wiring among the various components if
the design has to be modified or changed.
CPU’s with hardwired control unit – Intel 8085, RISC CPUs.
• Microprogrammed organization
• The control information is stored in a control memory.
• The control memory is programmed to initiate the required
sequence of micro operations.
• Changes or modifications can be done by updating the
microprogram in the control memory.
• Micro-programmed control unit is slower in speed because of the
time it takes to fetch microinstructions from the control memory.
CPUs with microprogrammed control unit – Intel 8080, CISC CPUs.
Control
logic
gates
Important
• Instruction read from memory transferred to IR.
• The contents of 15th bit of IR is transferred to a flipflop
named I.
• The 3-bits (12, 13, 14) of opcode id decoded with 3X8
decoder & applied to control logic gates.
• The bits (0 through 14) of IR is applied to control logic gates.
• 4-bit sequence counter(SC)
• It can count in binary from 0 through 15.
• The output of the counter are decoded into 16 timing signals T0
through T15.
• SC is incremented to provide timing signals T0, T1, T2, T3 and T4 in
sequence.
• At time T4 SC is cleared to 0 if decoder output D3 is active.
• D3T4: SC 0
• SC responds to the positive transition of the clock.
• Initially CLR input of SC is active. The first positive transition
clears SC to 0 which in turn activates the timing signal T0
out of the decoder.
• SC is incremented with every positive clock transition,
unless its CLR input is active.
• This produces the sequence of timing signals T0, T1, T2, T3,
T4 and so on.
• If SC is not cleared, the timing signals will continue with T5,
T6, up to T15 and back to T0.
• SC is cleared when D3T4=1.
• This causes the timing signal T0 to become active instead of
T5.
Instruction Cycle
• A program in memory unit of computer consists of a
sequence of instructions.
• The program is executed in the computer by going
through a cycle for each instruction. The steps
required to execute an instruction is known as
Instruction Cycle.
• Instruction cycle consists of the following phases:
(important)
1. Fetch an instruction from memory.
2. Decode the instruction
3. Read the effective address from memory if the
instruction has an indirect address.
4. Execute the instruction.
• Upon completion of step 4, the control goes to step 1.
• This process continues indefinitely unless a HALT
instruction is encountered.
Fetch and Decode
• PC loaded with address of first instruction.
• Sequence Counter(SC) is cleared to 0.
• After each clock pulse SC is incremented by one, so that the timing
signals go through a sequence T0, T1, T2, and so on.
• T0: AR <- PC content of PC transferred to AR
• T1: IR <- M[AR], memory address at AR is accessed & its content transferred to IR
PC <- PC+1 PC is incremented to point to the next instruction
• T2: D0, D1, …….,D7 <- Decode IR(12-14), opcode is decoded
AR <- IR(0-11), operand location transferred to AR
I <- IR(15) mode field transferred to flip flop I
Below shows
the first two
register transfer
stmts.
