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Central Processing Unit

The document discusses central processing unit and its components. It then explains general register organization using a diagram and describes how instructions are executed using the registers and arithmetic logic unit. Finally, it covers stack organization and how a stack can be implemented using registers or memory.

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0% found this document useful (0 votes)
43 views43 pages

Central Processing Unit

The document discusses central processing unit and its components. It then explains general register organization using a diagram and describes how instructions are executed using the registers and arithmetic logic unit. Finally, it covers stack organization and how a stack can be implemented using registers or memory.

Uploaded by

deepakbinoy51
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Unit 2

Topics covered:
Central Processing Unit
Course outline and schedule
Introduction
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Unit 2
Contents

❑ Central Processing Unit


❑ General Register Organization
❑ Stack Organization
❑ Addressing Modes
❑ Instruction Classification
❑ Program Control Instructions

Reference:
❑ M. M. Mano – Computer Systems Architecture –
Edition 3 – Pearson Publication1

* 1
Central Processing Unit

❑ The part of the computer that performs the bulk


of data processing operations is called central
processing unit (CPU).

❑ The CPU is made up of 3 major components:


1. Register set : store intermediate result during
execution
2. ALU : perform arithmetic &logic operations
3. Control unit: instruct the ALU to perform the
desired operation and supervise the transfer of
info.

* 2
* 3
List of registers for the basic computer

* 4
GENERAL REGISTER ORGANIZATION
(important)

❑ The memory locations are used for storing pointers,


counters, return address, temporary results, and
partial product during multiplication.

❑ Having to refer to the memory location for such


application is time consuming. So most convenient and
efficient way is to store these intermediate values in
processor registers.

❑ When large no. of registers are included in the CPU, it


is most efficient to connect them through common bus
system.

Explain General Register Organization with the help of a


* 5
neat diagram. (15 marks)
❑ The registers communicate each other for direct
data transfers, & for performing various
microoperations.

❑ Hence a common unit that can perform all the


arithmetic, logic, & shift microoperations in the
processor is necessary.

❑ A bus organization for 7 CPU registers is shown in


the following fig.

* 6
* 7
❑ The output of each register is connected to two
multiplexers (MUX) to form the two buses A and B.
❑ The selection lines in each multiplexer select one
register or the input data for the particular bus
❑ The A and B buses form the inputs to a common
arithmetic logic unit (ALU).
❑ The operation selected in the ALU determines the
arithmetic or logic microoperation that is to be
performed.
❑ The result of the microoperation is available for
output data and also goes into the inputs of all the
registers.
* 8
❑ The register that receives the information from
the output bus is selected by a decoder.

❑ The decoder activates one of the register load


inputs, thus providing a transfer path between the
data in the output bus and the inputs of the
selected destination register.

❑ The control unit that operates the CPU bus system


directs the information flow through the registers
and ALU by selecting the various components in
the system.
* 9
Eg. to perform the operation: R 1 <--R2 + R3

❑ The control must provide binary selection variables to


the following selector inputs:
1. MUX A selector (SELA): to place the content of
R2 into bus A .

2. MUX B selector (SELB): to place the content of


R3 into bus B .

3. ALU operation selector (OPR): to provide the


arithmetic addition A + B .

4. Decoder destination selector (SELD): to transfer


the content of the output bus into R1.
* 10
❑ CONTROL WORD: The four control selection
variables are generated in the control unit and must
be available at the beginning of a clock cycle.

* 11
❑ Control Word:
◆ There are 14 binary selection inputs in the unit,
and their combined value specifies a control word.
◆ The 3 bits of SELA select a source register for
the A input of the ALU.
◆ The 3 bits of SELB select a register for the B
input of the ALU.
◆ The 3 bits of SELD select a destination register
using the decoder and its seven load outputs.
◆ The 5 bits of OPR select one of the operations in
the ALU

* 12
* 13
* 14
❑ Eg. R 1 <- R 2 - R3

* 15
STACK ORGANIZATION
❑ A stack is a storage device that stores information in
such a manner that the item stored last is the first
item retrieved(LIFO).

❑ The stack in digital computers is a group of memory


locations with a register that holds the address of top
element.

❑ This register that holds the address of top element of


the stack is called Stack Pointer (SP).

Explain Stack Organization in detail? (15 mark)


* 16
Stack operations

❑ The operation of insertion into stack is called push.


❑ The operation of deletion is called pop.

❑ These operations are simulated by incrementing or


decrementing the stack pointer (SP) register.
❑ The binary content of SP will be the address of the
word that is currently on top of the stack.

* 17
Implementation of stack

❑ In digital computers, stack can be


implemented in two ways:
◆ Register Stack
◆ Memory Stack

* 18
REGISTER STACK

❑ A register stack is organized as a collection of finite


number of registers that are used to store temporary
information during the execution of a program.

❑ Fig. shows the organization of a 64-word register


stack.

❑ The stack pointer (SP) is a register that contains a


binary no. whose value is equal to the address of the
word that is currently on top of the stack.

* 19
64 Word Register Stack

* 20
❑ To insert a new item, the stack is pushed by
incrementing SP and writing a word in the next-higher
location in the stack.

❑ The first item stored in the stack is at address 1. The


last item is stored at address 0.

❑ To remove the top item, the stack is popped by reading


the memory word at that address and decrementing the
content of SP.

❑ During pop operation, item has been read out but not
physically removed.
* 21
❑ In a 64-word stack, the stack pointer contains 6
bits because 26 = 64.

❑ Since SP has only six bits, it cannot exceed a


number greater than 63 (111111 in binary).

❑ When 63 is incremented by 1, the result is 0 since


111111 + 1 = 1000000 in binary, but SP can
accommodate only the six least significant bits.

❑ Similarly, when 000000 is decremented by 1, the


result is 1 1 1 1 1 1 .
* 22
❑ The one-bit register FULL is set to 1 when the
stack is full, and the one-bit register EMPTY is
set to 1 when the stack is empty of items.

❑ DR is the data register that holds the binary data


to be written into or read out of the stack.

* 23
❑ The push operation is implemented with the following
sequence of microoperations;

Initially, SP <- 0, EMPTY <- 1 and FULL <- 0.


SP <- SP + 1 Increment stack pointer

M[SP] <- DR Write item on top of the stack

If(SP = 0) then (FULL <-1) Check if stack is full

EMPTY <-0 Mark the stack not empty

* 24
❑ The pop operation consists of the following sequence
of microoperations:
A new item is deleted if the stack is not empty
(EMPTY <- 0).

DR <-M[SP] Read item from the top of stack

SP <-SP – 1 Decrement stack pointer

If(SP = 0) then (EMPTY <- 1) Check if stack is empty

FULL <- 0 Mark the stack not full

* 25
MEMORY STACK

❑ The stack can be implemented in a random-access memory


attached to a CPU.

❑ The implementation of stack in the CPU is done by assigning


a portion of memory to a stack operation and using a
processor register as a stack pointer.

❑ The starting memory location of the stack is specified by


the processor register as stack pointer.

❑ Figure shows a portion of computer memory partitioned into


three segments: program, data, and stack.
* 26
* 27
Memory Stack

❑ The program counter PC points at the address of


the next instruction in the program.

❑ The address register AR points at an array of


data.

❑ The stack pointer SP points at the top of the


stack

* 28
❑ The three registers are connected to a common
address bus, and either one can provide an address
for memory.

❑ PC is used during the fetch phase to read an


instruction.

❑ AR is used during the execute phase to read an


operand.

❑ SP is used to push or pop items into or from the


stack.
* 29
❑ In the fig. the initial value of SP is 4001 and the
stack grows with decreasing addresses.

❑ Thus the first item stored in the stack is at


address 4000 , the second item is stored at
address 3999, and the last address that can be
used for the stack is 3000.

❑ No provisions are available for stack limit checks.


❑ The items in the stack communicate with a data
register DR.

* 30
❑ A new item is inserted with the push operation as follows:
– SP <-SP - 1
– M[SP] <-DR

❑ A new item is deleted with a pop operation as follows:


– DR <-M[SP]
– SP <-SP + 1

❑ The stack limits can be checked by using two processor


registers: one to hold the upper limit (3000 in this case), and
the other to hold the lower limit (4001 in this case).

❑ After a push operation, SP is compared with the upper-limit


register and after a pop operation, SP is compared with the
lower-limit register.
* 31
❑ The advantage of a memory stack is that the CPU
can refer to it without having to specify an
address, since the address is always available and
automatically updated in the stack pointer.

* 32
Reverse Polish Notation (important)

❑ A stack organization is very effective for


evaluating arithmetic expressions.

❑ The common arithmetic expressions are written in infix


notation, with each operator written between the operands.
◆ A * B
❑ Polish notation (prefix) , places the operator before the
operands.
◆ *AB

❑ The postfix notation, referred to as reverse Polish


notation (RPN), places the operator after the operands.
◆ AB*

* 33
❑ A + B Infix notation
❑ + AB Prefix or Polish notation
❑ AB + Postfix or reverse Polish notation (RPN)

* 34
❑ The reverse Polish notation is in a form
suitable for stack manipulation.

❑ The expression
A*B+C*D
is written in reverse Polish notation as
AB * CD * +

* 35
The reverse polish notation(RPN) is evaluated as
follows:

❑Scan the expression from left to right. When an


operator is reached, perform the operation with the
2 operands found on the left side of the operator.
❑Remove the two operands & the operator & replace
them by the no. obtained from the result of the
operation.
❑Continue to scan the expression & repeat the
procedure for every operator encountered until
there are no more operators.
* 36
Conversion from infix to RPN
❑We should consider the operational hierarchy
adopted for infix notation.
◆ It tells that we first perform all arithmetic
inside inner parentheses, then inside outer
parentheses, and do multiplication and division
operations before addition and subtraction
operations.
❑(A+B)*[C*(D+E)+F]
❑RPN form is
◆ AB+DE+C*F+*

* 37
* 38
Evaluation of Arithmetic Expressions using Stack

❑ Reverse Polish notation, combined with a stack


arrangement of registers, is the most efficient
way known for evaluating arithmetic expressions.

❑ The procedure consists of first converting the


arithmetic expression into its equivalent reverse
Polish notation.

❑ Scan the expression from left to right.

❑ The operands are pushed into the stack in the


order in which they appear.
* 39
* 40
Evaluation of Arithmetic Expressions (Cont.)

❑ Consider the arithmetic expression


❑ (3 * 4) + (5 * 6)
❑ In reverse Polish notation, it is expressed as
❑ 34 * 56 * +

* 41
Assignment

❑ ..\COA ASSIGNMENT march 11.pdf

* 42

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