INTRODUCTION TO 8086

MICROPROCESSOR
MICROPROCESSOR

• It is a program controlled semiconductor device, which fetches(from memory),

decodes and executes instructions.

• It is used as CPU in computers • Microprocessors consist of an ALU (Arithmetic

Logic Unit), an array of registers and a CU(Control Unit).

• ALU performs arithmetic and Logical operations on data received from the
memory or an input device. Register array consist of registers and accumulator.
The control unit controls the flow of data and instructions with in the computer.
Microprocessor follows the sequence – Fetch, Decode and execute.

• Initially the instructions are stored in memory in a sequential order. The

microprocessor fetches these instructions from memory thendecodes it and
executes those instructions till STOP instruction reached. Later it sends the
result in binary to the output port. Between these processes , the registers stores
the temporary data and ALU performs the computing functions.

• The microprocessor is identified with the size of the data, the ALU of the
processor can work with at a time.

• The 8085 processor has 8 bit ALU , hence it is called 8-bit processor. The 8086
processor has 16 bit ALU and it is called 16-bit processor.
8086 MICROPROCESSOR

• First 16-bit processor released by INTEL in the year 1978• 8086 is designed
using HMOS (High density n-type Metal Oxide Silicon field effect Transistors)
technology, and now it is manufactured using HMOS III technology, contains
approximately 29,000 transistors.
• 8086 is packed in a 40 pin DIP (Dual Inline Package),and requires 5 volt supply.
• 8086 does not have internal clock circuit. The 8284 clock generator is used to
generate the required clock for 8086.
• The maximum internal clock of 8086 is 5MHz.
• Other variations of 8086 with different clock rate are 8086-1 : 10MHz 8086-2 :
8MHz 8086-4 : 4MHz

• It consist of powerful instruction set , which provides operations like

multiplication and division easily.

• It supports two modes of operations, that is maximum mode and minimum

mode.

• Maximum mode is suitable for system having multiple processors and

minimum mode is suitable for system having Single processor.

• It was the first 16-bit processor having 16 bit ALU, 16 bit Registers, internal data
bus and 16 bit external data bus resulting in faster processing.
REGISTER ORGANIZATION OF 8086

8086 contains general purpose and special purpose registers. All registers are 16
bit registers.
• General purpose registers are used to holding data, variables and intermediate
results temporarily.
• Special purpose registers are used as a segment registers, pointers , index
registers or as offset storage registers for particular addressing modes.
a) GENERAL DATA REGISTERS
• The registers AX, BX, CX and DX are the general purpose 16 bit registers.
• AX is used as 16 bit accumulator, with the lower 8 bits of AX
designated as AL and the higher 8 bits as AH.

• The letter L and H specify Lower and Higher bytes of a

particular register.

• The letter X is used to specify the complete 16 bit register.

• The register BX is used as offset storage for forming

physical address. Used as base register. Store starting base
address of the memory area with in the data segment.
CX is used as a default counter (store loop counter)
• DX is used as an implicit operand or destination in case of a few instructions.
(Hold I/O port addresses for I/O instructions)
b) SEGMENT REGISTERS
• Segment is a logical unit of memory. Minimum size of segment can be 16
bytes and maximum can be 64 KB.
• CS – Code Segment Register
• DS – Data Segment Register
• ES – Extra Segment Register
• SS – Stack Segment Register
Segmentation

• Segmentation is the process in which the main memory of the computer is logically
divided in to different segments and each segment has its own base address.

• It is basically used to enhance the speed of execution of the computer system so that
the processor is able to fetch and execute the data from the memory easily and fast.

• CS contains the segment address for the code where the executable program is
stored.

• DS points to the data segment of the memory where the data is stored. • ES points to
another data segment of the memory .It also contains data.
• SS is used for addressing stack segment of the memory. Stacksegment is used
to store stack data.

• The segment register hold the upper 16 bits of the starting address(base
address) of 4 memory segments that 8086 is working with atany particular time.

• While addressing any location in the memory bank, the physical address is
calculated from two parts. The first is Segment address, second is offset. • Any
of the pointers and index registers or BX may contain the offsetof the location to
be addressed.
c) POINTERS & INDEX REGISTERS

Pointers – IP, BP, SP

Index Registers – SI, DI

SP – Stack Pointer

BP – Base Pointer

IP – Instruction Pointer

SI – Source Index

DI – Destination Index
• The pointer IP contains the offset with in the code segment.

• BP contains the offset with in the data segment

• SP contains the offset with in the stack segment

• Index registers are useful for string manipulations

• SI is used to store the offset of source data in data segment. DI is used to store
the offset of destination in data segment or extra segment.

d) FLAG REGISTER

• Contains the results of computations in the ALU. • It also contains some flag
bits to control the CPU operations.
8086 ARCHITECTURE

• 8086 provides 16 bit ALU , 16 bit registers and segmented memory

addressing capabilities.
• 8086 has a rich instruction set , powerful interrupt structure.8086
has pipelined architecture.
• The architecture of 8086 can be internally divided into two separate functional
units. Bus Interface Unit (BIU) Execution Unit (EU)
• The BIU fetch instructions , reads data from memory and I/O ports, write data to
memory and I/O ports.
• The BIU contains the circuit for physical address calculations(address
generation unit) , bus control unit, segment registers, Instruction pointer and
instruction queue.
• The EU execute instructions that have already been fetched by theBIU. The BIU
and EU functions independently.
• The instruction queue is a FIFO (First In First Out)group of registers. The size of
queue is 6 bytes. The BIU fetches instruction code from memory and store in
queue. The EU fetches instruction codes from the queue.
• BIU is responsible for establishing communication with external devices and
peripherals including memory via bus
The complete physical address which is 20 bit long generated using segment
and offset registers ,each 16 bit long. The content of the segment register is
called segment address and offset register content is called offset address.

• For generating a physical address, segment address is shifted left bit- wise 4
times, and to this result, offset address is added to produce 20 bit physical
address.
• The segment register indicate the base address of a particular segment , while
the offset indicate the distance of the required memory location in the segment
from the base address.

• In execution unit 16 bit ALU performs arithmetic and logical operations. 16 bit
flag register contains the result of execution by ALU. Memory Segmentation

• To address a specific memory location, with in a segment we need an offset

address. The offset address is also 16 bit long so that the maximum offset value
can be FFFFH and the maximum size of any segment is thus 64K locat
Two types of segments are overlapping segments and nonoverlapping segments.

Overlapping Segment : A segment starts at a particular address and its maximum size
can go up to 64KB. But if another segment starts before this 64KB locations of the first
segment , the two segments are said to be overlapping segments.

Non-Overlapping Segment : A segment starts at a particular address and its maximum

size can go up to 64 kilobytes. If another segment starts along with this 64Kbytes
location of the first segment, then the two are said to be Non-overlapping segment.
Advantages of memory Segmentation

• It provide a powerful memory management mechanism.

• Data related or stack related operation can be performed in different segments.

• Code related operations can be done in separate code segments

• It allows to processes to easily share data.

• It allows to extend the address capability of a processor. Ie, segmentation

allows the use of 16-bit registers to give an addressing capability of 1MB.
Without segmentation it would require 20 bit registers.
FLAG REGISTER

• A flag is a flip-flop used to store the information about the status of the
processor and the status of the instruction executed most recently. 8086 has 9
flags
O – Overflow Flag : This flag is set if an overflow occurs.
• D – Direction Flag : Used by string manipulation instructions. If this flag bit is 0,
the string is processed beginning from the lowest address to the highest address
(auto incrementing mode). Otherwise the string is processed from the highest
address towards the lowest address (auto decrementing mode)
• I – Interrupt Flag : If this flag is set , the maskable interrupt are recognized by
the CPU , otherwise they are ignored.
• T – Trap Flag : If this flag is set , the trap interrupt is generated after execution
of each instruction.
• S – Sign Flag : This flag is set when the result of any computation is negative.
• Z – Zero Flag : This flag is set , the result of the computation is zeroor
comparison performed by the previous instructions is zero

• Ac –Auxiliary carry Flag : This is set if there is a carry from the lowest nibble.

• P – Parity Flag : This flag is set to 1 , if the result has even parity and the parity
is cleared to zero for odd parity of the result

• Cy – Carry Flag : is set if there is a carry from the addition or borrow from
subtraction.
SIGNAL DESCRIPTIONS OF 8086

The microprocessor 8086 is a 16 bit CPU available in three clock rates (5, 8 and
10 MHz) and it operate in a single processor and multi processor configurations,
to achieve high performance.

The signals can be categorized in to three groups

1. Signals having common functions for maximum mode

2. Signals having special functions for minimum mode

3. Signals having special functions for maximum mode

Pin configurations of 8086
𝐀𝐃𝟏𝟓 - 𝐀𝐃𝟎 : (Address/Data bus)

These are 16 address data bus. AD0- AD7 carries low order byte data and AD8 -
AD15 carrieshighorder byte data. During the first clock cycle it carries 16 bit
address and after that it carries 16 bit data.

𝐀𝟏𝟗/𝑺𝟔 , 𝐀𝟏𝟖/𝑺𝟓 , 𝐀𝟏𝟕/𝑺𝟒 , 𝐀𝟏𝟔/𝑺𝟑 : (Address/Status bus)

These are the four address /status bus. During the first clock cycle, itcarries 4 bit
address and later it carries status signals.
BHE / 𝑺𝟕 : (Bus High Enable/ Status) . It is used to indicate the transfer of data
using data bus 𝑫𝟓 - 𝑫𝟖. This signal is low during the first clock cycle , there after
it is active.
RD : (Read) used to read signal for read operation. It is an output signal . It is
active when low.
READY : This is an acknowledgement from the slow devices or memory that they
have completed the data transfer. It is an active high (1) signal.
INTR : (Interrupt Request). It is an interrupt request signal which is sampled
during the last clock cycle of each instruction to determine if the processor
considered this as an interrupt or not. This signal is active high and internally
synchronized.
TEST : This input is examined by a WAIT instruction. If the TEST pingoes low (0),
execution will continue, else the processor remains inan idle state.

NMI : (Non Maskable Interrupt). This is an edge triggered input which causes a
Type2 Interrupt. NMI is non maskable internally by software. This input is
internally synchronized.

RESET : It is used to restart the execution. It causes the process or to

immediately terminate its present activity. This signal is active high and must be
active for at least 4 clock cycles. RESET is also internally synchronized.
CLK : (Clock Input). Clock input provides the basic timing for processor operation
and bus control activity. It is an asymmetric square wave with a 33% duty cycle.

VCC : Power supply (+5v DC) GND : Ground for the internal circuit MN/MX :
(Minimum/Maximum). This pin signal indicates whatmode of the processor will
operate in.

M/IO : (Memory/ IO) . This signal is used to distinguish between memory and
I/O operations. When it is low it indicates the CPU is having an I/O operation.
When it is high it indicates that the CPU is having a memory operation.
INTA : (Interrupt Acknowledge). When the microprocessor receives this signal, it
acknowledges the interrupt. When it goeslow it means that the processor has
accepted the interrupt.
ALE : (Address Latch Enable). This output signal indicate the availability of the
valid address on the address/data line. This signal is active high. A positive pulse
is generated each time the processor begins any operation.
DT/ R : (Data Transmit / Receive). It decides the direction of data flow through
the transreceivers (bidirectional buffers). The signal is high when the data is
transmitted and the signal is low when the processor is receiving data.
DEN’ : (Data Enable). This signal indicate the availability of valid data over the
address/data lines. It is used to enable the transreceiver to separate data from
the Address/Data bus.
HOLD : This signal indicates to the processor that external devices are
requesting to access the Address /Data buses. HLDA : (Hold Acknowledge). This
signal acknowledges the HOLD signal.
𝑺𝟐’, 𝑺𝟏’, 𝑺𝟎 ‘: (Status Lines). These are the status lines (signals) that provides the
status of operation, which is used by the bus controller 8288 to generate memory
and I/O control signals. Following table shows the status line.
LOCK ‘: It is an active low pin. This indicate that other system bus masters will be
prevented from gaining the system bus , while the lock signal is low.
𝑸𝑺𝟏, 𝑸𝑺𝟎 : (Queue Status). These signals indicate the status of the internal 8086
instruction queue according to the table shown below.
RQ’/ 𝑮𝑻𝟎’ , RQ’/ 𝑮𝑻𝟏’ : (Request/Grant). It is used by other processors requesting
the CPU to release the system bus. When the signal is received by CPU, then it
sends acknowledgement. RT/𝐺𝑇0has a higher priority than RQ/ 𝐺𝑇1. Each of the
pin is bidirectional.
ADDRESSING MODES OF 8086
Indicate the way of locating data or operands
Describe the type of operands
The different ways in which a source operand is denoted in an instruction is
known as addressing modes.
These are the instructions used to transfer the data from one register to another
register, from the memory to the register, and from the register to the memory
without any alteration in the content.
The effective address refers to the address of an exact memory location in
which an operand’s value is actually present.
Categorization of instructions based on Flow of instruction execution Sequential
control transfer instructions

• Transfer control to next instruction immediately after it

Eg: Arithmetic , logical, data transfer, processor control instructions Control

transfer instructions

• Transfer control to some predefined address/ address specified inthe

instruction

Eg: INT(Interrupt) , CALL, RET (Return from CALL), JUMP

ADDRESSING MODES FOR SEQUENTIAL CONTROL TRANSFER INSTRUCTIONS

Immediate : Immediate data is a part of instruction MOV AX , 0005H 2. Direct :

16 bit memory address(offset/displacement) is directly specified in the
instruction.

MOV AX , [5000H]

• Here data resides in a memory location in the data segment

• Effective address= offset address + segment address (content of DS)

10H*DS+5000H
EXAMPLE

• Given DS=1000H

• Shifting a number 4 times is equivalent to multiplying it by 16D or10H

3 Register : Data is stored in register. All the registers except IP can be used.

Eg: MOV BX, AX

4. Register Indirect : offset of data is in either BX or SI or DI registers. The default

segment is either DS or ES

Eg : MOV AX, [BX]

• Here data is in DS whose offset address is in BX Effective address= 10H *

DS+[BX]
Example :

• Given DS=1000H and BX=2000H

5 Indexed : offset of the operand is stored in one of the index registers.
• For SI (source index), default segment is DS
• For DI(destination index), default segment is ES
Eg: MOV AX, [SI] Effective address= 10H*DS+[SI]
6. Register relative : Data is available by adding the displacement with the content of
any one of the register BX, BP, SI and DI
• Default segment is DS or ES
Eg: MOV AX, 50H [BX] Effective address= 10H*DS+50H+[BX]
Example: MOV AX, 5000 [BX]

• Given DS=1000H and BX=2000H

7. Based Indexed : effective address is sum of base register (BX orBP) and Index
register (SI or DI)

• Default segment register may be ES or DS

Eg: MOV AX , [BX] [SI] Effective address= 10H*DS+[BX]+[SI]

Example: • Given DS=1000H, BX=2000H and SI=3000H

8. Relative Based Indexed : effective address is formed by adding

displacement with the sum of content of any of base registers (BXor BP) and any
one of the index registers Eg: MOV AX, 50H [BX] [SI]

Effective address= 10H*DS+50H+[BX]+[SI]

Example: • Given DS=1000H, BX=2000H and SI=3000H

ADDRESSING MODES FOR CONTROL TRANSFER
INSTRUCTIONS

Intersegment: Destination location is in different segment.

• Intrasegment: Destination location is in same segment.

Intersegment Direct

• Destination is in different segment

• Provides branching from one code segment to another code segment

• CS and IP of destination address are specified directly in theinstruction.

Example:
Intersegment Indirect

• Destination lies in different segment

• Destination location is passed to the instruction indirectly.

Example: JMP [2000H];

• Jump to an address in the other segment specified at effective address 2000H

in DS
Intrasegment Direct

• Destination lies in same segment

• Displacement is computed using the content of the IP Intrasegment Indirect

• Destination lies in same segment

• Destination location is passed to the instruction indirectly.

• Branch address is found as the content of a register

Example