Sequential Synchronous Circuit Analysis

 General Model
• Current State at time (t) is stored in an array of flip-flops.
• Next State at time (t+1) is a Boolean function of State and
Inputs.
• Outputs at time (t) are a Boolean function of State(t) and
(Mealy) of Inputs (t).

Inputs Outputs
Combina-
tional
Storage Logic
Elements
Next
State State

CLK
 Example 1: Analysis

 Input: x(t)
 Output: y(t) x
D Q A

 State: (A(t), B(t)) Next State

C Q A

 What is the Output

Function?
D Q B

y(t) = x(t)(B(t) + A(t)) CP C Q' B

 What is the Next State y

Function? Output

A(t+1) = A(t)x(t) + B(t)x(t)

B(t+1) = A(t)x(t)
State Table Characteristics

 State table – a multiple variable table with the

following four sections:
• Present State – the values of the state variables for
each allowed state.
• Input – the input combinations allowed.
• Next-state – the value of the state at time (t+1) based
on the present state and the input.
• Output – the value of the output as a function of the
present state and (Mealy) the input.
 From the viewpoint of a truth table:
• the inputs are Input, Present State
• and the outputs are Output, Next State
Example 1: Alternate State Table

The time sequence of inputs,

A(t+1) = A(t) x(t) + B(t) x(t)
outputs, and flip-flop states can
B(t+1) = A(t) x(t) be enumerated in a state table
y(t) = x(t) (B(t) + A(t)) (sometimes called transition
table).
A+ = A x + B x
B+ = A x
y = x (B + A)
 x
D Q A

Example 1 Next State

C Q A

 Where in time are inputs, outputs and states defined?

D Q B

A+ = A x + B x CP C Q' B
y = x (B + A)
B+ = A x
y

Output
Functional Simulation
0.0 53ns
- Fig.
106ns
4-18159ns
Mano &212ns
Kime 265ns 318ns 371ns 424ns 477ns 530ns

Reset
l RESET..........

l CLOCK..........

Clock
l X..............

l NA.............

l
X
NB.............

A..............

Next A
l

l
B..............

Y..............

Next B
l t t+1 t+2 t+3
i

A
B
Y
State Diagrams

 The sequential circuit function can be represented in

graphical form as a state diagram with the following
components:
• A circle with the state name in it for each state
• A directed arc from the Present State to the Next State for
each state transition
• A label on each directed arc with the Input values which causes
the state transition, and
• A label:
 On each circle with the output value produced:
Moore type
or
 On each directed arc with the output value produced:
Mealy type.
Example 1: State Diagram

 Diagram gets
confusing for 0/1
0/0 1/0
large circuits
 For small circuits, AB
usually easier to 00 10
understand than
the state table 0/1

1/0 0/1 1/0

A+ = A x + B x
B+ = A x
y = x (B + A) 01 11
1/0

1/0 : means input x = 1

output y = 0

Mealy
Analysis with JK Flip-Flops

JA = B KA = B x
JB = x KB = Ax + Ax = A x

8
Moore
 Analysis with JK Flip-Flop
 The circuit can be specified by the flip-flop input equations:
JA = B KA = B x
JB = x KB = Ax + Ax = A x

9
Analysis with JK Flip-Flops

JA = B KA = B x
A+ = JA + KA
B+ = JB + KB JB = x KB = Ax + Ax = A x

 Substituting the values of JA and KA from the input equations,

we obtain the state equation for A:
A = BA + (Bx)A = AB + AB +Ax
 The state equation provides the bit values for the column under
next state of A in the state table. Similarly, the state equation
for flip-flop B can be derived from the characteristic equation by
substituting the values of JB and KB:

B = xB + (A x)B = Bx + ABx + ABx

10
Analysis with JK Flip-Flops
 The state diagram of the sequential circuit is:
A = BA + (Bx)A = AB + AB +Ax

B = xB + (A x)B = Bx + ABx + ABx

11

Moore
Analysis With T Flip-Flops
 Characteristic equation:

Q=T Q

TA = B x
TB = x
y=AB
12

Moore
 Analysis With T Flip-Flops
 Consider the previous sequential circuit. It has two flip-flops A
and B, one input x, and one output y. It can be described
algebraically by two input equations and an output equation:

TA = B x
TB = x
y=AB

A=(Bx)A+(Bx)A
=AB+Ax+ABx
B=xB
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Analysis With T Flip-Flops
 Characteristic equation:

Q(t + 1) = T Q
00/0 : means state is 00
and output is 0

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Sequential Circuit Analysis

 Initialization: reset to (0, 0, 0)

A
 Equations: D Q Z

A=BC C RQ

B=BC+BC D Q
B

C=AC C RQ

C
D Q

Z=A Clock C RQ
Reset

Moore
Example 2: State Table

A (t)
BC A’ B’ C’ Z
(t+1)
0 0 0 0 0 1 0
0 0 1 0 1 0 0
A=BC
0 1 0 0 1 1 0
B=BC+BC
C=AC 0 1 1 1 00 0
1 0 0 000 1
Z=A 1 0 1 010 1
1 1 0 010 1
1 1 1 100 1
Example 2: State Diagram

Reset ABC
000

111 100 001

011 010 101

 What is the function of

the circuit? 110
 Which states are used?
Moore
Analysis with D Flip-Flop

 The circuit we want to analyze is described by the input

equation
DA = A x y

 The DA symbol implies a D flip-flop with output A. The x and

y variables are the inputs to the circuit. No output
equations are given, so the output is implied to come from
the output of the flip-flop.
Moore
Analysis with D Flip-Flop
 The binary numbers under A x y are listed from 000 through 111.
The next state values are obtained from the state equation
DA = A x y
 The state diagram consists of two circles-one for each state
Equivalent State Definitions

 Two states are equivalent if their response for each

possible input sequence is an identical output
sequence.

 Alternatively, two states are equivalent if their

outputs produced for each input symbol is identical
and their next states for each input symbol are the
same or equivalent.

 Two states that are not equivalent are distinguishable

Equivalent State Example

0 1/0
 For states S3 and S2,
• the output for input S0/0 S1
0 is 1 and input 1 is 0, 0/1
and
• the next state for input 0/1
0/1 1/0
0 is S0 and for input
1 is S2.
• states S3 and S2 are
S2
1/0
S3
equivalent.
1/0
 0 1/0

Equivalent State Example S0/0

0/1
S1

0/1
0/1 1/0

0/0 1/0 S2
1/0
S3
1/0

S0 S1
0/1
 Replacing S3 and S2
by a single state gives
state diagram: 0/1 1/0

 Examining the new diagram, S2

states S1 and S2 are equivalent since
• their outputs for input 1/0
0 is 1 and input 1 is 0,
and
• their next state for input
0 is S0 and for input 0/0
1 is S2, 1/0

S0 S1
 Replacing S1 and S2 by a 0/1
single state gives state
diagram:
1/0
Moore and Mealy Models

 Sequential Circuits or Sequential Machines are also called

Finite State Machines (FSMs).

 Two formal models exist:

 Moore Model  Mealy Model

• Named after E.F. Moore • Named after G. H. Mealy
• Outputs are a function • Outputs are a function of
ONLY of states inputs AND states
• Usually specified on the
• Usually specified on the
state transition arcs.
states.
Moore and Mealy Example Diagrams & Tables

 Mealy Model State Diagram

maps inputs and state to outputs
Present Next State Output x=1/o=0
State x=0 x=1 x=0 x=1 x=0/o=0
0 1
0 0 1 0 0
1 0 1 0 1 x=0/o=0 x=1/o=1
 Moore Model State Diagram x=0
maps states to outputs
0/0
Present Next State Output x=0
State x=0 x=1
0 0 1 0 x=1 x=1
x=0
1 0 2 0
2 0 2 1 1/0 2/1
x=1
Mixed Moore and Mealy Outputs

 In real designs, some outputs may be Moore type

and other outputs may be Mealy type.

 Example: Figure can be modified to illustrate this

• State 00: Moore 0 1
• States 01, 10,
and 11: Mealy 00/0 01
0/1

0/1
0/1 1/0
 This simplifies output
specification
1/0
10 11
1/0
State Reduction

Example : next state

state a a b c d e f f g f ga

input 0 1 0 1 0 1 10 10 0
output 0 0 0 0 0 1 1 0 1 0 0

t0 t1 t2 t3 …

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 State Reduction
 We now proceed to reduce the number of states for this example.
First, we need the state table; it is more convenient to apply
procedures for state reduction using a table rather than a
diagram. The state table of the circuit is listed in Table 5-6 and is
obtained directly from the state diagram.
 State Reduction
 States g and e are two such states: they both go to states a and f
and have outputs of 0 and 1 for x=0 and x=1, respectively. Therefore,
states g and e are equivalent and one of these states can be
removed. The procedure of removing a state and replacing it by its
equivalent is demonstrated in Table 5-7. The row with present g is
removed and state g is replaced by state e each time it occurs in the
next-state columns.

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 State Reduction
 Present state f now has next states e and f and outputs
0 and 1 for x=0 and x=1, respectively. The same next
states and outputs appear in the row with present state
d. Therefore, states f and d are equivalent and state f
can be removed and replaced by d. The final reduced
table is shown in Table 5-8. The state diagram for the
reduced table consists of only five states.

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State Reduction
Example :

state a a b c d e f f g f ga (e, g)  e
input 0 1 0 1 0 1 10 10 0
(d, f)  d
output 0 0 0 0 0 1 1 0 1 0 0

state a a b c d e dd e d ea
output 0 0 0 0 0 1 1 0 1 0 0

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State Assignment

pseudo

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