STM8S

Flash &
Control System May 2009

STM8S Technical Training

STM8S Memory main features (1/2)

• Up to 128Kbyte Program memory (flash) based on

EEPROM technology
• Up to 2K Data EEPROM memory
• Read While Write capability
• Write protection with Memory Access Security
System (MASS keys)
• Programmable write protected User Boot Code
area (UBC)
• Read Out Protection (ROP)

4
STM8S Memory main features (2/2)

• Byte, word and block programming capability

• 6ms programming time (3ms erase + 3ms write)
• In Circuit Programming (ICP) and In Application
Programming (IAP) capability
• One Interrupt vector dedicated to end of
programming and attempt to write in protected area
• Configurable memory state in low power modes
(Halt and Active Halt)
• Boot ROM embedding ST proprietary boot loader
code

5
 STM8S Family memory mapping
• The program memory always RAM (up to 6K) 00 0000h
starts at address 00 8000h
– End is determined by the Stack (up to 1K)
memory size (02 7FFFh for
128K). 00 4000h
Data E2PROM (up to 2K)
– Interrupt vectors are located at
the beginning of this memory Option bytes 00 4800h
area. 00 5000h
– Programmable User Boot Code Peripheral registers
area includes the It vectors
(from 1K up to 128K). Boot Vector 00 6000h
• The RAM starts from 00 0000h Boot ROM (2K)
– Up to 1KBytes Stack is located
00 8000h
at the end of the available RAM. User reset and IT Vectors
• The Data EEPROM starts from UBC area
00 4000h. Program memory
– The option bytes are located (up to 128K)
after the available data EEP

6
Memory organization granularities
Program 128 bytes
Memory Matrix
128 bytes
Data 128 bytes
Memory
Block
32 words = 128 bytes or 16 words = 64 bytes

byte byte byte byte ECC

Word
Word = 4 Bytes + 6 bits ECC

EEPROM access time allows to run the device up to 16

MHz at least without adding wait state.
For higher frequency (i.e. HSE@24Mhz), one wait state
is necessary.

7
 STM8S family memory ranges

• Low density
– From 8 Kbytes of Flash Program  128 pages of 64 bytes
– 640 bytes of Data EEPROM  10 pages of 64 bytes
• Medium density
– From 16 to 32 Kbytes of Flash Program  64 pages of 512 bytes
– 1 Kbytes of Data EEPROM  2 pages of 512 bytes
• High density
– From 32 to 128 Kbytes of Flash Program  256 pages of 512 bytes
– Up to 2 Kbytes of Data EEPROM  4 pages of 512 bytes

• For low density 1 page = 1 block

• For medium & high density 1 page = 4 blocks

8
 Memory Access Security System (MASS)
(Unlock mechanism)

• In order to prevent any unwanted write access to the Program memory, to the
Data EEPROM and to the Option bytes, the whole NVM memory is Write
protected by default after a device reset.
• The memory lock must be removed by software before any programming
operation loading in the right order 2 MASS keys in a given Flash register.

Unlock register MASS Keys

Program FLASH_PUKR 0x56 (1°)

Memory 0xAE (2°)
Data Memory FLASH_DUKR 0xAE (1°)
&Option 0x56 (2°)

After programming it is safer to re-protect the given memory area by

clearing PUL or DUL bit in the Flash status register FLASH_IAPSR.

9
Memory dedicated option bytes:
Read-out protection
• There are two option bytes dedicated to memory protection: the
Read-out protection (ROP) and the UBC protection

• When the ROP is set, it is impossible to read back the memory

– Only embedded code can read the Program and Data
memories
– ICP/SWIM will not allow to read the memory, only the option
byte can be read
– Programming tools cannot read the memory

• It is possible to remove the ROP in ICP/SWIM only

– But when it is removed, the complete memory is erased
– As a consequence we cannot proceed with Memory FAR

ROP provides a reasonably good level of piracy protection.

10
 Memory dedicated option bytes:
UBC protection

• The goal of the UBC protection is to Page 00 8000h

prevents a part of the memory from LD/MHD Reset ad IT vectors
P
being written (especially in IAP), 0/0-1 UBC[7:0]=01 r
o
protecting critical application routine t
from unwanted modifications. 1/2 UBC[7:0]=02
e
c
• When the UBC protection is active, the t
2/3 UBC[7:0]=03 e
protected area always include the d
reset and interrupts vectors .
• In order to activate the protection, .
UBC[7:0] option byte and its .
complement NUBC[7:0] must be set Program
with the number of pages you want to memory
protect: this UBC area is not
unlocked by the MASS keys.
• To unprotect the “UBC area”, the
option byte needs to be cleared (not
available in IAP)

11
Memory programming methods

There are three methods to program the device memory:

Use a programming tool with socket:

–The unsoldered part is placed in the programmer socket.
Use In Circuit Programming (ICP):
SWIM
– The device is soldered on the application board
– The programming tool is connected to the user application with the
SWIM wires.
Use the Boot Loader:
ST Boot
– It allows the customer to store the application into the internal EEPROM
Loader
using one of device serial interface (UART, LIN, CAN).
Use the In Application Programming (IAP):
– The device is soldered on the application board and the application is
running.
IAP – The application can reprogram itself receiving the new firmware through
any available communication protocol.
– The IAP code must have been programmed using one of the previous
methods.

12
In Circuit Programming

• ICP is using the SWIM (Single Wire Interface Module)

– The SWIM protocol uses an hardware communication peripheral

– It uses only one I/O that can also be used as PD1 GPIO pin.
• By default the pin is in SWIM mode after reset
• Switch to PD1 is done by software with a bit in the Global Configuration
Register (CFG_GCR)
• It is generally good to use a jumper on the application board.

I/O for application STM8

SWIM
PIN
SWIM interface for tools
Jumper selection
for debug
purpose

13
 SWIM connection
Supply

STM8 VDD
NRST
1
2
3
4

PD1
SWIM VDD

GND
4 3 2 1

SWIM connector
Dedicated connector with only 4-pins : 1
2

SWIM, Reset, GND, VDD (for monitoring) 3

4

For further information: http://www.erni.com

14
ST Boot Loader
• The Boot Loader is stored into the internal 2 Kbytes Boot ROM memory.

• This program uses USART (set as a normal UART), CAN or LIN peripherals
(handled in polling mode) to download/update into Program memory, Data
EEPROM and Option byte area respectively the code (including vector
table), the data and the option bytes, thus using ST proprietary protocol.

• According to the content of the Reset Vector location (0x8000) the host can
decide to re-program or not the EEPROM by checking two option bytes, as
showed in the following table:

EEPROM Reset Opt_byte Opt_byte Actual EEPROM status 

vector @0x8000 @ 0x487E @0x487F Action
1°
XXh ≠(82h or ACh) XXh XXh EE virgin  jump to BL
2° EE already written  jump to
XXh=(82h or ACh) 55h AAh
BL
3°
XXh=(82h or ACh) XXh ≠ 55h XXh ≠ AAh EE already written  jump to
EEPROM reset
15
In Application Programming (1)

• In Application Programming
– In case of in application programming, there is an user boot sector
containing a boot program that will reprogram part of the
application itself.
– A new version of the firmware to be updated is received by the boot
program using any possible protocol, usually a serial
communication port (USART, SPI, I2C, CAN, LIN ….).
• The User Boot Code area feature answers to the IAP
needs:
– For the IAP to be safe, the boot sector must always be write
protected.
– In the event of a power failure, the boot program will be able to
restart the firmware update from the beginning.
– The boot sector contains the Reset vector which points into the boot
program on the reset routine.
– The boot program contains the update communication driver.
16
In Application Programming (2)

Reset vector to the Vectors

UBC area Reset routine Write protected
UBC sector area
For 128k
Firmware Communication Programming Min = 1 kbyte
driver routines
update Granularity = 0.5k

Area to be
Application updated
firmware

17
Byte programming
• Byte programming is done with a simple load instruction at the target
address.
• If the write instruction is run from Program memory to itself, the core is
stalled during the whole programming phase, otherwise if it is fetched from
RAM the program can do something else (but no access to the program
memory).
• The interrupt remain pending until the operation is not completed (core is
stalled on IT when code fetched from RAM).
• If the write instruction is run from Program memory to Data EEPROM the
Read While Write (RWW) capability allows to continue the program without
constraints.
– RWW is NOT available for low density memory
• Control flags can be used to check the end of programming status.
• The programming lasts 3ms if the “word” was empty (no erase phase
needed) or 6ms if not.
• To erase a location, simply write 00h.
Don’t forget to unprotect the memory with MASS keys

18
Word programming
• Word programming allows the user to program 4 bytes with only one
programming cycle which minimizes the programming time.
• The mechanism is similar to byte programming but the activation is
done with dedicated bit and consecutive loads of 4 bytes in given
word.

• The Read While Write (RWW) capability is available for medium

and high density memories, NOT for low density memory.

• Control flags can be used to check the end of programming status.

• Word programming lasts always 6ms (erase + write times).

Don’t forget to unprotect the memory with MASS keys

19
Block programming (1)

• The block programming feature is available for both the Program

memory and the Data EEPROM.
• Block programming allows the user to program of 128 bytes in one
programming cycle; the gain of time is very significant.
• There are three block programming possible operations activated by
dedicated control bits:
– Standard block programming: the block is first erased then programmed.
– Fast block programming: the block is not erased before programming.
This mode has to be used only when the block is blank before operation;
else the content is not guaranteed.
– Block erase: The full block is erased. In this case it is enough to write ‘0’ in
the first word of the block (4 bytes).

Don’t forget to unprotect the memory with MASS keys

20
Block programming (2)
• For block programming (Standard or fast block programming), the 128 data
bytes have to be sequentially loaded. The actual programming phase starts
automatically when the last byte is latched. The initial address must be the
first block address.
• Attention! The data loading operation for block writing has to be
performed from the RAM even when addressing the Data EEPROM.
• In case of Program memory programming after programming finishing only the
soft can return executing in Program memory.
• In case of Data EEPROM programming the soft can return into Program
memory as soon as dedicated flag HVOFF gives the green light when
programming HV starts and thus to perform other tasks. It means that the
RWW capability is available during the actual programming phase after the
data loading.
• The RWW is NOT available for low density memory

Don’t forget to unprotect the memory with MASS keys

21
Option byte programming

• The option byte programming is very similar to

byte programming to Data EEPROM.
• But there is an additional control bit to allow write
access to option bytes.

• It is possible to re-program the option bytes in

IAP or user mode, but the new option byte value
is taken into account after next reset only.

22
Memory Programming
Nber of Programming Programming Fast Programming
Core
Bytes from: to: Programming Time

Program Mem Program Mem Stalled

~3ms if the
Running but stalled if Yes memory were
Byte 1 RAM Program Mem
interrupt occurs empty or 6ms
(Auto)
RAM Data EEP Running otherwise
or Prog Mem or Opt Byte No constraints: RWW (1)
Program Mem Program Mem Stalled
Running but stalled if
RAM Program Mem
Word 4 interrupt occurs No ~6ms
RAM Data EEP Running
or Prog Mem or Opt Byte No constraints: RWW (1)
Program Mem Program Mem Not possible
Running but stalled if
RAM Program Mem ~3ms in Fast
interrupt occurs
Yes mode only if the
Block 128 RAM (Ctrl memory were
or Prog Mem Bit) empty or 6ms in
Data EEP Running
Data loading standard mode
or Opt Byte No constraints: RWW (1)
from RAM
ONLY

(1) In case of low density memory the RWW is not available. The core is stalled during
programming from Program memory to Data EEP or Opt Bytes

23
References

• PM0051 STM8 Flash Programming Manual

• UM0560 STM8 Bootloader User Manual
• UM0462 STM32 and STM8 Flash Loader
Demonstrator
• AN2659 STM8 in-application programming
(IAP)
using a customized user-bootloader

24
Quiz

• What is the use of IAP?

– In Application Programming: possibility for the user to update part of
firmware.
• How works the MASS?
– Memory Access Security System: 2 keys to unlock the memory which is
write protected by default.
• What is the specificity of the UBC?
– User Boot Code: programmable area which is write protected in IAP (no
effect of MASS keys)
• What is guaranteed thanks to the ROP?
– Read-Out Protection: memory is totally protected in ICP/SWIM mode
(R/W impossible) but ROP byte “reset” which does global erase.
• Which connection is needed on the application in order to do In
Circuit Programming ?
– SWIM connection only
• Is it possible to re-program option bytes in user mode?
– Yes if ROP not set : the new value is valid after next reset.

25
STM8S CLOCK CONTROLLER

26
Features

• 4 clock sources:
– HSE crystal: 1-24 MHz High Speed External crystal
– HSE user-ext: Up to 24 MHz High Speed user-external clock
– HSI RC: 16 MHz High Speed Internal RC oscillator
– LSI RC: 128 kHz Low Speed Internal RC

• Efficient clock switching mechanism

• Clock Security System (CSS)
• Peripheral Clock Gating (PCG)
• Configurable Clock Output (CCO)

• EMS-hardened clock configuration registers which values

have to be complemented otherwise in case of corruption a
reset is generated.

27
Block Diagram (1/2)
Reset configuration
CKM[7:0]

HSE Ext.
C PU DIV [2:0 ]
fH SE
OSC IN
HS E OSC
/1
1 -24 M H z to CAN, AWU
OSC OUT /2
EXTCLK OPT BIT
/4
fMA STER /8 f C PU
Master
Clock /16
CSS HS ID IV[1: 0] Switch /32
/64
/8 /12 8
H SI R C fH SI /4 fHSID IV
16 M Hz /2
to CPU and
/1 Window Watchdog

fLSI
LSI RC
12 8 kH z

to AWU to peripherals

28
Block Diagram (1/2)

Peripheral Clock
Enable
to AWU

fLSI to Timers

PRSC(1:0) OPT BITS

fMASTER USART
LINUART
fHSE 128 kHz Independent Watchdog Peripheral Clock I2C
SPI
Enable
ADC
CKAWUSEL OPT BIT

CCO SEL[3:0]
Peripheral Clock
CANDIV[2:0]
Enable
/1, /2 ../8 to CAN fH S I
fH S I D IV
fH S E
fL SI
fM A S TE R
CCO = PE0 or PD0 pin fC P U
fC P U / 2
PE0 default configuration fC P U / 4
fC P U / 8
PD0 selected by option bit fC P U / 16
fC P U / 32
fC P U / 64

29
Clock Sources

• All clock sources can be used as CPU clock source

• From 1 to 24MHz external crystal/ceramic resonator
– HSE OSCIN (PA1) and HSE OSCOUT (PA2)
– From 3 V to 5.5 V supplied
– -40 to 125 °C
– 45-55 % duty cycle
– < 2 ms max startup time @ 24 MHz
– Bypass with HSE Ext. done by option bit
• 16MHz HSI RC factory trimmed
– < 2 µs max startup time
– 1.8 V internally supplied, 1.2 µA max in Halt
– ±1 % accuracy at 25 °C
– ±5 % for the whole voltage and temp. range (3–5.5 V; -40 to 150 °C)
– Further user trimming possible (8 steps to keep precision of 1.5 %)
• 128KHz LSI RC factory trimmed
– 1.8 V supplied, 0.3 µA max in Halt, ±2.5 % accuracy at 25 °C
– ±12.5 % accuracy over full voltage and temp. range

30
Master Clock Switching

• The Clock Controller offers a fast and easy master clock

(fMASTER) switch feature with one dedicated interrupt (SWIE)
and its associated flag (SWIF)

• There are 2 clock switch methods:

– Automatic: switches to the clock source as soon as it is ready
• SWEN=1, new clock master in CLK_SWR
– Manual: allows to control the exact time of the clock switch
• New clock in CLK_SWR, wait clock ready, SWEN=1

• After the switch, the previous clock has to be switched OFF

manually if required for low power

31
CSS: Clock Security System

• Protection against HSE crystal clock source failure

• When a failure occurs:

– Automatic connection of fMASTER to the auxiliary clock source (HSI/8)
• HSI prescaler can then be modified by the user if needed
– HSE is switched off
• For safety reason, once enabled this CSS feature cannot be
disabled anymore until next reset

• A dedicated interrupt associated to the CSS detection event

and its flag are available (CSSDIE with CSSD flag)

32
PCG: Peripheral clock gating

• PCG allows to cut the clock feeding to selected peripherals

in order to decrease the power consumption.

• Peripherals which can be gated:

– Enabled by default
– USART, LINUART, SPI, I2C, TIMERS, ADC
– CAN, AWU (only clock system to register, not counter clock)

• To disable or enable the clock for each peripheral:

– Reset/Set the corresponding PCKEN bit in CLK_PCKENR register
– Then set the peripheral enable bit in the corresponding control
register

33
CCO: Configurable Clock Output

• Steps to configure the required CCO:

– Configure CCO output push pull (set the related bit in CR1)
– Select clock to output through CLK_CCOR register
– Enable CCO feature (CCOEN bit)

• The clock source selected in the CCO register will be

automatically switched ON if not done previously by the
user

• in order to know if the selected clock signal is output: check

CCORDY bit

• If the CCO feature is switched OFF, the CCO pin has to be

re-configured in input floating (default I/O state) by the user

34
Quiz

• What is the HSI RC value ?

– 16MHz
• What is clock frequency at start-up?
– HSI/8
• What are the master clock switching modes ?
– Automatic and manual
• What is the auxiliary clock used by the CSS feature ?
– HSI/8 (the clock after reset)
• Can HSI be output on the CCO pin when Fmaster is using
HSE ?
– Yes
• Which are the two clock controller interrupts?
– Clock switch (SWIE - SWIF) and CSS Detection (CSSDIE - CSSD)

35
STM8S AUTO WAKE-UP (AWU) and BEEPER

36
Features

• AWU function with Low Speed clock

– The AWU has been designed to implement the Active Halt
low power mode.
– Dedicated AWU interrupt vector

• BEEPER function
– 1 kHz, 2 kHz or 4 kHz output signal frequencies

• LSI frequency measurement

– It is possible thanks to LSI connection to one internal timer input
capture. This operation allows to define precise time base for
AWU and to make a calibration to keep Beeper frequency at 1K,
2K or 4K.

37
AWU Block Diagram

CKAWUSEL
PRESC[1:0] OPTION bit
OPTION bits
HSE clock
(4 - 24 MHz)
Prescaler MSR
~ 128 kHz LS clock to Timer Input Capture
LSI RC (for measurement)
128 kHz

APR[5:0]

6-BIT PROG
COUNTER

AWUTB[3:0]
15 time bases
AWU COUNTERS AWU Interrupt

AWUEN & HALT/WAIT

38
AWU description
• AWU operation
1. LSI measurement if needed (see dedicated slide)
2. Find the AWUTB[3:0] and APR[5:0] according to targeted wake-up interval
(see dedicated slide)
3. AWUEN=1 to enable the AWU interrupt and LS clock source to the
counters (if LSI RC is selected it will start automatically)
4. HALT
• In Halt mode (after Halt instruction):
– the counters start to run when entering this mode
– the AWU interrupt wakes-up the CPU at the regular programmed intervals :
This is the Active Halt mode

• Power consumption reduction: AWUTB[3:0] = “0000”

– Puts AWU in stand-by: time-base OFF (default value)
• APR[5:0] different from 3Fh (reset setting) to get counter running

39
Time base selection (1/3)
• The Time base selection is done with the determination of 2
parameters:
– APR[5:0], it gives the prescaler division factor APRDIV
– AWUTB[3:0], it gives the counter output rank
The chosen Time base depends on precise LSI frequency.
We propose to define first 15 non overlapped ranges of intervals
according to counter output rank.
– 0001 > 2/fLS – 64/fLS, APRDIV moving from 2 to 64
– 0010 > 2x32/fLS - 2x2x32/fLS, APRDIV moving from 32 to 64 (std)
– 0011 > 2x64/fLS - 2x2x64/fLS, APRDIV moving from 32 to 64 (std)
– …
– 1101 > 211x64/fLS - 211x128/fLS, APRDIV moving from 32 to 64 (std)
– 1110 > 211x130/fLS - 211x320/fLS, APRDIV moving from 26 to 64
– 1111 > 211x330/fLS - 212x960/fLS, APRDIV moving from 11 to 64

Important to measure LSI to get precise interval ranges

40
Time base selection (2/3)

• The targeted Time base is in one of the above ranges.

– It gives the TB value
Then the choice of APRDIV is the result of one of the
equations:
– Interval = 2nxAPRDIV/fLS where n depends on the TB value
– Interval = 5x211xAPRDIV/fLS
– Interval = 30x211xAPRDIV/fLS
The result is not necessarily an integer. It means that
the targeted interval is reached with an error.
The maximum error is half of the step in a given range;
it is relatively more important for lowest targeted
values.
For standard range the maximum error is
– 0.5xstep/min range value -> 1/64 = 1.5625%
41
Time base selection (3/3)

• Example with fLS=128KHz

• Target time interval is 3s

The appropriate interval range is:

– 1110 : 211x130/fLS - 211x320/fLS = 2.08s – 5.12s

3s = 5x211xAPRDIV/fLS => APRDIV = 3xfLS/5x211 = 37.5

The reached time interval is :

– 5x211x37/fLSE = 2.96s (or 5x211x38/fLSE = 3.04s)
– This is not precisely 3s
– Error = (3-2.96)/3 = 1.33%

42
Beeper Block Diagram

LS Clock 5-BIT BEEPER PROG ~8 kHz 3-BIT 1 kHz, 2 kHz, 4 kHz

COUNTER COUNTER
BEEP pin
BEEPEN

BEEP pin = PD4 when AFR7 option bit is set to 1

43
Beeper description

• Beeper operation
1. LSI measurement and calibration if needed (see
dedicated slide)
2. Define BEEPDIV[4:0] values to get right BEEPDIV
division factor
3. Choice of BEEPSEL to select respectively:
fLS/(8xBEEPDIV) , fLS/(4xBEEPDIV) and fLS/(2xBEEPDIV)
4. BEEPEN =1

• BEEPDIV[4:0] must be different from 1Fh (reset

setting) to get counter running.

44
LSI Calibration for Beeper

• The LSI frequency is around 128KHz

• If you still need to adjust it to provide more
accurate Beeper output at 1KHz, 2KHz or 4KHz
the procedure below must be followed:
• Calibration procedure
1. MSR=1 to connect LSI to Timer TIM3 input capture 1
2. Measure LSI frequency with TIM3
3. Write the calibration value BEEPDIV[4:0] as follows:
A and x being the integer and fractional part of fLSI/8 in
KHz the calibration value is:
– BEEPDIV[4:0] = A-2 when x is less than or equal to A/(1+2*A)
– BEEPDIV[4:0] = A-1 otherwise

45
Calibration (2/2)

• Example with fLSI = 115KHz:

fLSI/8 = 14.375KHz
-> A = 14
-> A/(1+2*A) = 0.483

-> x = 0.375
-> x is less than A/(1+2*A) therefore:
BEEPDIV[4:0] = A-2 = 12 = 0Ch

• The prescaler output frequency is

– 115/14 = 8.2KHz
• Clock is calibrated for Beeper at 1.025KHz, 2.05KHz or
4.1KHz
46
Quiz

• What are the clock sources used for AWU

operations ?
– LSI
– HSE prescalered
– Timer clock for LSI measurement
• What are the beeper output frequencies ?
– 1kHz, 2kHz or 4kHz
• What is the BEEPDIV[4:0] correct value when LSI
frequency is 128KHz ?
– Divider /8 = 16 BEEPDIV = 16-2 (because fractional part
is null) -> 0Eh

47
 STM8S POWER SUPPLY,
RESET AND VOLTAGE DETECTION

48
Power Supply Features

• There are 4 power supplies:

– VDD/VSS - Main power supply
– VDDIO/VSSIO - I/O ring power supply
– VDDA/VSSA - Analog functions
– VREF+/VREF- - ADC Reference
VCAP

VDD Main Voltage Regulator STM8 Digital

1.8V
RAM
Low Power Voltage Reg. FLASH

I/Os
VDDIO
Refer to HW getting started Application Note

49
Voltage Detectors

• 2 Voltage Detectors
– BOR to monitor main power supply
– Power On Reset with Power Down Capability
NRST
VDD/VDDIO
VDD

Vth+
Vth-

1V

BOR triggered by POR POR restarted by BOR

50
Reset Circuit Block Diagram

EXTERNAL
RESET
FILTER

POR/BOR
20us PULSE IWDG/WWDG/SW
GENERATOR SWIM
ILLEGAL OPCODE
EMS

51
External Reset

• External reset pin: NRST

– In practice a negative reset pulse larger than 300ns on
NRST pin generates an internal reset system.
– However NRST pin is also an open-drain output which
delivers a minimum pulse of 20µs controlled by internal
temporization.
– Therefore the observed reset pulse is 20µs minimum.
– There is an internal weak pull-up to maintain the reset
pin at 1 when reset is not forced. It avoids spurious reset.

52
Internal Reset sources (1/2)
• Power On Reset (POR):
– The POR is always active only during Power On (rising edge)
– Generate trigger to start LVD, then switched off

• BOR
– When voltage falls bellow level, generate trigger for POR

• SWIM reset
– A specific SWIM command generates a reset when sent.

• Illegal op-code reset

– In case of noise on the product corruption can lead to wrong op-code value
which is detected and generates a reset.

• Window Watchdog, Independent Watchdog and software resets.

– This 3 reset sources are directly controlled by software.

53
Internal Reset sources (2/2)

• EMS reset
– The most critical registers of the product are implemented with
their complement in such way any mismatch in the opposite values
on EMS disturbances leads to a reset:
• Copy of option byte registers,
– UBC Protection registers for instance
• Clock Controller switch registers,
– Clock master register
– Switch register

• Watchdogs, Illegal op-code and EMS reset ensure

product robustness allowing application to recover
normal operation.
• Related flags can be tested and cleared in RST_SR

54
STM8S versus ST7

• ST7 • STM8
– LVD – POR
+ Power-On Reset • Starts the system
+ Voltage Drop Reset
+ 3 thresholds – BOR
- Option byte switchable • Voltage Drop Reset
- When deactivated, no • Fixed Threshold
more POR • Active during RUN

– AVD
• Interrupt
• 3 thresholds
• Activated with LVD
• Option byte

55
Quiz

• What are the 8 internal reset sources?

– POR,IWDG,WWD, SW, SWIM, Illegal Opcode, EMS,
BOR
• What are the reset sources implemented for
robustness purpose?
– All of the above
• Which regulators are implemented?
– Main and Low Power Voltage Regulators

56
STM8S POWER MANAGEMENT

57
Generalities (1/2)

• In a silicon device there are two kind of consumption:

– Static power consumption
• Due to analog polarization and leakage
• It is negligible in RUN, but marginal for (Active) Halt
– Dynamic power consumption
• It depends on VDD, clock frequency and load capacitance
• Microcontroller consumption depends on:
– MCU size (number of gates)
– Design of analog features (linked to performances)
– VDD
– Clock frequency
– Number of active peripherals (analog and digital)
– Low power operating levels/modes

58
Generalities (2/2)

• Low consumption feature is more and more important:

– Application on battery with very long life time
– Minimization of the consumption contribution for global application
system
– Good for the environment

• The challenge is to provide low power consumption

keeping the system operating or able to reenter quickly
in operation.

• Performances are very important to minimize the time

the system is operating and therefore to maximize the
time in inactive low power levels.

59
Power management features

• Flexible clock speed choices through:

– Clock sources
– Various clock division choices

• Peripheral Clock Gating

• Peripheral deactivation

• Several low power modes:

– Wait, Fast Active Halt, Slow Active Halt, Halt
– Various consumption levels in each mode according to :
• Clock speed and clock gating for Wait
• Different voltage regulators for Fast/Slow Active Halt modes

60
Clock management

• Slowing the system clocks:

– Choice of the clock sources HSE, HSI, LSI with programmable
division factor for HSI
• Effective in both Run and Wait modes
– Choice of fMASTER division factor to generate CPU clock
• Possible in Run mode only (so called Slow Mode)
• fPERIPHERALS remains on full speed
• Peripheral clock gating:
– Give the possibility to switch-off by software the clock branch of non
used peripherals
• Effective in both Run and Wait modes
– It doesn’t mean the peripheral is off…
• Each clock speed reduction or clock switch-off
condition represent a different low power level.
61
Peripheral switch-off

• Each single peripheral can be deactivated to

reduce the power consumption
– Except the watchdogs and the IO ports

• It is true for both analog and digital peripherals

62
Low power modes

• The four Low power modes main characteristics:

Modes / Main Wake-up

Oscillators CPU Peripherals
consumption Regulator event

Wait ON (if no clk Int/ext ITs,

ON ON OFF
- gating) BOR, reset
Fast Active AWU and
Halt OFF, except AWU, ext ITs,
ON OFF IWDG if
LSI/HSE BOR, reset
-- activated
Slow Active AWU and
Halt OFF, except AWU, ext ITs,
OFF OFF IWDG if
LSI/HSE BOR, reset
--- activated
Halt external ITs,
OFF OFF OFF OFF
---- BOR, reset

63
Low power modes (1/3)

• Wait mode

– The MCU enters this mode when Wait For Interrupt instruction is
executed.

– CPU clock are stopped.

– Registers and RAM contents are preserved.

– The clock configuration defined before to enter in this mode remains

unchanged.

– The clock speed slow-down changing the clock source and PCG use are
both means to reduce further the consumption.

– Therefore there are again different low power levels for this low power Wait
mode.

64
Low power modes (2/3)
• Active Halt modes
– The MCU enters this mode when Halt instruction is executed.
• And if AWU and IWD are activated before.

– All clocks are stopped; the CPU and all the peripherals are disable by definition.
• Except LSI or HSE divided

– Digital part of MCU consumes almost no power but leakages.

• Except running AWU and IWD counters

– Registers and RAM contents are preserved.

– By default the clock configuration defined before to enter in this mode remains
unchanged.

• Slow Active Halt versus Fast Active Halt:

– When “Slow Active Halt” bit = “1”, Low Power Regulator is used instead of
Main Power Regulator
– On the contrary, Main Voltage Regulator remains active in Fast Active Halt to
ensure fast startup (“Slow Active Halt” bit = “0”)

65
Low power modes (3/3)

• Halt mode
– The MCU enters this mode when Halt instruction is executed.
• And if IWD and AWU are not activated

– All clocks are stopped; the CPU and all the peripherals are disabled
by definition; Main Regulator is switched off

– Digital part of MCU consumes almost no power but leakages.

– Registers and RAM contents are preserved.

– By default the clock configuration defined before to enter in this

mode remains unchanged.

66
Additional power controls (1/3)

• Fast clock wake-up feature:

– In the clock controller there is the possibility thanks to the FHW bit in
the Internal Clock Register (CLK_ICKR) to force the HSI clock when
MCU returns from Halt or Active Halt.
– HSI clock because the HSI RC oscillator start-up time is very short
compare to HSE Crystal oscillator
– This possibility is important to optimize the time during which
the MCU is active between two low power periods. It is in
complement of pure CPU performance.

• IRET behaviour configuration (CFG_GCR.AL)

– Retrieve context and return to main (default, AL=0)
– OR return back to WFI/HALT (AL=1)
• Context saved on first IT only
• Context restored when AL is reset in IT before IRET

67
Additional power controls (2/3)

• Fast Flash wake-up from Halt mode

– In Halt mode, by default the Flash is in Power-down mode with

negligible current leakages to ensure a very low Halt consumption.

– But the Flash wake-up time is long.

– However if the HALT bit in Flash control register 1 (FLASH_CR1) is

set the Flash switches to Operating mode when MCU enters Halt
mode.
• It ensures a fast wake-up time.

– But the Halt consumption increases up to a few µAmps.

68
Additional power controls (3/3)

• Very low Flash consumption in Active Halt mode

– In Active Halt mode, by default the Flash remains in Operating

mode to ensure the best wake-up time.

– But the Flash consumption is not negligible around a few µAmps.

– However if the AHALT bit in Flash control register 1 (FLASH_CR1)

is set the Flash switches to Power-down mode when MCU enters
Active Halt mode.
• It ensures a negligible Flash consumption.

– But the Active Halt wake-up time increases.

69
Quiz

• What are the low power modes?

– Run, (Slow), Wait, Active Halt, Halt
• How many low power levels are available?
– Many of them
• What are the five main parameters influencing
silicon device power consumption?
– VDD, Frequency, Load Capacitance, Leakeges, Analog
Polarization, ...
• What are the possible trigger events to wake-up
from Active Halt?
– AWU, External Interrupt, BOR, POR

70
Window Watchdog (WWDG)

71
 WWDG features
• Window Watchdog can be activated by Option byte
WWDG
WWDG_WR
or by software (setting WDGA) Reset

- W W W W W W W
• Configurable time-window, can be programmed to comparator 6 5 4 3 2 1 0
= 1 when
detect abnormally early or late application behavior T6:0 > W6:0

CM
P
• Conditional reset Write WWDG_CR

– Reset when the down counter value becomes less

WD T6 T5 T4 T3 T2 T1 T0
than 40h (T6=0) WWDG_CR 6-Bit Down Counter
GA
– Reset if the down counter is reloaded outside the
time-window Fcpu Divider
by 12288

• To prevent WWDG reset: write T[6:0] bits at regular T[6:0] CNT down counter

intervals while the counter value is lower than the

time-window value (W[6:0]) W[6:0]

• WWDG reset flag (in RST_STAT) to inform when a 3Fh

WWDG reset has occured

• Min-max timeout value @16MHz : Refresh
not allowed
Refresh
Window
time

0.768ms/49.152ms by step of 0.768ms T6 bit

Reset

Best suited to applications which require the watchdog to

react within an accurate timing window

72
Independent Watchdog (IWDG)

73
 IWDG features

• Selectable HW/SW start through option byte

• Advanced security features:
– IWDG clocked by its own dedicated low-
Prescaler Reload Key
speed clock (LSI) and thus stays active Register Register Register
even if the main clock fails
– Once enabled the IWDG can’t be disabled 8-bit
(LSI can’t be disabled too) reload value
LSI
– Safe Reload Sequence (by key) (128KHz)
8-bit 8-bit IWDG
/2 PRESCALER down counter Reset
– IWDG is still functional all low power
modes except in halt (LSI stopped)
• To prevent IWDG reset: write IWDG_KR
with AAh key value at regular intervals
before the counter reaches 0 Best suited to applications which require the
watchdog to run as a totally independent
• IWDG reset flag (in RST_STAT) to inform process outside the main application
when a IWDG reset occurs
• Min-max timeout value @64kHz (LSI/2):
62.5us / 1s

74
Quiz
• How the WWDG reset is refreshed ?
– By writing in WWDG_CR

• When must be refreshed the WWDG reset ?

– When the WWDG counter is below the value in WWDG_WR and
before WWDG counter rolls below 40h

• Which clock feeds the IWDG down counter ?

– LSI 128kHz through a prescaler

• How is refreshed the IWDG ?

– By writing AAh in the key register

• What is the maximum IWDG timeout ?

– 1s when prescaler 256 and reload value is FFh

75
Reference

• RM0016 STM8S Reference Manual

• AN2752 Getting Start with STM8
• AN2780 Real-time keeping on STM8S
devices and usage of AWU and beeper
• AN2822 STM8S HSI Oscillator Calibration
• AN2857 STM8S Family Power Management

76
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