MICROPROCESSOR

Sejal M Chopra

8255: Extra Programs

Q 1) WAP to initialize 8255 as follows:
Port A --- Mode1 ---- i/p
Port B --- Mode1 ---- o/p
Port C --- Handshaking
Assume 8255 is at 80H.Also mention the functions of each line of port C.
Solution:
Port A: Input Port
Handshaking Signals are:
PC4 : STB* ; PC5 :IBF ;PC3:INTR
Port B: Output Port
Handshaking Signals are:
PC2 :ACK* ; PC1 :OBF* ;PC0:INTR
PC6/7 :I/O

Program:
MOV AL, B4H; Control Word = 1011 0100 = B4H
OUT 86H, AL

Q 2) WAP to initialize 8255 as follows:

Port A --- Mode1 ----o/p
Port B --- Mode1 ---- i/p
Port C --- Handshaking
Assume 8255 is at 80H.Also mention the functions of each line of port C.
Solution:
Port A: Input Port
Handshaking Signals are:
PC4 : STB* ; PC5 :IBF ;PC3:INTR
Port B: Output Port
Handshaking Signals are:
PC2 :ACK* ; PC1 :OBF* ;PC0:INTR
PC6/7 :I/O

Program:
MOV AL, B4H; Control Word = 1011 0100 = B4H
OUT 86H, AL

Q 3) Generate a square wave on a display device connected to PortC3 by BSR command. Assume
8255 is at 80H.
Solution:
Back: MOV AL, 06H
OUT 86H, AL // BSR Command (Send 0) = 0000 0110
CALL Delay
MOV AL, 07H
OUT 86H, AL // BSR Command (Send 1) = 0000 0111
CALL Delay
JMP Back

Q 4) WAP to generate “positive spikes” on a display device connected to PortC3 using BSR
command.
Solution:
Back: MOV AL, 06H
OUT 86H, AL // BSR Command (Send 0) = 0000 0110
CALL Delay
MOV AL, 07H
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Sejal M Chopra

OUT 86H, AL // BSR Command (Send 1) = 0000 0111

JMP Back

Q 5) WAP to generate a rectangular wave with a 25% duty cycle on a display device connected to
PortC3 using BSR command.
Solution:
Back: MOV AL, 06H
OUT 86H, AL // BSR Command (Send 0) = 0000 0110
CALL Delay
CALL Delay
CALL Delay
MOV AL, 07H
OUT 86H, AL // BSR Command (Send 1) = 0000 0111
CALL Delay
JMP Back

Q 6) Generate a Staircase waveform on a display device connected to Port A.

Solution:
MOV AL, 80H
OUT 86H, AL // Initialize Port A as Output port
Back: MOV AL, 00H
OUT 80H, AL
CALL Delay
INC AL
JNZ Back

Q 7) Generate a Ramp waveform on a display device connected to Port A.

Solution:
MOV AL, 80H
OUT 86H, AL // Initialize Port A as Output port
Back: MOV AL, 00H
OUT 80H, AL
INC AL
JNZ Back

Q 8) Generate a Saw-tooth waveform on a display device connected to Port A.

Solution:
MOV AL, 80H
OUT 86H, AL // Initialize Port A as Output port
Back: MOV AL, 00H
OUT 80H, AL
INC AL
JMP Back

Q 9) Generate a triangular waveform on a display device connected to Port A.

Solution:
MOV AL, 80H
OUT 86H, AL // Initialize Port A as Output port
Back: MOV AL, 00H
OUT 80H, AL
INC AL
JNZ Back // 00H ………………………… FFH
MOV AL, 0FEH
Back2:OUT 80H, AL
DEC AL
JNZ Back2 // FEH ………………………… 01H
JMP Back
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Sejal M Chopra

Introduction to 8255-Programmable Peripheral Interface

1. Introduction:
 The 8255 is a programmable, parallel I/O device simply called PPI.
 It can be programmed to transfer data in various modes of I/O.
 It provides 24 I/O pins that can be grouped into three 8 bit parallel ports: PORT A, PORT
B and PORT C.
 The 8 bits of port C is separated into two 4-bit ports: PORT C UPPER (PC4-PC7) and PORT
C LOWER (PC0-PC3).
 It provides 3 modes of data transfer: simple I/O, handshake I/O and bi-directional
handshake I/O.
 Individual bits of only Port C can be altered using bit set/reset mode.

Viva Question: What is need of 8255 for I/O interfacing?

There are two reasons for using 8255 between 8086 and I/O devices.
1) To achieve Speed compatibility between high speed microprocessor and slow I/O devices.
2) Reducing hardware complexity by interfacing the I/O devices through program.

Reason 1: Let us consider a keyboard interfaced serially to 8086 microprocessor as shown in Fig.
In the Fig, microprocessor receives ASCII code of a key serially, which is sent from keyboard after
the key hit. Here keyboard is mechanical device on which a user can type characters at rate up
to 130 words per minute and microprocessor is high speed semiconductor device, which accept
and process millions of words per second.There is no speed compatibility between these two
devices. To achieve the speed compatibility, place a semiconductor bidirectional buffer (called
as port in 8255 ) (synchronize the buffer and microprocessor) between microprocessor and
Keyboard.
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Sejal M Chopra

When key is hit, the ASCII code of the key transferred to buffer serially. If the buffer is full, then
it intimates the microprocessor through a separate signal (IBF) that it has received a key. Now
the microprocessor collects the entire 8-bit data by reading buffer. In this way, speed
compatibility is achieved. There are three programmable ports are available in 8255.

Reason 2: microcomputer is used for general purpose; so that many devices are interfaced to
microprocessor. For example, keyboard, mouse, printer, monitor, Hard drive, etc., To interface
all these devices to microprocessor require more buffers and I/O lines, which increases the
circuit complexity and space occupied. This can be solved by controlling fixed number of buffers
or PORTs programmatically. 8255 PPI has three bi-directional I/O PORTs (labeled A, B, C). These
ports are programmed as input/output using control word register and interface many devices
using time share basis using these fixed ports.
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Sejal M Chopra

2. Pin Diagram:

 VCC: The +5V power supply pin.

 GND: Ground.
 DATA BUS (D0-D7): The Data Bus lines are bidirectional three-state pins connected to
the system data bus. These are the data input/output lines for the device. All
information read from and written to the 8255 occurs via these 8 data lines.
 RESET: A high on this input clears the control register and all ports (A, B, C) are set to
the input mode.
 CHIP SELECT*: Chip select is an active low input used to enable the 82C55A
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Sejal M Chopra

 WRITE*: This control signal enables the write operation. When the signal goes low,
microprocessor writes data into a selected I/O Port or control register.
 ADDRESS (A0, A1): These input signals, control the selection of one of the three ports
or the control word register. A0 and A1 are normally connected to the A1 and A2 bits of
the Address Bus of processor.
 PA0 - PA7, PB0 - PB7, PC0 - PC7 : These signal lines are used as 8-bit I/O ports. They
can be connected to peripheral devices. The 8255 has three 8 bit I/O ports and each one
can be connected to the physical lines of an external device. These lines are labeled
PA0- PA7, PB0-PB7, and PC0-PC7. The groups of the signals are divided into three
different I/O ports labeled port A (PA), port B (PB), and port C (PC).

3. Architecture:

Data Bus Buffer:

This bi-directional 8-bit buffer is used to interface the 8255 to the system data bus. Data is
transmitted or received by the buffer upon execution of input or output instructions by the CPU.
Control words and status information are also transferred through the data bus buffer.
Read/Write and Control Logic:
The function of this block is to manage all of the internal and external transfers of both Data and
Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn,
issues commands to both of the Control Groups.
(CS*) Chip Select. A "low" on this input pin enables the communication between the 8255 and the
CPU.
(RD*) Read. A "low" on this input pin enables 8255 to send the data or status information to the
CPU on the data bus. In essence, it allows the CPU to "read from" the 8255.
(WR*) Write. A "low" on this input pin enables the CPU to write data or control words into the
8255.
(A0 and A1) These input signals, in conjunction with CS* control the selection of one of the three
ports or the control word register.
(RESET) Reset. A "high" on this input initializes the control register to 9Bh and all ports (A, B, C)
are set to the input mode.
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Sejal M Chopra

CS* A1 A0 SELECTION
0 0 0 PORT A
0 0 1 PORT B
0 1 0 PORT C
0 1 1 CONTROL REGISTER
1 X X 8255 IC NOT SELECTED
Group A and Group B Controls:
The functional configuration of each port is programmed by the systems software. In essence,
the CPU "outputs" a control word to the 8255. The control word contains information such as
"mode", "bit set", "bit reset", etc., that initializes the functional configuration of the 8255. Each
of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write Control
logic, receives "control words" from the internal data bus and issues the proper commands to its
associated ports.
Ports A, B, and C:
The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of
functional characteristics by the system software but each has its own special features or
"personality" to further enhance the power and flexibility of the 8255.
Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up" and
"pull-down" bus-hold devices are present on Port A.
Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer.
Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input).
This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a
4-bit latch and it can be used for the control signal output and status signal inputs in conjunction
with ports A and B.

4. Interfacing 8255 IC with 8086 processor:

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Lecturer: Sejal Chopra

Working/Operating modes of IC 8255

1. Control word register of 8255:
There are two different operating modes for the 8255. These modes must be defined by the
microprocessor by writing program or control words of 8255.
If bit D7=1, 8255 operates in I/O mode and if bit D7=0, 8255 operates in BSR mode.

2. Operating Modes:

a) Bit Set-Reset mode (BSR) :

 BSR mode is used only for port C wherein the individual bits can be set/reset .
 It is used while interfacing devices like A to D converter or a seven segment display.
 It will not affect the I/O operations of 8255.
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Lecturer: Sejal Chopra

Write a program assuming IC 8255 is working in BSR mode with port A address configured at 60H for
the following cases: a) To reset bit 6 of port C b) To set bit 4 of port C c) To glow LEDs connected on
PC3 and PC7

Calculate the selection address as follows:

Selection A7 A6 A5 A4 A3 A2(CONNECTE A1(CONNECTE A0(USED

Address D TO A1 OF D TO A0 OF FOR
Ports 8255) 8255) BANKING)
Selecte
d
Port A 0 1 1 0 0 0 0 0
Port B 0 1 1 0 0 0 1 0
Port C 0 1 1 0 0 1 0 0
CWR 0 1 1 0 0 1 1 0

a) To reset bit 6 of port C:

CWR Format:
D7 D6 D5 D4 D3 D2 D1 D0
0 X X X 1 1 0 0
MOV AL, 0C H
OUT 66H, AL

b) To set bit 4 of port C

CWR Format:
D7 D6 D5 D4 D3 D2 D1 D0
0 X X X 1 0 0 1
MOV AL, 09 H
OUT 66H, AL

c) To glow LEDs connected on PC3 and PC7

MOV AL, 07H

OUT 66H, AL
MOV AL, 0FH
OUT 66H, AL

Write a program to blink an LED connected on port C bit 2 of IC 8255 (working in BSR mode) with port
A address configured at 61H.
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Lecturer: Sejal Chopra

Program:
LABEL: MOV AL, 05H
OUT 67H, AL
CALL DELAY
MOV AL, 04H
OUT 67H, AL
CALL DELAY
JMP LABEL

DELAY SUBROUTINE:
MOV CL, FFH
LABEL: DEC CL
JNZ LABEL

b) I/O mode (Data Transfer Mode):

 It is used for I/O data transfer.

 If bit D7=1, 8255 operate in I/O mode and the bits D6-D0 determines I/O operations in
various modes.
 For example, in fig the bits D2, D1, D0 determine the Group B control. Bit D2 is for I/O
mode selection and bits D1 and D0 are used to initialize the ports as Input or output.
 Similarly the bits D6-D3 determines the Group A control. D6 and D5 bits are for mode
selection and the bits D4 and D3 are used to initialize the ports as input or output.
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Lecturer: Sejal Chopra

Viva Question: On reset of IC 8255, what is the content of control register?

Answer: 9BH=1001 1011( this is because default mode is mode 0 and all ports are configured as input
ports)

i) Mode 0(Simple Input or Output):

 In this mode, ports A, B and C are used as simple 8-bit I/O ports.
 This mode doesn’t require handshaking signals or requires interrupting capability. Hence slower
devices cannot be interfaced. Consider an example where the processor simply sends the data to
output device. The processor doesn’t care about the data sent has been received or not by the
device. For example, consider 8255 is driving a led, connected to one of the output ports. Here,
8255 simply sends logic high to glow an LED. But it doesn’t care about the signal reached to LED
or not.

ii) Mode 1(Handshake or strobed I/O):

 This functional configuration provides a means for transferring I/O data to or from, a specified
port in conjunction with strobes or “hand shaking” signals.
 When Group A and Group B are programmed to mode1. The two ports operated in strobed I/O
mode. Mode 1 Basic Function Definitions:Two Groups (Group A and Group B),Each group contains
one 8-bit port(A or B) and 3 lines of port C for handshake. The 8-bit data port can be either input
or output.
 Interrupt Driven data transfer and status driven data transfer is possible.
 Slower devices can be interfaced.ex: In many I/O applications, valid data is present on an
external device only at certain time, so it must be read in at that time. For example, when a key
is pressed on the keyboard. It sends out the ASCII code for the pressed key, and also sends out a
strobe signal on another line to indicate that valid data present.
 The handshake signals are different for the input and output modes.

Group A and B as input in mode1:

Input control signal Definition:

STB *(Strobe Input): A Logic low on this input loads data into the port from external
peripheral device.
IBF (Input Buffer Full): Logic high on this output indicates to the peripheral device that the
data has been loaded into the 8255 port (i.e., Ack to peripheral device). IBF is set by STB* input
being low and is reset by the rising edge of the RD* input.
INTR (Interrupt Request): INTR is a signal used to indicate the microprocessor, that a byte has
been received on 8255 port. Now the microprocessor collects the data byte from the 8255 port.
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INTR is set by the condition: STB* == 1, IBF == 1 and INTE == 1. It is reset by the falling edge of
RD*.
Timing diagram:

Control word format:

Group A and B as output in mode1:

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Lecturer: Sejal Chopra

Output control signal Definition:

OBF* (Output Buffer Full):
The logic low on this signal is an indication to the peripheral device that the microprocessor written a
data byte into the 8255 port.
ACK* (Acknowledge input):
After receiving OBF* signal, the peripheral sends ACK* signal as low to 8255 indicating that it is ready
to accept the data.
INTR (Interrupt request):
Logic high on this output can be used to interrupt the microprocessor when an output device has
accepted data transmitted by the microprocessor. INTR is set when ACK* == 1, OBF* == 1 and INTE ==
1. It is reset by the falling edge of WR*.
Timing diagram:

Control word format:

Mode 2 (Bi-Directional handshaking I/O):

 This mode is used primarily in applications such as data transfer between two
computers.
 In this mode, PORT A can be configured as the bidirectional port and PORT B
either in Mode0 or Mode1.
 PORT A uses five signals from PORT C as handshake signals for data transfer.
 The remaining three signals from PORT C can be used either as simple I/O or
as handshake for port B.
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Lecturer: Sejal Chopra

Bi-Directional Bus I/O Control Signal Definition:

Output Operations:
OBF*(Output Buffer Full). The logic low on this signal is an indication to the peripheral device
that the microprocessor written a data byte into the 8255 port.
ACK* (Acknowledge). After receiving OBF* signal, the peripheral sends ACK* signal as low to
8255 indicating that it is ready to accept the data.
INTE1:The INTE flip-flop associated with OBF.
Input Operations:
STB* (Strobe Input): A Logic low on this input loads data into the port from external peripheral
device.
IBF (Input Buffer full): Logic high on this output indicates to the peripheral device that the data
has been loaded into the 8255 port (i.e., Ack to peripheral device). IBF is set by STB*
INTR (Interrupt Request): A high on this output can be used to interrupt the microprocessor for
both input or output operations.

Control word format (when port B is in mode 0 –input):

D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X X 0 1 1/0

Control word format (when port B is in mode 1 –output):

D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X X 1 0 X
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Lecturer: Sejal Chopra

Timing Diagram:
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Lecturer: Sejal M Chopra

8257: Direct Memory Access Controller

1. Concept of DMA:
When DMA operates:
•Device requests service of DMA by pulling DREQ (DMA request) high
•DMA puts high on HRQ (hold request)
•CPU finishes present bus cycle (not necessarily present instruction) and puts high on HDLA (hold
acknowledge). HOLD remains active for duration of DMA
•DMA activates DACK (DMA acknowledge), telling device to start transfer
•Example: DMA starts transfer by putting address of first byte on address bus and activating MEMR;
it then activates IOW to write to peripheral. DMA decrements counter and increments address
pointer. Repeat until count reaches zero
•DMA deactivates HRQ, giving bus back to CPU.

Viva Question: In case of simultaneous occurrence of signals on the following pins which has
highest priority?
 RESET (1)
 HOLD (2)
 NMI (3)
 INTR (4)
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2. Features:
 It is a device to transfer the data directly between IO device and memory without through the
CPU. So it performs a high-speed data transfer between memory and I/O device.
 It has four channels which can be used over four I/O devices.
 Each channel has 16-bit address and 14-bit counter, can transfer data up to 64KB, can be
programmed independently and can have either fixed or rotating priority mode.
 Each channel can perform either of the three DMA operations: read transfer, write transfer and
verify transfer operations.
 It generates MARK signal to the peripheral device that 128 bytes have been transferred.
 Its frequency ranges from 250Hz to 3MHz.
 It operates in either Master mode or Slave mode.
 It has four data transfer modes: Single, Block, demand and cascade transfer modes

Viva Question: What is the difference between DMA read, DMA write and DMA verify
operations?

• DMA read: DMA reads from memory and writes into an I/O, active signal are MEMR* &
IOW*
• DMA write: DMA reads from an I/O and writes into memory, active signal are IOR* &
MEMW*
• DMA verify: no data transfer takes place, error detection and correction technique is
implemented wherein data transferred is verified.

Viva Question: What is the difference between fixed and rotating priority mode?

In the fixed priority, channel 0 has the highest priority and channel 3 has the lowest priority.

In rotating priority mode, the priority of the channels has a circular sequence. In this, channel
being serviced gets the lowest priority and the channel next to it gets the highest priority.
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Lecturer: Sejal M Chopra

3. Pin Diagram:

DRQ0−DRQ3 :
These are the four individual channel DMA request inputs, which are used by the peripheral devices
for using DMA services. When the fixed priority mode is selected, then DRQ 0 has the highest priority
and DRQ3 has the lowest priority among them.
DACKo* − DACK3*:
These are the active-low DMA acknowledge lines, which updates the requesting peripheral about the
status of their request by the CPU.
Do − D7:
These are bidirectional, data lines which are used to interface the system bus with the internal data
bus of DMA controller. In the Slave mode, it carries command words to 8257 and status word from
8257. In the master mode, these lines are used to send higher byte of the generated address to the
latch.
IOR*:
It is an active-low bidirectional input line, which is used by the CPU to read internal registers of 8257
in the Slave mode. In the master mode, it is used to read data from the peripheral devices during a
memory write cycle.
IOW*:
It is an active low bi-direction line, which is used to load the contents of the data bus to the 8-bit
mode register or upper/lower byte of a 16-bit DMA address register or terminal count register. In the
master mode, it is used to load the data to the peripheral devices during DMA memory read cycle.
CLK:
It is a clock frequency signal which is required for the internal operation of 8257.
RESET:
This signal is used to RESET the DMA controller by disabling all the DMA channels.
Ao - A3:
These are the four least significant address lines. In the slave mode, they act as an input, which
selects one of the registers to be read or written. In the master mode, they are the four least
significant memory address output lines generated by 8257.
CS*:
It is an active-low chip select line. In the Slave mode, it enables the read/write operations to/from
8257. In the master mode, it disables the read/write operations to/from 8257.
A4 - A7:
These are the higher nibble of the lower byte address generated by DMA in the master mode.
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READY:
It is an active-high asynchronous input signal, which makes DMA ready by inserting wait states.
HRQ:
This signal is used to receive the hold request signal from the output device. In the slave mode, it is
connected with a DRQ input line 8257. In Master mode, it is connected with HOLD input of the CPU.
HLDA:
It is the hold acknowledgement signal which indicates the DMA controller that the bus has been
granted to the requesting peripheral by the CPU when it is set to 1.
MEMR*:
It is the low memory read signal, which is used to read the data from the addressed memory
locations during DMA read cycles.
MEMW*:
It is the active-low three state signal which is used to write the data to the addressed memory
location during DMA write operation.
ADSTB:
This signal is used to convert the higher byte of the memory address generated by the DMA controller
into the latches.
AEN:
This signal is used to disable the address bus/data bus.
TC:
It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present peripheral
devices.
MARK:
The mark will be activated after each 128 cycles or integral multiples of it from the beginning. It
indicates the current DMA cycle is the 128th cycle since the previous MARK output to the selected
peripheral device.
Vcc:
It is the power signal which is required for the operation of the circuit.

4. Block Diagram:
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Data Bus Buffer:

 Bi-directional, eight bit buffer which interfaces the 8257 to the system data bus.
 In the slave mode, it is used to transfer data between microprocessor and internal registers
of 8257.
 In master mode, it is used to send higher byte address (A8-A15) on the data bus.
Read/Write Logic:

 When the CPU is programming or reading one of the internal registers of 8257 (i.e, when the
8257 is in the slave mode), the Read/Write logic accepts the I/O Read (IOR*) or I/O Write
(IOW) signal, decodes the least significant four address bits (A0 – A3) and either writes the
contents of the data bus into the addressed register (if IOW* is low) or places the contents of
the addressed register onto the data bus (if IOR*is low).
 During DMA cycles (i.e. when the 8257 is in the master mode) the Read/Write logic generates
the I/O read and memory write (DMA write cycle) or I/O write and memory read (DMA read
cycle) signals which control the data transfer between peripheral and memory device.

Channels:

Provides four identical channels, labeled CH0 to CH3. Each channel has two sixteen bit registers:

1. A DMA address register, and

2. A terminal count register.

DMA address register : It specifies the address of the first memory location to be accessed. It is
necessary to load valid memory address in the DMA address register before channel is enabled.

Terminal Count Register :

Control logic:

It controls the sequence of operations during all DMA cycles (DMA read, DMA write, DMA verify) by
generating the appropriate control signals and the 16-bit address that specifies the memory location
to be accessed. It consists of mode set register and status register. Mode set register is programmed
by the CPU to configure 8257 whereas the status register is read by CPU to check which channels
have reached a terminal count condition and status of update flag.
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Mode Set Register:

Least significant four bits of mode set register, when set, enable each of the four DMA channels.
Most significant four bits allow four different options for the 8257 .It is normally programmed by the
CPU after initializing the DMA address registers and terminal count registers. It is cleared by the
RESET input, thus disabling all options, inhibiting all channels, and preventing bus conflicts on
power-up.

 The use of mode set register is,

1. Enable/disable a channel.
2. Fixed/rotating priority
3. Stop DMA on terminal count.
4.Extended/normal write time.
5. Auto reloading of channel-2.

 The bits B0, B1, B2, and B3 of mode set register are used to enable/disable channel -0, 1, 2 and 3
respectively. A one in these bit position will enable a particular channel and a zero will disable it.

 If the bit B4 is set to one, then the channels will have rotating priority and if it zero then the
channels wilt have fixed priority.

1. In rotating priority after servicing a channel its priority is made as lowest.

2. In fixed priority the channel-0 has highest priority and channel-3 has lowest priority.

 If the bit B5 is set to one, then the timing of low write signals (MEMW and IOW) will be extended.

 If the bit B6 is set to one then the DMA operation is stopped at the terminal count.

 The bit B7 is used to select the auto load feature for DMA channel-2.

 When bit B7 is set to one, then the content of channel-3 count and address registers are loaded in
channel-2 count and address registers respectively whenever the channel-2 reaches terminal count.
When this mode is activated the number of channels available for DMA reduces from four to three.

Status Register:

It indicates which channels have reached a terminal count condition and includes the update flag
described previously.

 The bit B0, B1, B2, and B3 of status register indicates the terminal count status of channel-0, 1,2 and
3 respectively. A one in these bit positions indicates that the particular channel has reached terminal
count.

 These status bits are cleared after a read operation by microprocessor.

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 The bit B4 of status register is called update flag and a one in this bit position indicates that the
channel-2 register has been reloaded from channel-3 registers in the auto load mode of operation.

Priority Resolver:

It resolves the peripherals requests. It can be programmed to work in two modes, either in fixed
mode or rotating priority mode.

Note: The Register Organization of 8257 IC consists of following registers:

DMA address register, terminal count register, Mode Set Register and Status Register
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Lecturer: Sejal M Chopra

5. Data Transfer Modes:

DMA controller has four modes for data transfer:

1. Single Byte Transfer Mode/ Cycle Stealing:

 Once the DMAC becomes the bus master, it will transfer only ONE BYTE and return the bus
back to the microprocessor. As soon as the microprocessor performs one bus cycle, DMAC will
once again take the bus back from the microprocessor.
 Both DMAC and microprocessor are constantly stealing bus cycles from each other. It is the
most popular method of DMA, because it keeps the microprocessor active in the background.
 For further bytes to be transferred, the DREQ line must go active again, and then the entire
operation is repeated.

2. Block Transfer Mode:

 In this mode, the DMAC is programmed to transfer all the bytes in one complete DMA
operation.
 The system bus is returned to the µP, only after all the bytes are transferred. i.e. TC is
reached or EOP signal is issued. It is the fastest form of DMA but keeps the microprocessor
inactive for a long time.
 The DREQ signal needs to be active only in the beginning for requesting the DMA service
initially. Thereafter DREQ can become low during the transfer.

3. Demand Transfer Mode:

 It is very similar to Block Transfer, except that the DREQ must active throughout the DMA
operation.
 If during the operation DREQ goes low, the DMA operation is stopped and the busses are
returned to the µP.
 In the meantime, the µP can continue with its own operations. Once DREQ goes high again,
the DMA operation continues from where it had stopped.

4. Cascade Transfer Mode:

 In this mode, more than one DMACs are cascaded together. It is used to increase the number
of devices interfaced to the µP. Here we have one Master DMAC, to which one or more Slave
DMACs are connected.
 The Slave gives HRQ to the Master on the DREQ of the Master, and the Master gives HRQ to
the µP on the HOLD of the µP.
 MICROPROCESSOR
Lecturer: Sejal M Chopra

Programming IC 8259
1. Initialization Sequence:
The 8259 accepts two types of command words generated by the CPU:
1. Initializat ion Command Words (ICWs): Before normal operation can begin, each 8259 in the
system must be brought to a starting point by a sequence of 2 to 4 bytes timed by WR* pulses.
2. Operation Command Words (OCWs): These are the command words which command the
8259 to operate in various interrupt modes. These modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259 anytime after initializat ion.

2. INITIALIZATION COMMAND WORDS (ICWS):

Whenever a command is issued with A0 = 0 and D4 = 1, this is interpreted as Initialization
Command Word 1 (ICW1). ICW1 starts the initialization sequence during which the following
automatically occur.
a. The edge sense circuit is reset, which means that following initialization , an interrupt
request (IR) input must make a low-to-high transition to generate an interrupt.
b. The Interrupt M ask Register is cleared.
c. IR7 input is assigned priority 7.
d. The slave mode address is set to 7.
e. Special M ask M ode is cleared and Status Read is set to IRR.
 MICROPROCESSOR
Lecturer: Sejal M Chopra

f. If IC4 = 0, then all functions selected in ICW4 are set to zero. (Non-Buffered mode*, no
Auto-EOI).

a) Initialization Command Words 1 and 2 (ICW1, ICW2):

In an 8086/88 system, the 8 request levels will generate CALLs to 8 locations equally
spaced in memory.
LTIM : If LTIM = 1, then the 8259 will operate in the level interrupt mode. Edge detect logic
on the interrupt inputs will be disabled. ADI: CALL address interval. ADI = 1 then interval =4;
ADI = 0 then interval = 8. SNGL: Single. means that this is the only
8259 in the system. If SNGL= 1 no ICW3 will be issued.
IC4: If this bit is set ICW4 has to be read. If ICW4 is not ne eded, set IC4 = 0.

b) Initialization Command Word 3 (ICW3):

This word is read only when there is more than one 8259 in the system and cascading
is used, in which case SNGL = 0. It will load the 8-bit slave register.
 MICROPROCESSOR
Lecturer: Sejal M Chopra

c )Initialization Command Word 4 (ICW4):

SFNM : If SFNM = 1 the special fully nested mode is programmed.
BUF: If BUF = 1 the buffered mode is programmed. In buffered mode SP/EN becomes an
enable output and the master slave determination is by M /S.
M /S: If buffered mode is selected: M /S = 1 means the 8259 is programmed to be a master, M /S
= 0 means the 8259 is programmed to be a slave. If BUF = 0, M /S has no fu nction.
AEOI: If AEOI = 1 the automatic end of interrupt mode is programmed. mPM : M icroprocessor
mode: mPM = 0 sets the 8259 for M CS-80, 85 system operation, mPM = 1 sets the 8259 for 8086
system operation.

3. OPERATION COMMAND WORDS (OCWS):

After the Initialization Command Words (ICWs) are programmed into the 8259, the
chip is ready to accept interrupt requests at its input lines. However, during the 8259
operation, a selection of algorithms can command the 8259 to operate in various modes
through the Operation Command Words (OCWs).
 MICROPROCESSOR
Lecturer: Sejal M Chopra

a) Operation Control Word 1 (OCW1):

OCW1 sets and clears the mask bits in the Interrupt M ask Register (IM R). M 7±M 0
represent the eight mask bits. M = 1 indicates the channel is masked (inhibited), M = 0
indicates the channel is enabled.

b) Operation Control Word 2 (OCW2)

R, SL, EOI :These three bits control the Rotate and End of Interrupt modes and
combinations of the two.A chart of these combinations can be found on the Operation
Command Word Format. L2, L1, L0:These bits determine the interrupt level acted upon when
the SL bit is active.

c) Operation Control Word 3 (OCW3):

ESMM :Enable Special Mask Mode . When this bit is set to 1 it enables the SM M bit to set or
reset the Special M ask M ode. When ESM M = 0 the SM M bit becomes a ``don't care''.
SMM:Special Mask Mode. If ESM M = 1 and SM M = 1 the 8259 will enter Special M ask M ode. If ESM M =
1 and SM M = 0 the 8259 will revert to normal mask mode. When ESM M = 0, SM M has no effect.
 MICROPROCESSOR
Lecturer: Sejal M Chopra

Programming Exercise:
1. Write a program to initialize a single 8259 IC with the following specification:
• It should be edge triggered working in EOI mode as well as non -buffered mode.
• IR1 and IR5 should be masked.
• Vector no .of IR0 is 60 H.
• Assume that 8259 is at port address 80 H.
2. Write a program to initialize a cascaded 8259 IC ‘s with one master and two slaves on
IR1 and IR3 of master with the following specification:
• Master:Port address is 10 H.Vector no.of IR5 is 95 H.It is edge triggered ,AEOI
mode,special fully nested mode and scanner is connected to IR7.
• Slave1: Port address is 70 H.Vector no.of IR0 is 80 H.It is edge triggered ,normal EOI
mode,printer and keyboard is connected to IR3 and IR5.
• Slave2: Port address is 90 H.Vector no.of IR3 is 62 H.It is level triggered ,AEOI
mode,external interrupts on IR1,IR2,IR3 and IR7.
• For all the above 8259 IC’s mask the unwanted interrupts.
Solution:
1. Calculate the selection address as follows:
Selection A7 A6 A5 A4 A3 A2 A1(CONNECTED A0(USED
Address TO A0 OF FOR
Command 8259) BANKING)
words
ICW1 1 0 0 0 0 0 0 0
ICW2 1 0 0 0 0 0 1 0
ICW4 1 0 0 0 0 0 1 0
OCW1 1 0 0 0 0 0 1 0

Program:
M OV AL,17H
OUT 80H,AL
M OV AL,60H
OUT 82H,AL
 MICROPROCESSOR
Lecturer: Sejal M Chopra

M OV AL,01H
OUT 82H,AL
M OV AL,22H
OUT 82H,AL

2. The selection address (I/O map) as follows:

MASTER:
Selection A7 A6 A5 A4 A3 A2 A1(CONNECTED A0(USED
Address TO A0 OF FOR
Command 8259) BANKING)
words
ICW1 0 0 0 1 0 0 0 0
ICW2 0 0 0 1 0 0 1 0
ICW3 0 0 0 1 0 0 1 0
ICW4 0 0 0 1 0 0 1 0
OCW1 0 0 0 1 0 0 1 0

Program:
M OV AL,15H
OUT 10H,AL
M OV AL,90H
OUT 12H,AL
M OV AL,0AH

OUT 12H,AL
M OV AL,13H
OUT 12H,AL
M OV AL,75H
OUT 12H,AL

SLAVE1:
The selection address (I/O map) as follows:
Selection A7 A6 A5 A4 A3 A2 A1(CONNECTED A0(USED
Address TO A0 OF FOR
Command 8259) BANKING)
words
ICW1 0 1 1 1 0 0 0 0
ICW2 0 1 1 1 0 0 1 0
ICW3 0 1 1 1 0 0 1 0
ICW4 0 1 1 1 0 0 1 0
OCW1 0 1 1 1 0 0 1 0

Program:
M OV AL,15H
OUT 70H,AL
M OV AL,80H
OUT 72H,AL
M OV AL,01H
OUT 72H,AL
M OV AL,01H
OUT 72H,AL
M OV AL,D7H
OUT 72H,AL

SLAVE2:
The selection address (I/O map) as follows:
Selection A7 A6 A5 A4 A3 A2 A1(CONNECTED A0(USED
Address TO A0 OF FOR
Command 8259) BANKING)
words
ICW1 1 0 0 1 0 0 0 0
ICW2 1 0 0 1 0 0 1 0
 MICROPROCESSOR
Lecturer: Sejal M Chopra

ICW3 1 0 0 1 0 0 1 0
ICW4 1 0 0 1 0 0 1 0
OCW1 1 0 0 1 0 0 1 0

Program:
M OV AL,1DH
OUT 90H,AL
M OV AL,5FH
OUT 92H,AL
M OV AL,03H
OUT 92H,AL
M OV AL,03H
OUT 92H,AL
M OV AL, 71H
OUT 92H,AL
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MICROPROCESSOR

IC 8259-Programmable Interrupt Controller

1. Features:
 The 8259 is a device specifically designed for using real time, interrupt driven
microcomputer systems.
 The 8259 programmable interrupt controller (PIC) adds eight vectored priority encoded
interrupts to the microprocessor.
 This controller can be expanded to accept up to 64 interrupt requests. This requires a
master 8259 and eight 8259 slaves.
 Vector an Interrupt request anywhere in the memory map.
 Resolve eight levels of interrupt priorities in a variety of modes, such as fully nested mode,
automatic rotation mode, and specific rotation mode. The priority modes can be changed or
reconfigured dynamically at any time during the main program.
 Mask each of the interrupt request individually.
 Read the status of the pending interrupts, in-service interrupts and masked interrupts.
 It issues a single interrupt request to the CPU.
 In response to the INTA/, it issues a unique type number (vector) for each interrupt request
input. In addition, type numbers are programmable.
 This means that the complete interrupt structure can be defined as required, based on the
total system environment.

2. Block Diagram:

Interrupt Request Register (IRR) And In-Service Register (ISR):

The interrupts at the IR input lines are handled by two registers in cascade, the
Interrupt Request Register (IRR) and the In-Service (ISR). The IRR is used to store all the
interrupt levels which are requesting service; and the ISR is used to store all the interrupt
levels which are being serviced.
Priority Resolver:
This logic block determines the priorities of the bits set in the IRR. The highest
priority is selected and strobed into the corresponding bit of the ISR during INTA* pulse.
Interrupt Mask Register (IMR):
The IMR stores the bits which mask the interrupt lines to be masked. The IMR operates on
the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower
quality.
Control logic: Used to control the operation of various blocks on the 8259 IC and issues INT
signal.
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MICROPROCESSOR

INT (Interrupt):
This output goes directly to the CPU interrupt input. The VOH level on this line is
designed to be fully compatible with the 8080A, 8085A and 8086 input levels.
INTA (Interrupt Acknowledg e)* :
INTA* pulses will cause the 8259 to release vectoring information onto the data bus.
The format of this data depends on the system mode of the 8259.
Data Bus Buffer:
This 3-state, bidirectional 8-bit buffer is used to interface the 8259 to the system
Data Bus. Control words and status information are transferred through the Data Bus Buffer.
Read/Write Control Logic:
The function of this block is to accept OUTput commands from the CPU. It contains
the Initialization Command Word (ICW) registers and Operation Command Word (OCW)
registers which store the various control formats for device operation. This function block
also allows the status of the 8259 to be transferred onto the Data Bus.
CS (Chip Select)*:A LOW on this input enables the 8259. No reading or writing of the chip
will occur unless the device is selected.
WR (Write)*:A LOW on this input enables the CPU to write control words (ICWs and OCWs)
to the 8259.
RD (READ)*: A LOW on this input enables the 8259 to send the status of the Interrupt
Request Register (IRR), In Service Register (ISR), the Interrupt Mask Register (IMR), or the
Interrupt level onto the Data Bus.
A0:This input signal is used in conjunction with WR* and RD* signals to write commands into
the various command registers, as well as reading the various status registers of the chip.
This line is tied directly to A1of address lines.
The Cascade Buffer/Comp arator:
This function block stores and compares the IDs of all 8259's used in the system. The
associated three I/O pins (CAS0-2) are outputs when the 8259 is used as a master and are
inputs when the 8259A is used as a slave. As a master, the 8259 sends the ID of the
interrupting slave device onto the CAS0±2 lines. The slave thus selected will send its
preprogrammed subroutine address onto the Data Bus during the next one or two
consecutive INTA* pulses.
SP*/EN*:If the IC works in buffered mode ,EN* works as an output line wherein the outputs
of the data bus buffer are allowed .In non-buffered mode ,it works as an input line to
distinguish between the master and slave PIC’s.If SP* (slave Program)is connected to gnd,it
is a slave IC and if it is connected to Vcc it is master IC.

Viva Question: Which one is preferred: Level triggering or edge triggering on IR0 –IR7
lines?
Because output can change in precise amount of time while dealing with edge triggered
lines.

3.8259-Interrupt sequence:
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 One or more of the INTERRUPT REQUEST lines (IR7-IR0) are raised high, setting the
corresponding IRR bit(s).
 The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate.
 The CPU acknowledges the INT and responds with an INTA/ pulse.
 Upon receiving an INTA/ from the CPU, the highest priority ISR bit is set, and the
corresponding IRR bit is reset. The 8259 does not drive the data bus this cycle.
 The 8088/8086 will initiate a second INTA/ pulse. During this pulse, the 8259 releases an 8-
bit pointer onto the Data Bus where it is read by the CPU.
 This completes the interrupt cycle. In the AEOI mode, the ISR bit is reset at the end of the
second INTA/ pulse. Otherwise, the ISR bit remains set until the appropriate EOI command is
issued at the end of the Interrupt Service Routine (ISR).
 The IRR is a transparent latch. Bits of IRR are frozen by the FREEZE/ signal starting at the
beginning of first INTA/ pulse till the end of the second INTA/ pulse.
 Whatever interrupt requests arrive at the IRR will be latched transparently.
 If the interrupt request is not masked as per the Interrupt Mask Register (IMR), it will reach
to the Priority Resolver (PR).
 IF new request’s priority is higher than the interrupt under service, INT signal is raised by the
PR to make a request to the CPU.
 After some time, the CPU sends the first INTA/ pulse. Now the requests in IRR are frozen,
and the highest priority interrupt is identified by the PR. The corresponding bit in the ISR is
set, and the corresponding bit of IRR is cleared.
 During the second INTA/ pulse, the vector type is sent out, and then the INT signal is
lowered.
 The ISR records the requests currently being serviced.
 It enables the 8259 to check whether any of the incoming new requests has higher priority
than the priority of the currently in-service requests. If so, the 8259 will again raise the INT
signal and wait for INTA/.
 The ISR bit(s) get cleared.
 At the end of the ISR, there should be an instruction to send End of Interrupt (EOI) command
to the 8259. Then the highest priority ISR bit gets reset.
 Note: If End Of Interrupt (EOI) is not issued at the end of ISR, all interrupt requests of equal
or lower priority remain blocked until the ISR bit is cleared.
 For nesting of interrupts, ISR bit is reset at the end of the second INTA/ pulse (It is a
programmable feature called Automatic End of Interrupt (AEOI)).
 MICROPROCESSOR
Sejal M Chopra

Decoding Techniques
Address Decoding Techniques in 8086 Microprocessor:
Note: Used for interfacing RAM and ROM chips

The Different types of Address Decoding Techniques in 8086 Microprocessor are,

 Absolute decoding (Full Decoding)

 Linear decoding (Partial Decoding)

1. Absolute Decoding :

In absolute decoding technique the memory chip is selected only for the specified logic level on
the address lines; no other logic levels can select the chip. Fig shows the memory interface with
absolute decoding. Two 8K EPROMs (2764) are used to provide even and odd memory banks. BHE*
and A0 are used to enable outputs of odd and even memory banks respectively. As each memory
chip has 8K memory locations, thirteen address lines are required to address each locations,
independently. All remaining address lines are used to generate an unique chip select signal.
This addressing technique is normally used in large, memory systems.

Special Case of Full decoding:

Block Decoding:

In a microcomputer system the memory array is often consists of several blocks of memory chips.
Each block of memory requires decoding circuit. To avoid separate decoding for each memory
block special decoder IC is used to generate chip select signal for each block. Fig. shows the
block Address Decoding Techniques in 8086 Microprocessor using 74138, 3:8 decoder.
 MICROPROCESSOR
Sejal M Chopra

2.Linear Decoding :

In small systems, hardware for the decoding logic can be eliminated, by using only required
number of addressing lines (not all). Other lines are simply ignored. This technique is referred as
Linear Decoding or Partial Decoding. Fig. shows the addressing of 16K RAM (6264) with linear
decoding. BHE* and A0 are used to, enable odd and even memory banks, respectively. The
address line A19 is used to select the RAM chips. When A19 is low, chip is selected, otherwise it is
disabled. The status of A14 to A18 does not affect the chip selection logic. This gives you multiple
addresses (shadow addresses). This technique reduces the cost of Address Decoding Techniques
in 8086 Microprocessor circuit, but it has drawback of multiple addresses.
 MICROPROCESSOR
Sejal M Chopra

Designing Examples
Design an 8086 based Maximum Mode system working at 6 MHz having the following:
32KB EPROM using 16KB chips,
128KB RAM using 32KB chips,

Note:
** Every designing problem has three components:
1) Mode of Operation of 8086 processor: Minimum mode or Maximum mode
2) Memory Interfacing: Using ROM and RAM chips (we will construct a Memory Map and
interfacing diagram)
3) I/O Interfacing: Using 8255 ICs (not in syllabus)

Solution:
1) Mode of Operation:
Show 8086 max. mode configuration with a crystal of 18 MHz.

Note for variations:

1) If crystal frequency is specified, then show that value directly over crystal; but if
operating frequency is specified then crystal frequency=3* operating frequency.
2) If mode of operation not specified then draw minimum mode configuration.
3) Important points in the diagram are: Crystal frequency and MN/MX* pin status.
4) Instead of minimum mode or maximum mode ,interfacing of any chip (IC-8259,IC-8253,IC-
8257 can be asked)
 MICROPROCESSOR
Sejal M Chopra

2) Memory Calculations:
EPROM:
Required size = 32 KB, Available size = 16 KB
No. of chips required = Required size / Available size =2 chips.
No. of sets required= No. of chips required/ No. of banks= 2/2=1
Set size= Available Chip size x no .of banks= 16 x 2= 32 KB=32 x 1KB= 25 x 210 =215

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 7 F F F

Ending Address=FFFFFH
Starting address of EPROM is calculated as:
=Ending Address – Set size
=F F F F F H- 7 F F F H=F8000H
 MICROPROCESSOR
Sejal M Chopra

Chip Address Even Bank Odd Bank

EPROM Set 1 Starting Address F8000H F8001H
Ending Address FFFFEH FFFFFH
No. of address lines required for interfacing is dependent on size of a single available EPROM chip
= 16 KB
= 16 x 1KB = 24 x 210
= 214
= 14 address lines= (A 14 … A1)…note A0 is reserved for banking….IMPORTANT during interfacing

RAM:
Required size = 128 KB, Available size = 32 KB
No. of chips required = Required size / Available size = 4 chips.
No. of sets required= No. of chips required/ No. of banks= 4/2=2
Set size= Available Chip size x no .of banks= 32 x 2= 64 KB=64 x 1KB= 2 6 x 210 =216

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 F F F F

Starting address of RAM Set1=00000H

Ending address of RAM Set1 is calculated as:
=Starting Address + Set size
=00000 H +0 F F F F H
=0FFFFH

Starting address of RAM Set2= Ending address of RAM Set1+1=10000H

Ending address of RAM Set2 is calculated as:
=Starting Address + Set size
=10000 H +0 F F F F H
=1FFFFH

Chip Address Even Bank Odd Bank

RAM Set 1 Starting Address 00000H 00001H
Ending Address 0FFFEH 0FFFFH
RAM Set 2 Starting Address 10000H 10001H
Ending Address 1FFFEH 1FFFFH

No. of address lines required for interfacing is dependent on size of a single available RAM chip
= 32 KB
= 32 x 1 KB = 25 x 210
= 215
= 15 address lines
= (A15 … A1)…. note A0 is reserved for banking….IMPORTANT during interfacing
 MICROPROCESSOR
Sejal M Chopra

MEMORY MAP

Let’s construct first the memory map

 MICROPROCESSOR
Sejal M Chopra

Interpreting Memory Map for Memory Interfacing:

 MICROPROCESSOR
Sejal M Chopra

Memory Interfacing:
Step1: Interfacing RAM set1
 MICROPROCESSOR
Sejal M Chopra

Step2: Interfacing RAM set2

 MICROPROCESSOR
Sejal M Chopra

Step 3: Interfacing EPROM set1

Note for variations:

1) If application memory is mentioned it means RAM chips and if monitor programming
memory mentioned it means EPROM chips.
2)Generally we use absolute (full) decoding technique (especially block) for memory
interfacing.
3) Instead of the required size sometimes you have IC numbers given ,we need to know their
size.
Chips IC Number Memory Size(Available Size)
EPROM 2716 2K x 8
2732 4K x 8
2764 8K x 8
27128 16K x 8
27256 32K x 8
27512 64K x 8
RAM 6116 2K x 8
6264 8K x 8
62256 32K x 8
 MICROPROCESSOR
Sejal M Chopra

4) Depending on the address lines used, sometimes we need to use either 2:4 decoder(IC-
74139) or3:8 decoder(IC 74138) or 4:16 decoder(74154)
5) Specifications of these decoders are as follows:
2:4 decoder (IC-74139): It has 2 inputs and 4 active low outputs. It has one active low G pin.
3:8 decoder (IC 74138): It has 3 inputs and 8 active low outputs. It has one active high G 1 pin
and two active low G2A and G2B pin.
4:16 decoder (74154): It has 4 inputs and 16 active low outputs. It has two active low G 1 and
G2 pin.

Complete Interfacing Diagram (You need to draw this final diagram)

 MICROPROCESSOR
Sejal M Chopra

Practise Question:
Design an 8086 based system working at 7 MHz having the following:
128KB EPROM using 32KB chips,
32KB RAM using 8KB chips,
Two 8-bit input and two 8-bit output ports all interrupt driven

Solution:
Memory Calculations:
EPROM:
Required size = 128 KB, Available size = 32 KB
No. of chips required = Required size / Available size =4 chips.
No. of sets required= No. of chips required/ No. of banks= 4/2=2
Set size= Available Chip size x no .of banks= 32 x 2= 64 KB=64 x 1KB= 2 6 x 210 =216

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 F F F F

Ending Address of EPROM set1=FFFFFH

Starting address of EPROM set1 is calculated as:
=Ending Address – Set size
=F F F F F H- F F F F H=F0000H

Ending Address of EPROM set2= Starting address of EPROM set1 -1=F0000H-1=EFFFFH

Starting address of EPROM set2 is calculated as:
=Ending Address – Set size
=E F F F F H- F F F F H=E0000H

Chip Address Even Bank Odd Bank

EPROM Set 1 Starting Address F0000H F0001H
Ending Address FFFFEH FFFFFH
EPROM Set 2 Starting Address E0000H E0001H
Ending Address EFFFEH EFFFFH
No. of address lines required for interfacing is dependent on size of a single available EPROM chip
= 32 KB
= 32 x 1KB = 25 x 210
= 215
= 15 address lines= (A 15 … A1)…note A0 is reserved for banking….IMPORTANT during interfacing

RAM:
Required size = 32 KB, Available size = 8 KB
No. of chips required = Required size / Available size = 4 chips.
No. of sets required= No. of chips required/ No. of banks= 4/2=2
Set size= Available Chip size x no .of banks= 8 x 2= 16 KB=16 x 1KB= 2 4 x 210 =214

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 3 F F F

Starting address of RAM Set1=00000H

Ending address of RAM Set1 is calculated as:
=Starting Address + Set size
=00000 H +0 3 F F F H
=03FFFH

Starting address of RAM Set2= Ending address of RAM Set1+1=04000H

 MICROPROCESSOR
Sejal M Chopra

Ending address of RAM Set2 is calculated as:

=Starting Address + Set size
=04000 H +0 3 F F F H
=07FFFH

Chip Address Even Bank Odd Bank

RAM Set 1 Starting Address 00000H 00001H
Ending Address 03FFEH 03FFFH
RAM Set 2 Starting Address 04000H 04001H
Ending Address 07FFEH 07FFFH

No. of address lines required for interfacing is dependent on size of a single available RAM chip
= 8 KB
= 8 x 1 KB = 23 x 210
= 213
= 13 address lines
= (A13 … A1)…. note A0 is reserved for banking….IMPORTANT during interfacing

Draw the memory map further for this question and also interfacing diagram.
 Interfacing the 8259 in single and cascaded mode

Interfacing the 8259 in single mode:

 Figure below shows that how an 8259 can be interfaced with the 8086 microprocessor
system in minimum mode. In case of 8088 microprocessor same interfacing diagram can be
used except M/I0 signal.

Interfacing of 8259 with 8086 in minimum mode

 The A0 input of the 8259A is used to select one of the two internal addresses in the device.
Ao of the 8259A is connected to system line Al.
 The data lines of an 8259 are connected to the lower half of the system data bus; because
the 8086 expects to receive interrupt types on these lower eight data lines.
 RD and WR signals are connected to the system RD and WR lines.
 The interrupt request signal INT from the 8259 is connected to the INTR input of the 8086
and INTA from the 8086 is connected to INTA on the 8259A. As we are using single 8259 in
the system SP/EN pin is tied high and CAS0-CAS2 lines are left open.
 The eight IR inputs are available for interrupt signals.
Interfacing the 8259 in cascaded mode:
 The 8259 can be easily interconnected to get multiple interrupts.
 Fig below shows how 8259 can be connected in the cascade mode.
 In cascade mode one 8259 is configured in Master mode and other should be configured in
the Slave mode. In this figure 8259 is in the master mode and others are in slave mode.
 Each slave 8259 is identified by the number which is assigned as a part of its initialization.
Since the 8086 has only one INTR input, only one of the 8259 INT pins is connected to the
8086 INTR pin. The 8259 connected directly into the 8086 INTR pm is referred as the
master.
 The INT pins from other 8259 are connected to the IR inputs of the master 8259. These
cascaded 8259s are referred as slave. The INTA signal is connected to both master and slave
8259.
 The cascade pins CAS0 to CAS2 are connected from the master to the corresponding pins of
the slave. For the master these pins function as outputs, and for the slave these pins
function as inputs. The SP/EN signal is tied high for the master. However it is grounded for
the slave.
 Each 8259A has its own addresses so that command words can be written to it and status
bytes read from it.
Master and slave operation:

When the slave receives an interrupt signal on one of its IR inputs, it checks mask condition and
priority of the interrupt request. If the interrupt is unmasked and its priority is higher than any
other interrupt level being serviced in the slave, then the slave will send an NT signal to the IR
input of a master. If that IR input of the master is unmasked and if that input is a higher priority
than any other IR inputs currently being serviced, then the master will send an INT signal to the
8086 INTR input. If the INTR interrupt is enabled, the 8086 will go through its INTR interrupt
procedure and sends out two INTA pulses to both the master and the slave. The slave ignores the
first interrupt acknowledge pulse but the master outputs a 3-bit slave identification number on the
CAS0-CAS2 lines. Sending the 3-bit ID number enables the slave. When the slave receives the
second INTA pulse from the 8086, the slave will send the desired type number to the 8086 on the
eight data lines. If an interrupt signal is applied directly to one of the IR inputs of the master, the
master will send the desired interrupt type to the 8086 when it receives the second INTA pulse from
the 8086.
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Pentium 4

1. Comparison of 8086,80386,Pentium-I,Pentium-II and Pentium-III processor:

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2. Pentium4 Net burst Architecture:

There are four main sections: the in-order front end, the out-of-order execution engine, the integer and
floating-point execution units, and the memory subsystem.
In-Order Front End:
The in-order front end is the part of the machine that fetches the instructions to be executed next in the
program and prepares them to be used later in the machine pipeline.
Its job is to supply a high-bandwidth stream of decoded instructions to the out-of-order execution core,
which will do the actual completion of the instructions. The front end has highly accurate branch prediction
logic that uses the past history of program execution to speculate where the program is going to execute
next.
The predicted instruction address, from this front-end branch prediction logic, is used to fetch instruction
bytes from the Level 2 (L2) cache.
These IA-32 instruction bytes are then decoded into basic operations called uops (micro-operations) that
the execution core is able to execute.
The NetBurst microarchitecture has an advanced form of a Level 1 (L1) instruction cache called the
ExecutionTrace Cache.
Unlike conventional instruction caches, the Trace Cache sits between the instructions decode logic and
execution core as shown in Figure 1.
In this location the Trace Cache is able to store the already decoded IA-32 instructions or uops.
Storing already decoded instructions removes the IA-32 decoding from the main execution loop.
Typically the instructions are decoded once and placed in the Trace Cache and then used repeatedly from
there like a normal instruction cache on previous machines.
The IA-32 instruction decoder is only used when the machine misses the Trace Cache and needs to go to the
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L2 cache to get and decode new IA-32 instruction bytes.

Out-of-Order Execution Logic:

The out-of-order execution engine is where the instructions are prepared for execution.
The out-of-order execution logic has several buffers that it uses to smooth and re-order the flow of
instructions to optimize performance as they go down the pipeline and get scheduled for execution.
Instructions are aggressively re- ordered to allow them to execute as quickly as their input operands are
ready.
This out-of-order execution allows instructions in the program following delayed instructions to proceed
around them as long as they do not depend on those delayed instructions.
Out-of-order execution allows the execution resources such as the ALUs and the cache to be kept as busy
as possible executing independent instructions that are ready to execute.
The retirement logic is what reorders the instructions, executed in an out-of-order manner, back to the
original program order.
This retirement logic receives the completion status of the executed instructions from the execution units
and processes the results so that the proper architectural state is committed (or retired) according to the
program order.
The Pentium 4 processor can retire up to three uops per clock cycle.
This retirement logic ensures that exceptions occur only if the operation causing the exception is the
oldest, non-retired operation in the machine.
This logic also reports branch history information to the branch predictors at the front end of the machine
so they can train with the latest known-goodbranch-history information.

Integer and Floating-Point Execution Units:

The execution units are where the instructions are actuallyexecuted.
This section includes the register files that storethe integer and floating-point data operand values that the
instructions need to execute.
The execution units include several types of integer and floating-point execution units that compute the
results and also the L1 data cache that is used for most load and store operations.

Memory Subsystem:
Figure 1 also shows the memory subsystem. This includes the L2 cache and the system bus.
The L2 cache stores both instructions and data that cannot fit in the Execution Trace Cache and the L1
data cache.
The external system bus is connected to the backside of the second-level cache and is used to access main
memory when the L2 cache has a cache miss, and to access the system I/O resources.
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3. Translation Look-aside Buffer:

4. Hyper-Threading (HT)

Hyper-Threading (HT) concept was introduced by Intel on desktop CPUs with the Pentium 4 HT. Pentium 4
is a single CPU core and cannot perform multi-tasking and in order to address this situation, Hyper
threading allows the two logical CPU cores to share physical execution resources. HT enables multiple
threads which are sequences of instruction to be run by each core to make the CPU run more efficiently.
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Uses of Hyper-threading

When the hyper-threading is enabled, each logical core of processor can act independently and can be
interrupted, halted and operated separately from the other virtual processor sharing the same core. In this
process, when one logical core is idle, the second core can take over the resources of other logical core.
Hyper threading allows the processor to work on more instruction threads in a given time. Hyper threading is
a hardware-based virtualization at the processor hardware level. Applications that take benefit of hyper-
threading are heavy-duty audio/video transcoding apps and scientific applications built for maximum multi-
threaded performance. By using hyper-threading performance can be boost up to 30%.

How Hyper-Threading works

HT Technology is applied where multiple tasks are scheduled so that there will be no idle time on your
processor. Video editing, 3D rendering are examples of hyper-threading. Hyper Threading does not increase
the cores of processors; it will only help to handle the task efficiently. Hyper Threading technology enables
each core to run two threads at same time parallelly.

Hyper-Threading Performance

Hyper Threading increases the performance of CPU cores by enabling hyper-threading feature. Multiple
threads are sequences of the instructions to be run by each core to make the CPU operate more efficiently.
CPU can execute more tasks in the same amount of time. Hyper threading only helps to handle the
instructions. With Hyper Threading, the OS will recognize each physical core as 2 virtual or logical cores.
Eventually, Hyper threading virtually doubles the number of cores that are on the CPU. Dual-core processors
acts like a virtual quad-core processor.

Hyper-Threading Technology Benefits

Hyper Threading Technology improves the utilization of CPU resources so that a second thread can be
processed in the same processor. Hyper Threading provides two logical processors in a single processor
package. Hyper Threading Technology offers:

 Improved overall system performance.

 Increased number of users.
 Improved throughput because tasks run on different threads.
 Improved reaction and response time.
 Increased number of instructions that can be executed at a same time.
 Compatibility with existing IA-32 software.

Disadvantages of using Hyper threading

HT is responsible for generating extra heat. Cores are made to perform additional calculations per cycle,
which results in more leakage, consequently more heat, which negatively impacts overclocking.
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Pentium Processor

1. Features of Pentium:
 Introduced in 1993 with clock frequency ranging from 60 to 66 MHz
 It has data bus of 64 bit and address bus of 32-bit
 There are two separate 8kB caches – one for code and one for data.
 The primary changes in Pentium Processor were:
 Superscalar Architecture
 Dynamic Branch Prediction
 Pipelined Floating-Point Unit
 Separate 8K Code and Data Caches
 Writeback MESI Protocol in the Data Cache
 64-Bit Data Bus
 Bus Cycle Pipelining

2. Pentium Architecture:
University Question: Draw and explain Pentium Processor architecture. Highlight architectural features
 There are two separate 8kB caches – one for code and one for data. Each cache has a separate
address translation TLB which translates linear addresses to physical.
 Code Cache:
 2 way set associative cache
 256 lines b/w code cache and prefetch buffer, permitting prefetching of 32 bytes (256/8) of
instructions
 Prefetch Buffers:
 Four prefetch buffers within the processor works as two independent pairs.
▪ When instructions are prefetched from cache, they are placed into one set of prefetch buffers.
▪ The other set is used as when a branch operation is predicted.
 Prefetch buffer sends a pair of instructions to instruction decoder
 Instruction Decode Unit:
 It occurs in two stages – Decode1 (D1) and Decode2(D2)
 D1 checks whether instructions can be paired
 D2 calculates the address of memory resident operands

 Control Unit :
 This unit interprets the instruction word and microcode entry point fed to it by Instruction
Decode Unit
 It handles exceptions, breakpoints and interrupts.
 It controls the integer pipelines and floating point sequences
 Microcode ROM :
 Stores microcode sequences
 Arithmetic/Logic Units (ALUs) :
 There are two parallel integer instruction pipelines: u-pipeline and v-pipeline
 The u-pipeline has a barrel shifter
 The two ALUs perform the arithmetic and logical operations specified by their instructions in their
respective pipeline
 Address Generators :
 Two address generators (one for each pipeline) form the address specified by the ins tructions in
their respective pipeline.
 They are equivalent to segmentation unit.
 Paging Unit :
 If enabled, it translates linear address (from address generator) to physical address
 It can handle two linear addresses at the same time to support both pipelines with one TLB per
cache
 Floating Point Unit:
 It can accept upto two floating point operations per clock when one of the instruction is an
exchange instruction
 Three types of floating point operations can operate simultaneously within FPU: addition, divi sion
and multiplication.
 Data Cache:
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 It is an 8KB write-back , two way set associative cache with line size of 32 bytes
 Bus Unit:
 Address Drivers and Receivers:
 Push address onto the processor’s local address bus (A31:A3 and BE7:BE0)
 Data Bus Transceivers:
 gate data into the processor ‘s local data bus
 Bus Control Logic:
 controls whether a standard or burst bus cycle is to be run
 Branch Target Buffer: supplies jump target prefetch addresses to the code cache

3. Superscalar Operation:
UQ: Explain with block diagram how superscalar operation is carried out in Pentium Processor
• The prefetcher sends an address to code cache and if present, a line of 32 bytes is send to one of
the prefetch buffers
• The prefetch buffer transfers instructions to decode unit
• Initially it checks if the instructions can be paired.
• If paired, one goes to ‘u’ and other goes to ‘v’ pipeline as long as no dependencies exist between
them.
• Pair of instructions enter and exit each stage of pipeline in unison.
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• Pentium uses a five stage execution pipeline as shown:

4. Integer Pipeline:
UQ: Explain in brief integer instruction pipeline stages of Pentium
• The pipelines are called “u” and “v” pipes.
• The u-pipe can execute any instruction, while the v-pipe can execute “simple”
instructions as defined in the “Instruction Pairing Rules”.
• When instructions are paired, the instruction issued to the v -pipe is always the next sequential
instruction after the one issued to u-pipe.
 The integer pipeline stages are as follows:

Prefetch (PF):
 Instructions are prefetched from the on-chip instruction cache

Decode1 (D1):
 Two parallel decoders attempt to decode and issue the next two sequential instructions
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 It decodes the instruction to generate a control word

 A single control word causes direct execution of an instruction
 Complex instructions require microcoded control sequencing

Decode2 (D2):
 Decodes the control word
 Address of memory resident operands are calculated

Execute (EX):
 The instruction is executed in ALU
 Data cache is accessed at this stage
 For both ALU and data cache access requires more than one clock.

Writeback(WB):
 The CPU stores the result and updates the flags
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5. Integer Instruction Pairing Rules:

UQ: Explain the instruction pairing rules for Pentium
 To issue two instructions simultaneously they must satisfy the following conditions:
 Both instructions in the pair must be “simple”. Simple Instructions:
• They are entirely hardwired
• They do not require any microcode control
• Executes in one clock cycle
–Exception: ALU mem,reg and ALU reg,mem are 3 and 2 clock operations respectively
• The following integer instructions are considered simple and may be paired:
1. mov reg, reg/mem/imm 2. mov mem, reg/imm
3. alu reg, reg/mem/imm 4. alu mem, reg/imm
5. inc reg/mem 6. dec reg/mem
7. push reg/mem 8. pop reg
9. lea reg,mem 10. jmp/call/jc near
11. nop 12. test reg, reg/mem
13. test acc, imm
 There must be no read-after-write(R AW) or write-after-write register(WAW)
dependencies
RAW:
i1. R2 € R1 + R3 i2. R4 € R2 + R3
WAW:
i1. R2 € R4 + R7 i2. R2 € R1 + R3
 The two instructions should not have immediate values.
 Instruction with prefixes (lock,repne) can only occur in the u-pipe

6. Instruction Issue Algorithm:

UQ: List the steps in instruction issue algorithm
 Decode the two consecutive instructions I1 and I2

 If the following are all true:

 I1 and I2 are simple instructions
 I1 is not a jump instruction
 Destination of I1 is not a source of I2
 Destination of I1 is not a destination of I2
 Then issue I1 to u pipeline and I2 to v pipeline
 Else issue I1 to u pipeline

7. Floating Point Pipeline:

UQ: Explain the floating point pipeline stages.
 The floating point pipeline has 8 stages as follows:
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Prefetch(PF) :
 Instructions are prefetched from the on-chip instruction cache
Instruction Decode(D1):
 Two parallel decoders attempt to decode and issue the next two sequential instructions
 It decodes the instruction to generate a control word
 A single control word causes direct execution of an instruction
 Complex instructions require microcoded control sequencing
Address Generate (D2):
 Decodes the control word
 Address of memory resident operands are calculated
Memory and Register Read (Execution Stage) (EX):
 Register read, memory read or memory write performed as required by the instruction to access
an operand.
Floating Point Execution Stage 1(X1):
 Information from register or memory is written into FP register.
 Data is converted to floating point format before being loaded into the floating point unit
Floating Point Execution Stage 2(X2):
 Floating point operation performed within floating point unit.
Write FP Result (WF):
 Floating point results are rounded and the result is written to the target floating point register.
Error Reporting(ER)
 If an error is detected, an error reporting stage is entered where the error is reported and
FPU status word is updated.

8. Instruction Issue for Floating Point Unit:

The rules of how floating-point (FP) instructions get issued on the Pentium processor are :
 FP instructions do not get paired with integer instructions.
 When a pair of FP instructions is issued to the FPU, only the FXCH instruction can be the second
instruction of the pair.
 The first instruction of the pair must be one of a set F where F = [ FLD,FADD, FSUB, FMUL,
FDIV, FCOM, FUCOM, FTST, FABS, FCHS].
 FP instructions other than FXCH and instructions belonging to set F, always get issued
singly to the FPU.
 FP instructions that are not directly followed by an FXCH instruction are issued singly to the FPU.

9. Branch Prediction Logic:

UQ : Explain how the flushing of pipeline can be minimized in Pentium Architecture
 Performance gain through pipelining can be reduced by the presence of program transfer
instructions (such as JMP,CALL,RET and conditional jumps).
 They change the sequence causing all the instructions that entered the pipeline after program
transfer instruction invalid.
 Suppose instruction I3 is a conditional jump to I50 at some other address(target address), then
the instructions that entered after I3 is invalid and new sequence beginning with I50 need to be loaded in.
 This causes bubbles in pipeline, where no work is done as the pipeline stages are reloaded.
 To avoid this problem, the Pentium uses a scheme called Dynamic Branch Prediction.
 In this scheme, a prediction is made concerning the branch instruction currently in pipeline.
 Prediction will be either taken or not taken.
 If the prediction turns out to be true, the pipeline will not be flushed and no clock cycles will be
lost.
 If the prediction turns out to be false, the pipeline is flushed and started over with the correct
instruction.
 It results in a 3 cycle penalty if the branch is executed in the u-pipeline and 4 cycle penalty in
v-pipeline.
 It is implemented using a 4-way set associative cache with 256 entries. This is referred to as
the Branch Target Buffer(BTB).
 The directory entry for each line contains the following information:
 Valid Bit : Indicates whether or not the entry is in use
 History Bits: track how often the branch has been taken
 Source memory address that the branch instruction was fetched from (address of I3)
 If its directory entry is valid, the target address of the branch is stored in corresponding
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data entry in BTB

 BTB is a look-aside cache that sits off to the side of D1 stages of two pipelines and
monitors for branch instructions.
 The first time that a branch instruction enters either pipeline, the BTB uses its source memory
address to perform a lookup in the cache.
 Since the instruction has not been seen before, this results in a BTB miss.
 It means the prediction logic has no history on instruction.
 It then predicts that the branch will not be taken and program flow is not altered.
 Even unconditional jumps will be predicted as not taken the first time that they are seen by BTB.
 When the instruction reaches the execution stage, the branch will be either taken or not
taken.

 If taken, the next instruction to be executed should be the one fetched from branch target
address.

 If not taken, the next instruction is the next sequential memory address.
 When the branch is taken for the first time, the execution unit provides feedback to the branch
prediction logic.
 The branch target address is sent back and recorded in BTB.
 A directory entry is made containing the source memory address and history bits set as
strongly taken

History Bits Resulting Prediction If branch is If branch is

Description Made taken not taken
11 Strong ly Taken Branch Taken Remains Downgrades to
Strongly Weakly
Taken Taken

10 Weakly Taken Branch Taken Upgrades to Downgrades to

Strongly Weakly
Taken Not Taken

01 Weakly Not Branch Not Upgrades to Downgrades to

Taken Taken Weakly Strongly
Taken Not Taken

00 Strong ly Not Branch Not Upgrades to Remains

Taken Taken Weakly Strongly Not
Not Taken Taken

10. Cache organization :

UQ: Explain the cache organization of Pentium Processor
 The Pentium processor implements two internal caches for a total integrated cache size of 16
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Kbytes: an 8 Kbyte data cache and a separate 8 Kbyte code cache.

 These caches are transparent to application software to maintain compatibility with
previous Intel Architecture generations.
 The data cache fully supports the MESI (modified/exclusive/shared/invalid) writeback cache
consistency protocol.
 The code cache is inherently write protected to prevent code from being inadvertently
corrupted, and as a consequence supports a subset of the MESI protocol, the S(shared) and I (invalid) states.

 The caches have been designed for maximum flexibility and performance. The data cache is
configurable as writeback or writethrough on a line-by-line basis.
 Memory areas can be defined as non-cacheable by software and external hardware. Cache
writeback and invalidations can be initiated by hardware or software.
 On the Pentium processor, each of the caches are 8 Kbytes in size and each is organized as a 2-
way set associative cache. There are 128 sets in each cache, each set containing 2 lines (each line has its
own tag address). Each cache line is 32 bytes wide.

 In the Pentium processor, replacement in both the data and instruction caches is handled by the
LRU mechanism which requires one bit per set in each of the caches.
 The instruction and data caches can be accessed simultaneously. The instruction cache can
provide up to 32 bytes of raw opcodes and the data cache can provide data for two data references all in
the same clock.
 This capability is implemented partially through the tag structure. The tags in the data cache are
triple ported. One of the ports is dedicated to snooping while the other two are used to lookup two
independent addresses corresponding to data references from each of the pipelines.
 The instruction cache tags of the Pentium processor are also triple ported. Again, one port
is dedicated to support snooping and the other two ports facilitate split line accesses
(simultaneously accessing upper half of one line and lower half of the next line).
 The storage array in the data cache is single ported but interleaved on 4-byte boundaries to be
able to provide data for two simultaneous accesses to the same cache line.
 Each of the caches are parity protected. In the instruction cache, there are parity bits on a
quarter line basis and there is one parity bit for each tag.
 The data cache contains one parity bit for each tag and a parity bit per byte of data.

Instruction cache Data cache

Directory Entry P Tag/Page(A31:A12) S/I P Tag/Page(A31:A12) MESI
structure states

Cache Line P QW P QW P QW P QW DW DW DW DW DW DW DW DW
structure
------ Each DW has:
P Byte P Byte P Byte P Byte
32 bit address tag/page (20 Index (7 Byte (5bits) Tag/page Line Bank XX
interpretation bits) bits) (20 bits) (7 bits) select (3 (2 bits)
bits)
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 Each of the caches are accessed with physical addresses and each cache has its own TLB
(translation lookaside buffer) to translate linear addresses to physical addresses. The TLBs associated with
the instruction cache are single ported whereas the data cache TLBs are fully dual ported to be able to
translate two independent linear addresses for two data references simultaneously.
 The tag and data arrays of the TLBs are parity protected with a parity bit associated with each of
the tag and data entries in the TLBs.
 The data cache of the Pentium processor has a 4-way set associative, 64-entry TLB for 4- Kbyte
pages and a separate 4-way set associative, 8-entry TLB to support 4-Mbyte pages.
 The code cache has one 4-way set associative, 32-entry TLB for 4-Kbyte pages and 4-Mbyte pages
which are cached in 4-Kbyte increments.
 Replacement in the TLBs is handled by a pseudo LRU mechanism (similar to the Intel486 CPU)
that requires 3 bits per set.

11. MESI Model ( Cache Consistency Protocol):

UQ: Explain the cache consistency protocol of Pentium Processor
Cache consistency on the Pentium processor is maintained using the MESI protocol. The protocol is used to
decide if a cache entry should be updated or invalidated
The data cache supports the Cache Consistency Protocol, which is a set of rules by which states are assigned
to cached entries or lines. The protocol consists of four states that define whether a line is valid (HIT or
MISS), if it is available in other caches, and if it has been modified. The four states, which make up what is
referred to as the MESI protocol, are the M (Modified), E (Exclusive), S (Shared) and the I (Invalid) states.
The following is a description of each state:
 An M-state line is modified meaning that it is different from main memory. An M -state line can also
be accessed (read/written to) without sending a cycle out on the bus.
 An E-state line is not modified. An E-state line can also be accessed (read/written to) without
generating a bus cycle, with a write causing the line to become modified.
 An S-state indicates that the line is potentially shared with other caches meaning that the same
line may exist in more than one cache. Reading from this line does not generate bus activity however a
write will generate a write-through cycle on the bus and may also invalidate this line in other caches. A
write to an S-state line updates the cache.
 An I-state indicates that the line is not available in cache. Reading from this line may cause a MISS
and cause the processor to execute a LINE FILL where the whole line is fetched from main memory and
placed back into cache. Writing to an INVALID line causes the processor to execute a write-through cycle on
the bus.

The other piece of L1 cache, the code side, supports a subset of the MESI protocol, the S (Shared) and I
(Invalid) states in order to prevent code from accidentally being corrupted since it is inherently write
protected.