Memory Modeling
How to Model Memory?
• Memory is typically included by instantiating a pre‐designed module from a
design library.
• Alternatively, we can model memories using two‐dimensional arrays.
• Array of register variables (behavioural model).
• Mainly used for simulation purposes.
• Even used for the synthesis of small‐size memories.
Memory Modeling
• Behavioral models of memories are modeled by declaring an array of register
variables; any word in the array may be accessed using an index into the array.
• A temporary variable is required to access a discrete bit within the array.
Syntax: reg [wordsize:0] array_name [0:arraysize]
Declaration: reg [7:0] my_memory [0:255];
Storing Values: my_memory[address] = data_in;
Reading Values: data_out = my_memory[address];
Example
module memory_model ( …….. )
…
reg [7:0] mem [0:1023];
…
endmodule
module memory_model ( …….. )
reg [7:0] mem [0:1023];
initial begin Each memory word is of type
mem[0] = 8’b01001101; [7:0], i.e. 8 bits.
mem[4] = 8’b00000000; • The memory words can be accessed as
end mem[0], mem[1], …, mem[1023].
endmodule
Initializing Memory from File
• Verilog provides a very useful system task to initialize memories from a data file.
• Two tasks are provided to read numbers in binary or hexadecimal format.
• Keywords $readmemb and $readmemh are used to initialize memories.
Syntax - $readmemb
Usage:
$readmemb("<file_name>", <memory_name>);
$readmemb("<file_name>", <memory_name>, <start_addr>);
$readmemb("<file_name>", <memory_name>, <start_addr>,<finish_addr>);
• The <file_name> and <memory_name> are mandatory;
• <start_addr> and <finish_addr> are optional.
• Defaults are start index of memory array for <start_addr> and end of the data file or memory for
<finish_addr>.
$readmemb- Example
module readmem_test;
reg [7:0] memory [0:7];
integer n;
initial begin
$readmemb("D:/Academics/verilog/Verilog Examples/System Task/init.dat",memory);
for (n=0; n<8; n=n+1)
$display("%b", memory[n]);
end
endmodule
$readmemb- Example
• The file init.dat contains the initialization data.
• Addresses are specified in the data file with
@<address>. A sample file, init.dat, is shown below.
• Addresses are specified as hexadecimal numbers. @002
• Data is separated by whitespaces. 11111111
• Data can contain x or z. 01010101
00000000
• Uninitialized locations default to x. 10101010
@006
1111zzzz
00001111
When the test module is simulated, we will get the following output:
Memory [0] = xxxxxxxx Memory [1] = xxxxxxxx Memory [2] = 11111111 Memory [3] = 01010101
Memory [4] = 00000000 Memory [5] = 10101010 Memory [6] = 1111zzzz Memory [7] = 00001111
Single‐port RAM with synchronous read/write
module ram_1 (addr, data, clk, rd, wr, cs);
input [9:0] addr; input clk, rd, wr, cs;
inout [7:0] data;
reg [7:0] mem [1023:0];
reg [7:0] d_out;
assign data = (cs && rd) ? d_out : 8’bz;
always @(posedge clk)
if (cs && wr && !rd)
mem[addr] = data;
always @(posedge clk)
if (cs && rd && !wr)
d_out = mem[addr];
endmodule
Single‐port RAM with asynchronous read/write
module ram_2 (addr, data, rd, wr, cs);
input [9:0] addr; input rd, wr, cs;
inout [7:0] data;
reg [7:0] mem[1023:0]; reg [7:0] d_out;
assign data = (cs && rd) ? d_out : 8’bz;
always @(addr or data or rd or wr or cs)
if (cs && wr && !rd)
mem[addr] = data;
always @(addr or rd or wr or cs)
if (cs && rd && !wr)
d_out = mem[addr];
endmodule
An Important Point to Note
• Some simulation or synthesis tools give inconsistent behaviour when using the
“inout” data type.
– Such “inout” bidirectional data should be avoided.
• A better way to design a memory unit is to keep the data input and data output
bus signal lines separate.
DUAL PORT RAM ‐ Example
module ram_3 (data_out, data_in, addr, wr, cs);
parameter addr_size = 10, word_size = 8,memory_size = 1024;
input [addr_size-1:0] addr;
input [word_size-1:0] data_in;
input wr, cs;
output [word_size-1:0] data_out;
reg [word_size-1:0] mem [memory_size-1:0];
assign data_out = mem[addr];
always @(wr or cs)
if (wr)
mem[addr] = data_in;
endmodule
Reference
• Dr. S. Ramachandran, “Digital VLSI Systems Design - A Design Manual for Implementation of Projects on
FPGAs and ASICs Using Verilog”
