IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 12, NO.

2, JUNE 2012 357

Enhanced Detection of Double and Triple Adjacent

Errors in Hamming Codes Through
Selective Bit Placement
Alfonso Sánchez-Macián, Member, IEEE, Pedro Reviriego, Member, IEEE, and
Juan Antonio Maestro, Member, IEEE

Abstract—Hamming codes that can correct one error per word read. Therefore, the encoding and decoding latency directly
are widely used to protect memories or registers from soft errors. impact the memory access time. To minimize this effect ECCs
As technology scales, radiation particles that create soft errors for which decoding is simple are used in most cases. One
are more likely to affect more than 1 b when they impact a
memory or electronic circuit. This effect is known as a multiple example of codes for which decoding can be done with low
cell upset (MCU), and the registers or memory cells affected by delay is Single Error Correction (SEC) codes. SEC codes have
an MCU are physically close. To avoid an MCU from causing a minimum distance of three and therefore a double error can
more than one error in a given word, interleaving is commonly be mistaken for a single error and erroneously corrected. To
used in memories. With interleaving, cells that belong to the same avoid this issue Single Error Correction Double Error Detec-
logical word are placed apart such that an MCU affects multiple
bits but on different words. However, interleaving increases the tion (SEC-DED) codes are preferred in memory applications
complexity of the memory device and is not suitable for small [3], these codes have a minimum distance of four. There are
memories or content-addressable memories. When interleaving is different options for SEC-DED codes that reduce slightly the
not used, MCUs can cause multiple errors in a word that may not implementation cost [7] or the miscorrection probability for
even be detected by a Hamming code. In this paper, a technique triple errors [8]. In any case, Hamming codes are attractive
to increase the probability of detecting double and triple adjacent
errors when Hamming codes are used is presented. The enhanced as they are simple to construct for any word length and the
detection is achieved by placing the bits of the word such that encoding and decoding can be done with low delay. Hamming
adjacent errors result in a syndrome that does not match that of codes are SEC codes and can be extended with a parity bit
any single error. Double and triple adjacent errors are precisely covering all bits to implement a SEC-DED code [1]. Therefore,
the types of errors that an MCU would likely cause, and therefore, they are suitable for memory applications and also to protect
the proposed scheme will be useful to provide error detection for
MCUs in memory designs. registers in digital circuits.
However, as technology scales, it is more likely that a ra-
Index Terms—Error correction codes (ECCs), Hamming codes, diation particle upsets more than one memory cell or register
memory, multiple cell upsets (MCUs).
causing multiple errors [9]. This is known as a Multiple Cell
Upset [10]. The cells affected by the MCU are physically close
I. I NTRODUCTION
and in many cases adjacent [11]. This is because errors are

H AMMING codes were introduced more than 60 years

ago [1] and they are still used in many applications.
One example is the protection of memories or registers against
created along the path that the particle traverses. MCUs can
therefore cause multiple errors on a given word causing a failure
even when a SEC-DED code is used. This can be avoided by
radiation induced soft errors [2]. A soft error occurs when a using interleaving which places the bits of a word physically
radiation particle hits the device and changes the logical value apart such that an MCU can only affect one bit per word [12],
of a memory cell or register. Error Correction Codes (ECCs) [13]. An issue is that interleaving makes the design more com-
are used to prevent soft errors from causing data corruption plex and can impact area and power consumption [12]. In other
in memories and registers [3], [4]. The codes used range from cases, such as small memories or content-addressable memories
simple codes such as Hamming to more powerful and complex (CAMs) interleaving cannot be used or is not practical [14],
codes like Bose–Chaudhuri–Hocquenghem (BCH) and Euclid- [15]. When interleaving is not used, MCUs will cause adjacent
ean Geometry (EG) codes [5], [6]. In all cases, the data is errors. In that case SEC codes can cause an erroneous correction
encoded when it is written into the memory and decoded when when two adjacent bits are in error while SEC-DED codes can
cause an erroneous correction when three adjacent bits are in
error. In both cases, that would lead to Silent Data Corruption
Manuscript received December 7, 2011; revised January 17, 2012; accepted (SDC) where the system is unaware that an error has occurred
January 30, 2012. Date of publication February 6, 2012; date of current version
June 6, 2012. This work was supported by the Spanish Ministry of Science and and continues its operation. This can lead to an incorrect system
Innovation under Grant AYA2009-13300-C03-01. behavior and further data corruption.
The authors are with the Universidad Antonio de Nebrija, 28040 In this paper, a technique to maximize the probability that
Madrid, Spain (e-mail: [email protected]; [email protected]; jmaestro@
nebrija.es). a Hamming code detects double adjacent errors and that a
Digital Object Identifier 10.1109/TDMR.2012.2186965 parity extended Hamming code detects triple adjacent errors

1530-4388/$31.00 © 2012 IEEE

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358 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 12, NO. 2, JUNE 2012

TABLE I TABLE III

H AMMING C ODES PARAMETERS G ENERATION A LGORITHM FOR H AMMING C ODE (7, 4)

An algorithm to generate Hamming code words from infor-

mation bits is as follows: a) positions are numbered from 1 to
TABLE II n; b) positions are written in their binary form (1, 10, 11, etc.);
S HORTENED H AMMING C ODES PARAMETERS
c) bits in positions 2r are parity bits for those other positions
where the binary form of those positions has the bit r + 1 set
to one. For instance, in the Hamming code (7,4) with n = 7,
k = 4 and m = 3, positions c1, c2 and c4 are parity bits (p1, p2
and p3) and the information bits (d1, d2, d3 and d4) are placed
in order in the rest of positions as shown in Table III.
Parity bits are calculated as follows:
c1 = c3 + c5 + c7 or p1 = d1 + d2 + d4
is presented. This is achieved by placing the bits of the word c2 = c3 + c6 + c7 or p2 = d1 + d3 + d4
such that those adjacent errors provoke a syndrome value that
c4 = c5 + c6 + c7 or p3 = d2 + d3 + d4.
is different from those caused by single errors. The results show
that the detection of such adjacent errors can be close to 100% As an example, with this scheme the code word for data bits
in some cases. Therefore, the proposed technique can be useful (1 0 1 0) is (1 0 1 1 0 1 0). This approach can be represented as
to avoid SDC in the presence of MCUs. a non-canonical generator matrix where rows are relocated to
The rest of the paper is organized as follows Section II place the bits in the appropriate position.
presents an overview of Hamming codes. In Section III the In order to check the code word, the parity bits can be re-
detection of double and triple errors in Hamming codes is calculated again from the information bits and compared to the
discussed. Then in Section IV the Selective Bit Placement original set of parity bits. If they match, then no error was intro-
strategy to enhance the detection of adjacent double and triple duced (or it is not detected), otherwise, an error is detected and
errors is presented. The proposed approach is validated with the non-matching parity bits can provide us with the informa-
results for different word sizes in Section V. The conclusions in tion of the bit that was flipped so that the error can be corrected.
Section VI end the paper. From a linear algebra approach, the parity-check matrix can
be used to detect an error. The product of this matrix by
the current value of the code word results in a vector called
II. H AMMING C ODES
syndrome. If this vector is the null vector, then the current value
Hamming codes are linear block error-correcting codes that of the word is an actual code word. In any other case, an error
were proposed by R.W. Hamming [1]. They provide single error occurred in the code word.
correction or double error detection. For any positive integer There is a special parity-check matrix where column i con-
m ≥ 3 they have the following parameters [16]: tains the binary representation of i. It is called the lexicographic
check matrix. The lexicographic matrix for the shortened Ham-
n = 2m − 1 ming code (12, 8) is shown in
k =n − m ⎛ ⎞
0 0 0 0 0 0 0 1 1 1 1 1
dmin = 3 (1) ⎜0 0 0 1 1 1 1 0 0 0 0 1⎟
HLex =⎝ ⎠. (2)
0 1 1 0 0 1 1 0 0 1 1 0
where n is the block size, m the parity check bits, k the
1 0 1 0 1 0 1 0 1 0 1 0
number of information bits and dmin the minimum distance
of the code. The parity bits are organized in a special way If a single bit error occurs in the code word, the syndrome
so different incorrect bits produce different error results when vector that results from the product of the lexicographic matrix
decoding. Some possible values of the parameters are illustrated with the error code word gives the binary representation of the
in Table I. For memory applications, the number of information position where the error was inserted. Using as an example
bits k is commonly a power of two and Hamming codes are Hamming code (12, 8), data bits (01010100) are coded as
shortened to fit that word length as illustrated in Table II. (000010110100). When an error occurs and, for instance, the
Hamming codes are linear codes and, consequently, can be third bit is changed the code word turns into (001010110100).
generated and decoded using the generator and parity-check The product of this vector by the lexicographic check matrix
matrices, respectively. These matrices have a canonical form, results in the syndrome vector (1100) corresponding to the
but also equivalent non-systematic code matrices can be ob- binary representation of three (note that the bits are placed with
tained by column permutations and other row operations. the most significant bit to the right as shown in Table III).

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SÁNCHEZ-MACIÁN et al.: DETECTION OF DOUBLE AND TRIPLE ERRORS IN HAMMING CODES 359

A Hamming code can be used to correct single errors or, the lexicographic check matrix, it results in a syndrome vector
alternatively, to detect single and double errors. As the mini- (1011), which is the binary value of position 13. It cannot be
mum distance between two words is three, it is not possible to corrected as it does not match a valid code bit position.
distinguish between single and double errors. Coming back to In Hamming (13, 8) a triple error in the code bits is usually
the previous example, if there is a double error in the original detected as a single error and corrected erroneously. However,
word in positions 3 and 4 we get the vector (001110110100). some triple error combinations are detected without correc-
Syndrome in this case is (1110) corresponding to the binary tion. In the example, when changing bits 1, 7 and 11 in the
representation of 7. In this case, code word would be corrected original word (0000101101000) produces the erroneous word
into (001110010100) instead of the right word. (1000100101100). If the parity bit is excluded and the lexico-
An option is to use an extended version of the Hamming graphic check matrix from the original Hamming code is used,
code that includes an additional parity bit that covers all the the syndrome vector is (1011) instead of the null vector. It is not
bits in the code word. This solution increases the minimum corrected as the syndrome value does not correspond to that of
distance to four and allows performing single error correction any single error, therefore there are at least two bits in error.
and double error detection (SEC-DED) simultaneously. Alter- These special combinations of double and triple bit errors
natively, it can be used to detect triple errors. In this case, are randomly distributed through the code word and only a
the extended Hamming code (13, 8) encodes (01010100) into small subset of them includes adjacent bits. As MCUs typically
(0000101101000). The double error in positions 3 and 4 turns cause errors in adjacent bits, most of double and triple bit errors
the code word into (0011101101000). This produces a no zero caused by them are miscorrected.
valid syndrome with no error in the parity bit. Therefore, a From the previous discussion it becomes apparent that by
double error is detected and no correction is done since single changing the bit placement, the probability of double or triple
errors have a valid syndrome and error in the parity bit. adjacent error detection can be maximized. For instance, a
With a minimum distance of 4, a triple error in the extended simultaneous error in positions 1 and 12 in the Hamming (12,
Hamming code can be miscorrected. In the previous example, 8) code is detected and no correction is performed. So we can
errors in bits 3, 4 and 7 produce a zero syndrome and error in reorder the code word to place together these two bits. Simi-
the parity bit. This would be interpreted as a single error in the larly, for the extended Hamming (13, 8) code, errors in bits 1, 7
parity bit and miscorrected. and 11 are also detected appropriately. Thus, we can place them
next to each other in any possible way (e.g., 11, 1 and then 7).
This idea is studied in more detail in the following sections.
III. D OUBLE AND T RIPLE B IT E RROR D ETECTION
W ITH S HORTENED H AMMING C ODES
As pointed out in the previous section, it is possible to correct IV. S ELECTIVE B IT P LACEMENT S TRATEGY
a single error with Hamming codes. However, when a double As pointed out before, there are special combinations of
error occurs, the algorithm miscorrects the code word. double and triple bit errors that are detected and not miscor-
To avoid this problem, the extended version of Hamming rected in the shortened Hamming code and the parity extended
which includes an additional parity bit and increases the dis- version, respectively. The bit positions for those combinations
tance from 3 to 4 can be used. Unfortunately, if a triple error are randomly distributed through the word. The objective is to
occurs with this approach, it is also miscorrected. reorder the bits of the code word to maximize the adjacency of
As discussed before, for memory applications, the number the special combinations.
of data bits (k) is typically a power of two such that short- To achieve this goal, the following procedure is followed:
ened codes are used (See Table II). These shortened versions • Using a software program, find all double and triple error
of Hamming codes have a special behavior. There are some combinations which produce a syndrome that does not
double error combinations that are detected and not erroneously match any of the ones caused by a single error.
corrected. Additionally, some triple errors combinations do not • Reorder the word manually to maximize the number of
generate a valid word and, therefore, can be detected as well adjacent bits matching the error combinations found in the
and not miscorrected when using the extended Hamming code. previous stage.
This feature comes from the fact that these errors generate a
To find all the possible combinations of special double and
new word which is 2 bits away from a valid code word. Coming
triple error bits, the program executes the following steps:
back to the Lexicographic check matrix and the syndrome
calculation and focusing on shortened Hamming codes, code • A code word from a Hamming code is selected.
words with errors can generate syndrome vectors which do not • All 2-error and 3-error combinations of this code word are
correspond to a code position due to shortening. generated.
The syndrome vector in the Hamming (12, 8) example shown • The error words generated in the previous step are multi-
in the previous section has 4 bits. So its maximum value is plied by the lexicographic check matrix.
15, but there are only 12 positions in the shortened code. If • Those bit error combinations producing a word with a
a syndrome of 13, 14, or 15 is found, the error is detected, syndrome higher than the maximum bit position of the
but not corrected. For instance, when there is a double error code are selected.
in the code word (000010110100) affecting positions 1 and 12, • Positions are printed out.
the error word is (100010110101). When it is processed with The detailed procedure is presented in Fig. 1.

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360 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 12, NO. 2, JUNE 2012

TABLE VI
S UGGESTED B IT P LACEMENTS

TABLE VII
S UMMARY OF R ESULTS

Fig. 1. Selective bit placement strategy procedure. the proposed order, all adjacent bits match the special error
combinations except 2–4-p and p-10–12, resulting in 9 out of
TABLE IV 11 triple adjacent errors detected and not miscorrected.
D OUBLE A DJACENT E RROR D ETECTION FOR H AMMING (12, 8)
The results for the Hamming (12, 8) and the parity ex-
tended Hamming (13, 8) codes show how the selective bit
placement strategy can increase significantly the detection of
double adjacent errors in Hamming codes and triple adjacent
errors in parity extended Hamming codes. In the next section,
TABLE V further results are presented for different word sizes to provide
T RIPLE A DJACENT E RROR D ETECTION FOR H AMMING (13, 8)
a comprehensive evaluation of the technique.

V. S IMULATION R ESULTS
The same procedure has been applied to Hamming codes
(21, 16), (38, 32) and the extended versions (22, 16) and
Using this program for the Hamming(12, 8) code, the follow- (39, 32). Suggested bit placements are presented in Table VI to
ing special two bit error combinations are found: 1–12, 2–12, reduce the number of miscorrected multiple adjacent errors for
3–12, 4–9, 4–10, 4–11, 5–8, 5–10, 5–11, 6–8, 6–9, 6–11, 7–8, these codes. P stands for the additional parity bit in the extended
7–9 and 7–10. The only combination including adjacent bits Hamming. Results in terms of number of combinations detected
is 7–8 so only 1 of the 11 adjacent pairs are correctly detected and not miscorrected when adjacent errors occur are presented
when using the normal order. With this information, a new order in Table VII.
is proposed in Table IV. All adjacent bits match the special There is a particular characteristic of the special combi-
error combinations except 2–3 and 3–6, resulting in 9 out of nations introduced in Section III that deserves attention. As
11 double adjacent errors detected and not miscorrected. pointed out before, when checking these combinations against
There are 49 special three bit error combinations for the the lexicographic check matrix, they produce a syndrome cor-
Hamming (12, 8) code. These combinations do not cause a responding to positions that do not exist in the code. All these
miscorrection in the extended Hamming (13, 8) code. Only positions are higher than the existing ones and have the most
one of them (10–11–12) is composed by adjacent bits in the significant bit (MSB) set. Taking a look to the lexicographic
default code word order. A new order is suggested in Table V matrix, to be able to generate this kind of positions it is neces-
where p is the additional parity bit. It is important to point out sary that at least one of the errors affects a bit position with the
that, apart from these triplets, any combination of the parity bit MSB set. For instance, the row generating the syndrome vector
with one of the duplets used in Hamming (12, 8) are correctly MSB bit from the lexicographic check matrix for Hamming
detected as well without miscorrection (e.g., 4-p-10). With (12, 8) presented in Section II is (000000011111). If an error

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SÁNCHEZ-MACIÁN et al.: DETECTION OF DOUBLE AND TRIPLE ERRORS IN HAMMING CODES 361

TABLE VIII bits in the memory such that adjacent errors produce a syn-
N UMBER OF E RRORS C OMBINATIONS AND U PPER B OUND
drome that does not match any of those that correspond to
a single error. The proposed approach has been implemented
and tested for different word sizes showing that it can be
effective, achieving in some cases a large error detection rate
for double and triple adjacent errors. The proposed scheme
does not require any additional circuitry. Since the method only
reorders the way in which the bits are stored in the memory
there are no implementation penalties. The memory area, power
and speed will be the same as with the traditional bit placement.
It can be used to detect errors caused by Multiple Cell Upsets
occurs in any of the seven first positions of the code word, (MCUs) that tend to affect adjacent cells, reducing the overall
where this row has 0 values, no consequences are shown in the probability of miscorrection for double and triple errors when
syndrome MSB. One of the positions eight (1000) to twelve MCUs are present.
(1100), i.e., those with the MSB set, has to be part of the Future work will study the application of the proposed
combination. scheme to other Single Error Correction (SEC) and Single
Taking this property into account, an upper bound on the Error Correction Double Error Detection (SEC-DED) codes. In
number of adjacent combinations not miscorrected can be principle since error detection is also based on the syndrome
defined for every code. To maximize the detection, for every computation, selective bit placement can also be used to en-
two or three successive bits one and only one of them should hance adjacent error detection in those codes.
correspond to a position with the MSB set. In the Hamming
(12, 8) there are five positions fulfilling this requirement, so
there is a maximum of 10 (5 ∗ 2) two bit adjacent errors and R EFERENCES
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362 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 12, NO. 2, JUNE 2012

Alfonso Sánchez-Macián (M’11) received the Juan Antonio Maestro (M’07) received the M.Sc.
M.Sc. and Ph.D. degrees in telecommunications degree in physics and the Ph.D. degree in com-
engineering from the Universidad Politécnica puter science from the Universidad Complutense
de Madrid, Madrid, Spain, in 2000 and 2007, de Madrid, Madrid, Spain, in 1994 and 1999,
respectively. respectively.
He has worked as a Lecturer and a Researcher at He has served both as a Lecturer and a Researcher
several universities, such as the Universidad Politéc- at several universities, such as the Universidad Com-
nica de Madrid; the IT Innovation Centre, Univer- plutense de Madrid; the Universidad Nacional de
sity of Southampton, Southampton, U.K.; and the Educación a Distancia (Open University), Madrid;
Universidad Antonio de Nebrija, Madrid, where he Saint Louis University, Madrid; and the Universi-
currently manages the IT Department. He previously dad Antonio de Nebrija, Madrid, where he currently
worked in numerous national and multinational companies as the Project manages the Computer Architecture and Technology Group. His current ac-
Manager and a Senior Consultant for IT projects. His current research interests tivities are oriented to the space field, with several projects on reliability and
include fault tolerance and reliability, performance evaluation of communi- radiation protection, as well as collaborations with the European Space Agency.
cation networks, and knowledge representation and reasoning in distributed Aside from this, he has worked for several multinational companies, man-
systems. aging projects as a Project Management Professional and organizing support
departments. He is the author of numerous technical publications, both in
journals and international conferences. His areas of interest include high-level
Pedro Reviriego (A’03–M’04) received the M.Sc. synthesis and cosynthesis, signal processing, real-time systems, fault tolerance,
and Ph.D. degrees (with honors) in telecommu- and reliability.
nications engineering from the Technical Univer-
sity of Madrid, Madrid, Spain, in 1994 and 1997,
respectively.
From 1997 to 2000, he was an R&D Engineer with
Teldat, Madrid, working on router implementation.
In 2000, he joined Massana to work on the devel-
opment of 1000BaseT transceivers. During 2003, he
was a Visiting Professor at the Universidad Carlos
III de Madrid, Leganés, Spain. From 2004 to 2007,
he was a Distinguished Member of the technical staff with LSI Corporation,
working on the development of Ethernet transceivers. He is currently with the
Universidad Antonio de Nebrija, Madrid. He is the author of numerous papers
in international conference proceedings and journals. He has also participated
in the IEEE 802.3 standardization for 10 GBaseT. His research interests include
fault-tolerant systems, performance evaluation of communication networks,
and the design of physical-layer communication devices.

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