DEPARTMENT OF

ELECTRONICS AND COMMUNICATION ENGINEERING

SUBJECT: VLSI DESIGN

III BTECH I SEM ECE

UNIT I
Lecture-11: “Determination of pull-up to pull-down ratio
(Zp.u/Zp.d) for an NMOS inverters”

By
Y.Pradeep
Associate Professor

1
Review of Previous Lecture
NMOS Inverter

2
 Agenda
Determination of pull-up to pull-down ratio (Zp.u/Zp.d) for an
NMOS inverter driven by another NMOS Inverter

Pull-up to pull-down ratio (Zp.u / Zp.u ) for an NMOS inverter

driven through one or more pass transistors

3
 Determination of pull-up to pull-down ratio(Zp.u/Zp.d) for an
NMOS inverter driven by another NMOS inverter

Consider the arrangement shown below in which an inverter driven

from the o/p of another similar inverter.

When cascading logic devices care must be taken to preserve integrity of

logic levels
i.e. design circuit so that Vin = Vout = Vinv

Vin = Vout = Vinv ,where Vinv = 0.5VDD

Depletion mode Transistor Vgs = 0 under all conditions.
4
 Vin = Vout = Vinv
VDD VDD

Vout Vin
o/p
Vin

Depletion NMOS as a load and

enhancement mode NMOS as as a driver
- NMOS inverters 5
Assume equal margins around inverter; Vinv = 0.5 Vdd
Both transistors of NMOSinverter are in saturation

W (Vgs − Vt )
2
Ids =K
L 2
for depletion mode transistor V gs = 0, V t = V td

Wp.u ( − Vtd ) 2
∴ Ids = K
L p.u 2

for enhancement mode transistor V gs = V inv

Wp.d (Vinv − V ) 2
Ids = K t
L p.d 2
6
Since currents are same

K
W p.d (V −V )2
inv t = K
W p.u ( −Vtd )2

L p.d 2 L p.u 2
(Convention Z = L/W)
L p.d L p.u
where Z p.d = , Z p.u = ,
W p.d W p.u

1 1
∴ Vinv −Vt


 2

= 

−Vtd  2

Z p.d Z p.u
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 = Vt − V td
V inv
Z p.u Z p.d
Substitute in typical values
V t = 0.2V DD , V td = − 0.6V DD , V inv = 0.5V DD

0.6
∴ 0.5 = 0.2 +
Z p.u Z p.d

or Z p.u Z p.d = 2

or Z p.u Z p.d = 4 1
“An inverter driven directly from the o/p of another should have a
Zp.u/Zp.d ratio of ≥4/1.” 8
 Pull-up to pull-down ratio(Zp.u / Zp.u ) for an NMOS inverter
driven through one or more pass transistors
It is often the case that two inverters are connected via a series of switches (Pass
Transistors)
We are concerned that connection of transistors in series will degrade the logic
levels into Inverter 2.

Consider the arrangement shown below. All pass transistor gates connected
to VDD so there is a loss of Vtp i.e Vin2 = VDD – Vtp. (Vtp = pass transistor Vt )

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 VDD VDD
VDD
VDD

o/p
i/p i/p

NMOS inverters

10
 VDD VDD
VDD
VDD

o/p
o/p
i/p
i/p

NMOS inverter NMOS inverter

11
 VDD VDD
VDD
VDD

o/p
i/p i/p

NMOS inverters

12
13
Consider inverter1:
Case1: Pull up Transistor, It is a D-NMOSFET where Vgs =0
So it is operated directly in saturation region.

  
2

p.u1 
W Vgs −V
I1=Ids-saturation= K
t
 
 
L
p.u1 2 
 
but Vgs = 0 & Vt = Vtd
( − )2
W
∴I1= K p.u1 Vtd 
Lp.u1 2 

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Case2:Pull down Transistor, It is a E-NMOSFET where
i/p = VDD 1st operated in resistive region where Vds1 < VDD – Vt.

 
KW
2 
Ids = I1 = (VDD−Vt)Vds1−V
p.d1
 ds1
L  
p.d1  2 
 
 
V 1 1  
∴ R1 = ds1 = Z pd1 
Ids k − −
 V ds1
VDD Vt  
 2 

NOTE: Vds1 is small so ignore V ds1

2
15
  
1 1 
∴ R1 = Z pd1 
k V DD −V 


t
 ( −
1  V td  ) 2
and I1 = K  
Zp.u1 2 
Z 
p.d1  1 ( − V td)2 


I1R1 = Vout1 =   
Z 
p.u1  V DD −V 2 
 
t

16
Consider inverter2:
Case1:Pull up Transistor, It is a D-NMOSFET where Vgs =0
So it is operated directly in saturation region.
  
2

p.u2  Vgs −V
= KW
I1= Ids-saturation 

t


L p.u2  2 
 
but Vgs = 0 & Vt = Vtd
p.u2 ( −Vtd) 
W  2
∴ I2= K  
Lp.u2  2 

1  ( −Vtd)2 
or I2= K  

Zp.u2 2 

17
 Case2: Pull down Transistor, It is a E-NMOSFET where
i/p = VDD - Vtp 1st operated in resistive region where Vds1 < VDD – Vt.

 
= K W p.d2
( − ) V2 
Is
d  VDD Vt Vds2− ds2
Lp.d2  2 
 
 
V 1  1 
∴ R2 = ds2 = Z pd2 
Ids k 
− − V ds2 
 VDD Vt 
 2 

V ds2
NOTE: Vds2 is small so ignore
2

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  
1 1  
∴ R2= Z pd2  
k V DD − V 


t
but V DD = V − V DD tp

 
1  1 
∴ R2= Z pd2  
k 
(V DD
 − V tp ) − V 
t 

1  ( − V td )2 
I2 = K  
Z p.u2  2 
 
Z p.d2  1  ( − V td )2 
I 2 R 2 = V out2 =   
Z 
p.u2  V DD − V tp − V 
t   2 

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 If V out1 = V out2 then
 
Z p.u2 = Z p.u1  (V DD − V t ) 
 
Z p.d2 Z p.d1  V DD − V tp − V t 
for V t = 0 . 2 V DD , V tp = 0 . 3 V DD
Z p.u2 = Z p.u1  0 . 8 
 
Z p.d2 Z p.d1  0 . 5 
or Z p.u2 ÷ 2 Z p.u1 = 8
Z p.d2 Z p.d1 1
“An inverter driven through one or more pass transistors should have a
Zp.u/Zp.d ratio of ≥8/1.”
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 Conclusion-1:
“Inverter driven directly from the o/p of another inverter should
have a Zp.u/Zp.d ratio of ≥4/1.”

21
Conclusion-2:
“An inverter driven through one or more pass transistors should
have a Zp.u/Zp.d ratio of ≥8/1.”
VDD VDD
VDD
VDD

o/p
o/p
i/p
i/p

DNMOS inverter DNMOS inverter

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Thank U…….

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