2004 35th Annual IEEE Power Electronics Specialists Conference Aachen, Germany, 2004

Novel Load Adaptive Frequency Tracking Control Scheme

for High Frequency Inverter Witliout PLL Scheme

Hiroyasu KIFUNE Mutsuo NAKAOKA

Takumi YAMAGUCHI Yamaguchi University
Daichi YOSHIDA Email: nakaoka@pe-news 1 .eee.yamaguchi-u.ac.jp
Yoshihiro HATANAKA
Tokyo University of Marine Science and Technology
Email: [email protected]
which are used for a primiuy side of isolated DC-DC
Abslraa-A Load adaptive frequency tracking control converter and for the high frequency inverter of induction
scheme that is named Conduction Time Balanced Loop (CTBL) heating applications. However, the phase difference is
for the high frequency inverter is presented without PLL changed by the phase shift modulated output power regulation
scheme. Using this control method for the gate circuit ofthe high scheme, which interferes the PLL controller detecting phase
frequency inverter that operates in resonant frequency, it is
realized to have both the power regulation function and the load difference in the high frequency inverter. In short, the PLL
adaptive tracking control function by one inverter, though the scheme and the PSM-PWM scheme are exclusive in one high
conventional PLL high frequency inverter cannot do. This paper frequency inverter. Therefore, the PLL controlled high
describes the principle of the proposed control scheme with high frequency inverter needs to employ not just a converter using
frequency inverter operation and the relation between the a passive diode rectifier hut a converter using active power
CTBL and the power regulation by the phase shift modulation. switches for the inverter output power regulation, shown in
Fig.l.b, in the conventional high frequency inverter system
[2]-[4]. Therefore, the additional active converter increases
1. INTRODUCTION cost of a high frequency inverter system in the PLL controlled
It is well known that the magnetic characteristics change inverter power supply system. And it makes the inverter
drastically when the temperature of the material such a metal system very complicated.
rise to the certain temperature called Curie point. And the load This paper presents CTBL (Conduction Time Balanced
constants vary significantly, too. The load impedance change
causes the resonant frequency change, which leads to low Dc HF-AC
power factor of a resonant high frequency inverter. Therefore,
a high power high frequency load resonant inverter power
supply system must be able to provide a load adaptive
frequency tracking control in the case that it is used for the
induction heating applications, for instance hardening,
annealing and melting. To maintain high power factor, it is
necessary that an inverter operation frequency be tuned to the
load adaptive frequency (resonant frequency). In general,
PLL (Phase Locked Loop) scheme is introduced to control the
operation frequency of the high frequency inverter for
tracking load adaptive frequency [I]-151. In the PLL a. Conventional PLL high frequency inverter system
controlled inverter, phases of the resonant capacitor voltage,
the inverter output voltage, or the inverter output current are Dc HF-AC
detected as the feedback signals for its controller, and the
operation frequency is controlled so that the difference of the
detected signal phases are maintained to be constant or zero. I .................. ..........
As a result, PLL controlled inverter always operates in load
adaptive frequency and keep high power factor.
Also, the high frequency inverter must be able to regulate 1.TTT **
its output power. For instance, in induction heating
applications, the inverter output power should be controlled Controller by CTBL

appropriately based on some feedback load temperature

IntegratedCantml Interface
information so that the temperature of heated load is setting
value. The many full bridge type resonant inverters adopted
b. Proposed CTBL high frequency inverter syslem
PSM-PWM (Phase Shift Modulation - Pulse Width
Modulation) scheme as the output power control method, Fig. I . High frequency power supply system

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 2004 35th Annual IEEE Power Electronics Specialirrs Conference Aachen. Germany, 2004

Loop) as a novel load adaptive frequency tracking control

scheme for a solution of these problems instead of the PLL.
The CTBL scheme doesn't need any information of the phase
difference in the inverter main circuit, in order to tuning the
operation frequency to the resonant frequency. Therefore, it
can provide both the load adaptive frequency tracking control Resonant
function and the output power regulation function by one
inverter simultaneously, if the PSM-PWM high frequency
T
inverter introduces the proposed CTBL scheme, as shown in
Fig.1.a. In the result, the active converter becomes not
necessary for power regulation of high frequency inverter
system, and the system configuration can be simplified
drastically and reduces total cost. This paper mentioned the
Fig. 2. PSM-PWM high frequency invelter
principle of CTBL scheme, and clarified the relation between
CTBL and PSM-PWM.

11. PSM-PWM HIGH FREQEUENCY INVERTER

Proposed the novel load adaptive frequency tracking
control that is named Conduction Time Balanced Loop
(CTBL) in this paper should be introduced to PSM-PWM
high frequency resonant inverter operating in the resonant
frequency [6].At first, let's discuss the operation of the high
frequency inverter.
The PSM-PWM high frequency inverter is a full bridge
type circuit that has a load resonant circuit as shown in Fig. 2.
In conventional PLL controlled inverter and PFM controlled
inverter operate in the frequency that is little higher than the
resonant frequency of resonant circuit [ I]-[4]. When it
operates in that condition, it can achieve ZVZCS (Zero
Voltage Zero Current Switching) turn-off operation by the
resonance of current. And turn-off operation also can be
approved to ZVS easily by connecting loss-less snubber
capacitor in parallel with active switches. The high frequency
inverter introducing the proposed controlled scheme,
however, operates in just the resonant frequency. It can
realize the soft switching condition by giving the phase
difference to the gate pulse voltages even though it operates in
not a little higher frequency of resonant frequency but in the
resonant frequency. Fig. 3 illustrates waveforms of the gate
pulse voltages V,, inverter output voltage Vab, inverter output
current I., and the current flowing through each switching
devices.
The current waveforms ofeach switch i, to i4 are shape that
the cut out inverter output current by the each gate pulse. SI
and S2 operate in current lagging mode that the current
flowing through anti-parallel diodes DI and D2 change to the
switch current continuously by the load resonance. S3 and S4 Fig.'3.' PSM-PWM hig
operate in leading mode that the current flowing through them
change to the diode current of D3 and D4 continuously by the
discussed without the loss-less snubbers and its effect in this
load resonance. Thus it is feature that there are two operation
paper.
modes in this inverter due to giving the phase difference and
In this inverter, the phase difference 0p (=27cAt/T) is given
operating in the resonant frequency. It is possible to approve
to the gate pulses between V,, to VG4 and Vo2 to VG3. At
turn-off operation of SI and S2 to ZVS by employing
loss-less snubber capacitors and turn-on operation of S3 and means the difference time of gate pulses, and T is the inverse
number of the operation frequency. The overlapping period of
S4 can be improved by connecting the loss-less snubber
inductors in series with S3 and S4, if it is required. To focus the gate pulses T, is changed by 0p, which makes change of
the operation frequency control method, however, it is the effective value of the inverter output voltage Vab. The
effective value VI of fundamental wave of Vabis achieved by

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 2004 35th Annul IEEE Power Elecrronics Specialists Conference Aachen, Germany, 2004

the Fourier transform as following [6]. Phase Locked Loop in this paper. Although the period To1

VI = /e:e,
d

Bd = 2nTd / T
C O S 2 P (I)
and Tw are used to explain CTBL concept, CTBL can be
implemented by detecting the conduction time of current in
the following devices paring.
a) DI and D4, b) 0 2 and D3, c) DI and D3, d) D2 and D4
Ed is the input DC bus voltage, and Td is the dead time of e) SI and S4, 9 S2 and S3, g) SI and S3, h) S2 and S4
gate pulse.
CTBL is realized in the condition that any one following
The name of phase shift modulated PWM is derived from
equations consists.
changing the overlapping time T, by the phase shift control.
The inverter power factor is assumed to be almost I, because ToI-Tm=O, TI, -TD3=0
this inverter operates in just a resonant frequency. Thus the TDI-To3=0, TD2-Tw=0
load resonant circuit can he equal to a resistance, and the (4)
Tsl-Tw=O, Ts2-Ts3=0
inverter output power Po is given by following equation. TsI-Ts~=O, Ts2-Ts~0
Therefore the current detectors can be set up flexibly, it is
profitable in the actual circuit mounting.
R is the load resistance. In PSM power regulation range, the
soft switching operation obtained from the current resonance
is limited by the dead time Td. Hence, Equation 1 and
equation 2 are effect in a following condition [6].
edsepsn-ed (3)

111. CONDUCTION TIME BALANCED LOOP

A. Principle ofproposed control scheme

Fig.4 shows the current waveforms of SI operating lagging
mode and the current waveforms of S4 operating leading
mode in the condition that the operation frequency fo is tuned
to the resonant frequency fr. The both current waveforms are Fig. 4. Operating waveforms in fo=fr
generally symmetrical appearance. In addition, the time Tol
that DI is on state and the time Tw that D4 is on state are
equal when the high frequency inverter operates in a resonant
frequency. It is same in D2 and D3.
If the load inductance changes to be larger owing to the
load fluctuation from this condition, the resonant frequency
becomes lower. And if the operation frequency is still
constant, the current waveforms change as shown in Fig3
(fo>fr). In this figure, S4 cannot achieve ZVZCS turn on by
the current resonance, and it is obvious T,, is longerthan Tm.
On the other hand, if the load inductance changes to be lower,
the resonant frequency becomes higher. And if the operation Fig. 5. Operating waveforms in fo>fr
frequency is still constant, the current waveforms change as
shown in Fig.6 (fo<fr). In this condition, Tw is longer than
ToI. Hence, the difference occurs between TDIand Tw when
the operation frequency and the resonant frequency are not
matched as shown in Fig.5 and Fig.6. Tuning the operation
frequency to the resonant frequency from these conditions,
Tol becomes equal to TD4again though each absolute value
change.
We can find a novel conceptual control scheme through
these considerations. In short, the operation frequency fo can
be always tuned to the resonant frequency fr by controlling fo
so that the condition "Tal= To," is kept. This control scheme
is named Conduction Time Balanced Loop (CTBL) against Fig. 6 . Operating waveforms in fo<d

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 2004 35rh Annual IEEE Power Elecrronics Speciulisrs Conference Aachen, Germany, 2004

B. Characteristics of proposed control scheme

CTBL scheme needs not the phase difference but the
conduction time of semiconductor devices. Therefore,
proposed scheme doesn’t care if the delay occurs while the
signals transfer in detecting circuit including the current
detectors. In addition, the equations (4) indicate that the
length of time is not important for its control. CTBL requires
if there is the time difference of conduction time on each
device and if the difference is plus or minus.

C. Relation between PSM-P WM and CTBL

As mentioned above, the high frequency inverter can
realize its output power by changing the phase difference of
the gate pulse voltages. In the PLL high frequency inverter,
the phase difference interferes PLL operation frequency
control scheme.that works to fix it to zero or constant phase
angle. In the CTBL high frequency inverter, however, the
phase difference doesn’t interfere CTBL operation frequency
control scheme, because the difference of conduction time is Fig. 7. Assuming output current as sinusoidal wave
always about zero in any phase difference angle whenever
fo=fr.

&ii1i\
Let’s discuss the details of the relation o f PSM-PWM
scheme and CTBL scheme. The current flowing though
semiconductor devices are same waveforms as a half cycle of 0.04
output current I, (see Fig.3). Considering the output current
waveforms as a sinusoidal wave of fo, the switch current can 2 0’02 <? :I 150 IS?

be treated as a half cycle of the sinusoidal waveform current

.., 0.00
g -0.02
P ase shift angle, 9,. deg

(refer to Fig.7). In this assumption, the phase el ofthe current 5 -004

flowing through S I is expressed as follows.
-0.08
-0.06
-0.10 1
Fig. 8. Error resulting from sinusoidal wave assumption
And the phase ea of the current flowing through SI is
expressed as follows.
1.10
er =-2n.- TD4 (6)
T I.06
I04
The gate pulse phase angle epfor PSM-PWM output power
regulation is defined as
ep = e 1 -e4 (7)

The fundamental wave phase of I. to the fundamental wave 0:”

0.92
, , fa: W a n ,o n frequency
, ulntrollcd,by C l B L
R: Resonant fqumsy dcfind by Land C
,
of inverter output voltage is the mean value ofthe phases of I I
0.90
and lo.
0 30 60 shifi angle,
Phase 90 e,,Iieg
0 150 180

Fig. 9. Operation waveform in fo=fr

L, C, and R a r e the series equivalent resonant inductance,

the series equivalent resonant capacitance, and the series results in that the phase difference occurred by changing ep
doesn’t affect the CTBL that works to maintain the condition
equivalent load resistance. w 2 n f o . 8. is the phase ofl,, and it
TDI=TOJ.
is also the power factor angle of high frequency inverter.
Exactly, this assumption causes slight sampling error
Therefore, it becomes zero in fo=fr, and the condition
inevitably, because the shapes of switch currents are not the
TDI=Tmis always kept regardless of the value of 8, and €I4.It
half cycle of sinusoidal wave. Fig.8 indicates the calculation

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 2004 35th A n n u l IEEE Power Elecrronics Speciolisrs Conference Aachen, Germany, 2 W

inverter has been set up using the 4th generation trench gate
IGBT's modules (Mitsubishi electric: CMlOODU-I2F), high
frequency resonant capacitors (Soshin electric: RC24P801).
The water cooled resistors (Tokai-konetsu-kogyou:
W-1000D) were used for consuming high frequency power
instead of the real induction heating load applications, and it
was also used to measure the high frequency power because
the accurate measurement values are achieved in high
frequency power meter (Hioki: 3167) connecting to pure
resistor that its measured power factor is 1. The round flat coil
r -7 (so called the Pan-cake type coil) with litz wire and the
0 30 60 90 120 150 180 high-permeability ferrite boards were used as an imitation of
Phase shiA angle: qp, deg the induction heating load inductance. To make the situations
a. lnvener output power to phase shift angle changing the load inductance, ferrite boards were dropped on
the coil or removed rapidly while the high frequency inverter
operates. CTBL control circuit utilized the current
transducers (LEM: LA 55-PISPI).
Fig.11 shows the observed waveforms of SI and S4 in
initial condition k 6 5 b H , R=3.3Q, C=0.6pF, and
fo=25.2kHz. SI achieved ZVZCS condition in the current
lagging mode, and S4 also achieved ZVZCS condition in the
current leading mode. Fig.12 shows the observed waveforms
I-; -- after decreasing the inductance by removing a ferrite board
from the coil. The operation frequency tracked the resonant
frequency (30.0kHz) with CTBL control, and ZCZCS
operation was kept in the lagging and leading modes.
Increasing the inductance by putting a ferrite board on the
coil form the initial condition, we got the waveforms shown in
(ii) (iv) Fig.13. The operation frequency regulated with CTBL was
able to track the resonant frequency becoming lower
b. Operation wavcforms of SI and S4 in each phase shift angles (20.2kHz).
Fig. IO. Simulation results
On the other hand, Fig.14 and Fig.15 show the observed
(i)+30, (ii)%=70, (iii) 0,=110, (iv) 8,=150
waveforms after changing inductance without CTBL control.
In Fig.14, SI that should be in lagging mode operated in
result of error to the phase shift angle epin a condition that leading mode, and it couldn't accomplish the turn-on and
fo=fr, both frequencies are constant, and without CTBL turn-off operation because the operation frequency didn't
regulation. The error is defined as (TDl-TM)/T.The signals
for controlling operation frequency are available with margin
of sampling error of plus or minus 0.02, and it tends to be
almost zero in around ep=45-50.
Fig.9 illustrates the operation frequency regulated by
CTBL scheme based on the information including errors in
Fig.8. It can be seen that fa tends to be little higher than fr in
ep-45. However, the error mentioned above is enough
admissible since it doesn't affect ZVZCS operation of
switches as shown in Fig.10. Fig.10 (a) shows the inverter
output power to the gate pulse phase shift angle Op under
CTBL control. Fig.10 (b) illustrates the simulated waveforms
in (i) to (iv) in Fig. IO (a). It can be seen that TDIis about equal
to TD4in any condition of €Ip, and ZVZCS operation (marked
with dotted circle) is achieved.

IV. EXPERIMENT
To demonstrate the proposed operation frequency control
Fig. 11. Observed waveforms in CTBL conaol
with CTBL, an experimental prototype high frequency (Initial condition: f ~ 2 5 . 2 k H qL=65uH,EeIOOV)

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 2004 35th Annual IEEE Power Electronics Specialists Conference Aachen, German),, 2004

Fig. 12. Observed waveforms in CTBL control Fig. 14. Observed waveforms without CTBL control
(fo=30.0kH~L=45pH, Eg100V) (fo=25.2kHz, L=45vH, ErIOOV)

Fig. IS. Observed waveforms without CTBL control

Fig. 13. Observed waveforms in CTBL control
( f ~ 2 5 . 2 k HL=97pH,
~ EeIOOV)
(fo=ZO.ZkHz. L=97pH, Ed=IOOV)

match the resonant frequency. In the same way, S4 couldn’t its output power regulation function simultaneously. Thus, the
achieve ZVZCS operation in Fig.15. high frequency inverter power supply system required these
tinctions can be simplified drastically, because DClDC
v. CONCLUSION converter is not necessary for regulating output power in the
A novel conceptual load adaptive frequency tracking system using CTBL inverter. The principle of CTBL scheme
conbol scheme was proposed for the PSM-PH’M high is that the operation frequency fo is tuned to the resonant
frequency inverter, and it was named The Conduction Time frequency fr by controlling fo so that the two condition times
Balanced Loop (CTBL) against the conventional Phase of current flowing through semiconductor devices is kept to
Locked Loop (PLL). The high frequency inverter introducing be balanced. The characteristics of CTBL are followings,
PLL scheme can not regulate its output power while it 1. CTBL scheme required not the phase difference but the
maintained the operation frequency to the load adaptive conduction time of semiconductor devices. Therefore the
frequency, because the change of phase difference caused by current detectors can be set up in 8 ways, it was profitable
PSM-PWM scheme for the power regulation interfered PLL in the actual circuit mounting.
method that keeps the phase difference constant or zero. The 2. The lengths of detected two-conduction time are not
high frequency inverter controlled by CTBL was able to important for its control. CTBL required if there is the time
provide both the tuning function of operation frequency and difference of conduction times on each device and if the

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 2004 351h Annual IEEE Power Elecrronics Specialists Conference Aarhen, Germany, 2W4

difference is plus or minus. In PSM-PWM high frequency

inverter operating the resonant frequency, the lengths of
conduction times were changed, however the time
difference of these times is not changed by PSM-PWM
operation. As a result, the CTBL scheme and PSM-PWM
scheme coexist in one high frequency inverter.
3. It doesn’t care if the delay occurs while the signals transfer
in detecting circuit including the current detectors.
The sampling error caused in principle was explained by
means of diagrams. However, the signals for controlling
operation frequency are available with margin of sampling
error of plus or minus 0.02. And it was shown based on the
simulation results that it didn’t affect the soft switching
operation. Furthermore, experimental evaluations performed
in changing the inductance revealed that CTBL inverter
accomplishes soft switching operation in any condition.
From these considerations, one may well conclude that the
proposed CTBL scheme is highly suitable, sufficiently cost
effective and simplification as a novel load adaptive
frequency tracking control method for high frequency power
supply.

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