FPGA DESIGN FOR EMBEDDED SYSTEMS

Submitted by
Tejas Bajad
AP22110020030
 INDEX

Experiment number Experiment name

1 Logic gates

2 Decoders

3 Adders

4 Flip Flops

5 4-Bit Ripple carry adder using user created IP(full adder)

6 16-Bit comparator using user created IP (4-Bit comparator)

7 Multiplier IP Core

8 ALU design
Experiment 1
Date : 15 -02 -2024

Logic Gates

Aim : To write VHDL description for the basic and universal digital logic gates
and verify the function of each gate using the HDL simulator.

Apparatus : Xilinx VIVADO 19.1

Theory :
Logic gates are the building blocks of digital circuits, performing basic logical
operations on binary inputs to produce binary outputs. There are several types of
logic gates, each with its unique functionality: AND gates output a high signal only
when all inputs are high, OR gates produce a high signal if any input is high, and
NOT gates invert the input signal. XOR gates output a high signal when the number
of high inputs is odd, while NAND and NOR gates are combinations of AND and
NOT, and OR and NOT gates respectively. These gates are used to implement
Boolean algebra and construct more complex digital circuits. Combinations of logic
gates form the basis of logic circuits, such as flip-flops, multiplexers, and adders,
enabling tasks like data storage, selection, and arithmetic operations in digital
systems. Logic gates are implemented using electronic components like transistors,
with various technologies offering trade-offs between speed, power consumption,
and size. They are essential in modern computing, found in everything from simple
calculators to advanced microprocessors, driving the functionality of digital
electronics.
Design Steps :
● List out the inputs and outputs.
● Derive the logic for behavioral description based on the truth table.
● Write a VHDL description.
● Skip step 2 and 3 to write VHDL description in structural style using the logic
diagram.
● Write a VHDL description for each component in the logic diagram as separate
entities.
● Simulate the description using the HDL simulator.
● Correct the VHDL description if there are any syntax errors.
● After corrections verify the outputs.
● Correct the logic in VHDL description if the outputs are not expected.
● Analyze the output timing diagram.

Pin diagrams and Respective truth tables

NOTgate

AND gate

XNOR gate
VHDL code :
Entity all_inone_gates is
Port (a : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(6 downto 0));
End all_inone_gates;
Architecture Dataflow of all_inone_gates is
Begin
y(0)<=a or b;
y(1)<=a and b;
y(2)<=not a;
y(3)<=a nor b;
y(4)<=a nand b;
y(5)<=a xor b;
y(6)<=a xnor b;
End Dataflow;

Simulation Results :

Result : From this experiment we learnt how to design two input gates using VHDL
description for the basic and universal digital logic gates and verified the function of each
gate using HDL simulator.
Experiment 2
Date : 22 -02 -2024

Decoders

Aim : To write VHDL description for 3 to 8 decoder and verify the function using HDL
simulator.
Apparatus : Xilinx VIVADO 19.1
Model sim

Theory :
Decoders are fundamental components in digital circuit design, converting coded
inputs into a corresponding set of outputs. A Binary Decoder, for instance, interprets binary
input and activates a specific output line based on the input value, allowing for multiple
control options. Similarly, an n to 2^n Decoder accepts 'n' inputs and selects one of 2^n
output lines, expanding versatility in digital systems. Demultiplexers function similarly to
decoders but serve the specific purpose of routing data from one input to multiple outputs
based on a control signal, enabling efficient data distribution.
Priority Encoders prioritize input lines, generating a binary code representing the
highest active input, crucial in scenarios where prioritization is essential. Specialized
decoders like BCD to 7 Segment Decoders facilitate the conversion of binary coded
decimal input into signals suitable for displaying decimal digits on a 7 segment display,
pivotal in numeric display applications. These components find wide applications in
memory addressing, data routing, and display control within digital systems, enhancing
functionality and flexibility. Truth tables succinctly outline the relationship between input
and output states, aiding in circuit design and analysis. As part of combinational logic,
decoders ensure outputs depend solely on the current input state, simplifying operation
and reducing complexity. Leveraging basic logic gates like AND, OR, and NOT gates,
decoders are implemented efficiently, forming the backbone of many digital systems with
their versatile functionality and ease of integration.
Design steps :
● List out the inputs and outputs
● Derive the logic for behavioral description based on the truth table
● Write a VHDL description
● Skip step 2 and 3 to write VHDL. description in structural style using the logic
diagram
● Write VHDL descriptions for each component in the logic diagram as separate
entities
● Simulate the description using HDL simulator
● Correct the VHDL description if there are any syntax errors
● After corrections verify the outputs
● Correct the logic in the VHDL description if the outputs are not as expected.

Diagrams and Truth Tables :

VHDL code :
entity decoder 3x8 is
Port (1: in STD_LOGIC_VECTOR (0 to 2),
D: out STD_LOGIC_VECTOR (0 to 7)), end decoder 3x8,
architecture Behavioral of decoder 3x8 is
begin
process(1)
begin
case (1) is
when "000" =>
D<="10000000",
when "001" =>
D<="01000000";
when "010" =>
D<="00100000";
when "011" =>
D<="00010000";
when "100" =>
D<="00001000";
when "101" =>
D<="00000100",
when "110" =>
D<="00000010",
when "111" =>
D<="00000001",
when others =>
D<="00000000",
end case,
End process,
end Behavioral,
 Simulation Results:

BCD to Seven segment decoder

Aim : To write VHDL description for BCD to 7 segment decoder.
Apparatus : Xilinx VIVADO 19.1
Model sim
Circuit diagram and Truth Table :
VHDL code :
entity bcd_7segment is
Port (a: in STD_LOGIC_VECTOR (3 down to 0);
y: out STD_LOGIC_VECTOR (7 down to 0)); end bcd_7segment,
architecture Behavioral of bed_7segment is
begin
process(a)
begin
case(a) is
when "0000" => y<="11111101";
when "0001" => y<="01100001";
when "0010" => y<="11011011";
when "0011" => y<="11110011";
when "0100" => y<="00100111";
when "0101" => y<="10110111";
when "0110" => y<="10111111";
when "0111" => y<="11100001";
when "1000" =>y<="11111111";
when "1001" => y<="11101011";
when others => y<="00000000";
end case;
end process;
end behavioral;

Simulation Results:
Experiment 3
Date : 14 -03 -2024
Adders
Aim : To design and verify the half adder and full adder in a structural model and
verify the function using the HDL simulator.
Apparatus : Xilinx VIVADO 19.1
Model sim
Theory :
Adders are fundamental digital circuits used for arithmetic operations,
primarily addition, in computer and digital systems. They take two binary
numbers as input and produce their sum along with an optional carry output.
Basic adders include half adders, which compute the sum and carry for a
single bit, and full adders, which incorporate carry input from the previous
stage. Ripple carry adders cascade full adders to handle multi bit addition, with
carry bits propagating sequentially. Carry lookahead adders improve efficiency
by generating carry bits in parallel, reducing propagation delay. Parallel prefix
adders further optimize performance by utilizing prefix computation to
calculate carry bits. Adders play a crucial role in arithmetic logic units (ALUs),
enabling operations like addition, subtraction, and multiplication in digital
processors. They are implemented using logic gates like AND, OR, and XOR
gates, with designs varying in speed, area, and power consumption based on
application requirements. Adder architectures continue to evolve, with modern
designs integrating features like carry skip and carry select to enhance
performance in high speed computing applications.

Design steps :
● List out the inputs and outputs
● Derive the logic for behavioral description based on truth table
● Write a VHDL description
● Skip step 2 and 3 to write VHDL. description in structural style using the logic diagram
● Write VHDL descriptions for each component in the logic diagram as separate entities
● Simulate the description using HDI. simulator
● Correct the VHDL description if there are any syntax errors
● After corrections verify the outputs
● Correct the logic in VHDL. description if the outputs are not as expected
● Analyze the output timing diagram

Circuit Diagram and Truth Tables :

Half adder

Full adder
Half adder VHDL code :
library IEEE;
use IEEE STD_LOGIC_1164 ALL;
entity HA Structural is
Port (A in STD_LOGIC
Bin STD_LOGIC,
SUM out STD_LOGIC;
 CARRY out STD_LOGIC);
end HA Structural;

architecture Structural of HA_Structural is

component XOR2 is
Port (a,b in STD_LOGIC,
y out STD_LOGIC);
end component;
component AND21 is
Port (A,B in STD_LOGIC,
Y out STD_LOGIC);
end component;
begin
X1 XOR2 Port Map(A,B,SUM);
X2 AND21 Port Map(A,B,CARRY);
end Structural;
Full adder VHDL code :
library IEEE,
use IEEE STD_LOGIC_1164 ALL,
entity FA STRUCTURAL is
Port (a in STD_LOGIC,
b: in STD_LOGIC;
c in STD_LOGIC,
sum: out STD_LOGIC,
carry out STD_LOGIC),
end FA_STRUCTURAL,
architecture Structural of FA_STRUCTURAL is
component HA_Structural is
Port(A,B in STD_LOGIC,
SUM,CARRY out STD_LOGIC).
end component,
component OR2 is Port(a,b in std_logic, y out STD_LOGIC ).
end component,
Signal s1,52,53 STD LOGIC,
begin
XI HA Structural Port map(abs1.s2),
X2 HA Structural Port map(51.c.sum,s3),
X3 OR2 port map(s3.s2.carry).
end Structural
Simulation Results:

Results :
From this experiment we learnt how to design and verify the half adder and full
adder in a structural model and verify the function using the HDL simulator.
Experiment 4
Date : 21 -03 -2024
Flip Flops
Aim: To write VHDL description for JK and D Flip Flops and verify the function using
HDL simulator.
Apparatus : Xilinx VIVADO 19.1
Model sim
Theory :
JK Flip Flop:
JK flip flops are sequential logic circuits used as memory elements in digital
systems. They are characterized by their ability to toggle their output state based on
clock pulses and input signals. The JK flip flop has two inputs: J (set) and K (reset),
along with a clock input. When J and K are both set to 1, the flip flop toggles its
output state on each clock pulse, making it function as a frequency divider. In
contrast, setting both J and K to 0 maintains the current state. By manipulating the J
and K inputs, various operations such as toggling, setting, or resetting the flip flop
can be achieved. JK flip flops are widely used in digital systems for tasks like
frequency division, data storage, and sequential logic implementation. They are
essential components in counters, shift registers, and memory units, providing
flexibility and versatility in digital circuit design.
D Flip Flop:
D flip flops, or data flip flops, are fundamental building blocks in digital electronics
used for sequential circuit design and memory storage. They are bistable devices
capable of storing a single bit of data. Unlike other flip flops, the D flip flop has a
single data input (D) and two outputs: one for the stored data (Q) and another for its
complement (\(\overline{Q}\)). The output state of a D flip flop changes only on the
rising (positive) edge of the clock signal, allowing for synchronized data transfer. D
flip flops can be used to store binary values, synchronize signals, and control the
timing of operations in sequential circuits. They find widespread application in
registers, counters, and memory elements within digital systems. Implementations of
D flip flops vary, including simple latch based designs and more complex designs
utilizing NAND or NOR gates. Their versatility, simplicity, and reliability make D flip
flops indispensable components in modern digital circuit design.
Design steps :
● List out the inputs and outputs
● Derive the logic for behavioral description based on truth table
● Write a VHDL description
● Skip step 2 and 3 to write VHDL. description in structural style using the logic diagram
● Write VHDL descriptions for each component in the logic diagram as separate entities
● Simulate the description using HDI. simulator
● Correct the VHDL description if there are any syntax errors
● After corrections verify the outputs
● Correct the logic in VHDL. description if the outputs are not as expected
● Analyze the output timing diagram

Logic Diagrams

Circuit diagram and Truth tables :

JK Flip Flop
D Flip Flop

JK Flipflop VHDL code:

library IEEE,
use IEEE STD_LOGIC_1164 ALL,
entity JKFF is
Port (j in STD_LOGIC,
K in STD_LOGIC,
elk in STD_LOGIC,
q out STD_LOGIC,
q0 out STD_LOGIC),
end JKFF;
architecture Behavioral of JK FF is
begin
process(clk.j.k)
variable temp: STD_LOGIC,
begin
if(clk'event and clk = '1') then
if(j='0 and k=0') then
temp = temp, elsify='0' and k = '1') then
temp = '0'; elsif(j'1' and k = '0') then temp = '1',
else temp not temp;
end if,
end if q<=temp;
q0not temp;
end process.
end behavioral;

D Flip Flop
library IEEE,
use IEEE STD_LOGIC_1164 ALL;
entity DFF is
Port (d in STD_LOGIC,
e in STD_LOGIC,
q out STD_LOGIC,
q0 out STD_LOGIC);
end DFF;
architecture Behavioral of DFF is
begin
process(e)
begin
if(e'event and e = '1')then
q<=d;
q0<= not d;
end if;
end process;
end behavioral;

Simulation Results:
JK Flip Flop
D Flip Flop

Result : From this experiment we learnt how to write VHDL description for JK and D
Flip Flops and verify the function using HDL simulator.
Experiment 5
Date : 04 -04 -2024
4 bit ripple carry adder using user created IP(full adder)
Aim : To write VHDL description for 4 bit ripple carry adder using user created IP (full
adder) and verify the functionality using HDL simulator.
Apparatus : Xilinx VIVADO 19.1
Model sim
Theory :
A 4 bit ripple carry adder is a digital circuit used to perform addition of
two 4 bit binary numbers. It consists of four full adders and an additional carry
input. Each full adder adds three inputs: two from the input numbers and one
carry input from the previous stage. The sum output of each full adder forms
the corresponding bit of the result, while the carry output is propagated to the
next stage.

To implement this, you can create a user defined Intellectual Property (IP) for
the full adder. The full adder IP takes in three inputs: two bits from the input
numbers and one carry input from the previous stage, and produces two
outputs: the sum bit and the carry out. By cascading four instances of this full
adder IP, you can construct the 4 bit ripple carry adder.

In the first stage, the least significant bits of the input numbers are added
together using the first full adder. The carry out from this stage becomes the
carry input for the next stage, and this process continues for each subsequent
stage until the most significant bits are added. This sequential propagation of
carry bits gives rise to the term "ripple carry."

The efficiency of the ripple carry adder is limited by the need to wait for carry
propagation through each stage, making it slower than other types of adders
like carry lookahead adders. However, it is simple to design and implement,
making it suitable for many applications where speed is not critical.
Design steps :
● List out the inputs and outputs
● Derive the logic for behavioral description based on truth table
● Write a VHDL description
● Skip step 2 and 3 to write VHDL. description in structural style using the logic diagram
● Write VHDL descriptions for each component in the logic diagram as separate entities
● Simulate the description using HDI. simulator
● Correct the VHDL description if there are any syntax errors
● After corrections verify the outputs
● Correct the logic in VHDL. description if the outputs are not as expected
● Analyze the output timing diagram

VHDL code:
library IEEE;
use IEEE.STD LOGIC 1164. ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
port (AO: in STD_LOGIC;
A1: in STD_LOGIC;
A2: in STD_LOGIC;
A3: in STD_LOGIC;
BO: in STD_LOGIC;
B1: in STD_LOGIC;
B2: in STD_LOGIC;
B3: in STD_LOGIC;
Cin: in STD_LOGIC;
Cout: out STD_LOGIC;
50: out STD_LOGIC;
S1: out STD_LOGIC;
S2: out STD_LOGIC;
S3: out STD_LOGIC );
end design_1_wrapper;
architecture STRUCTURE of design_1_wrapper is component design_1 is
port (Cin: in STD_LOGIC;
Cout: out STD_LOGIC;
AO: in STD_LOGIC;
A1: in STD_LOGIC;
A2: in STD_LOGIC;
A3: in STD_LOGIC;
BO: in STD_LOGIC;
B1: in STD_LOGIC;
B2: in STD_LOGIC;
B3: in STD_LOGIC;
SO: out STD_LOGIC;
S1: out STD_LOGIC;
S2: out STD_LOGIC;
S3: out STD_LOGIC );
end component design_1;
begin
design_1_i: component design_1
port map (
A 0=>A0,
A 1 Rightarrow A1,
A 2 Rightarrow A2
A 3 Rightarrow>A3
BO Rightarrow BO
B 1 Rightarrow B1,
B 2 Rightarrow B2
B3 => B3,
Cin => Cin,
Cout => Cout,
S 0=>S0
S 1 Rightarrow S1,
S 2 Rightarrow>S2
S 3=>S3);
end STRUCTURE;
Diagram :

Simulation Results:

Results : The 4 bit ripple carry adder, leveraging a user created IP for the
full adder module, embodies a robust application of modular design
principles in digital circuitry. The modular approach not only streamlines the
implementation of the 4 bit adder but also promotes reusability across
different designs, enhancing productivity and reducing development time
Experiment 6
Date : 04 -04 -2024
16 bit comparator using user created IP(4 bit comparator)
Aim: To write VHDL description for 16 bit comparator using user created IP(4 bit
comparator) and verify the functionality using HDL simulator.
Apparatus : Xilinx VIVADO 19.1
Model sim
Theory :
A 16 bit comparator is a digital circuit used to compare two 16 bit binary
numbers and determine their relationship (e.g., if one number is greater than,
less than, or equal to the other). It can be built using smaller comparators,
such as 4 bit comparators, as building blocks.

To create a 16 bit comparator using a user defined Intellectual Property (IP) for
a 4 bit comparator, you would cascade four instances of the 4 bit comparator
IP. Each 4 bit comparator compares a corresponding group of four bits from
the two 16 bit numbers. The outputs of these 4 bit comparators are then
combined to produce the final result for the entire 16 bit comparison.

In the comparison process, the most significant bits are compared first. If they
are equal, the comparison moves to the next lower significant bits, and so on,
until all 16 bits have been compared. The final comparison result indicates
whether the first 16 bit number is greater than, less than, or equal to the
second number.

By leveraging smaller building blocks like the 4 bit comparator IP, you can
efficiently design and implement a 16 bit comparator while maintaining
modularity and reusability in your digital circuit design. This approach allows
for easier testing, debugging, and maintenance of the comparator circuit.
Design steps :
● List out the inputs and outputs
● Derive the logic for behavioral description based on truth table
● Write a VHDL description
● Skip step 2 and 3 to write VHDL. description in structural style using the logic diagram
● Write VHDL descriptions for each component in the logic diagram as separate entities
● Simulate the description using HDI. simulator
● Correct the VHDL description if there are any syntax errors
● After corrections verify the outputs
● Correct the logic in VHDL. description if the outputs are not as expected
● Analyze the output timing diagram

VHDL code :
library IEEE;
use IEEE STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity comparator_16_wrapper is
port (a: in STD_LOGIC_VECTOR (15 down to 0);
aeb: out STD_LOGIC;
aebo: in STD_LOGIC;
agb: out STD_LOGIC;
agbo in STD_LOGIC;
alb: out STD_LOGIC;
albo in STD_LOGIC;
b: in STD_LOGIC_VECTOR (15 down to 0));
end comparator_16_wrapper,
architecture STRUCTURE of comparator_16_wrapper is component comparator_16 is
port (alb: out STD_LOGIC;
agb out STD_LOGIC;
aeb: out STD _LOGIC;
a: in STD_LOGIC_VECTOR (15 down to 0);
b: in STD_LOGIC_VECTOR (15 down to 0);
albo in STD_LOGIC;
agb0 in STD_LOGIC;
aeb0: in STD_LOGIC);
end component comparator_16;
begin
comparator_16_i: component comparator_16
port map (a(15 down to 0) => a(15 down to 0),
aeb => aeb;
aebo => aebo;
agb => agb;
agbo => agbo;
alb => alb;
albo => albo;
b(15 downto 0) => b(15 downto 0));
end STRUCTURE;

Diagram :

Simulation Results :

Result : The 16 bit comparator utilizing a user created IP, specifically a 4 bit
comparator, offers a streamlined approach to efficiently compare two 16 bit binary
numbers By leveraging the reusable 4 bit comparator IP, the design optimizes resource
utilization while ensuring accurate comparison functionality This integration
underscores the significance of modular design in enhancing both performance and
scalability within digital systems.
Experiment 7
Date : 18 -04 -2024
Multiplier IP core
Aim : To write VHDL description for multiplier IP core and verify the functionality using
HDL simulator.
Apparatus : Xilinx VIVADO 19.1
Model sim
Theory :
A Multiplier IP core is a specialized hardware component designed to efficiently
perform multiplication operations in digital systems. Unlike basic arithmetic operations like
addition, multiplication is a more complex operation involving repeated addition and
shifting of binary digits. Multiplier IP cores are optimized to handle this computation
efficiently, especially in high performance applications like signal processing, graphics
rendering, and cryptography.

These IP cores typically employ algorithms such as Booth's algorithm or Wallace tree
multiplication to reduce the number of partial products generated and minimize the
computational overhead. Booth's algorithm, for example, exploits the redundancy in binary
representation to generate partial products more efficiently. Wallace tree multiplication
further optimizes this process by reducing the number of partial products through tree
based parallel processing.

Multipliers can be designed to support various operand widths and precision levels,
allowing flexibility in different application scenarios. They often incorporate features like
pipelining and parallelism to enhance performance and throughput, enabling faster
computation of multiplication results. Additionally, optimizations such as operand encoding
schemes and hardware sharing techniques are employed to reduce area and power
consumption.

These cores are commonly implemented using hardware description languages (HDL) like
Verilog or VHDL and synthesized into application specific integrated circuits (ASICs) or
field programmable gate arrays (FPGAs). By integrating a Multiplier IP core into a digital
system, designers can significantly accelerate multiplication operations while conserving
resources and meeting performance requirements in a wide range of applications.

Design steps :
● List out the inputs and outputs
● Derive the logic for behavioral description based on truth table
● Write a VHDL description
● Skip step 2 and 3 to write VHDL. description in structural style using the logic diagram
● Write VHDL descriptions for each component in the logic diagram as separate entities
● Simulate the description using HDI. simulator
● Correct the VHDL description if there are any syntax errors
● After corrections verify the outputs
● Correct the logic in VHDL. description if the outputs are not as expected
● Analyze the output timing diagram

VHDL code :
library IEEE;
use IEEE STD_LOGIC_1164.ALL;
library UNISIM:
use UNISIM.VCOMPONENTS.ALL;
entity design_3_wrapper is
port (A_0: in STD_LOGIC_VECTOR (3 down to 0);
B_0: in STD_LOGIC_VECTOR (3 down to 0);
P_0: out STD_LOGIC_VECTOR (7 down to 0));
end design_3_wrapper;
architecture STRUCTURE of design_3_wrapper is component design 3 is
port (A_0: in STD_LOGIC_VECTOR (3 down to 0);
B_0: in STD_LOGIC_VECTOR (3 down to 0);
P_0: out STD_LOGIC_VECTOR (7 down to 0) );
end component design_3;
begin
design_3_i: component design 3
port map (A_0(3 down to 0) =>A_0(3 down to 0), B_0(3 down to 0) => B_0(3 down to 0), P_0(7
down to 0) => P_0(7 down to 0) );
end STRUCTURE;

Diagram :

55
Simulation Results :

Results : From this experiment we learnt the designing and simulation of multipliers
and verified the functionality using VHDL simulator.
Experiment 8
Date : 22- 04- 2024
ALU Design
Aim :
To write VHDL description for arithmetic logic unit (ALU) and verify the
functionality using HDL simulator.
Apparatus :
Xilinx VIVADO 19.1
Model sim
Theory :
The Arithmetic Logic Unit (ALU) is a vital component of the central
processing unit (CPU) in a computer, responsible for performing arithmetic and
logic operations on binary data. ALU design involves integrating various
computational elements such as adders, subtractors, AND -OR gates, shifters,
and multiplexers. Its primary function includes executing operations like
addition, subtraction, multiplication, division, bitwise AND, OR, XOR, and
logical shifts. ALUs often incorporate control logic to select operations based
on the instruction set architecture (ISA) and carry out operations in response
to the CPU's instruction stream. ALU architectures can vary widely, from
simple designs with minimal functionalities to complex implementations with
support for floating point arithmetic and SIMD (Single Instruction, Multiple
Data) operations. Performance considerations such as speed, area, power
consumption, and instruction throughput heavily influence ALU design
choices. Modern ALUs often feature pipelining and parallelism techniques to
enhance performance and efficiency, crucial for meeting the computational
demands of contemporary computing applications ranging from general
purpose computing to scientific simulations and artificial intelligence tasks.
Design steps :
● List out the inputs and outputs
● Derive the logic for behavioral description based on truth table
● Write a VHDL description
● Skip step 2 and 3 to write VHDL. description in structural style using the logic diagram
● Write VHDL descriptions for each component in the logic diagram as separate entities
● Simulate the description using HDI. simulator
● Correct the VHDL description if there are any syntax errors
● After corrections verify the outputs
● Correct the logic in VHDL. description if the outputs are not as expected
● Analyze the output timing diagram
4 bit ALU VHDL code :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
Uncomment the following library declaration if using
arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
Uncomment the following library declaration if instantiating
any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents. all;
entity ALU_4 is
Port (a, b: in STD_LOGIC_VECTOR (3 down to 0); s: in STD_LOGIC_VECTOR (2 down to 0); y:
out STD_LOGIC_VECTOR (3 down to 0)); end ALU_4;
architecture Behavioral of ALU_4 is
begin
process(a,b, s)
begin
case (s) is when "000" =>
y<= a + b;
when "001" =>
y<=a b;
when "010" =>
y=a+1;
when "011" =>
y=a 1;
when "100" =>
y<=a and b;
when "101"=>
y<=a or b;
when "110" =>
y=a xor b;
when others =>
y<=not a;
end case;
end process;
end behavioral;

Simulation Results :

Results : From this experiment,we learnt the designing and stimulation of ALU and
verified the functionality using VHDL simulator.