MICROPROCESSORS

Introduction to Intel Microprocessors

Slides adapted from slides by Prof. Levent Eren

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Outline
• Intel microprocessors history
• Basic microprocessor and system architecture
• Memory
• Programming model
• Memory addressing
• Real mode
• Protected mode
• Differences between C and ASM
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Intel Microprocessors History

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Microprocessor Architecture
Basic Components
• CPU Registers
• special memory locations constructed from flip-flops and
implemented on-chip
• e.g., accumulator, count register, flag register
• Arithmetic and Logic Unit (ALU)
• ALU is where most of the action takes place inside the CPU
• Bus Interface Unit (BIU)
• responsible for controlling the address and data busses when
accessing main memory and data in the cache
• Control Unit and Instruction Set
• CPU has a fixed set of instructions with which to work, e.g., MOV,
CMP, JMP, ADD
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Microprocessor Architecture
Instruction processing
• Processing of an instruction by a microprocessor consists
of three basic steps
• (1) fetch instruction from the memory,
• (2) decode the instruction, and
• (3) execute (usually involves accessing the memory for getting
operands and storing results)
• Operation of an early processor, e.g., 8085

Fetch Decode Execute Fetch Decode Execute …... Microprocessor

1 1 1 2 2 2

Busy Idle Busy Busy Idle Busy …... Bus

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Microprocessor Architecture
Instruction processing
• Modern microprocessors can process several instructions
simultaneously at various stages of execution
• this ability is called pipelining
• Operation of the pipelined microprocessor, e.g., 80486

Fetch Fetch Fetch Fetch Store Fetch Fetch Read Fetch

1 2 3 4 1 5 6 2 7 Bus Unit

Decode Decode Decode Decode Decode Decode

1 2 3 4 Idle 5 6 Idle Instruction Unit

Execute Execute Execute Execute Execute Execute

1 2 3 4 Idle 5 6 Execution Unit

Generate Generate
Address Address Address Unit
1 2
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System Architecture

A19
Address Bus provides a memory Address Bus
address to the system memory and
I/O address to the system I/O A0
devices
8086 D15 To memory
Data Bus transfers data between Data Bus
System (16 bit) and I/O
the microprocessor and the memory
and I/O attached to the system D0

Control Bus provides control signals

that cause the memory or I/O to Control Bus RD/WR
perform a read or write operation Memory
I/O
Processor Data and Address Bus Sizes
Examples

Processor Data Bus Address Bus Max Addressable Memory

8088 8 20 1,048,576 (1M)

8086 16 20 1,048,576 (1M)

80286 16 24 16,777,21 (16M)

80386dx 32 32 4,294,976,296 (4G)

80486 32 32 4,294,976,296 (4G)

80586/Pentium (Pro) 64 32 4,294,976,296 (4G)

Pentium II, III, 4 64 36 68,719,476,736 (64G)

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Memory
• Microprocessor addresses a maximum of 2n different
memory locations, where n is a number of bits on the
address bus.
• The memory system is divided into three main parts: TPA
(transient program area), system area, and XMS (extended
memory system).
• The first 1M byte of memory (TPA and system area) is called
the real or conventional (DOS) memory system because
each Intel microprocessor is designed to function in this area
by using its real mode of operation.
• Computer systems based on the 80286 through the Core2
not only contain the TPA (640K bytes) and system area
(384K bytes), they also contain extended memory.
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Memory
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TPA and System Area

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Memory (cont.)
• Logical Memory
• 80x86 supports byte addressable memory
• byte (8 bits) is a basic memory unit
• e.g., when you specify address 24 in memory, you get the entire
eight bits, nothing less, nothing more
• when the microprocessors address a 16-bit word of memory, two
consecutive bytes are accessed
• Physical Memory
• The physical memories of 80x86 family differ in width
• e.g., 8088 memory is 8 bits wide,
• 8086, 80286 memory is 16 bits wide, and
• 80386dx, 80486 memory is 32 bits wide
• Pentiums memory is 64 bits wide
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Memory (cont.)
• For programming there is no difference in memory width,
because the logical memory is always 8-bit wide
• Memory is organized in memory banks
• a memory bank is an 8-bit wide section of the memory.
• e.g., the 16-bit microprocessors contain two memory banks to form
a 16-bit wide section of memory that is addressed as bytes or
words.
• 32-bit microprocessors contain four memory banks to form a 32-bit
wide section of memory that is addressed as bytes, words or
double words.
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Physical Memory System

Example (16 bit microprocessor)

High Bank Low Bank

(odd bank) (even bank)
FFFFFF FFFFFE

FFFFFD FFFFFC

FFFFFB FFFFFA

8 bits

8 bits

000005 000004

000003 000002

000001 000000
D15 - D8 D7- D0
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Accessing Data in Memory

Example (16 bit microprocessor)

• Accessing word from an even address - L.O. byte from the

address specified and the H.O. byte from the next
consecutive address
• What if you access a word on an odd address?
• Example: access memory on address 125, i.e., we want to access data on address
125 (L.O.) and 126 (H.O.)
• this requires two memory operations
• read byte on address 125
• read byte on address 126
• swap the positions of these bytes internally since both entered the CPU on the wrong half
of the data bus
• 80x86 CPUs recognize this and perform transfer automatically

• Your programs can access words at any address and the

CPU will properly access and swap the data in memory
• Think about the speed of your program when accessing
words at odd addresses
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Memory
Data Types
• Numbers
• bit (e.g.: 0,1) ; nibble = 4 bits
• DB: define Byte = octet = 8 bits
• DW: define Word = 2 bytes = 16 bits (80x86 terminology)
• DD: define Doubleword = 4 bytes = 32 bits (80x86 terminology)
• DQ: define Quadword = 4 bytes = 64 bits (80x86 terminology)
• Intel uses little endian format (i.e., least significant byte at lower address)
• Signed Integers (2's complement)

• Text
• Letters and characters (7-bit ASCII standard), e.g., 'A'=65=0x41
• Extended ASCII (8-bit) allows for extra 128 graphics/symbols)
• Collection of characters = Strings
• Collection of Strings = Documents
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Memory
Data Types (cont.)

• Programs
• Commands (MOV, JMP, AND, OR, NOT)
• Collections of commands = subroutines
• Collection of subroutines = programs
• Floating point numbers (covered later)
• Images (GIF, TIF, JPG, BMP)
• Video (MPEG, QuickTime, AVI)
• Audio (voice, music)
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Example of Memory with Stored Data

Address Data (8-bits) Interpretation
0xFFFFF
...
0x75000 0x55 byte
...
0x70009 '$’ String
0x70008 '1'
0x70007 ‘9’
0x70006 ‘2’
0x70004 ‘E’
0x70003 ‘C’
0x70002 ‘E’
...
0x60511 0x12 Word
0x60510 0x34 3x1 integer array
0x6050F 0x12 Word of 16-bit words
0x6050E 0x34
0x6050D 0x12 Word
0x6050C 0x34
...
0x55504 0xFE JE-2 Program
0x55003 opcode
0x55002 0x02 ADD AL,2
0x55001 opcode
...
0x00000
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Examples
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Real Numbers

Float converter:
https://www.h-schmidt.net/FloatConverter/IEEE754.html
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Programming Model
Registers (Program visible)

Note:
32 bit registers are
not available on
8086, 8088, 80286
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Programming Model
64-bit Extension
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Programming Model
Multipurpose Registers
• RAX (accumulator) is addressable as RAX, EAX, AX, AH, or AL.
• It often holds the temporary result after an arithmetic and logic operation.
• EAX, RAX may hold offset addresses.
• RBX (base) is addressable as RBX, EBX, BX, BH, or BL.
• It often holds the base (offset) address of data located in the memory.
• EBX, RBX can address memory data.
• RCX (count) is addressable as RCX, ECX, CX, CH, or CL.
• It often holds the count for various instructions (shift, rotate, REP/
REPE/REPNE and LOOP).
• ECX, RCX can address memory data.
• RDX (data) is addressable as RDX, EDX, DX, DH, or DL.
• It often holds a part of the result from a multiplication or part of the dividend
before a division.
• EDX, RDX can address memory data.
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Programming Model
Multipurpose Registers
• RBP (base pointer) is addressable as RBP, EBP, or BP.
• It points to a memory location for memory data transfers.
• RDI (destination index) is addressable as RDI, EDI, or DI.
• it often addresses string destination data for the string instructions.
• RSI (source index) is addressable as RSI, ESI, or SI.
• It often addresses string source data for the string instructions.
• R8 through R15 are found are only found in the Pentium 4 and
Core2 if 64-bit extensions are enabled.
• Data in these registers are addressed as 64-, 32-, 16-, or 8-bit
sizes and are of general purpose.
• Most applications will not use these registers until 64-bit processors
are common.
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Programming Model
Special-Purpose Registers
• RIP (instruction pointer) addresses the next instruction in a
section of memory defined as a code segment.
• This register is IP (16 bits) when the microprocessor operates in the real
mode and EIP (32 bits) when the 80386 and above operate in the
protected mode. In the 64-bit mode, RIP contains a 40-bit address at
present to address a 1T flat address space.
• The instruction pointer can be modified with a jump or a call instruction.
• RSP (stack pointer) addresses an area of memory called the
stack (LIFO).
• The stack memory stores data through this pointer using PUSH and POP
instructions that address stack data.
• This register is referred to as SP if used as a 16-bit register and ESP if
referred to as a 32-bit register.
• RFLAGS indicate the condition of the microprocessor and
control its operation.
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Programming Model
Flag Register

• C(carry) indicates carry after addition or a borrow after subtraction.

• Z(zero) indicates that the result of an arithmetic or logic operation is zero.
• T(trap) when the trap flag is set , it enables trapping through the on-chip
debugging feature.
• I (interrupt) controls the operation of the INTR (interrupt request) input pin.
• D(direction) selects either the increment or decrement mode
for the DI and/or SI registers during string instructions.
• O(overflow) is a condition that occurs when signed numbers are added or
subtracted.
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Programming Model
Segment Registers
• Segment registers are 16-bit special-purpose registers
that generate memory addresses along with other
registers in the microprocessor
• CS(code) defines the starting address of the section of
memory-holding code (programs and procedures used by
programs)
• DS(data) a section of memory that contains most data used
by a program
• ES(extra) an additional data segment
• SS(stack) defines the area of memory used for the stack
• FS and GS (available on 80386, 80486 and later) allow two
additional memory segments for access by programs
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Real Mode Memory Addressing

• 80286 - 80486 microprocessors or above operate in either the
real mode or protected mode.
• 8086, 8088, and 80186 only operate in the real mode.
• Real mode operation allows the microprocessor to only address
the first 1M byte of memory space (even if it is an 80486
microprocessor).
• Each of 80x86 processors operates in the real mode by default.
• All real mode memory addresses consist of a segment address
plus an offset address
• the segment address (in one of the segment registers) defines the
beginning address of any 64K byte memory segment
• the offset address selects a location within the 64K byte memory
segment
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Real Mode Memory Addressing (cont.)

• Generation of 20-bit linear address from a segment:offset
address
• in the real mode, each segment register (16 bits) is
internally appended with a 0h on its rightmost end (i.e.,
the segment is shifted left by 4 bits)
• The segment and the offset are
then added to form 20-bit memory
address.
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Real Mode Memory Addressing

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Real Mode Memory Addressing

Examples
(1) Linear address for Segment:Offset = 2222:3333 = 25553
Segment: offset address for Linear address=25553:
• Many Answers - One possibility: 2222:3333
• Many Answers - One possibility: 2000:5553

(2) Linear address for Segment:Offset = 1200:F445 = 21445

Segment: offset address for Linear address=21445:
• Many Answers - One possibility: 1200:F445
• Many Answers - One possibility 2000:1445
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Default Segment and Offset Registers

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Protected Mode Memory Addressing

• In 80286 and later processors the addressing capabilities
of a microprocessor are extended by changing the function
the CPU uses to convert a logical address to the linear
address space.
• The protected mode processors use a look up table to compute the
physical address.
• The segment value (selector) is used as an index into an array
(descriptor table) .
• The contents of the selected array element (descriptor) provides the
starting address for the segment , length and access rights.
• The CPU adds this value to the offset to obtain the physical address.
• There are two descriptor tables for global (system) and local
(application) descriptors, each table contains 8192 descriptors and
every descriptor 8 bytes in length.
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Protected Mode Segment Register

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Descriptors
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Access Rights Byte

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Example
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Program-Invisible Registers
• The program-invisible registers are not directly addressed
by software.
• These registers control the microprocessor when operated
in protected mode (80286 and above).
• Each of the segment registers contains a program-invisible
portion (cache) used in the protected mode.
• The GDTR (global descriptor table register) and IDTR
(interrupt descriptor table register) contain the base address
of the descriptor table and its limit.
• The LDTR (local descriptor table register) is loaded with a
selector, just as a segment register is loaded with a selector.
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Program-Invisible Registers
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Flat Mode Memory

• A flat mode memory system (64-bit systems) is one in
which there is no segmentation.
• The address of the first byte in the memory is at 00 0000
0000H and the last location is at FF FFFF FFFFH (address
is 40-bits).
• The flat model does not use a segment register to address a
location in the memory.
• The segment register still selects the privilege level of the
software or to define access rights for only a code segment
• The offset address is the actual physical address in 64-bit
mode.
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Flat Mode Memory

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Memory Paging
• The memory paging mechanism located within the 80386
and above allows any physical memory location to be
assigned to any linear address.
• The linear address (logical) is defined as the address
generated by a program.
• The physical address is the actual memory location
accessed by a program.
• With the memory paging unit, the linear address is invisibly
translated to any physical address, which allows an
application written to function at a specific address to be
relocated through the paging mechanism.
• It also allows memory to be placed into areas where no
memory exists.
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Paging Registers
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Peripherals
• Memory-mapped devices (special memory locations in
the normal address space of the CPU)
• BIOS: 0xF0000-0xFFFFF (bootstrap, I/O calls)
• Video: 0xA0000-0xBFFFF and vBIOS: 0xC0000-0xC7FFF
• I/O mapped devices (sound card, com ports, parallel
port)
• I/O addresses different than Memory addresses
• Address Range: 0x0000 - 0xFFFF (16-bit)
• Interrupts
• Notifies the CPU when an event has occurred
• Timer [update clock] , serial I/O [input data], Parallel I/O [ready]
• Network adapter [packet arrived]
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C vs. ASM

x86 assembly C
Null EQU 0 #define null 0

myseg SEGMENT PUBLIC

myvar DW 017fh int myvar = 0x017f,
myvar2 DW ? myvar2;

start: Start()
{
mov ax, cs
mov ds, ax

mov si, myvar _SI=myvar

mov myvar2, null myvar2 = null;
call dosxit dosxit();
}
END start

myseg ENDS
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Hints for MP0

Basic Instructions

Operation (example) Function

MOV AX, CSEG Move contents of Code segment register to the AX

register.
MOV DX, constant Load the register DX with a fixed value.

INC AX Increment register AX.

CALL procedure Call a procedure. A return address will go on the

stack.
CMP AL, constant Compare the register AL with a constant. Set Flags

JE label If flags indicate that previous compare was equal,

jump to the address of the address defined by label.
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Hints for MP0

Program Directives

C ASM Description

#define EQU Compile-time substitutions.

main main Where the program begins.

#include extrn: Define external routine.

int x = 0x5 x db 05h Allocate memory for a variable and initialize it with
a value.