CSE 213

Computer Architecture

Lecture 7: Input /Output

Military Institute of Science

and Technology
 Outline
• General

• Interfacing I/O Devices to CPU

• Processor involved I/O : Between Memory and
External Devices

• DMA

• I/O Channel

• Infini Band
 External Devices : Types
• Human readable
– Screen, printer, keyboard
• Machine readable
– HDD
• Communication
– Modem
– Network Interface Card (NIC)
 Classification : I/O Devices
• Block devices
– Information is stored in fixed size blocks
– Block sizes range from 128-1024 bytes
– I/O is done by reading/writing blocks
– Hard disks, floppies, CD ROMS, tapes are in this
category
• Character devices
– I/O is done as characters (ie., stream of bits)
– Terminals, printers, mouse, joysticks are in this
category
 IO Interface
• I/O devices can not directly communicate with the CPU
due to various differences between them.
• Major issues :-
– Wide variety of peripherals
• Different data formats
• Different control logics
– Differs in speed with CPU / RAM
– Un-necessary to build all the different control logics
into a Processor, thus complicating it.
• Therefore there is a need for I/O modules
• IO interface provides a method for transferring
information between Processor , Memory and external
I/O devices.
 I/O Module Function
• Provide interfaces for communication between the
CPU / Memory and I/O devices:-
– Internal : Processor and Memory
– External : I/O devices
• Control & Timing
– Generate address for each I/O device.
– Synchronize timing for I/O op.
– Contains logic specific to each device it controls.
• Data Buffering
• Error Detection

Hide details of timing, formats, and the electromechanics of external

device allowing processor to function in terms of simple R/W commands.
I/O Bus and Interface Modules
 I / O Module : Functioning
• I/O bus is attached to all peripherals through
their respective I/O interfaces.
• The Interfaces monitor address on address
lines.
• CPU puts address of I/O device on address
lines
– On finding its own address, the respective I/O interface,
activates path between itself and the I/O device.
– All the other devices are disabled by their interfaces.
• CPU initiates communication :
– I/O command is made available in the control lines.
• I/O module responds to CPU communication :
– Data to read or write is made available in the data lines.
Generic I/O Module
External Device Block Diagram
I/O Module: Internal Block Diagram
Interfacing I/O Devices to
CPU
 Interfacing I/O Devices
• I/O devices can be connected to microprocessor in
two modes :-
– Parallel. Done in groups of 8 bits using the entire
data bus.

– Serial. Data is transferred one bit at a time using

the SID and SOD pins on the Microprocessor.
 Serial : I/O

• The SID and SOD pins (5 & 4) are used to

connect serial devices to the processor directly.

• The serial devices are connected using a I/O

module which will function as discussed earlier
to control the communication between
processor and I/O device.

• Multiple serial devices can be connected to

these two pins , using multiplexing techniques.
 Parallel I/O
• There are 3 ways in which Processor communicates
with memory and IO :-
– Separate buses for memory and I/O devices
– Shared data and address bus :-
• Isolated I/O – separate control lines.

• Memory Mapped I/O – common control lines.

 Isolated IO
• In the first method, CPU has independent set of
buses for both memory and IO. It is done in
computers that has separate IOP and CPU.
• In second method (Isolated I/O) :-
– Common bus used to transfer data between IO /
memory and CPU. However, a separate control
line (IO/M pin) is used.
– IO is activated using a high state during IO
transfer & memory is activated using low state
during memory transfer.
– This configuration isolates all I/O interface address
with the memory address and is referred to as
Isolated IO method.
IO/M Pin : Select Memory / IO device

This status signal indicates that the read / write

operation relates to whether the memory or I/O
device.
• High to indicate an I/O operation.
• Low for memory operations.
 Isolated IO
• I/O devices are treated separately from memory.

– I/O devices are assigned an address / “port

number” within the 8-bit address range of
00H to FFH.

– The user in this case would access these

devices using the IN and OUT instructions
only.
 Memory Mapped IO
• In third method (Memory Mapped I/O) :-
– Computer treats interface as part of the
memory system.
– Same address space is used for both memory
and IO interface.
– Address space assigned to I/O interface
cannot be used for memory.
– The user uses the same instructions used for
memory read / write
Difference :Memory & I/O mapped
Memory Mapped I/O Mapped
IO is treated as memory. IO is treated as external device.

Memory & I/O share the entire Processor provides separate

address range of processor address range for memory & I/O
Processor provides more address Less address lines for accessing I/O
lines for accessing memory
More Decoding is required Less decoding is required

Memory control signals used to control I/O control signals are used to
Read & Write I/O operations control Read & Write I/O operations

16-bit addressing. 8-bit addressing.

Memory Instructions are used. Special Instructions are used like IN,
OUT.

Arithmetic and logic operations can be Arithmetic and logic operations can
performed on data. not be performed on data.
Processor involved I/O :
Between Memory and
External Devices
 Input Output : Types
• I/O to Memory transfer through CPU :-
– Programmed I/O
– Interrupt driven I/O

• Direct I/O device to Memory channel :

– Direct Memory Access (DMA)
Input Output : Types
 Programmed I/O : Basics
• CPU requests I/O operation on behalf of a
process
• Process waits for the I/O operation to complete
• CPU has direct control over I/O
– Sensing status periodically
– Issues read/write commands to transfer data
• CPU completes data transfer and the process
starts execution.
• Wastes CPU time

PROGRAMMED I/O MODE NOT APPROPRIATE DUE TO PROLONGED WAIT

STATES IN CASE OF ASYNCHRONOUS I/O DEVICES LIKE KEYBD
 Interrupt Driven I/O : Basics
• The processor receives an I/O command from an I/O
device
• The process under execution is suspended and the
I/O is initiated by processor
• The processor may execute another process during
I/O progress
• When the I/O device is ready, the processor is
interrupted to notify same, and I/O begins
• Advantages:-
– I/O module interrupts when ready
– Overcomes CPU waiting
– No repeated CPU checking of device
 Interrupts
• Interrupt is a mechanism through which an
external device can get the attention of the
microprocessor
• The process starts from the I/O device
• The process is asynchronous.
• An interrupt is considered to be an emergency
signal that may be serviced.
• When the Microprocessor receives an
interrupt signal, it suspends the currently
executing program and jumps to an
Interrupt Service Routine (ISR) to respond
to the incoming interrupt.
• Each interrupt generally has its own ISR.
 Classification of Interrupts
• Interrupts can be classified into two types:
• Maskable Interrupts
– Can be delayed or Rejected
– Enabled Or Disabled By EI And DI
Instruction
• Non-Maskable Interrupts
– Can not be delayed or Rejected
• Interrupts can also be classified into:
• Vectored - address of the service routine is
hard-wired
• Non-vectored - address of the service routine
needs to be supplied externally by the device
Interrupt Driven I/O : Basic Operation
Memory and Registers States : Interrupt
 Design Issues
• How do you identify the module issuing the
interrupt?
• How do you deal with multiple simultaneous
interrupts?
 Identifying Interrupting Module
• Different line for each module ?
– Impractical to have large number of interrupt lines /
pins on a processor
– How can one decide on the number of devices
• Software poll
– INTR and INTA lines are used
– CPU branches execution to a generic Interrupt
Service Routine (ISR)
– ISR checks which each I/O module in turn to identify
the interrupting device
– On identifying I/O device suitable device service
routine executed
– Slow
Identifying Interrupting Module
• Hardware poll / Daisy Chain
– I/O Modules are daisy chained
– Interrupt Acknowledge sent down a chain
– Module responsible places vector / address of
it’s service routine on bus
– CPU executes the Device service Routine
• Bus Arbitration / Master
– Module must claim the bus before it can raise
interrupt
– The vector address of the Device Service
Routine is then placed on data bus
Resolving Multiple Interrupts
• There are number of IO devices attached
to the computer.
• They are all capable of generating the
interrupt.
• When the interrupt is generated from more
than one device, priority interrupt
system is used to determine which device
is to be serviced first.
• Devices with high speed transfer are given
higher priority and slow devices are given
lower priority.
 Resolving Multiple Interrupts
• Assign each device a priority level for purpose of
interrupts
– Software polled devices are polled in the order of
their priority

– Hardware polled devices :-

• Daisy chained according to priority
• Hardware priority controller unit used

– In bus mastering only current master can interrupt

Software Polling : Procedure
• There is one common Interrupt Sub Routine
for all I/O devices.
• The common ISR identifies as well as
resolves priority in case of multiple interrupts.
• This ISR contain code to poll the interrupt
sources in sequence as per pre-defined
priority.
• The particular device service routine of the
interrupting device is then executed.
• Disadvantage. Polling time can be long if
large number of I/O devices are connected.
Hardware Polling : Procedure
• Hardware priority unit functions as an overall
manager.
• It identifies interrupt requests and determine
the priorities.
– Serial / Daisy chaining. Polling is required
– Parallel Priority system. Polling is not required
Serial or Daisy Chaining Priority
• Devices are connected in order of priority.
• Device that wants the attention send the interrupt
request to the CPU.
• CPU sends INT ACK signal which is applied to PI(priority
in) of the first device.
• If it had requested the attention, it place its VAD(vector
address) on the bus. And, it blocks the signal by placing
0 in PO(priority out).
• If not, it passes the signal to next device through
PO(priority out) by placing 1.
• This process is continued until appropriate device is
found.
• The device whose PI is 1 and PO is 0 is the device that
sent the interrupt request.
Serial or Daisy Chaining Priority
 Parallel Priority Interrupt
• It consists of interrupt register whose bits are
set according to priority of the interrupting
devices
• Mask register is used to provide masking of
lower priority devices by higher priority ones
• Corresponding interrupt bit and mask bit are
ANDed and applied to priority encoder
• Priority encoder
– Generates vector address
– Generates the INTR signal for CPU
Parallel Priority Interrupt
DMA
 Direct Memory Access
• Interrupt driven and programmed I/O require
active CPU intervention
– Transfer rate is limited
– CPU is tied up
• DMA provides better solution :-
– Additional Module (hardware) on bus
– DMA controller takes over from CPU for I/O
• DMA controller uses buses and transfer the data
directly between I/O devices and memory

DMA is a means of having a peripheral device control a processor's

memory bus directly.
DMA : Configuration
 DMA Operation
• CPU receives and acks the DMA signal
• CPU disconnects itself from the buses
• CPU carries on with other work
• DMA controller deals with transfer
• DMA controller has:-
– Device address
– Starting address of memory block for data
– Amount of data to be transferred
– Read/Write
• DMA controller interrupts CPU when finished
DMA permits peripheral (UART) to transfer data directly to or from memory
without having each byte (or word) handled by the processor.
 DMA Controller
• Has four registers:-
– Address register
• Contains address of memory location to read or write
• Incremented after each word is transferred
- Data register
• Contains data
– Word count register
• Holds the number of words to be transferred.
• Decremented by one after each word is transferred into memory and
checked for zero
– Control register
• Each DMA Controller has four request, ack lines and an independent set
of a/m registers for each set of req / ack lines
• DMA channel - Each set of req / ack line connects an individual I/O
device
DMA Controller
 DMA : Transfer Modes
• Transfer can be perform in two ways:
– Burst Transfer
• Number of memory words are transferred in a
continuous burst
• Done while communicating with fast devices
– Cycle Stealing
• One data word is transfer at a time
• CPU delays it operation for one cycle during
which DMA transfer takes place
• Slows down CPU. But, not as much as in case
of processor involved I/O.
DMA and Interrupt Breakpoints
During an Instruction Cycle
Alternative DMA Configurations
With processor controlled programmed I/O, each transfer of a word consumes
two bus cycles.

The number of required bus cycles can be cut by integrating the DMA and I/O
functions.

In both of these cases (Figures7.13b and c), the system bus that the DMA
module shares with the processor and memory is used by the DMA module
only to exchange data with memory.

The exchange of data between the DMA and I/O modules takes place off the
system bus.
Alternative DMA Configurations
 I/O Channel
The I/O channel represents an extension of the DMA concept. An
I/O channel has the ability to execute I/O instructions, which gives
it complete control over I/O operations. In a computer system with
such devices, the CPU does not execute I/O instructions.

Two types of I/O channels are common

•Selector Channel
•Multiplexor Channel
I/O Channel
 InfiniBand
• Recent I/O specification aimed at the high-end server
market
• First version was released in early 2001
• Standard describes an architecture and specifications for
data flow among processors and intelligent I/O devices
• Has become a popular interface for storage area
networking and other large storage configurations
• Enables servers, remote storage, and other network
devices to be attached in a central fabric of switches and
links
• The switch-based architecture can connect up to 64,000
servers, storage systems, and networking devices
InfiniBand Switch Fabric
+
InfiniBand Operation

• Each physical link between a • The InfiniBand switch maps

switch and an attached traffic from an incoming lane to
interface can support up to 16 an outgoing lane to route the
logical channels, called virtual data between the desired end
lanes points
– One lane is reserved for
fabric management and • A layered protocol architecture
the other lanes for data is used, consisting of four
transport layers:
• A virtual lane is temporarily – Physical
dedicated to the transfer of – Link
data from one end node to
– Network
another over the InfiniBand
fabric – Transport