International Conference on Communications, Information Management and Network Security (CIMNS 2016)

Implementation of a Parallel Prefix Adder Based on

Kogge-Stone Tree
Yancang Chen1,*, Minlei Zhang1, Pei Wei1, Sai Sui1, Yaxin Zhao1 and Lunguo Xie2
1
Luoyang Electronic Equipment Test Center, Luoyang, China
2
National University of Defense Technology, Changsha, China
*Corresponding author

Abstract—Binary adder is an important module for The critical path of parallel prefix adder is the carry tree, so
microprocessors. We present a novel structure of binary adder, lots of people make their greatest efforts to improve the speed
named Hyper-Parallel Prefix Adder (HPPA) in this paper. The of carry tree and have presented lots of structures of carry tree,
basic idea of HPPA is to divide the addition into two levels, both such as Kogge-Stone tree[1], Brent-Kung tree[5], Sklansky
of which are parallel prefix adder architecture. It can perfectly tree[6], Han-Carlson tree[7], Ladner-Fischer tree, Knowles
reduce the delay of wire loads by reducing the wire length in the tree and so on. These structures have the same goal which is to
critical paths; hence the performance of the adder can be compute all the carry bits as soon as possible. The difference
significantly improved. Moreover, we present an optimized carry of these structures is the links between the nodes of trees.
tree structure which is based on Kogge-stone tree named
Among the architectures of carry tree, the Kogge-Stone tree is
Grouped-Kogge-Stone tree (GKS tree), which has small nodes
especially in the top level. Combining HPPA with GKS tree, we
the fast architecture in principle, but its area and power costs
designed and implemented a 64-bit full adder. At the top level, we are expensive.
divide the two 64-bit addition operands into 8 groups, each of In this paper, we present an optimized carry tree structure
which is 8-bit. At the bottom level, we divide each 8-bit group into which is based on Kogge-stone tree named Grouped-Kogge-
4 equal sub-groups. Both of the two levels are composed of Stone tree (GKS tree). By using the GHC tree hierarchically,
parallel prefix adders based on Grouped-Kogge-Stone tree. We we can design optimized hyper-parallel prefix adders.
design the adder using Verilog HDL to verify the performance.
We have implemented the adder under 0.13um CMOS process. The remainder of this paper is organized as follows:
Simulation results show that the maximal delay of the proposed Section 2 describes basic algorithmic of parallel prefix adder;
adder layout is 578ps with the average power of 18.3mW. Section 3 presents the Grouped-Kogge-Stone tree; Section 4
presents the hyper-parallel prefix adder (HPPA) based on GKS
Keywords-parallel prefix adder; CMOS process; maximal delay; tree; Section 5 describes the design and implementation of a
average power; kogge-stone tree 64-bit HPPA based on 8-bit GKS tree, including the detailed
structure of the adder, RTL model and verification, circuit of
I. INTRODUCTION the logical, simulation results and comparison; Finally, we
Binary adder is an important module of microprocessors. It give the conclusions and the future works.
is not only be used to complete addition and subtract operation,
but also be used to achieve multiplication operation, division II. BASIC ALGORITHMIC OF PARALLEL PREFIX ADDER
operation and so on. To the best of our knowledge, the main There are many theories about parallel prefix adders. This
structures of adder include Carry-ripple, Carry-skip, Carry- section we will describe the basic algorithmic of parallel prefix
select, Carry-look-ahead, Parallel- prefix, and so on. adder. This is similar with [3][11][13][14][15], and we made
Carry-Ripple is the basic structure of adders. Its carry bit some reasoning changes.
must be spread from the least significant bit to the most Parallel prefix adder is composed of bit-generate Gi and
significant bit which forms the critical path of the adder[4]. bit-propagate Pi functions, and can be considered as three stage
The carry-skip adder divides operands into several groups and circuits, preprocessing stage, parallel prefix calculation stage
can improve performance only in some cases. Because of the and computing sum stage, respectively. Figure I shows the
use of forward-looking, the performance of carry-select adders details work flow and detail operations of each stage.
improved significantly. The critical path of carry-select adders
is the cascade of the carry bit of the first group and several Let’s consider the addition of two n-bit binary numbers
multiplexers. Each carry bit of carry-look-ahead adders has which are denoted as A=An-1An-2 …A0 and B=Bn-1Bn-2 …B0.
nothing to do with the front carry bit. The increasing The carry bits and the sum are denoted as C=Cn-1Cn-2…C0 and
complexity of each carry circuit makes the delay of adders S=Sn-1Sn-2 … S0. The following functions are hold. Note,
symbols +,  and  denote logical AND, OR and exclusive-OR
increasing linearly. The parallel prefix adder is an improved
architecture of carry-look-ahead adders.
operations, respectively.
Parallel prefix adder is particularly because it can be
attractively fast and compact when implemented in VLSI [3].

© 2016. The authors - Published by Atlantis Press 234

 C0= A0  B0 III. GROUPED-KOGGE-STONE TREE
S0=A0  B0 In 1973, P. Kogge and H. Stone presented the Kogge-
C1= A1  B1+( A1  B1)  C0 Stone tree [1] which is the fastest architecture in theory. Its
S1=A1  B1  C0 fan-out is a constant in all the nodes of the carry tree, and its
…… structure is regular and easy to be realized in VLSI. However,
Ci= Ai  Bi+( Ai  Bi)  Ci-1 when N is 64, the number of prefix nodes is up to 321[2]. So,
its area and power costs are expensive.
Si=Ai  Bi  Ci-1 (  i, 0  i  n-1) (1)
We presents Grouped-Kogge-Stone tree (GKS tree) based
According to the well-known equations Gi=Ai  Bi and on Kogge-Stone tree in the following section. The principle of
Pi=Ai  Bi, the functions (1) can be simply written as: Parallel prefix adder based on GKS tree is similar with our
previous adder presented in paper [2] which combines the
advantages of parallel prefix adders and carry-select adders.
Ci= Gi+(Pi)  Ci-1,
The tree presented by P. Kogge and H. Stone can be simply
Si= Pi  Ci-1 (  i, 0  i  n-1) (2) seen as 1-bit Grouped-Kogge-Stone tree (GKS tree). The tree
needs to compute every carry bit, and the wires between
Unwinding the expression of Ci according to the quations correlative nodes are so long that they will become the critical
(2) as follows path of the tree. In order to improve the speed of the tree, we
can decrease nodes through dividing the tree’s inputs into a
Ci=Gi+Pi  Ci-1 few groups. Every group maybe includes N-bits. In principle,
Ci =Gi+Pi  Gi-1+ Pi  Pi-1  Ci-2
N can be any non-zero integers, but actually N has better to be
(3)
2’s power, such as 2, 4, 8, 16 and so on, because with these
…… values we can make every group has the same size and easy to
be realized in VLSI. Figure II shows the architecture of a 64-
Ci=Gi+Pi  Gi-1+Pi  Pi-1  Gi-2 +Pi  Pi-1  …  Pj+1  Gj+ bit adder’s carry tree based on 4-bit GKS tree.
Pi  Pi-1  …  Pj  Cj-1 (4) We can obtain the 8-bit GKS tree by combining some
nodes of from 4-bit GKS tree. The reduce number of nodes is
Ci =Gi,j +Pi,j  Cj-1 (5) 32. Compared with the traditional Kogge-Stone tree, the 8-bit
GKS tree has many advantages. It needs only 12.5% nodes of
where Gi,j＝Gi+Pi  Gi-1+Pi  Pi-1  Gi-2+Pi  Pi-1  …  Pj+1  Gj Kogge-Stone tree in the CM3, CM4 and CM5, so the wire is
and Pi,j ＝Pi  Pi-1  …  Pj represent group bit-generate and 12.5% as long as the traditional Kogge-Stone tree and the wire
group bit-propagate, respectively[3][15]. [15] presented a load delay is 1.56% (strictly is 1/64) of Kogge-Stone tree. The
prefix operator  to transform carry computation to prefix largest fan-out of GKS tree is the same as Kogge-Stone tree.
problem. The definition of prefix operator is shown as
following.
(G, P)  (G’,P’) = (G+P  G’, P  P’)
Therefore, (Gi,j, Pi,j)can be represented as follow.

(Gi,j, Pi,j) = (Gi, Pi)  (Gi-1,Pi-1)  …  (Gj+1, Pj+1)  (Gj, Pj) (6)

The equation (6) is the basis of prefix computation. The

basic algorithmic of prefix operation is described in Figure I.
Bn1 An1 B0 A0
(Gn1 , Pn1 ),, (G0 , P0 ), Cin

C n1 , C n 2 ,, C1 , C 0 , C out

Gi  Ai  Bi Pi  Ai  Bi

Gn 1 , Pn 1 G0 , P0
FIGURE II. 4-BIT GROUPED-KOGGE-STONE TREE OF 64-BIT
ADDERS
(G0, 0 , P0,0 )  (G0 , P0 )
Cin
(G1,0 , P1,0 )  (G1 , P1 )  (G0 , P0 )
Ci  Gi , j  Pi , j  C j 1
IV. HYPER-PARALLEL PREFIX ADDER
(G j ,0 , Pj ,0 )  (G j , Pj )    (G0 , P0 )
Cout C n 1 C0 We designed a Hyper-Parallel Prefix Adder (HPPA) by
C 0  G0  P0  C in using Grouped-Kogge-Stone tree to improve the performance
S i  Pi  Ci 1
C j  G j  Pj  C j 1
of the adder. In this adder, the two operands of addition are
S n1 C out  C n divided into several groups. As shown in Figure III, operand A
S0
is divided into j groups which are A0, A1, …, Ai, …, Aj-2, Aj-1,
respectively. Accordingly, operand B should also be split into j
FIGURE I. THE WORK FLOW OF PARALLEL PREFIX ADDER
groups which can be expressed as B0, B1, …, Bi, …, Bj-2, Bj-1,.

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Note that, Ai and Bi must have the same number of bits which Both of the two 8-bit PPA have two common output
assumed to be Ni. In the operation of A plus B, Ai and Bi must signals G/P, which will be used in the top level of the 64-bit
do addition operator with the carry bit which we do know yet. adder. The input signals of the multiplexers come from 2-bit
In order to improve the speed of the operation, we use two Carry-Ripple adders. The output signals of the multiplexers
child parallel prefix adders to compute the sum, which is the are also used by the top level of the 64-bit adder.
same as carry-select adders. The select control signal comes 2
PG 7 6 5 4 3 1 0 PG 7 6 5 4 3 2 1 0
from the GKS tree. All the groups shown in Figure III are
divided again. CM0 1 1 CM0 1 1
1

CM1 CM1

A j 1 A j 2 Ai A1 A0
CM2 CM2

MUX MUX MUX MUX MUX MUX MUX

B j 1 B j 2 Bi B1 B0
G/P S(7:6) S(5:4) S(3:2) S(1:0) G/P S(7:6) S(5:4) S(3:2) S(1:0)

FIGURE IV. THE CARRY 8-BIT PPA AND NON-CARRY 8-BIT PPA
BASED ON 2-BIT GKS TREE
FIGURE III. DIVIDE OPERANDS A AND B
B. The Top Level of the Adder
Actually, a hyper-parallel prefix adder has two levels, both
of which are parallel prefix adders, which is the reason for its The architecture of the top level of the 64-bit adder is
name. The top level combines all the lower level together. shown in Figure V. All of the input signals of the top level
come from the bottom level.
The hyper-parallel prefix adder which has several child
parallel prefix adders is the improvement of parallel prefix
adder. It can fully develop parallelism insides adder, hence
may significantly improve the performance of adder. In order
to testify the performance of HPPA, we design a 64-bit HPPA
based on 8-bit GKS tree.

V. IMPLEMENTATION OF 64-BIT HPPA

In order to verify the performance of the adder we
presented, we design a 64-bit Hyper-Parallel Prefix Adder by
simply dividing the two operands of adder equally. The two
64-bit operands of addition are divided into eight equal groups, FIGURE V. TOP LEVEL OF THE ADDER
so each group has 8-bit. Each of the 8-bit group is divided into
4 equal sub-groups. Comparing the Figure II with the Figure V, you can see
Therefore, the 64-bit adder can be seen as two levels. At that the input signals of the carry tree of the top level of the
the bottom level of the adder, there are several 8-bit parallel adder come from the output signals G/P, and the input of
prefix adders and at the top level, there is only one 64-bit multiplexers come from the two kinds of 8-bit PPA. The first
adder which accepts the output of the bottom adders, other group does not need multiplexer because of non-carry bit. Of
than the original operands. The remainder of this section, we course, we can design adders support carry bit by change the
will introduce the structure of each level of the adder in detail. carry tree without decreasing the performance of the adder.
The critical path is lies in the carry tree, especially because of
A. The Bottom Level of the Adder: 8-bit PPA the wire loads delay.
In our design, we use two different 8-bit parallel prefix C. RTL Model Design and Verification
adders, both of which are based on 2-bit GKS tree, one of
them is used for non-carry bit addition and the other is used We designed RTL model of the presented adder using
for carry addition, as shown in Figure IV. As we seen from the Verilog HDL to verify its correctness. Then, we designed its
figure, there is only little difference between the two kinds of test module to generate random stimulus, created the abstract
8-bit PPA. model, compared outputs of the adder with the abstract model,
and outputted the results of the comparison to a file. The RTL
We reuse the common nodes of the two PPA to reduce the model of the adder has two modules, which are the bottom
total area of the 64-bit adder. Except for the first 8-bit group of module and the top module respectively.
operands, each of the other groups uses both of the two kinds
of 8-bit PPA once. The first group which is also called the D. Implementation Circuits
lowest group just uses non-carry 8-bit PPA once, because our
64-bit adder doesn’t has carry bit. In COMS process, AND gate is implemented by two level
gate which are NAND and NOT, and OR gate is implemented
by NOR gate cascades NOT gate. Therefore, we made

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exiguous changes to the previous circuits to minimize the source. The simulation results show that the maximal delay of
logical level of the adder. The changes are shown in Table I. the proposed adder is 679ps, as shown in Figure VII. Figure
VIII gives the vivid comparison of those adders. The figure
In our design, we use dynamic domino logical circuits to also gives the detailed information about other adders
implement the P and the G, and use pass-transistor logical designed in references [3], [8], [9], [10].
circuit to implement multiplexer. The other circuits are
designed using static logic. The sizes of transistors in the
circuits are elaborate set. In order to maximize the adder VI. CONCLUSIONS
performance, we adopt skew CMOS circuits when we design In this paper, we present adder architecture: Hyper-Parallel
the size of transistors. The skew CMOS logical circuit [12] is Prefix Adder (HPPA) based on the Grouped-Kogge-Stone tree.
presented by Alexandre Solomatnikov to design noise-immune It can fully develop parallelism inside adder and reduce the
high-performance low-power static circuits. delay of wire loads by reducing the wire length in the critical
We designed the 64-bit adder based on the structure we path, hence can significantly improve the performance of
presented using 0.13um CMOS process. The layout of the adders. In the future, we will consider to improving the
adder we designed is shown in Figure VI. Its length is 635um, performance of the adder by reducing the carry tree level
and height is 40um. through other structures of nodes of the carry tree.

ACKNOWLEDGMENT
TABLE I. UNITS AND CORRESPONDING SYMBOLS
This work was supported by Natural Science Foundation of
level P G China (Grant No. 61303061) and State Key Laboratory of high
P&G P  Ai  Bi Gi  Ai  Bi
performance computing (Grant No.201513-01).

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FIGURE VII. SIMULATION RESULT
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FIGURE VIII. PERFORMANCE COMPARISON

After the layout has been designed successfully, we

simulate the layout under the worst case using 1.2V electrical

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