CONTENTS
Abstract ………………………………………………………………. i
Contents ………………………………………………………………. ii – iii
List of Figures ……………………………………………………............ iv – v
List of Tables ……………………………………………………………. vi
List of Abbreviations Used………………………………………………. vii – viii
Chapter 1 INTRODUCTION…………………………………………... 1
1.1 Literature Survey ………….……………………………. 2
1.2 Contribution ……………………………………………. 3
1.3 Organization of Dissertation …………………………… 4
1.4 Tools Used ……………………………………………... 4
Chapter 2 HASH FUNCTIONS………………………………………. 5
2.1 Definition And Properties of Hash Functions…………... 5
2.2 Applications of Hash Functions………………………… 7
2.3 Attacks on Hash Functions……………………………… 13
2.4 Hash Computation Flow………………………………… 13
2.4.1 SHA1……………………………………………… 14
2.4.1.1 SHA1 Functions………………………………… 15
2.4.1.2 SHA1 Constants………………………………… 17
2.4.1.3 SHA1 Computation Flow……………….............. 17
2.5 Different Hash Implementations………………………... 20
i
LIST OF FIGURES
Fig 2-1 Hashing Operation…………………………………………....... 6
Fig 2-2 Pre-image Resistance………………………………………….. 6
Fig 2-3 Second Pre-image Resistance………………………………….. 7
Fig 2-4 Collision Resistance…………………………………………… 7
Fig 2-5 Verifying Data Integrity……………………………………….. 9
Fig 2-6 Storing The Hash of a Password………………………………. 10
Fig 2-7 Authenticating Users………………………………………....... 11
Fig 2-8 Application of Digital Signature……………………………..... 13
Fig 2-9 Verification of a Digital Signature…………………………… 13
Fig 2-10 General Hash Computation Flow…………………………........ 15
Fig 2-11 Ch Function Architecture……………………………………… 16
Fig 2-12 Parity Function Architecture…………………………………... 16
Fig 2-13 Maj Function Architecture…………………………………….. 17
Fig 2-14 Message Padding………………………………………………. 18
Fig 2-15 SHA-1 Computation Flow…………………………………….. 21
Fig 2-16 General Block Diagram for a Hash Function Implementation... 23
Fig 3-1 FPGA Architecture…………………………………………….. 29
Fig 3-2 HDL Based FPGA design Flow……………………………….. 30
Fig 3-3 Schematic Based FPGA design Flow…………………………. 31
Fig 3-4 Levels of Abstraction………………………………………….. 32
ii
LIST OF TABLES
Table 2-1 SHA Summary…………………………………………... 15
Table 2-2 SHA- 1 Functions………………………………………... 17
Table 2-3 SHA- 1 Constants………………………………………... 18
Table 2-4 Initial Hash Value for SHA-1……………………………. 19
Table 2-5 Commercial Hash Function Cores………………………. 27
Table 3-1 Comparison of Resources Available in various FPGAs… 33
Table 4-1 Resource Utilization of Initial module for Virtex5……… 37
Table 4-2 Resource Utilization of Round module for Virtex5……... 41
Table 4-3 Resource Utilization of Last Block module for Virtex5… 43
Table 4-4 Resource Utilization of Final module for Virtex5………. 46
Table 4-5 Resource Utilization of Top module for Virtex5………... 49
Device Utilization Summary after Synthesis (Virtex5-
Table 4-6 51
XC5VLX220)……………………………………………..
Table 4-7 Timing Report after Synthesis (Virtex5-XC5VLX220)… 51
iii
List of Abbreviations/ Symbols
AHC Advanced Hash Calculator
ASCII American Standard Code for Information Interchange
ASIC Application Specific Integrated Circuit
DSA Digital Signature Algorithm
DSS Digital Signature Standard
FIPS Federal Information Processing Standard
FPGA Field Programmable Gate Array
FTP File Transfer Protocol
HDL Hardware Description Language
HMAC Hash Message Authentication Code
IOB Input / Output Block
IP Intellectual Property
JTAG Joint Test Action Group
LED Light Emitting Diode
LUT Look-Up Table
MAC Message Authentication Code
Mbps Mega-bits Per Second
MD5, MD4 Message Digest
MHz Mega Hertz
NCD Native Circuit Description
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