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Educational Practice Board C6748 Workbook
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Program changes in “Hello World” program
1. You can edit the source code of hello.c file as per your requirement,
compile/build/rebuild and debug/execute the code.
2. Default hello world program consist default command file named “[Link]”.
a. Content is as shown here.
b. Here CPU TMS320C6748’s memory map is organized as per the datasheet.
c. MEMORY area consists of different types of memory’s start address and its total
length.
d. Comment line displays its type and total size for that memory section.
e. SECTIONS area consist of different section of programs i.e. text, stack, ebss ,
cinit etc.
f. This area decides runtime program memory allocation. User can change the
command file for this section as per their requirement.
These sections cover different parts of the object module, which must be “linked” to physical memory.
Our four sections are:
• .text This section collects all assembly code instructions
• .ebss The section covers all global and static variables
• .cinit This section is used for initial values
• .stack The stack memory for local variables, return addresses, parameters
Below [Link] command file will take care the default hello world program with SHRAM
memory that is 128KB shared RAM section.
g. Now execute the program with this SHRAM setting for Command file and check
the output using same
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/****************************************************************************/
/* [Link] */
/* Copyright (c) 2010 Texas Instruments Incorporated */
/* Author: Rafael de Souza */
/* */
/* Description: This file is a sample linker command file that can be */
/* used for linking programs built with the C compiler and */
/* running the resulting .out file on a C6748 */
/* device. Use it as a guideline. You will want to */
/* change the memory layout to match your specific C6xxx */
/* target system. You may want to change the allocation */
/* scheme according to the size of your program. */
/* */
/****************************************************************************/
MEMORY
{
DSPL2ROM o = 0x00700000 l = 0x00100000 /* 1MB L2 Internal ROM */
DSPL2RAM o = 0x00800000 l = 0x00040000 /* 256kB L2 Internal RAM */
DSPL1PRAM o = 0x00E00000 l = 0x00008000 /* 32kB L1 Internal Program RAM */
DSPL1DRAM o = 0x00F00000 l = 0x00008000 /* 32kB L1 Internal Data RAM */
SHDSPL2ROM o = 0x11700000 l = 0x00100000 /* 1MB L2 Shared Internal ROM */
SHDSPL2RAM o = 0x11800000 l = 0x00040000 /* 256kB L2 Shared Internal RAM */
SHDSPL1PRAM o = 0x11E00000 l = 0x00008000 /* 32kB L1 Shared Internal Program RAM */
SHDSPL1DRAM o = 0x11F00000 l = 0x00008000 /* 32kB L1 Shared Internal Data RAM */
EMIFACS0 o = 0x40000000 l = 0x20000000 /* 512MB SDRAM Data (CS0) */
EMIFACS2 o = 0x60000000 l = 0x02000000 /* 32MB Async Data (CS2) */
EMIFACS3 o = 0x62000000 l = 0x02000000 /* 32MB Async Data (CS3) */
EMIFACS4 o = 0x64000000 l = 0x02000000 /* 32MB Async Data (CS4) */
EMIFACS5 o = 0x66000000 l = 0x02000000 /* 32MB Async Data (CS5) */
SHRAM o = 0x80000000 l = 0x00020000 /* 128kB Shared RAM */
DDR2 o = 0xC0000000 l = 0x20000000 /* 512MB DDR2 Data */
}
SECTIONS
{
.text > SHRAM
.stack > SHRAM
.bss > SHRAM
.cio > SHRAM
.const > SHRAM
.data > SHRAM
.switch > SHRAM
.sysmem > SHRAM
.far > SHRAM
.args > SHRAM
.ppinfo > SHRAM
.ppdata > SHRAM
/* COFF sections */
.pinit > SHRAM
.cinit > SHRAM
/* EABI sections */
.binit > SHRAM
.init_array > SHRAM
.neardata > SHRAM
.fardata > SHRAM
.rodata > SHRAM
.[Link] > SHRAM
.[Link] > SHRAM
}
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3. Now change the command file as shown here and check the program output and verify.
Replace SHRAM from the SECTIONS section by DSPL2RAM and SHDSPL2RAM so that the
program sections will be downloaded to that RAM location and will be executed from that
location.
h. Same as change this SECTIONS section for different RAM locations and check the
program output and behavior.
/****************************************************************************/
/* [Link] */
/* Copyright (c) 2010 Texas Instruments Incorporated */
/* Author: Rafael de Souza */
/* */
/* Description: This file is a sample linker command file that can be */
/* used for linking programs built with the C compiler and */
/* running the resulting .out file on a C6748 */
/* device. Use it as a guideline. You will want to */
/* change the memory layout to match your specific C6xxx */
/* target system. You may want to change the allocation */
/* scheme according to the size of your program. */
/* */
/****************************************************************************/
MEMORY
{
DSPL2ROM o = 0x00700000 l = 0x00100000 /* 1MB L2 Internal ROM */
DSPL2RAM o = 0x00800000 l = 0x00040000 /* 256kB L2 Internal RAM */
DSPL1PRAM o = 0x00E00000 l = 0x00008000 /* 32kB L1 Internal Program RAM */
DSPL1DRAM o = 0x00F00000 l = 0x00008000 /* 32kB L1 Internal Data RAM */
SHDSPL2ROM o = 0x11700000 l = 0x00100000 /* 1MB L2 Shared Internal ROM */
SHDSPL2RAM o = 0x11800000 l = 0x00040000 /* 256kB L2 Shared Internal RAM */
SHDSPL1PRAM o = 0x11E00000 l = 0x00008000 /* 32kB L1 Shared Internal Program RAM */
SHDSPL1DRAM o = 0x11F00000 l = 0x00008000 /* 32kB L1 Shared Internal Data RAM */
EMIFACS0 o = 0x40000000 l = 0x20000000 /* 512MB SDRAM Data (CS0) */
EMIFACS2 o = 0x60000000 l = 0x02000000 /* 32MB Async Data (CS2) */
EMIFACS3 o = 0x62000000 l = 0x02000000 /* 32MB Async Data (CS3) */
EMIFACS4 o = 0x64000000 l = 0x02000000 /* 32MB Async Data (CS4) */
EMIFACS5 o = 0x66000000 l = 0x02000000 /* 32MB Async Data (CS5) */
SHRAM o = 0x80000000 l = 0x00020000 /* 128kB Shared RAM */
DDR2 o = 0xC0000000 l = 0x20000000 /* 512MB DDR2 Data */
}
SECTIONS
{
.text > DSPL2RAM
.stack > DSPL2RAM
.bss > DSPL2RAM
.cio > DSPL2RAM
.const > DSPL2RAM
.data > DSPL2RAM
.switch > DSPL2RAM
.sysmem > DSPL2RAM
.far > DSPL2RAM
.args > DSPL2RAM
.ppinfo > DSPL2RAM
.ppdata > DSPL2RAM
/* COFF sections */
.pinit > DSPL2RAM
.cinit > DSPL2RAM
/* EABI sections */
.binit > DSPL2RAM
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.init_array > DSPL2RAM
.neardata > DSPL2RAM
.fardata > DSPL2RAM
.rodata > DSPL2RAM
.[Link] > DSPL2RAM
.[Link] > DSPL2RAM
}
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Tested OK SECTIONS:
SHRAM
DSPL2RAM
SHDSPL2RAM
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