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Table 1-9:: I/O Capabilities

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10 views1 page

Table 1-9:: I/O Capabilities

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Thiện Khiêm
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R

I/O Capabilities

Table 1-9: Differential I/O Standards


Spartan-3 Spartan-3E Extended Spartan-3A
Standard VCCO
FPGAs FPGAs Family FPGAs
2.5V √ √ √
LVDS
3.3V √
BLVDS 2.5V √ √ √
2.5V √ √
MINI_LVDS
3.3V √
2.5V √ √ √
LVPECL
3.3V √
2.5V √ √ √
RSDS
3.3V √
2.5V
TMDS
3.3V √
2.5V √
PPDS
3.3V √
LDT 2.5V √
LVDSEXT 2.5V √
DIFF_SSTL - √ √ √
DIFF_HSTL - √ √ √
DIFF_TERM - √ √

Table 1-10: Spartan-3A FPGA DSP Available User I/Os and Differential (Diff) I/O Pairs
CS484 FG676
Device CSG484 FGG676

User Diff User Diff

309 140 519 227


XC3SD1800A
(56) (78) (110) (131)

309 140 469 213


XC3SD3400A
(56) (78) (60) (117)

Notes:
1. The number in bold indicates the maximum number of I/O and input-only pins. The number in italics
indicates the number of input-only pins. The differential (Diff) input-only pin count includes both
differential pairs on input-only pins and differential pairs on I/O pins within I/O banks that are
restricted to differential inputs.

Spartan-3 Generation FPGA User Guide www.xilinx.com 39


UG331 (v1.8) June 13, 2011

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