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1K views491 pages

Microchip SXP 12g Firmware User Manual 388661

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shantibhushan.sale

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PM73206_04 SXP 12G Firmware User Guide

Introduction
The PM73206_04 firmware supports the following series of Microchip SXP 12G SAS expanders:
• PM8056 SXP 68x12G
• PM8055 SXP 48x12G
• PM8054 SXP 36x12G
• PM8053 SXP 24x12G
• PM8044 SXP 36Sx12G
• PM8043 SXP 24Sx12G
These devices are 68, 48, 36, 24, 36, and 24-port SAS expanders. The firmware release consists of a single firmware
code base to support the six devices above.
The PM73206_04 firmware is compatible with Microchip’s maxSAS 3 Gbit/s and 6 Gbit/s SAS expanders. The
standard MIPS processor that is integrated into each expander provides a platform for developing your Enclosure
Management Application (EMA).
The following table describes the part family and firmware naming:
Table 1. Part Family/Firmware Naming

Expander Expander Family Expander Name Device Firmware

SXP 36x3G PM8387

SXP 24x3G PM8388

SXP 3G PM73206_02
SXP 36x3Gsec PM8398

SXP 24x3Gsec PM8399

SXP 36x6Gsec PM8005

SXP 6G PM73206_03
SXP 24x6Gsec PM8004
SXP
SXP 68x12G PM8056

SXP 48x12G PM8055

SXP 36x12G PM8054

SXP 12G PM73206_04
SXP 24x12G PM8053

SXP 36Sx12G PM8044

SXP 24Sx12G PM8043

This document refers to the PM8056 SXP 68x12G, PM8055 SXP 48x12G, PM8054 SXP 36x12G, PM8053 SXP
24x12G, PM8044 SXP 36Sx12G and PM8043 SXP 24Sx12G devices collectively as the “SXP 12G device”. Any
information that is unique to a device is explicitly stated.

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 1

SXP SAS Expander and Enclosure Management Overview
The SXP SAS expander is a highly integrated device. The expander function is combined with the firmware needed
to control expander operations through Serial Management Protocol (SMP) and the Ethernet interface (PM805x
devices only), and includes user-extensible firmware for performing Enclosure Management (EM).
The Enclosure Management Application (EMA) comprises the Storage Enclosure Processor (SEP) and the SEP
firmware. It is located within the drive array enclosure and, at a high level, performs the following functions:
• Initializes the system and peripherals at startup using driver and protocol initialization functions.
• Monitors the health of the enclosure through peripheral interfaces and controls peripherals where appropriate.
• Monitors and controls the data communication links in the transport portion of the device or chipset.
• Processes SES requests initiated from the controller or received from the protocol stack and reports the
appropriate data from the peripherals.
The following figure illustrates the protocol layers involved in SES communication with the Enclosure Management
Application in the expander device.
Figure 1. SES Protocol Layers
Enclosure M anagem ent Application

Application

SES

SCSI Target Em ulator

SPC

Device-Specific Transport

Protocols

Signaling

State M achines

Hardware

State M achines

Transm ission Protocol

Physical Links

Figure 2 shows the host communicating with the expander device. When the firmware is used with the
PM2513/14/15/16/32-KIT SXP 24/36/48/68/36Sx12G Evaluation Kit [28], the host is represented by a PC. In your
own system, the PC is replaced by your host controller, and the peripherals on the Evaluation Kit are replaced by the
peripherals in the enclosure that you are developing.

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 2

Figure 2. System Configuration

The SXP combines the expander and EMA functions within a single-chip SOC unlike traditional EM implementations
where an external processor or a separate Storage Enclosure Processor (SEP) is used. The SXP communicates
with the host through TWI and UART, through SES commands over SAS transport, and on the SXP 12G/6G,
through Ethernet (PM805x devices only). Although the device supports out-of-band reporting, using the SAS
transport reduces the number of communication mechanisms, increases transaction speeds, and provides industry
standardization through SES.

Firmware Overview

The PM73206_04 firmware is extensible and provides a base for developing an Enclosure Management Application
tailored to your peripheral hardware configuration and enclosure control algorithm. The PM73206_04 firmware is
designed, verified, and validated for use in your system.
The PM73206_04 firmware comprises library functions, user-extensible functions, and examples. The following table
summarizes the components of the firmware and how you should use them.
Table 2. How to Use the SXP Firmware

Firmware Component Type Comments

Operating System Functions Library Use as provided

Device Drivers Extensible Develop custom code around the provided drivers

Bootloader Extensible Modify as needed to meet your system requirements

Power-On Self-Test Extensible Modify as needed to meet your system requirements

Run-Time Services Extensible Modify as needed to meet your system requirements

Protocol Stack Library Library Use as provided

EMA Example Example Develop custom code to meet your system requirements

Application Code Examples Example Develop custom code to meet your system requirements

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 3

The EMA example provided in Section 18.2 Application Top-Level Project is built to run on the PM2516-KIT SXP
68x12G Evaluation Kit but can be ported to your system.

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 4

Table of Contents
Introduction.....................................................................................................................................................1
SXP SAS Expander and Enclosure Management Overview.................................................................. 2
Firmware Overview................................................................................................................................. 3

1. Preface....................................................................................................................................................9
1.1. Scope........................................................................................................................................... 9
1.2. Section Summary......................................................................................................................... 9
1.3. Audience.................................................................................................................................... 10
1.4. Notation...................................................................................................................................... 10
1.5. References................................................................................................................................. 10
1.6. Glossary of Terms and Acronyms...............................................................................................11

2. Functional Description...........................................................................................................................13
2.1. High Speed Serial Interfaces......................................................................................................14
2.2. Processor Subsystem................................................................................................................ 15
2.3. Expander Port Interfaces............................................................................................................17
2.4. Initialization, Management, and Enclosure Services Support.................................................... 18

3. Firmware Architecture........................................................................................................................... 20
3.1. Firmware Modules......................................................................................................................20
3.2. Thread Decomposition............................................................................................................... 24
3.3. Firmware PHY Bitmap Type....................................................................................................... 24

4. Firmware Download Mechanism...........................................................................................................26

4.1. Application Firmware Image Management and Launching Mechanism.....................................26
4.2. Firmware Download .................................................................................................................. 27
4.3. Flash Memory Image Verification............................................................................................... 30
4.4. Flash Partition Map ................................................................................................................... 31
4.5. Firmware Image Authentication..................................................................................................35

5. Bootloader.............................................................................................................................................39
5.1. Simplified Bootloader................................................................................................................. 40
5.2. Power-On Self-Test (POST)....................................................................................................... 41
5.3. System Recovery in Bootloader................................................................................................. 41
5.4. Reset Event and NMI Handling.................................................................................................. 41
5.5. Bootloader User-Defined Hooks.................................................................................................43

6. Operating System Functions.................................................................................................................47

6.1. Overview.................................................................................................................................... 47
6.2. System Initialization ...................................................................................................................50
6.3. User Memory Management........................................................................................................52
6.4. Threads...................................................................................................................................... 56
6.5. Messaging.................................................................................................................................. 59
6.6. Logging.......................................................................................................................................64
6.7. Timers.........................................................................................................................................75
6.8. Semaphores .............................................................................................................................. 81
6.9. Mutexes .....................................................................................................................................84

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6.10. Interrupt Control Framework...................................................................................................... 86
6.11. MBIC Interrupt Controller Framework........................................................................................ 89

7. Device Drivers.......................................................................................................................................93
7.1. Flash...........................................................................................................................................96
7.2. TWI........................................................................................................................................... 110
7.3. UART........................................................................................................................................125
7.4. SGPIO...................................................................................................................................... 130
7.5. GPIO........................................................................................................................................ 130
7.6. Ethernet....................................................................................................................................133
7.7. Real Time Clock (RTC) Driver..................................................................................................133
7.8. Application Timer Driver........................................................................................................... 134
7.9. MIPS 34Kc Hardware Abstraction APIs................................................................................... 137

8. Initialization String............................................................................................................................... 142

8.1. Flash Memory Initialization String............................................................................................ 142
8.2. SEEPROM Initialization String................................................................................................. 142
8.3. Initialization String Format........................................................................................................142

9. Time Services Library..........................................................................................................................219

9.1. Watchdog Thread and Watchdog Timer...................................................................................219
9.2. Debug Console/Thread............................................................................................................ 225
9.3. Database.................................................................................................................................. 229
9.4. LED Control through SGPIO.................................................................................................... 234
9.5. SXP Diagnostics.......................................................................................................................239
9.6. IPMB.........................................................................................................................................268

10. Port Manager Component...................................................................................................................272

10.1. Port Event Manager................................................................................................................. 272
10.2. Topology Discovery (SAS 1.1)..................................................................................................273
10.3. Topology Discovery (SAS-2.0)................................................................................................. 274
10.4. Disk Spin-up............................................................................................................................. 281
10.5. Programmable Staggered Spin-Up Algorithm.......................................................................... 286

11. Disk Qualification................................................................................................................................ 293

11.1. What is Disk Qualification?.......................................................................................................293
11.2. Devices Supporting the Disk Qualification Feature.................................................................. 293
11.3. Qualification Metrics................................................................................................................. 293
11.4. Disk Qualification Status.......................................................................................................... 295
11.5. Disk Qualification Thread Dependencies................................................................................. 295
11.6. Customization...........................................................................................................................296

12. Reduced Functionality and Non-I/O Disruptive Soft Reset................................................................. 297

12.1. Reduced Functionality (RF)......................................................................................................297
12.2. Non-I/O Disruptive Soft Reset (NDSR).................................................................................... 299

13. Zoning................................................................................................................................................. 304

13.1. What is Zoning?....................................................................................................................... 304
13.2. Zone PHY Information..............................................................................................................305

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 6

13.3. Access Permissions................................................................................................................. 306
13.4. INSIDE ZPSDS versus Not INSIDE ZPSDS............................................................................ 306
13.5. Source Check...........................................................................................................................307
13.6. Broadcast Processing.............................................................................................................. 307
13.7. Zone Manager.......................................................................................................................... 307
13.8. Zone Information Type............................................................................................................. 308
13.9. Zoning Configuration after System Power-on.......................................................................... 308
13.10. Zoning Configuration On The Fly............................................................................................. 309

14. Protocol Stack Library......................................................................................................................... 311

14.1. SAS Port Component............................................................................................................... 312
14.2. SCSI Enclosure Services (SES)...............................................................................................313
14.3. SCSI Target Emulator (STE).................................................................................................... 376
14.4. Serial SCSI Protocol (SSP) Target Transport Layer.................................................................396
14.5. Serial SCSI Protocol (SSP) Initiator Transport layer................................................................ 397
14.6. SCSI Tunneling Protocol (STP) Initiator Transport Layer.........................................................397
14.7. Serial Management Protocol (SMP) Application Layer............................................................ 397
14.8. Serial Management Protocol (SMP) Transport Layer...............................................................419
14.9. SAS Port Layer.........................................................................................................................419
14.10. Dethroughtions from the SAS Standard...................................................................................419
14.11. Telnet, TCP/IP and Ethernet.....................................................................................................420

15. PHY and Power Management.............................................................................................................423

15.1. Managed SAS Connector Support........................................................................................... 423
15.2. Optical Cable Support.............................................................................................................. 426
15.3. Coordination of SAS Device Power Consumption................................................................... 426
15.4. Wake-on-LAN / Wake-on-SAS................................................................................................. 426
15.5. Early Power Off Warning (EPOW)............................................................................................433
15.6. Power Disable.......................................................................................................................... 434

16. Inter-Expander Communication.......................................................................................................... 435

16.1. Inter-Expander Communication Over TWI............................................................................... 435
16.2. Inter-Expander Communication Over SAS...............................................................................435

17. Event Logging and Error Handling...................................................................................................... 438

17.1. Hardware and Firmware Block Errors...................................................................................... 438
17.2. Enhanced Event Logging......................................................................................................... 440
17.3. SMP Self Configuration Event Logging.................................................................................... 444
17.4. Error Codes.............................................................................................................................. 446
17.5. Log Parsing Instructions...........................................................................................................447
17.6. Fatal Error Handling................................................................................................................. 447
17.7. Assert Functionality.................................................................................................................. 453

18. Application Code Examples................................................................................................................ 455

18.1. twimon ..................................................................................................................................... 455
18.2. Application Top-Level Project .................................................................................................. 455

19. Host Utilities........................................................................................................................................ 460

19.1. Microchip SCSI Utility...............................................................................................................460

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 7

19.2. Microchip Log Parser Utility......................................................................................................465
19.3. Host Diagnostic Tool.................................................................................................................465

20. Revision History.................................................................................................................................. 473

The Microchip Website...............................................................................................................................488

Product Change Notification Service..........................................................................................................488

Customer Support...................................................................................................................................... 488

Microchip Devices Code Protection Feature.............................................................................................. 488

Legal Notice............................................................................................................................................... 489

Trademarks................................................................................................................................................ 489

Quality Management System..................................................................................................................... 490

Worldwide Sales and Service.....................................................................................................................491

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 8

Preface

1. Preface

1.1 Scope
The PM73206_04 SXP 12G software/firmware product is used with the SXP 12G evaluation kit. The SXP 12G
Firmware User Manual accompanies the SXP 12G firmware and describes peripheral drivers, the transport layer
protocols terminated by the firmware and upper layers of the protocol stack including the SCSI and EMA applications.

1.2 Section Summary

This section provides a brief overview of the sections in this document.
Table 1-1. Section Summary

Section Summary

Introduction Briefly introduces the background, SDK naming, and application.

SXP Device Function Provides a brief functional overview of the primary blocks in the device.
Description

Firmware architecture Introduces the firmware architecture.

Firmware Download Introduces the firmware download mechanism and describes changes.
Mechanism

Bootloader Introduces the bootloader.

Operating System Functions Presents an overview of the OSF layer.

Device Drivers Introduces various peripheral drivers.

Initialization String Discusses both flash memory and the SEEPROM initialization string.

Run Time Service Library Introduces the watchdog thread, debugging thread, database, SGPIO, and
diagnostics.

Port Manager Component Includes a description of the Port Event Manager, topology discovery and spin up.

Disk Qualification Introduces disk qualification.

Reduced Functionality and Presents RF functionality in the SAS specification and the Microchip NDSR feature.
Non-I/O Disruptive Soft
Reset

Zoning Introduces the zoning feature.

Protocol Stack Library Introduces the SSP, SMP, and STP transport and port layer.

PHY and Power Discusses connection management, power management, and EPOW.
Management

Inter-Expander Describes the method used for inter-expander communication.

Communication

Event Logging and Error Presents the event log format and APIs. Also describes the error handling method.
Handling

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 9

Preface

...........continued
Section Summary

Application Code examples Provides example code like TWImon and sxp_wks_evbd.gpj.

Host Utilities Describes pmc_scsi and diag_user usage.

1.3 Audience
This manual is intended for firmware developers familiar with C code development, storage system protocols
including SCSI, and RTOS concepts, and who are using peripheral devices such as temperature sensors, SGPIO
and UARTs. Although this manual gives an overview of how the firmware uses certain protocols and peripherals,
readers should have a working understanding of the protocols shown in the References section.

1.4 Notation
The following are the typographic conventions used in this document.
Table 1-2. Notation

Configuration parameter Configuration parameter variable name used in configuration tools

SW/FW Command SW/FW commands

function_name Function names

This is an alarm Alarms

This_is_a_STATE State

1.5 References
The documents listed in this section are referred to throughout this user manual. If you require any of these
documents, contact Microchip.
1. Express Logic, Inc., ThreadX User Guide, Part Number 000-1001, Revision 5.0
2. MIPS Technologies, Inc., Programming MIPS32™ 34K™ Processor Cores Family, Document Number
MD00427, Revision 01.62, Oct 31, 2007
3. American National Standard, Information Technology – Serial Attached SCSI – 1.1 (SAS-1.1). Project
T10/1601-D, Revision 10, 21 September 2005
4. American National Standard, Information Technology – Serial Attached SCSI – 2 (SAS-2). Project T10/1760-D,
Revision 16, 18 April 2009
5. American National Standard, Information Technology – Serial Attached SCSI – 2.1 (SAS-2.1). Project
T10/2125-D, Revision 07, 9 Dec 2010
6. American National Standard, Information Technology – Serial Attached SCSI – 3 (SAS-3). Project T10/2212-D,
Revision 05, 31 Jan 2013
7. American National Standard, Information Technology – SAS Protocol Layer – 2 (SPL-2). Project T10/2228-D,
Revision 05, 10 May 2012
8. SFF Committee, SFF-8448 Specification for SAS Sideband Signal Assignments. Revision 0.5. 2 Sept 2005
9. SFF Committee, SFF-8485 Specification for Serial GPIO (SGPIO) Bus. Revision 0.7. 1 Feb 2006.
10. SFF Committee, SFF-8489 Specification for Serial GPIO IBPI. Revision 0.4 Nov 2011.
11. SFF Committee, SFF-8644 Specification for Mini Multilane 12 Gb/s 8/4X Shielded Connector. Revision 2.9. 9
Aug 2012.
12. Microchip, SXP 12G Endianness-related SDK Changes, PMC-2112390, Issue 1.
13. INCITS SCSI Primary Commands - 3 (SPC-3). Revision 23. May 4, 2005

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 10

Preface

14. INCITS SCSI Primary Commands - 4 (SPC-4). Revision 36f. March 11, 2013
15. INCITS SCSI Block Commands – 2 (SBC-2). Revision 16. November 13, 2004
16. INCITS SCSI-3 Enclosure Services Command Set 2 (SES-2). Revision 20. May 23, 2008
17. INCITS SCSI-3 Enclosure Services Command Set - 3(SES-3). Revision 05. November 20, 2012
18. INCITS SCSI Architecture Model - 2 (SAM-2). Revision 24. September 11, 2002
19. INCITS SCSI Architecture Model - 4 (SAM-4). Revision 14. May 8, 2011
20. INCITS SCSI Architecture Model - 5 (SAM-5). Revision 14. May 09, 2013
21. Serial ATA Working Group, Serial ATA: High Speed Serial ATA Attachment, Revision 1.0, August 2001
22. Serial ATA Working Group, Serial ATA II: Extensions to Serial ATA, Revision 1.0a, October 2002
23. Microchip, JTAG Application Note, Issue 1, document number PMC-2021518
24. Microchip, Storage Enclosure Processor (SEP) Firmware User Manual, PMC-2041947, Issue 8
25. Intel, Hewlett Packard, NEC, Dell, Intelligent Platform Management Bus Communications Protocol. V1.0.
November 15, 1999.
26. T10/05 – 144r7 SAS-2 zoning, September 7, 2005.
27. Microchip, SXP 24/36x6GSec Release 03 Firmware User Manual, Document Number PMC-2072115, Issue 9
28. Microchip, PM2513/14/15/16/32-KIT Product Brief, Document Number PMC-2120050, Issue 2
29. Microchip, PM8056 and PM8055 SXP 12G Hardware Specification, Document Number PMC-2111573, Issue 5
30. Microchip, SXP 68x12G Revision B - Chip Level Register Descriptions, Document Number PMC-2124090,
issue 2
31. Microchip, SXP 68x12G Engineering Validation Board Document, Document Number PMC-2112045, Issue 2.

1.6 Glossary of Terms and Acronyms

The following table lists the terms and acronyms used in this document.
Table 1-3. Glossary of Terms and Acronyms

Terms/Acronym Definition

API Application Programming Interface

ATA Advanced Technology Attachment

BCT Back Channel Training, that is, SAS-3 PHY Transmitter Training

EM Enclosure Management

EMA Enclosure Management Application

EMIP Microchip Embedded 32-bit Micro Processor

FLM Flash Module

GPIO General Purpose Input/Output

IPMB Intelligent Platform Management Bus

ISR Interrupt Service Routine

LUN Logical Unit Number

NMI Non-maskable Interrupt

RTOS Real Time Operating System

SAS Serial Attached SCSI

SATA Serial Attached ATA

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 11

Preface

...........continued
Terms/Acronym Definition

SCSI Small Computer System Interface

SES SCSI Enclosure services

SEP Storage Enclosure Processor

SGPIO Serial General Purpose Input/Output

SMP Serial Management Protocol

SPS SAS/SATA Port Selector

SSP Serial SCSI Protocol

SSU Staggered Spin-Up

STE SCSI Target Emulator

STP Serial ATA Tunneled Protocol

SXP SAS Expander

TWI Two Wire Interface (I2C compatible)

UART Universal Asynchronous Receiver/Transmitter

WOL Wake-on-LAN feature in the SXP 12G SDK

WOS Wake-on-SAS feature in the SXP 12G SDK

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 12

Functional Description

2. Functional Description
This section provides a functional overview of the primary blocks in the device. It indicates what is done in the
hardware and firmware, and what parts of the hardware are programmable by the firmware. The firmware runs in the
MIPS core.
The following figure shows a simplified block diagram of the PM8056 SXP 68x12G device. The PM8056 is part of
Microchip’s 12G SAS expander family featuring SAS 3.0 T10 zoning, self-configuration, table-to-table routing, an
Ethernet port, and an integrated 34Kc MIPS processor with 1024 Kbytes scratchpad RAM for SES and enclosure
management support. For detail, refer to [29]. If there is any disagreement between this section and the Hardware
Specification document [29], the device design document should take precedence.
The block diagrams for the PM8055 SXP 48X12G, PM8054 SXP 36X12G, and PM8053 SXP 24X12G devices vary
by number of ports. PM8044 SXP 36SX12G and PM8043 SXP 24SX12G devices are the same as the device shown
in the block diagram, except port number differences and no Ethernet MAC and Local bus.
Figure 2-1. SXP 68x12G Block Diagram

Within the MIPS34Kc CPU subsystem is a memory controller that provides the logic for internal and external SRAM
and flash memory. The external local bus operates with a 16-bit data width. SXP 12G expanders support a 16-bit
flash memory device with optional inline ECC on the parallel flash. In addition, the memory controller provides a
Serial Peripheral Interface (SPI) to external serial memory. The SPI can operate in three modes:
• SPI (single lane)
• DSPI (dual lane)
• QSPI (four lane)

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Functional Description

The SPI does not support inline ECC. The MIPS 34Kc boots from either 16-bit parallel flash or from the serial SPI,
depending on the device bootstrap pins settings.
The CPU subsystem includes four UART ports, one of which is provided for debugging support. Up to 81 GPIOs
are supported. Four serial GPIO interfaces are also provided. An Ethernet MAC with RMII/MII interface provides
management capability.
The SXP 12G expanders provide up to 12 hardware-based multi-master Two-Wire Interfaces (TWIs) for device
configuration and control of peripheral devices such as temperature sensors or NVRAM.
All target ports incorporate the STP bridge function allowing either a SAS or SATA target device to be attached.
The SXP 12G supports table routing of up to 4,096 entries shared across zones, direct routing and subtractive
routing methods. Centralized table routing enables each input port to view all 4,096 table entries for a single zone
configuration. A table-to-table routing feature is also provided. For multiple zones configuration, the per port table
entry visibility is dependent on the actual zoning configuration in ECMR. The SXP 12G non-blocking crossbar in the
data-path allows any port to any port connections including arbitrary wide port configurations within the same zone.
Access security or zoning configuration may be performed by standard SMP/SSP commands from a designated zone
manager or out-of-band through TWI or programmed directly into external flash memory attached to the device. The
SXP 12G supports up to 256 zones.
Statistics counters and performance monitoring logic provide comprehensive diagnostic and performance monitor
functions. Each link of the SXP 12G expanders incorporates line rate PRBS and CJPAT pattern generators and
checkers for link integrity diagnostics. Per link disparity and code error injection capability are also provided.
The remainder of this section describes the hardware platform on which the firmware runs.

2.1 High Speed Serial Interfaces

The SERDES block receives and transmits serialized data between the various devices in the SAS domain.
Firmware must configure the programmable settings using a set of parameters read from initialization in an external
flash memory. Microchip provides a set of APIs to configure the expander function with parameters pulled from the
external flash.

2.1.1 High Speed Serial Receiver

The high-speed 12.0/6.0/3.0/1.5 Gbit/s serial receiver provides differential inputs with on-chip differential termination.
This reduces discontinuities in the channel and reduces the external component count and area footprint. The
high-speed serial receiver requires external AC-coupling.
The serial receiver incorporates a DSP-based clock and data recovery as well as FFE and DFE to counteract the
lossy effects of a backplane channel. This increases the data eye opening enabling robust data recovery.
Each high-speed serial receiver interface has an OOB detector that detects loss of signal on the interface. The
detector voltage threshold levels are programmable. An OOB state machine identifies COMINIT/COMRESET,
COMWAKE and COMSAS events on the serial interface to determine if the interface is connected to a SATA or
SAS device.

2.1.2 High Speed Serial Transmitter

The high-speed serial transmitter transmits a two-level NRZ stream at the rate of 12.0/6.0/3.0/1.5 Gbit/s over
controlled impedance transmission lines. It provides differential outputs and on-chip differential termination.
The serial transmitter has several pre-emphasis settings when pre-emphasis is enabled by the embedded
microprocessor.
The output voltage swing is programmable to allow for different levels, including SATA Gen1i/Gen1m, SATA Gen2i or
SATA Gen1x/Gen2x and SAS-1.1 / SAS 2.1. The high-speed transmitter includes programmable edge rates.
Transmitter amplitude and pre-emphasis settings can be fully controlled through the transmitter adaptation back-
channel as per the SAS-3 specification. OOB control is compatible with SAS-3.

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 14

Functional Description

2.2 Processor Subsystem

The SXP 12G processor subsystem consists of the MIPS34Kc core, a bus bridge with an integrated interrupt
controller and a memory controller and peripherals. This subsystem is one of the key differences between the SXP
12G and SXP 6G.

2.2.1 MIPS Processor Core

The MIPS 34Kc core:
• Operates at 600 MHz
• Includes 64 Kbytes of instruction cache and 32 Kbytes of data cache for improved CPU performance
• Enables MMU TLB to support physical address independent application code
• Supports 1 MB of on-chip scratch RAM
• Supports 64 Kbytes of on-chip DPRAM for Ethernet packet memory
• Supports 32 Kbytes of on-chip DSPRAM for data use only
• Includes processor functions in external interrupt controller (EIC) mode
• Works in Little Endian mode

2.2.2 Interrupt Controller

The SXP 12G uses a MBIC (MIPS34Kc Bridge and Interrupt Controller) to manage up to 120 external interrupt
sources mapped to 15 Interrupt Vectors of MIPS34Kc core in EIC mode. The priority of each interrupt vector can be
fully programmed in the MBIC. The MBIC manages up to 32 NMI (Non-maskable Interrupt) sources as well.

2.2.3 Memory Controller

The Memory Controller in the processor subsystem supports four memory interfaces:
• SPRAM (On-chip processor scratchpad RAM of 1 MB)
• DPRAM (64 Kbytes of on-chip dual port Ethernet packet memory with processor and MAC being the two
accessing agents)
• 16-bit wide Local Bus Interface support for external flash memory/SRAM. The interface has four chip selects:
Chip Select 0 is used for boot-up flash chip select and the other three local bus chip selects are reserved
for SRAM, flash and I/O expansion. Each chip select supports 16 MB of space. Also, the local bus interface
supports inline ECC for flash memory when enabled. No Local Bus Interface for PM804x devices.
• SPI serial flash interface supports external SPI-based flash.
• Describes primary memory map in SXP 12G.
Table 2-1. Memory Space Description

Component Start Address End Address Size Description

Memory 0xB000_0000 0xBFFF_FFFF 256 MB On-chip and off-chip memory space

DSPRAM 0xBC14_0000 0xBC14_7FFF 32 Kbytes MIPS 34Kc use this space for
DSPRAM

ET 0xBC13_0000 0xBC13_FFFF 64 Kbytes EurekaTech memory controller

registers including local buffer (for
writing 24 Bytes) and configuration
space (CS9)

ET 0xBC12_0000 0xBC12_FFFF 64 Kbytes On-chip. No Memory (CS8)

ET 0xBC11_0000 0xBC11_FFFF 64 Kbytes On-chip. No Memory (CS7)

ET 0xBC10_0000 0xBC10_FFFF 64 Kbytes On-chip DPRAM 64 Kbytes

organized as 16Kx4 (CS6)

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Functional Description

...........continued
Component Start Address End Address Size Description

ET 0xBC00_0000 0xBC0F_FFFF 1 MB On-chip SPRAM 1 MB organized as

16Kx64 (CS5)

SPI1 / ET 0xBB00_0000 0xBBFF_FFFF 16 MB Off-chip memory –SPI NOR flash

(CS4) when not used as boot. In
this case, firmware must program
the SPI controller memory address
range with CS4. When SPI as used
for boot, this space is assigned to ET
memory controller CS0.

SPI 2 0xBD00_0000 0xBDFF_FFFF 16 MB Off-chip memory –SPI NOR flash. In

this case, firmware has to program
the SPI controller memory address
range with CS4.

ET 0xBA00_0000 0xBAFF_FFFF 16 MB Off-chip memory–parallel NOR flash,

async SRAM, sync SRAM (CS3)

ET 0xB900_0000 0xB9FF_FFFF 16 MB Off-chip memory–parallel NOR flash,

async SRAM, sync SRAM (CS2)

ET 0xB800_0000 0xB8FF_FFFF 16 MB Off-chip memory–parallel NOR flash,

async SRAM, sync SRAM (CS1)

ET / SPI1 0xBF00_0000 0xBFFF_FFFF 16 MB Off-chip memory used for boot-up.

Memory can be parallel NOR flash
or SPI NOR flash (CS0). If SPI
isused for boot, CS4 is assigned
to ET. In this case firmware has to
program ET to the address range of
CS4. If ET is used for boot, CS4 is
assigned to SPI.

2.2.4 On-chip Peripherals

2.2.4.1 Application Timer

The SXP 12G supports four software timers. Each has a 32-bit counter and is clocked by a 75 MHz clock, allowing
software timer timeout periods of up to 57 seconds.

2.2.4.2 GPIO
The SXP 12G supports up to 81 GPIO ports for PM805x devices and 62 GPIO ports for 804x devices. These ports
are separately configurable as input or output under software control. Some GPIOs share pins with an extra UART,
SGPIO and TWI.

2.2.4.3 Local Bus Interface

The device has a 16-bit wide asynchronous local bus interface for connecting to external flash memory/SRAM
memory. This interface is able to address up to four devices and up to 16 MB per device. A 16-bit SRAM and 16-bit
flash memory devices are supported.
External parallel flash can utilize inline ECC.
The PM804x devices have no Local Bus Interface.

2.2.4.4 RTC
The device implements one real time clock that is a 1 μs counter.

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Functional Description

2.2.4.5 SGPIO
The SXP 12G provides four SFF-8485 SGPIO interfaces with timeslots for GPIO expansion over a standard four-
pin interface. Each SGPIO shares its pins with four TWI buses. Its configuration is compliant with the SFF-8448
specification for SAS Sideband Signal Assignments.

2.2.4.6 SPI
The SPI can connect a serial flash device to the SXP 12G. The SXP 12G can boot firmware from the SPI. The SPI
consists of a clock, SPI_CLK, a chip select, SPI_CSB, and SPIDATA [3:0]. The SPI operates in three modes listed as
follows.
• SPI mode (1 data lane)
• DSPI mode (2 data lanes)
• QSPI mode (4 data lanes)
The SPI interface operates at 18.75 MHz, 37.5 MHz, or 75 MHz. At bootup, the SPI interface defaults to SPI mode
and 18.75 MHz operation.

2.2.4.7 TWI
The SXP 12G TWI subsystem consists of a maximum of twelve independent master-slave ports that conform to the
Two-Wire protocol. Each TWI port has its own timing configuration.
Characteristics of this subsystem are:
• TWI hardware is responsible for TWI bus arbitration.
• TWI hardware handles TWI clock stretching.
• Each TWI bus has a dedicated TWI master instance and a dedicated TWI slave instance. The SXP 12G
supports simultaneous master and slave activity enabling efficient inter-expander communication over the TWI
bus.
• Efficient interrupt mechanism. Interrupts are generated when a transaction is completed.
• If a TWI port is configured as a slave, an external master can drive an SRSTB pin to generate a slave reset
interrupt to the SXP 12G TWI driver which performs a slave reset operation.

2.2.4.8 UART
The SXP 12G supports four instances of programmable Universal Asynchronous Receiver/Transmitter (UART)
compatible with the industry-standard 16550 interface. It serially receives and transmits data to a peripheral, modem
or data set. The SXP 12G contains registers to control the character length, baud rate, parity generation and
checking, and interrupt generation and uses standard RTS/CTS flow control.

2.2.4.9 Watchdog Timer

The SXP 12G integrates a hardware Watchdog Timer. Upon system reset, the Watchdog Timer is disabled. Once it
is enabled, it cannot be turned off until the next system reset. The Watchdog Timer counts from a pre-set (timeout)
value in descending order to zero.

2.3 Expander Port Interfaces

Expander Port Interfaces are the blocks labeled PHY and SXL in Figure 2-1. Target ports support spin-up control for
both SATA and SAS devices. For SAS devices, the SXP 12G can progressively send NOTIFY (ENABLE SPINUP)
primitives with a programmable group size and time stamp to target ports after a link reset sequence. For SATA
targets, the SXL port can delay device spin-up by halting the automatic PHY reset sequence.
Ports support the SAS link initialization sequence. During the initialization sequence between SAS devices, the port
exchanges IDENTIFY address frames with the remote end. The IDENTIFY information is stored for each port on the
device and is accessed by firmware as part of the discovery process. The topology master uses this information to
set table routing. The ECMR, a hardware component combining ECM and ECR functions within the expander, uses
the IDENTIFY information to configure direct routing.
The SXP 12G ports support SSP, SMP and STP connection management through the following process:
1. The SXP 12G device receives OPEN address frames and connection primitives such as BREAK and CLOSE
from the host ports and the SAS target ports.

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Functional Description

2. The received OPEN requests are sent to the centralized ECM (Expander Connection Manager) block, which
implements the OPEN arbitration and partial pathway blocking prevention algorithm.
3. The SXP ports generate the arbitration response primitives according to the ECM arbitration status.
4. When the ports are connected, a full-duplex data path is set up to pass data and primitive Dwords (except STP
flow control primitives) between the ports.
5. The STP flow control terminates on each link with a flow control buffer of 32 Dwords of data after that port
transmits HOLD.
SXP ports contain link activity logic that generates link activity indication that firmware uses to drive the SGPIO LED
state machines.

2.3.1 Connection Management and Routing

Connection management and routing is distributed between the blocks labeled Arbiter ECM and ECR in and the
firmware running in the MIPS core shown in Figure 2-1.
The SXP 12G device supports table routing, direct routing, and subtractive routing. This device, including the internal
SMP/SES processor, is associated with a single SAS address. When an OPEN address frame is received from any
port:
The SAS address in the frame is compared to the table routing addresses of the ports in the device.
• If a match is found and the matched port is not the input port of the OPEN frame, the OPEN request is routed to
the matched port.
• If a match is not found and the request is received from a port with the subtractive routing attribute, the OPEN
request is rejected for having an unknown address by sending an OPEN_REJECT (BAD DESTINATION).
• If no match is found and the OPEN frame is not received from a port with the subtractive routing attribute, the
frame is routed to the port with the subtractive routing attribute.
SXP firmware configures and updates the routing tables. It performs the discovery process to self-configure its
routing table and may also act as a management client that configures the routing tables of other expanders within
the domain. Alternatively, firmware can defer the routing table configuration to an external management application
client.

2.4 Initialization, Management, and Enclosure Services Support

In addition to implementing a virtual SMP/SSP port, the processor firmware controls several peripheral interfaces.
This includes twelve multi-master Two-Wire Interfaces (TWI), a 16550-compatible UART (can be up to 4 UARTs), a
local bus interface for user-programmable flash memory, SPI flash, an application timer, RTC, GPIO operation and
four Serial GPIO interfaces. The hardware blocks are shown in Figure 2-1.
Additionally, the embedded RISC processor includes an EJTAG debugging interface.
The SXP 12G device supports device initialization upon reset through the flash memory interface. Internal registers
are configurable by one of these three methods:
• TWI slave port mediated by firmware
• Embedded firmware terminating the SMP protocol
• Customer/application specific firmware
The flash memory interface lets you configure features of the device during the reset sequence. The firmware loads a
16 Kbytes initialization string after system reset. The initialization string contains information such as:
• The SAS base address of the SXP device
• Identification of a subtractive port
• SAS PHY configuration
• HDD spin-up delay values & delay interval values
• GPIO Muxing control
• Manufacturer-specific information.
• Zoning configuration
• EPOW configuration

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Functional Description

• Disk Qualification
• TCP/IP
A 32-bit checksum field in the initialization stream provides a data integrity check during the writing of the initialization
data to the flash memory. If the checksum fails, the valid inactive initialization string is used. If an invalid configuration
is detected, expander ports are kept in the default ‘disabled’ state until an external host updates a new, valid
initialization string to the flash memory.
Optionally, parts of the initialization string that are expected to vary from one board to the next can be stored in a
serial EEPROM to facilitate the task of configuring the system.
The initialization string can be reliably and flexibly adjusted independently of the firmware image stored in the flash
memory because it resides in a separate partition.

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Firmware Architecture

3. Firmware Architecture
The following figure shows an overview of the PM73206_04 firmware. Each block represents a firmware component
except the bottom block which represents the SXP hardware. Shaded blocks represent supplied firmware and green
blocks represent firmware that you must develop or acquire.
The firmware components are briefly described in the following subsections.
Figure 3-1. PM73206_04 Firmware Modules

3.1 Firmware Modules

3.1.1 RTOS
Expresslogic ThreadX provides the services of a Real Time Operating System (RTOS). Express Logic ThreadX5.1-
ST for MIPS34Kc is provided in object form for use with the SXP and licensing of the library is provided through
Microchip Marketing Team.

3.1.2 Operating System Functions

The Operating System Functions (OSF) is a wrapper layer that abstracts the ThreadX implementation of necessary
RTOS functions.
The OSF:
• Encapsulates RTOS functions with assertions and checks for the success or failure of the function calls.

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Firmware Architecture

• Groups sets of ThreadX initialization functions into single OSF functions.

• Limits access to only those RTOS services that are validated with the firmware.

3.1.3 Device Drivers

A device driver is a firmware module that directly controls the operation of a hardware resource. Device drivers may
use the services of the OSF for some of their functions, but they also interact directly with the hardware. Use these
device drivers as the base for building your own enclosure services firmware.
The PM73206_04 firmware provides a comprehensive set of device drivers for the SXP hardware. The PM73206_04
firmware provides examples showing sequences of operations.
An Ethernet driver is provided that is used with the Telnet application to provide an interface over Ethernet with
commands like CMDSVR.

3.1.4 Diagnostics API

The diagnostics API provides control of diagnostics modes within the SXP 12G device and access to status and
statistical information relating to system performance.

3.1.5 Boot-Up Services

3.1.5.1 Bootloader
The bootloader and the application code operate as separate applications within the firmware. (In this context,
“application code” means the PM73206_04 firmware components except the bootloader.)
An example bootloader module is provided to help you write your own. It demonstrates the typical tasks that the SXP
12G performs at boot time such as:
• Reset Event Handling (power-on, NMI, and so on)
• Power-on Self Test
• Firmware Application Image Management and Launching
The bootloader can use the features of the OSF if required, although a simple configuration may only require the
services of the startup environment provided by the C runtime library.
The bootloader selects one of two application code images to load. Loading the application code starts system
operation.

3.1.6 SCSI Target Emulator (Protocol Stack)

The SCSI Target Emulator (STE) implements the subset of the SCSI protocols required for the target side of an
enclosure services application. The STE implements portions of the SCSI Architecture Model –5 (SAM-5), and some
of the SCSI Primary Commands –4 (SPC-4). STE uses the transport services provided by the SAS Port Component
to communicate with the initiator.

3.1.7 SAS Port Component

The SAS Port Component operates with the SXP hardware to provide Serial Attached SCSI transport services. It has
a single operating system thread that implements the SAS transport layer, port layer and link layer state machines
described in the SPL-2 specification.

3.1.8 Serial Management Protocol Initiator

The SMP Initiator provides the Initiator implementation of the SMP interface. The SMP Initiator is described in more
detail in Section 14.7 Serial Management Protocol (SMP) Application Layer.

3.1.9 Serial Management Protocol Target

The SMP Target provides the Target implementation of the SMP interface. Section 14.7 Serial Management Protocol
(SMP) Application Layer lists the implemented SMP Target pages.

3.1.10 Serial Management Protocol Topology Master

The SMP Topology Master is an optional SMP initiator thread that learns the full SAS network topology and
distributes the routing information to any expanders that are not self-configuring. It monitors the topology for changes

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Firmware Architecture

and updates its topology view and routing table if necessary. It also updates the routing tables of expanders that are
not self-configuring.

3.1.11 Enclosure Management Application

The Enclosure Management Application (EMA) is the Enclosure Services application running on the SXP 12G
device. It is custom software that monitors and controls the various elements in your storage enclosure. The EMA
also processes SCSI Enclosure Services (SES) requests received through the SCSI/SAS transport stack to provide
external access to the monitoring and control functions of the enclosure. This manual provides a comprehensive
example to help you develop your EMA.

3.1.12 Disk Spin-Up

The Disk Spin-Up application manages the controlled and staggered spin-up of disks to reduce power-spikes due to
the disks trying to spin-up simultaneously.

3.1.13 Disk Qualification

The disk qualification application validates disk drives for standards compliance and for user-modifiable parameters
to ensure that only supported disk drives are enabled and reported to the host bus adapters.

3.1.14 SSP Initiator and SCSI Initiator Application (SIA)

The SSP Initiator interfaces with the SAS virtual port component to do SCSI transactions with the SCSI/SES target.
The SIA module provides the message interface to the upper-layer application, such as disk qualification application,
for initiating SCSI commands to the SAS disk or SES target.

3.1.15 STP Initiator and Serial ATA Host Application (SAHA)

The STP Initiator provides initiator functionalities that query the SATA disk drives in support of the disk qualification
feature.
Like the SIA module, the SAHA module supports the disk qualification process by initiating the appropriate ATA
commands to query SATA disk drive parameters.

3.1.16 Power Management

The SXP 12G SDK supports the following power management features:
• Early Power-Off Warning,
• SAS-3 Power Control,
• Wake-On-LAN
• Wake-On-SAS

3.1.17 SAS Zoning

SAS Zoning provides the implementation of the SAS 2/2.1/3.0 specification compliant port-based zoning. It supports
256 zone groups and zone-aware address-based routing tables.

3.1.18 Non-I/O Disruptive Soft Reset

This module enables the download of the SXP firmware image and activates the new image through NDSR. This
secures I/O traffic through the SXP from interruption during the online firmware upgrade process.
This module in the SXP 12G SDK supports the SXP SMP/SSP port handle SMP/SES transactions during firmware
image downloading.

3.1.19 Cable Management

This module manages the SAS-2.1/SAS-3 connector through connector management interfaces. Through the FPGA
logic in the SXP 12G FVB board, it assists in detecting cable removal/insertion/cable status events and firmware
automatically identifies the newly inserted cable type (active/passive/optical) and cable profiles, It also configures the
corresponding PHY settings, such as PHY mode, before enabling the PHY.

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Firmware Architecture

3.1.20 Inter-expander Communication

The SAS JBOD requires an efficient and reliable communication channel between expanders for synchronizing the
Enclosure Management Information and vendor-specific data. The SXP 12G SDK provides the APIs over TWI and
over in-band SAS for meeting this kind of application.

3.1.21 SATA Interlace Feature

SATA Interlace is a feature in the firmware that enables SATA drive commands to be sent from the expander. This
enhancement allows the expander to initiate SATA drive commands within the existing affiliation context even without
clearing the host affiliation.
Common use-cases for this feature include SATA drive temperature monitoring. This is performed using the SMART
READ DATA command. When the SEP determines that the temperature or power consumed by the enclosure is
higher than expected, then a SMART WRITE LOG command is issued to the drive to reduce the power consumption.
The command reduces temperature and power consumed by the enclosure.
SATA Interlace is implemented using SSSF buffering to execute commands from the SAS expander firmware
application code (SXP) and services SMART READ DATA and SMART WRITE LOG commands from the host for
temperature monitoring. It features the following:
• Implemented as a set of APIs to be executed by the application thread
• SXP bypasses the STP layer
– Command is executed in EMIP (SSSF processor)
– SATA multi-affiliation is not required
– All drive PHYs can execute interlaced commands in parallel
• Non-blocking
• Returned data is copied to the shared RAM
– EMIP copies return data and moves on
– SXP application will not cause further delay in host command execution
• SXP Application will handle all errors
– SSSF returns error to SXP application layer then processes next command in the host queue
This feature requires buffering to be enabled and can be tested by using the following CLI commands:

Command Function

satai ident <log_phy_id> Get SATA Device Identification data

satai smart_read_data <log_phy_id> Issue a SMART Read Data command to a drive

satai smart_read_log <log_phy_id> <log_page_addrs> Issue a SMART Read Log command to a drive

smart_write_log <log_phy_id> <log_page_addrs> Issue a SMART Write Log command to a drive

3.1.22 Command Server

This module provides the Command Line Interface (CLI) and a set of commands for SXP Debug purposes. The CLI
can be accessed through the UART console or Telnet Console.

3.1.23 TCP/IP Stack and Network-based Application

This module includes third party TCP/IP stack, network services and applications, such as a DHCP Client, Telnet
Server, TFTP client and Web Server.
The TCP/IP function is not supported for PM804x devices.

3.1.24 Event Logging and Error Handling

This module provides the SXP hardware/firmware event logging and tracing capability, and supports the configurable
event log filters and multiple in-band/out-of-band log retrieval methods.

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Firmware Architecture

3.1.25 SAS/SATA Store and Forward and BCT Microcode

This module includes the microcode running in the EMIP that assists the SSSF block in handling SAS/SATA buffering
and error handling. It also assists the SAS 3 PHY to process backchannel training state machine and error handling.
In addition, it includes the main firmware function of loading/activating microcode to the EMIP and detecting and
handling the error in the EMIP.

3.1.26 SXP SAS Hardware Block Drivers

The SDK provides the API layer for applications to access SXP SAS-related hardware blocks, such as the SSPL,
SXL, EMCR, MTSB, and PACK.

3.1.27 SXP Peripheral Drivers

The SDK provides the peripheral drivers for applications to access the peripherals, including the UART, TWI, SPI,
Flash, Watchdog, Timer, Interrupt controller, and Ethernet MAC (PM805x devices only).

3.2 Thread Decomposition

The firmware is partitioned into threads that communicate with each other through a messaging interface. Figure
3-2 shows the overall architecture of the firmware including the threads provided by the firmware, and the message
queues between the threads. The rest of this document describes the firmware components, thread scheduling, and
the format of the messages.
Figure 3-2. Thread Decomposition

3.3 Firmware PHY Bitmap Type

A firmware PHY bitmap is used widely in Portmgr/topology discovery, logrt, ECMR APIs, SXL APIs, and SPINUP
modules.
Firmware uses a UINT32[3] array to accommodate the 68 PHYs. It can hold 32*3 or a maximum of 96 PHYs. A
PHYMAP instance is defined here:

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Firmware Architecture

#define PHY_MAP_ARRAY_LEN 3
typedef UINT32 PHYMAP_TYPE[PHY_MAP_ARRAY_LEN];
If using the PHY map, replace the application code with the following APIs:
Table 3-1. Bootup Sequence

Function Description
Bit Operations PHY_MAP_BIT_SET Sets corresponding PHY bit to 1 in PHY map
PHY_MAP_BIT_CLR Clears corresponding PHY bit to 0 in PHY map
PHY_MAP_BIT_GET Gets corresponding PHY bit value in PHY map
Map Operations PHY_MAP_AND operation:
phy_map_dst = phy_map_src1 & phy_map_src2;

PHY_MAP_OR operation:
phy_map_dst = phy_map_src1 | phy_map_src2;

PHY_MAP_AND_NOT operation:
phy_map_dst = phy_map_src1 & ~phy_map_src2;

PHY_MAP_CP operation:
phy_map_dst = phy_map_src;

PHY_MAP_AND_CONDITION operation:
(phy_map1 & phy_map2) == TRUE

PHY_MAP_CMP_EQ operation:
(phy_map1 == phy_map2) == TRUE
Can only compare if they are equal or not

PHY_MAP_CMP_G operation:
(phy_map1 > phy_map2) == TRUE
Checks whether phy_map1 is greater than phy_map2

PHY_MAP_BIT_NOT operation:
phy_map_dst = ~phy_map_src;

PHY_MAP_IS_NONZERO Returns False if PHY map is 0

PHY_MAP_IS_ZERO Returns True if PHY map is 0
PHY_MAP_CLR Clears the PHY map to 0
PHY_MAP_SET Sets each valid PHY bit of the map to 1
PHY_MAP_R_SHIFT Shifts the whole PHY map to the right

11[0] HEX Signed image This field indicates whether the image is signed or not
bit

12 to 15 ASCII Firmware Rev This field is not used but should contain the firmware revision
of the code being downloaded.

16 to 19 HEX Firmware This field is used to check against the size of the destination
Length partition.
If the fw_length plus 8 bytes (for storing the CRC and
the length at the end of a partition) is greater than the
destination partition length, then fwdl_status_ptr is set to
FWDL_STATUS_HDR_INCORRECT.
If the total number of bytes received exceeds
this number, fwdl_status_ptr will be set to
FWDL_STATUS_LENGTH_INCORRECT. The final CRC
check is not to be performed until this exact number of bytes
has been received.

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Firmware Download Mechanism

...........continued
Byte Data Field Name Field Description
Offset

Firmware 20 to 23 HEX Firmware This field is used to check the CRC of the data written
CRC32 to flash memory. The CRC is calculated using the same
Data
number of bytes as the specified firmware length (any
padding to the end of the partition is not included).
If the CRC check fails fwdl_status_ptr is set to
FWDL_STATUS_CRC_INCORRECT.

24 to 27 HEX Startup This field is not used, but should contain the value
Routine 0xBF000000.
Address

28 to n HEX Application This field contains the application data as a binary image.
Firmware One way to generate this file is to add the –memory option.
Data

Table 4-2. Firmware Download Status

Status Code Description

READY 0x0 Firmware is ready for download

IN_PROGRESS 0x1 Download in progress

HDR_INCORRECT 0x2 Header incorrect – download aborted

OFFSET_INCORRECT 0x3 Offset incorrect – download aborted

CRC_INCORRECT 0x4 CRC incorrect – download aborted

LENGTH_INCORRECT 0x5 Firmware length incorrect – download aborted

HW_DOWNLOAD_ERR 0x6 Hardware download error – problem programming the flash memory
– download aborted

DOWNLOAD_COMPLETE 0x7 Download completed successfully.

DOWNLOAD_COMPLETE_IM 0x8 Download completed successfully. Reboot and activation are

AGE_PENDING_ACTIVATE required to update the firmware image.

DOWNLOAD_COMPLETE_DA 0x9 Download completed successfully. Reboot and activation are

TA_PENDING_ACTIVATE required to update the data image.

4.2.2 Firmware Download Procedure

When downloading the Firmware application image or initialization data image, user can choose any of the following
five in-band/out-of-band download methods, and use the following four steps.
1. The host downloads a new application image to the inactive image partition. SXP firmware supports 5 main
modes to download images, including:
– Send Diagnostic command (OpCode 1Dh) String Out diagnostic page (Page Code 04h). The page is to
download and save image, but not to set active flag. For example:
pmc_scsi –dwnld -d sxp_evbd_rom.bin 1000
– Send Diagnostic command (OpCode 1Dh) Download Microcode Control diagnostic page (Page Code
0Eh) Download Microcode Mode 07h/0Eh. See SES3r03 [17] Table49 – Download Microcode Mode. For
example:

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Firmware Download Mechanism

pmc_scsi –dwnld –d_mcr7 sxp_evbd_rom.bin 1000

pmc_scsi –dwnld –d_mcre sxp_evbd_rom.bin 1000
– Write Buffer command (OpCode 3Bh) Mode 07h/0Eh. See SPC4r33 [14] Table 288 – Write Buffer mode
field. For example:
pmc_scsi –dwnld –d_wb7 sxp_evbd_rom.bin 1000
pmc_scsi –dwnld –d_wbe sxp_evbd_rom.bin 1000
– Run tftp_dwld command through UART Command Server to download firmware images from TFTP
sever. Option ‘a’ is to set active flag. This requires TCP/IP stack in SXP 12G SDK. For example: input the
following command in the cmdsvr console
tftp_dwld 192.168.1.2 sxp_evbd_rom.bin a
– Download firmware images through UART Command Server. This is not recommended because of low
performance.
dwld –fl <offset> <hexdata0> <hexdata1> <hexdata2> <hexdata3> <hexdata4> …
2. If using the String Out diagnostic page download method or dwld command, toggle the active image flag for
the String Out diagnostic page by issuing the following commands (this step is automatically handled by the
other download methods):
– The FWDL Partition Control Page (0x91) in 14.2.3 Supported SES Pages and Limitations. For example:
pmc_scsi -scsi -x 1d 10 00 00 06 00 -o 91 00 00 02 01 00
3. Reset the SEP device by issuing one of the following:
– A power cycle
– Send Diagnostic command (OpCode 1Dh) Download Microcode Control diagnostic page (Page Code
0Eh) Download Microcode Mode 0Fh. For example:
pmc_scsi –dwnld –d_mcrf
– Write Buffer command (OpCode 3Bh) Mode 0Fh. For example:
pmc_scsi –dwnld –d_wbf
– The String out diagnostic page soft reset command. For example:
pmc_scsi –scsi –x 1d 10 00 00 06 00 –o 04 00 00 02 02 01
– The String out diagnostic page hard reset command. For example:
pmc_scsi –scsi –x 1d 10 00 00 06 00 –o 04 00 00 02 02 02
After reset and during booting, the bootloader checks the CRC-32 of the boot configuration images (image0
and image1) and then passes the image statuses (image 0/1 valid/invalid) to the user-defined hook
boot_hook_image_validate_hdlr() to handle the image validation/update result. If the CRC-32 of both images
is valid, bootloader selects the active image to execute. If the CRC-32 of only one image is valid, bootloader
selects the valid one to execute. If neither is valid, bootloader stops.
4. Check the active firmware and initialization version from the command server console and Scan all devices
from host side after updating.
See Section 19.1 Microchip SCSI Utility for help using the pmc_scsi to download the image, send SES page and
scan devices.

4.3 Flash Memory Image Verification

A CRC-based image verification mechanism allows the bootloader to determine if a flash memory image is valid. This
mechanism is implemented as follows:
• The last 32 bits in each flash partition are reserved for CRC.
• The second to last 32 bits in each flash partition are reserved for the length of the image in that partition.
• The host calculates a 32-bit CRC for the image.

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Firmware Download Mechanism

• On successful firmware download, the image length and 32-bit CRC are written to the last two 32-bit locations in
the flash partition.
• The bootloader reads the length from the partition, calculates the CRC-32 for the image, and compares the
result to the CRC stored in the partition.

4.4 Flash Partition Map

The flash partition map includes the following:
• Virtual address to MIPS physical address space translation and the restriction TLB entry with a 1M page mask
when enabling MMU/TLB,
• Logical (MIPS physical address)-to-physical (LBI Physical address) address mapping due to introduction of
ECC.
In the SXP 12G SDK, the flash partition map has two views,
• Logical view that is relative to MIPS addressing view and the address in link script is based on it.
• Physical view that is relative to Local Bus Interface, that is, flash memory address.
When using parallel flash with ECC disabled (PM805x device only) or when using SPI flash memory, the logical
view of the partition map is the same as its physical view. See the left diagram in and .
When using parallel flash with ECC enabled (PM805x device only), the logical view of the partition map is the
same as with ECC disabled, but it is different from its physical view. See the right diagram in and .
The summary of the new Flash Partition Map is as follows:
• Supports two kinds of partition maps in the link file sxp_common_base.ld: a 4M partition map and an 8M
partition map. By default, the 4M partition map is used. You can enable the 8M partition map by commenting out
the corresponding 4M partition boundary definition code and enabling the 8M partition boundary definition code
in the link file.
• 4M partition map:
– Supports 4M/8M/16M flash with ECC disabled
– Supports 8M/16M flash with ECC enabled
– Logical view with ECC enabled on 8M/16M flash is the same as with ECC disabled on 4M/8M/16M flash
– Reduces size of main firmware image partition from 1792K to logical 1664K
– Reduces size of unused region from 192K to logical 64K
– Adds a logical 96K NV-Log partition for critical fatal error logging
• 8M partition map:
– Supports 8M/16M flash with ECC disabled
– Supports 8M/16M flash with ECC enabled
– Logical view with ECC enabled on 8M/16M flash is the same as with ECC disabled on 8M/16M flash
– Increases size of main firmware image partition from 1792K to logical 2624K
– Reduces size of unused region from 192K to logical 128K
– Adds a logical 128K NV-Log partition for critical fatal error logging
• Both 4M partition map and 8M partition map:
– Changes logical partition boundary from 64K aligned to 128K aligned to support 128K sector size
– Reduces size of bootloader partition from 128K to logical 96K
– Restrict overall logical 320K to avoid mapping two logical partitions to a common physical sector

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Figure 4-2. Flash Partition Map Views

The following table shows the partition definition in logical view.

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Table 4-3. Flash Partition Map Table

Flash Memory Logical Logical

Logical Size Description
Partition Start Address End Address

64KB for 4M flash memory,

2080KB for 8M flash memory,
8224KB for 16M flash memory.
If the user wants to divide
Unused 0x1F3F_0000 0x1F3F_FFFF 64KB the unused region into several
partitions, calculations are
necessary to ensure two logical
partitions do not use a common
physical sector.

Image1 0x1F24_0000 0x1F3D_FFFF 1664KB For firmware image-1

Data1 0x1F22_0000 0x1F22_FFFF 64KB For initialization string-1

For active image flag and active

Bootcfg 0x1F20_0000 0x1F20_FFFF 64KB
data flag

NV-Log 0x1F1E_0000 0x1F1F_7FFF 96KB For non-volatile logs

Image0 0x1F04_0000 0x1F1D_FFFF 1664KB For firmware image-0

Data0 0x1F02_0000 0x1F02_FFFF 64KB For initialization string-0

The first partition contains the

bootloader and must reside at
Bootloader 0x1F00_0000 0x1F01_7FFF 96KB
the boot physical address of
0x1F00_0000.

To ensure two logical partitions,

do not use a common physical
Restricted Distributed 320KB sector. Never use these regions
if ECC is enabled on an 8M/16M
flash memory.

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Figure 4-3. 8M Flash Partition Map Views

Table 4-4. 8M Flash Partition Map Table

Flash Memory Logical Logical

Logical Size Description
Partition Start Address End Address

128 KB for 8M flash, 6128 KB

for 16M flash. If user want to
divide the unused region into
Unused 0x1F5E_0000 0x1F5F_FFFF 128 KB several partitions, calculation
work is necessary to ensure two
logical partitions do not use a
common physical sector.

Image1 0x1F34_0000 0x1F5C_FFFF 2624 KB For firmware image-1

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...........continued
Flash Memory Logical Logical
Logical Size Description
Partition Start Address End Address

Data1 0x1F32_0000 0x1F32_FFFF 64 KB For initialization string-1

For active image flag and active

Bootcfg 0x1F30_0000 0x1F31_7FFF 96 KB
data flag

NV-Log 0x1F2E_0000 0x1F2F_FFFF 128 KB For non-volatile logs

Image0 0x1F04_0000 0x1F2C_FFFF 2624 KB For firmware image-0

Data0 0x1F02_0000 0x1F02_FFFF 64 KB For initialization string-0

The first partition contains the

Bootloader and must reside at
Bootloader 0x1F00_0000 0x1F01_7FFF 96 KB
the boot physical address of
0x1F00_0000

To ensure two logical partitions

do not use a common physical
Restricted Distributed 320 KB sector, these regions should
never be used if ECC was
enabled on an 8M/16M flash

4.4.1 Flash Partition Map Customization

Follow these rules to customize a vendor-specific partition map:
• Rule#1: The Logical view with ECC enabled on 8M/16M flash must be the same as the Logical view with ECC
disabled on 8M/16M flash.
– This means that the same firmware image can be burned into the flash memory with or without ECC
enabled and runs.
• Rule#2: The Logical partition boundary must be aligned to 128K to meet the 128K sector size considering the
ECC disable case in the rule#1.
Formula#1:
Logical partition start address%128K = 0
• Rule#3: Adjacent logical partitions must not be mapped to any one common physical sector.
Formula#2:
(The logical end address of Logical partition [i] *4/3) /128K * 128K + 128K <= The logical start address of
Logical partition [i+1]*4/3
• Rule#4: The logical start address of Image0 partition - 1MB * x = The logical start address of Image1 partition –
1MB *y. (1MB is the TLB page mask size.)
– To make the image partition as large as possible, there is x = 0, y = 3.
Suggested Conventions:
• Bootloader, Data, Boot Config Partition should not cross two physical sectors
• The partition organization should keep the same order as recommended by Microchip.

4.5 Firmware Image Authentication

Firmware image signing is the process of digitally signing the expander firmware image with cryptographic hash.
Signature verification by the running firmware image will ensure that any expander firmware images to be flashed
on a running expander are correctly signed. Improperly signed images will be rejected by the running firmware. This
feature is disabled by default and can be enabled using UART command API fw_auth_en.

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4.5.1 Firmware Authentication Process

Figure 4-4. Firmware Signature Verification Flow Chart

Once running firmware receives firmware image header, it checks whether firmware image authentication feature is
enabled or not. If authentication is enabled and received image is signed, intermediate hash will be calculated. Once
firmware receives all the packets, it calculates final hash value. The last 256 bytes will be the signature, once all the
256 bytes received, running firmware will decrypt the signature and compare the decrypted signature with calculated
hash. If the decrypted signature matches with calculated hash, it completes the firmware download otherwise returns
error.
Figure 4-5. Signed Firmware Image

If the signature verification fails, the downloaded image will not be activated, running firmware returns CRC incorrect
error and signature failure message on UART console.

4.5.2 Firmware Image Header Modifications

To support this feature without dethroughting from current firmware download design, reserved byte 11 is used to
indicate whether the firmware image is signed or not and to indicate the final image. Bit 1 of byte 11 indicates the
image is signed or not, bit 2 of byte 11 will be set for the final image. [Refer Table 2]

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Firmware authentication tool signimage [refer 4.5.4 Firmware Authentication Tools to Sign Firmware Image] will
modify these bits while signing the firmware image.

4.5.3 Procedure to Sign Image

Here are the steps to sign firmware image using private key:
1. Place the publick key text file @ ...\fwcs\sxp12g\build as rsa_public.txt
– rsa_public.txt will be converted as publickey_loc.h
– Public key can be generated using tool keygen [refer 4.5.4 Firmware Authentication Tools to Sign
Firmware Image]
1. Build the firmware.
1.1. Use signimage tool to sign firmware image with private key. signimage will modify the firmware
image header to indicate the signature, calculate the hash using SHA256, and encrypt the hash
calculated using RSAES-PKCS1-V1_5 algorithm.
Figure 4-6. Firmware Image Signing Process

4.5.4 Firmware Authentication Tools to Sign Firmware Image

The following tools are available to generate key pair, modify header and sign the image
• Keygen: generate random RSA key pair
• Signimage: modify firmware header, calculate the hash and sign the hash using private key
• Verifyimage: verify image is signed properly at host end.

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WOL_NMI NMI for Wake-on-LAN 5 wol_nmi_hndl_hook

WDT_NMI NMI for watchdog timer 4 wdg_nmi_hndl_hook

expiration

ET_MEMCTL_UNCORR_ NMI for uncorrectable ECC 3 memctl_uncorr_nmi_hndl_hook

ECC error from Local Bus

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Bootloader

...........continued
NMI Source Description NMI ID NMI Handler Callback

DPRAM_MAC_UNCORR NMI for DPRAM MAC-Side 2 dpram_mac_ecc_nmi_hndl_hook

_ECC uncorrectable ECC error

DPRAM_MIPS_UNCORR NMI for DPRAM MIPS-Side 1 dpram_mips_ecc_nmi_hndl_hook

_ECC uncorrectable ECC error

SPRAM_UNCORR_ECC NMI for SPRAM uncorrectable 0 spram_ecc_nmi_hndl_hook

ECC error

Except WOL, all NMI sources are considered fatal errors. All callback functions are handled by the Customer Fatal
Error Handler. You can modify the handler to meet your specific needs. See section 17.6 Fatal Error Handling for
detail.

5.5 Bootloader User-Defined Hooks

As shown in Figure 5-1, limited resources (stack, RAM, and so on) are available at different stages of the reset
sequence. The user-defined hooks must comply with these resource limitations. When the user-defined hook
functions are returned, the reset sequence will continue. If you do not want the reset sequence to continue, the
user-defined hooks must reset the device or jump to a different routine instead of returning to the caller.
Table 5-2. Bootloader User-Defined Hook Functions

Function Description

boot_hook_gen_exc_hdlr General exception handler for boot-strapped exceptions.

boot_hook_reset_hdlr_wo_stack Reset handler without using the stack. Should handle reset caused by NMI
during stack POST.

boot_hook_stack_post_hdlr Handler called by stack POST function to handle the POST results.

boot_hook_hw_init Low-level hardware initialization hook.

boot_hook_reset_hdlr_w_stack Reset handler with stack available for use. Should handle all reset causes
not handled by boot_hook_reset_hdlr_wo_stack().

boot_hook_post_hdlr Handler called by memory and cache POST function to handle the POST
results.

boot_hook_main_start User hook called at the start of main() in the Bootloader.

boot_hook_image_validate_hdlr Handler called by boot image validation routine to handle the image
validation results.

5.5.1 boot_hook_gen_exc_hdlr
boot_hook_gen_exc_hdlr() is called by the boot-strapped general exception vector. This routine handles all
possible general exceptions when the processor is in boot-strapped mode (Status register BEV bit = 1). For example,
the default example of this hook reads the cause of exception from the Cause register and aborts.

Prototype void boot_hook_gen_exc_hdlr(void)

Inputs None

Outputs None

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Bootloader

Returns Success = None

Failure = None

Side Effects None

Resource Available Registers

5.5.2 boot_hook_reset_hdlr_wo_stack
boot_hook_reset_hdlr_wo_stack() is called by the reset vector after the cause of reset has been determined,
but before the stack is initialized. This hook handles the cause of reset so that if it returns, the reset sequence
can continue. If the reset is not caused by problems in the stack, the reset handling can be delayed until
boot_hook_reset_hdlr_w_stack().

Prototype void boot_hook_reset_hdlr_wo_stack(

UINT8 reset_type)

Inputs reset_type Input value denoting cause of reset (soft reset, hard reset, or NMI)

Outputs None

Returns Success = None

Failure = None

Side Effects None

5.5.3 boot_hook_stack_post_hdlr
boot_hook_stack_post_hdlr() is called by the stack POST routine to handle the results of stack POST so that
when it returns, the reset sequence can continue.

Prototype void boot_hook_stack_post_hdlr(

PMCFW_ERROR stack_post_rc)

Inputs stack_post_rc Stack post result code

Outputs None

Returns Success = None

Failure = None

Side Effects None

Resource Available Registers

5.5.4 boot_hook_hw_init
boot_hook_hw_init() is called by the reset vector after stack POST. This routine performs the low-level hardware
initialization that must be completed during the reset vector. For example, the default example of this hook configures
the timing of parallel flash and SPI flash memory, and initializes DSPRAM.

Prototype void boot_hook_hw_init(UINT8 reset_type)

Inputs reset_type Input value denoting cause of reset (soft reset, hard reset, or NMI)

Outputs None

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Bootloader

Returns Success = None

Failure = None

Side Effects None

Resource Available Registers, stack

5.5.5 boot_hook_reset_hdlr_w_stack
boot_hook_reset_hdlr_w_stack() is called by the reset vector after the cause of reset has
been determined and the stack is initialized. This hook handles the cause of reset not handled by
boot_hook_reset_hdlr_wo_stack() so that if it returns, the reset sequence can continue.

Prototype void boot_hook_reset_hdlr_w_stack(

UINT8 reset_type)

Inputs reset_type Input value denoting cause of reset (soft reset, hard reset, or NMI)
Outputs None
Returns Success = None
Failure = None
Side Effects None
Resource Available Registers, stack

5.5.6 boot_hook_post_hdlr
boot_hook_post_hdlr() is called by the memory and cache POST routine(s) to handle the results of memory
and cache POST when it returns, the reset sequence can continue.

Prototype void boot_hook_post_hdlr(

PMCFW_ERROR post_rc)

Inputs post_rc Memory and cache POST result code

Outputs None

Returns Success = None

Failure = None

Side Effects None

Resource Available Registers, stack

5.5.7 boot_hook_main_start
boot_hook_main_start() is at the beginning of the Bootloader main() routine. This handle performs the
necessary initialization for the Bootloader image validation, image execution, to run.

Prototype void boot_hook_main_start(void)

Inputs None

Outputs None

Returns Success = None

Failure = None

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Bootloader

Side Effects None

Resource Available Registers, stack, RAM, global/static data/variables, cache, full C environment

5.5.8 boot_hook_image_validate_hdlr
boot_hook_image_validate_hdlr() is called by the Bootloader image validation routine to handle the results of
image validation. If this function returns, the Bootloader will continue execution by jumping to the start address of the
validated image.

Prototype void boot_hook_image_validate_hdlr(

flm_partition_enum partition, BOOT_STATUS_ENUM image_status)

Inputs image_status Image validation status

Outputs None

Returns Success = None

Failure = None

Side Effects None

Resource Registers, stack, RAM, global/static data/variables, cache, full C environment

Available

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Operating System Functions

6. Operating System Functions

6.1 Overview
The Operating System Functions (OSF) module is a set of wrappers built on top of the ThreadX kernel[1]. The OSF
enhances certain functions and limits the use of RTOS features to those verified and validated with the firmware. The
OSF functionality has two parts:
• OSF run-time services.
• OSF set-up services.
Figure 6-1. OSF Components

Application

OSF Set-Up
Services

OSF Run-Time Services

6.1.1 OSF Run-Time Services

OSF run-time services provide generic APIs that can be used by any application, such as the message send and
receive functions. Additional functionality is implemented internal to the OSF API. For example, logging is bundled
with most OSF functions for diagnostic purposes.

6.1.2 OSF Set-Up Services

OSF set-up services are application definition services for configuring the processor and RTOS for your application.
They provide startup and initialization operations that allow you to define threads, create and configure memory
pools, and allocate memory for the thread stacks and message queues. You may customize the OSF application
component as needed. For example, you may want to move the thread stack and message queue to faster or slower
memory, or add more tasks and message queues.
Since these startup operations are based on fixed hardware resources, a failure in any of these operations indicates
either a failure in the hardware or a failure to map the application program to the available hardware. Such failures
are always unrecoverable. Consequently, many of the OSF operations either complete successfully and return or, if
they cannot complete successfully, assert pmcfw_assert. This results in a watchdog reset.
This built-in error handling significantly reduces the code size and error handling required by your application.

6.1.3 OSF Summary

The following table summarizes the functions provided by the OSF module and how to use them.
Table 6-1. Functions in the OSF Module

Functions Description

System Initialization OSF system initialization. Must be called before any other OSF functions can be used.

User Memory Management Create memory pools, allocate and free buffers.

Threads Create and manage threads.

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...........continued
Functions Description

Messaging Create mailboxes to allow threads to communicate with one another.

Logging Log specific events and OSF transactions.

Timers Create, start, stop, delete, and manage application timers.

Semaphores Create, delete, put, and get semaphores.

Mutexes Create, delete, put, and get mutexes.

Interrupt Control Enable and disable processor core interrupts; manage call back functions.
Framework

MBIC Interrupt Controller Enable or disable individual interrupts; assign priorities; manage interrupt vectors;
Framework acknowledge interrupts.

6.1.4 OSF Function Usage

OSF function usage is divided into four areas shown in the following table and listed as follows:
• Initialization: Before the scheduler starts, mainly in tx_application_define().
• Threads: In the context of any application threads.
• Timers: In the context of any timer ISRs.
• ISRs: In the context of all ISRs excluding the timer ISRs.
Calling functions in cases when they are not supported gives indeterminate results.
Table 6-2. OSF Function Usage

Function Initialization Threads Timers ISRs

osf_sys_init ✓ ✗ ✗ ✗

osf_sys_timestamp_get ✓ ✓ ✓ ✓

osf_sys_timestamp_adj_set ✓ ✓ ✓ ✓

osf_thread_create ✓ ✓ ✗ ✗

osf_thread_sleep ✗ ✓ ✗ ✗

osf_thread_hndl_self ✗ ✓ ✗ ✗

osf_thread_num_max_get ✓ ✓ ✓ ✓

osf_mem_pool_create ✓ ✓ ✗ ✗

osf_mem_pool_alloc ✓1 ✓ ✓1 ✓1

osf_mem_pool_calloc ✓1 ✓ ✓1 ✓1

osf_mem_pool_free ✓ ✓ ✓ ✓

osf_mem_pool_num_free_buf_get ✓ ✓ ✓ ✓

osf_mbx_create ✓ ✓ ✗ ✗

osf_mbx_add ✓ ✓ ✗ ✗

osf_mbx_name_get ✓ ✓ ✗ ✗

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...........continued
Function Initialization Threads Timers ISRs

osf_msg_header_fill ✓ ✓ ✓ ✓

osf_msg_send ✓1 ✓ ✓1 ✓1

osf_msg_recv ✓1 ✓ ✓1 ✓1

osf_sem_create ✓ ✓ ✗ ✗

osf_sem_delete ✗ ✓ ✗ ✗

osf_sem_put ✓ ✓ ✓ ✓

osf_sem_get ✓1 ✓ ✓1 ✓1

osf_mtx_create ✓ ✓ ✗ ✗

osf_mtx_delete ✗ ✓ ✗ ✗

osf_mtx_get ✓1 ✓ ✗ ✗

osf_mtx_put ✓ ✓ ✗ ✗

osf_int_global_disable ✓2 ✓ ✓ ✓3

osf_int_global_enable ✓4 ✓ ✓ ✓5

osf_int_global_restore ✓6 ✓ ✓ ✓7

osf_int_isr ✗ ✗ ✗ ✓8

osf_tmr_create ✓ ✓ ✗ ✗

osf_tmr_delete ✗ ✓ ✗ ✗

osf_tmr_start ✓ ✓ ✓ ✓

osf_tmr_stop ✓ ✓ ✓ ✓

osf_tmr_period_change ✗ ✓ ✗ ✓

osf_tmr_period_get ✓ ✓ ✓ ✓

osf_time_ticks_get ✓ ✓ ✓ ✓

osf_time_diff ✓ ✓ ✓ ✓

osf_time_ms_to_ticks ✓ ✓ ✓ ✓

osf_time_ticks_to_ms ✓ ✓ ✓ ✓

osf_time_s_to_ticks ✓ ✓ ✓ ✓

osf_time_ticks_to_s ✓ ✓ ✓ ✓

osf_log_event_filter_set ✓ ✓ ✓ ✓

osf_log_event_filter_clear ✓ ✓ ✓ ✓

osf_log_word1_filter_set ✓ ✓ ✓ ✓

osf_log_word1_filter_get ✓ ✓ ✓ ✓

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...........continued
Function Initialization Threads Timers ISRs

osf_log_app_event ✓ ✓ ✓ ✓

osf_log_fatal_event ✓ ✓ ✓ ✓

osf_log_app_ipmi_event ✓ ✓ ✓ ✓

osf_log_app_clear ✓ ✓ ✓ ✓

osf_log_app_read ✓ ✓ ✓ ✓

osf_log_app_raw_write ✓ ✓ ✓ ✓

Notes:
1. Only non-blocking calls allowed (that is, timeout option must be OSF_WAIT_NONE.)
2. Interrupts will stay disabled during initialization regardless of calling this function as the interrupt masks remain
cleared.
3. Interrupts will stay disabled inside an ISR regardless of calling this function as the Status(EXL) bit remains set.
4. Interrupts will stay disabled during initialization regardless of calling this function as the interrupt masks remain
cleared.
5. Interrupts will stay disabled inside an ISR regardless of calling this function as the Status(EXL) bit remains set.
6. Interrupts will stay disabled during initialization regardless of calling this function as the interrupt masks remain
cleared.
7. Interrupts will stay disabled inside an ISR regardless of calling this function as the Status(EXL) bit remains set.
8. This function should be called by exception vectors only.

6.2 System Initialization

The function described in this section allows you to initialize the non-reusable system memory and use the 64-bit
system time.
The system free memory managed by OSF is “non-reusable”. The memory is allocated once by OSF will never
be freed during the program execution. This non-reusable system memory is used for OS purposes only and is
allocated internally by OSF for thread stacks, memory pools, and mailbox message queues through some OSF
private functions. The memory allocation can be aligned or unaligned.
The 64-bit system time is based on the OSF system timer (see Section 6.7 Timers) but is adjustable by a user-
defined offset. This allows you to synchronize the OSF system time with your system.

6.2.1 External Interface

The OSF provides the following public system initialization functions:
Table 6-3. OSF Functions

Function Description

osf_sys_init OSF system initialization. Must be called before any OSF functions can
be used.

osf_sys_timestamp_get Gets the current 64-bit system time.

osf_sys_timestamp_adj_set Sets a constant adjustment to the 64-bit system time.

6.2.1.1 osf_sys_init
You must call osf_sys_init()before you can use any OSF services. In the case of ThreadX , this function must
be the first OSF function called in tx_application_define(). When you call this function, pass it a pointer to

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Operating System Functions

the system free memory and a user-configured osf_sys_cfg_struct.The osf_sys_cfg_struct contains OSF
system configuration information such as the total number of mailboxes, threads, memory pools, logs and log sizes in
the system. The OSF takes over the system free memory, allocates control structures for all the mailboxes, threads,
and memory pools and logs the application log memory in the system, if needed. See Section 6.2.2 Data Structures
for more information on osf_sys_cfg_struct.
At this point, the object control structures are un-initialized. The object control structures are initialized when you call
the corresponding osf_xxx_create() functions.

Prototype void osf_sys_init(

void *free_mem_ptr,
osf_sys_cfg_struct *cfg_ptr)

Inputs *free_mem_ptr (pointer to) system free memory

*cfg_ptr (pointer to) OSF configuration information

Outputs None

Returns Success = None

Failure = Assert and never return

Side Effects None

6.2.1.2 osf_sys_timestamp_get
The osf_sys_timestamp_get() function returns the current 64-bit system time in terms of the OSF system timer
ticks. osf_time_ticks_to_s() must be used to convert the returned current system time (in system timer ticks)
to the time (in seconds).

Prototype UINT64 osf_sys_timestamp_get(void)

Inputs None

Outputs None

Returns Success = Number of timer ticks since reset + constant offset set by user.

Failure =

Side Effects None

6.2.1.3 osf_sys_timestamp_adj_set
The osf_sys_timestamp_adj_set() function sets a constant adjustment to the 64-bit system time in terms of the
OSF system timer ticks. osf_time_s_to_ticks() must be used to convert a constant adjustment from the time
(in seconds) to the system timer ticks for use in this function.

Prototype void osf_sys_timestamp_adj_set(

UINT64 adj)

Inputs adj Constant adjustment to the 64-bit system time in terms of system timer
ticks

Outputs None

Returns Success =

Failure =

Side Effects None

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Operating System Functions

6.2.2 Data Structures

6.2.2.1 osf_sys_cfg_struct
The osf_sys_cfg_struct contains the configuration parameter required by the OSF system. You must configure
an instance of this structure and pass it to osf_sys_init().
See Section 6.6 Logging for information on app_log_size and log_cfg, and Section 6.7 Timers for
desired_tmr_period_ms.

/***************************************************************************
* STRUCTURE: osf_sys_cfg_struct * System structure controlling all OSF configuration
parameters.
*
* ELEMENTS: * app_log_size - Application log size (in number of bytes)
* desired_tmr_period_ms - Desired system timer period in ms.
* num_threads - Total number of threads in the system.
* num_mem_pools - Total number of memory pools in the system.
* num_mbx - Total number of mailboxes in the system.
* log_cfg - Logging configuration for the system
* app_log_addr - Logging saving start address
**************************************************************************/

typedef struct
{
UINT32 app_log_size;
UINT32 desired_tmr_period_ms;
UINT16 num_threads;
UINT16 num_mem_pools;
UINT16 num_mbx;
osf_log_cfg_enum log_cfg;
void *app_log_addr;
} osf_sys_cfg_struct;

6.2.3 Architecture
Each OSF service (messaging, memory, mutexes, and so on.) has one or more system control structures or
parameters. Those structures and parameters are allocated by and are internal to the OSF. These structures and
parameters are statically allocated inside each OSF file.
Some OSF services have object control structures for referencing the OSF object. These object control structures
can be divided into two categories:
1. Control structures for which OSF internally allocates memory, such as memory pools, mailboxes, and threads.
Use handles to reference these OSF objects.
2. Control structures that you allocate, such as timers, mutexes, and semaphores. You determine whether these
OSF control structures are statically or dynamically allocated, and you refer to them directly.
Regardless of how the OSF object control structures are allocated, only the OSF is allowed to modify them.
When you initialize the system using osf_sys_init(), you specify the total number of objects in category 1. The
OSF then allocates memory for the object control structures in category 1 from the system memory.
The system memory is a single block of memory passed into OSF at system initialization. In the ThreadX case, this
memory is the “. free_mem” section defined in the linker command file. ThreadX passes the start address of the “.
free_mem” to tx_application_define(), that passes this address to osf_sys_init(). OSF then takes over
control of its usage.
Memory is allocated sequentially from the system memory block as long as there is sufficient free memory. For
non-aligned address memory allocation, the memory allocated starts at the next free memory address. For aligned
memory allocation, the memory allocated starts at the next free memory address that matches the alignment
requirement.

6.3 User Memory Management

Besides the non-reusable system memory (see Section 6.2 System Initialization ) that is managed and allocated for
OS usage only, the OSF provides management functions for a second type of memory that is available to all OSF

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users. This memory is grouped into memory pools and is reusable. Each memory pool maintains several buffers of
the same size. The buffers can be allocated and freed during program execution and reused by different objects in
the program. Buffer size and the number of buffers may differ from pool to pool and are configured at instantiation.
Currently, the OSF does not support the priority memory allocation feature of ThreadX. All memory allocation is
based on FIFO order.

6.3.1 External Interface

The OSF supports the following memory management functions:
Table 6-4. User Memory Management Functions

Function Description

osf_mem_pool_create Creates a memory pool.

osf_mem_pool_alloc Allocates a buffer from the specified memory pool.

osf_mem_pool_calloc Allocates a cleared buffer from the specified memory pool.

osf_mem_pool_free Frees a previously allocated buffer.

osf_mem_pool_num_free_buf_get Returns the current number of free buffers in the pool.

Use osf_sys_init() to specify the maximum number of memory pools in the system. OSF allocates memory for
the corresponding number of memory pool control structures. At this point, the memory pool control structures are
un-initialized.

6.3.1.1 osf_mem_pool_create
After calling osf_sys_init(), call osf_mem_pool_create() to create a memory pool. If there is sufficient system
memory, OSF allocates memory for the number of buffers in the specified size for the pool, and assigns one of the
memory pool control structures allocated by osf_sys_init() for this memory pool. OSF returns a handle to the
memory pool control structure.
The firmware uses osf_mem_pool_create() and osf_mem_pool_alloc() to allocate fixed blocks of RAM
for inter-thread messaging at system start. This ensures that any memory allocation problems occur at system
start-up rather than midway through the application, simplifying error handling and improving the robustness of the
application. During run-time, a message can be sent to another thread only if there is room within the pre-allocated
block. If the destination thread runs out of space in its message block, it is being overloaded. The application must
provide a throttling mechanism to resolve this condition.

Prototype osf_mem_pool_hndl osf_mem_pool_create(

CHAR *name_ptr,
UINT32 buf_size,
UINT32 num_buf)

Inputs *name_ptr (pointer to) memory pool name string

buf_size Size of buffers in memory pool

num_buf Number of buffers in the pool

Outputs None

Returns Success = Handle to newly-created memory pool

Failure = OSF_ERR_FAIL
OSF_ERR_OUT_OF_RESOURCE

Side Effects None

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6.3.1.2 osf_mem_pool_alloc
Use osf_mem_pool_alloc() and the memory pool handle returned by osf_mem_pool_create() to allocate
buffers from the memory pool. OSF assigns the pointer to the allocated buffer to your input double pointer. If statistics
event logging is enabled, osf_mem_pool_alloc() logs a statistics event if the number of free buffers in a pool
reaches a new minimum after a buffer is allocated from that pool.
Ensure that the buffer size from the specified pool meets the memory allocation requirement. OSF will assert if the
required buffer size is larger than the buffer size for the specified memory pool.
A timeout value is specified for allocating buffers from the memory pool. Valid timeout values are:
• OSF_WAIT_NONE: Attempt to allocate a buffer and return right away.
• OSF_WAIT_FOREVER: Wait until a buffer is allocated. Thread is suspended while waiting.
• Finite value: Wait until the buffer is allocated, or the finite timeout period expires. Thread is suspended while
waiting. The valid timeout period is from OSF_WAIT_MIN to OSF_WAIT_MAX timer ticks.
The firmware uses osf_mem_pool_create() and osf_mem_pool_alloc() to allocate fixed blocks of RAM
for inter-thread messaging at system start. This ensures that any memory allocation problems occur at system
start-up rather than midway through the application, simplifying error handling and improving the robustness of the
application. During run-time, a message can be sent to another thread only if there is room within the pre-allocated
block. If the destination thread runs out of space in its message block, it is being overloaded. The application should
provide a throttling mechanism to resolve this condition.
Note: Each buffer in the pool will be aligned to a sizeof(void *) boundary.

Prototype PMCFW_ERROR osf_mem_pool_alloc(

osf_mem_pool_hndl pool_hndl,
UINT32 buf_size,
void **buf_pptr,
UINT32 wait_option)

Inputs pool_handle Handle of previously-created memory pool

buf_size Required size of buffers in memory pool

**buf_pptr (Pointer to) pointer to buffer

wait_option Timeout option if memory buffer is currently unavailable

Outputs buf_pptr On successful memory allocation, buf_pptr = pointer to allocated buffer

On failed memory allocation, *buf_pptr is unchanged

Returns Success = PMC_SUCCESS

Failure = OSF_ERR_FAIL
OSF_ERR_OUT_OF_RESOURCE
OSF_ERR_TIMEOUT

Side Effects None

6.3.1.3 osf_mem_pool_calloc
Similar to osf_mem_pool_alloc()except that the allocated buffers are cleared to 0.

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Prototype PMCFW_ERROR osf_mem_pool_calloc(

osf_mem_pool_hndl pool_hndl,
UINT32 num_ele,
UINT32 ele_size,
void **buf_pptr,
UINT32 wait_option)

Inputs pool_handle Handle of previously-created memory pool

num_ele Required number of elements in each buffer

ele_size Required size of elements in number of bytes

**buf_pptr (Pointer to) pointer to buffer

wait_option Timeout option if memory buffer is currently unavailable

Outputs buf_pptr On successful memory allocation, buf_pptr = pointer to allocated cleared

buffer
On failed memory allocation, *buf_pptr is unchanged

6.3.2 Data Structures

6.3.2.1 osf_mem_pool_hndl
The OSF returns a handle to the memory pool, osf_mem_pool_hndle, when a memory pool has been successfully
created.
typedef void *osf_mem_pool_hndl;

6.3.3 Example
You should use double pointers in allocating and freeing memory. The following example shows the use of the
Memory Management functions for allocating and freeing memory.

void *msg_ptr;
thread1_msg_union *recv_msg_ptr;
rc = osf_mem_pool_alloc(thr_ptr->pool_hndl,
sizeof(thread1_thread2_ping_msg_struct),
&msg_ptr,
OSF_WAIT_FOREVER);
osf_mem_pool_free((void **)&recv_msg_ptr);

6.3.4 Architecture
The following figure shows the memory allocation for the memory pools.
Figure 6-2. Memory Pool Allocation Architecture

osf system m em ory pool control

Statically allocated in the
structures and param eters
osf_m em .c file

array of m em ory pool control structures, one for each Allocated by OSF in
m em ory pool osf_sys_init()

Allocated by OSF in
m em ory pool A, ...... m em ory pool N, osf_m em _pool_create()
m em ory grouped m em ory grouped
into buffers into buffers

6.4 Threads
The OSF module supports preemptive multi-threading. The OSF thread functions are mainly wrappers for the
ThreadX functions. You assign a priority to each thread. The valid range is from OSF_THREAD_PRIO_HIGHEST to
OSF_THREAD_PRIO_LOWEST and each thread must have a unique priority. The time-slicing capability of ThreadX is
not used. All threads are configured to start immediately when the scheduler starts running.
Note that the OSF threads maintain the Status Register (SR) state as part of their thread context. When a thread gets
pre-empted, the SR state is stored. When the thread resumes, the SR is restored to the stored state.

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6.4.1 External Interface

The OSF supports the following thread functions:
Table 6-5. Thread Functions

Function Description

osf_thread_create Creates a thread specifying the stack size, entry function and entry function
input.

osf_thread_sleep Suspends the execution of the current task for a given number of ticks.

osf_thread_hndl_self Returns thread handle of currently executing thread.

osf_thread_num_max_get Returns the maximum number of threads in the system.

Use osf_sys_init() to specify the maximum number of threads in the system. OSF allocates the corresponding
number of thread control structures. At this point, the thread control structures are un-initialized.

6.4.1.1 osf_thread_create
After initialization, call osf_thread_create() to create a thread. Each thread has its own stack that is allocated
by OSF during osf_thread_create(). If there is sufficient system memory, OSF allocates the specified amount of
memory for the thread stack, and assigns one of the thread control structures allocated by osf_sys_init() for this
thread. osf_thread_create() returns a handle to the created thread.

Prototype osf_thr_hndl osf_thread_create(

CHAR *name_ptr,
void (*entry_function) (UINT32),
UINT32 entry_input,
UINT32 stack_size,
UINT16 priority)

Inputs *name_ptr (Pointer to) thread name

*entry_ function (Pointer to) thread entry function. This is the application defined function
called when the thread starts.

entry_input input value passed to thread entry function

stack_size Memory allocated to thread stack

priority Thread priority

Outputs None

Returns Success = Handle to newly-created thread

Failure = Assert and never return

Side Effects None

6.4.1.2 osf_thread_sleep
While the thread is executing, you can call osf_thread_sleep() to suspend its execution for a given number
of system timer ticks. Use the osf_time_ms_to_ticks() function (see Section 6.7 Timers) to convert a sleep
duration from milliseconds to ticks, as the underlying system timer tick duration may change for different platforms.

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Prototype void osf_thread_sleep(

UINT32 timer_ticks)

Inputs timer_ticks Sleep duration in timer ticks

Outputs None

Returns Success = None

Failure = Assert and never return

Side Effects None

6.4.1.3 osf_thread_hndl_self
osf_thread_hndl_self() returns the thread handle of the currently executing thread. If this function is being
called from a non-thread, the handle returned will be that of the last executing thread.

Prototype osf_thr_hndl osf_thread_hndl_self(void)

Inputs None

Outputs None

Returns Success = Thread handle of currently-executing thread

Failure =

Side Effects None

6.4.1.4 osf_thread_num_max_get
osf_thread_num_max_get() returns the maximum number of threads in the system. This is the value of the
number of threads in the system passed to OSF in osf_sys_init() by the user.

Prototype UINT32 osf_thread_num_max_get(void)

Inputs None

Outputs None

Returns Success = Maximum number of threads in the system.

Failure =

Side Effects None

6.4.2 Data Structures

6.4.2.1 osf_thr_hndl
OSF returns a handle to the thread object, osf_thr_hndl, when a thread has been successfully created:
typedef void *osf_thr_hndl;

6.4.3 States
For all normal execution, threads in this system will be in one of these states:
• Thread sleeping, due to osf_thread_sleep().
• Thread blocking, due to a blocking OSF call to currently unavailable OSF resources.
• Thread running.
Note: Currently, OSF does not support the ThreadX thread services of suspension, resumption, termination, deletion,
priority, or preemption threshold changes.

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6.4.4 Architecture
The following figure shows the memory allocation for the thread control structures and the thread stacks.
Figure 6-3. Memory Allocation Across Threads
osf system thread control
Statically allocated in the
structures and param eters
osf_thr.c file

Allocated by OSF in
array of thread control structures, one for each thread
osf_sys_init()

Allocated by OSF in
...... osf_thread_create()
thread stack A thread stack N

6.5 Messaging
Threads exchange data and event notifications by sending messages to the mailbox of the recipient thread. For
normal systems, each thread is associated with one mailbox.
Each mailbox supports up to osf_msg_prio_num message priorities. Messages are received first in order of priority,
then in order of arrival.
When a message is sent, it is copied to a mail slot in the mailbox, and copied out when the message is received.
To reduce the amount of copying, each message slot is one word (32 bits) long. The message must be a pointer to
point to an allocated buffer. The sender thread allocates a message buffer, fills the message buffer with its message,
and sends a pointer to point to this message buffer to the recipient’s message queue. Once the message has been
successfully sent to the recipient’s message queue, OSF changes the input pointer to point to NULL to prevent the
sender from modifying the buffer. The recipient thread must free the message buffer.
All messages must be prepended with a standard message header by including osf_msg_header_struct as the
first element of all message structures.
To improve memory efficiency despite variations in message payload sizes, the message buffers should be large
enough for normal message types but insufficient for large amounts of data. For message payloads that include large
amounts of data, allocate a separate data buffer for the data, and put a pointer to it in the message structure that will
reside in the message buffer. See Section 6.3 User Memory Management for more detail on memory buffers.

6.5.1 External Interface

The OSF supports the following messaging functions:
Table 6-6. Messaging Functions

Function Description

osf_mbx_create Creates a mailbox specifying the message priority and number of messages for this
priority.

Osf_mbx_add Adds a message priority to a previously created mailbox, specifying the number of
messages for this priority.

Osf_msg_header_fill Fills the required information into the input message header structure.

Osf_msg_send Sends a message to the recipient mailbox at the specified priority

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...........continued
Function Description

osf_msg_recv Receives a message from the specified mailbox at priority then arrival order.

Use osf_sys_init() to specify the maximum number of mailboxes in the system. OSF allocates the corresponding
number of mailbox control structures. At this point, the mailbox control structures are un-initialized.

6.5.1.1 Osf_mbx_create
After initialization, call osf_mbx_create() to create a mailbox. If there is sufficient system memory, OSF allocates
the specified amount of memory for the messages at the specified priority for this mailbox, and assigns one of the
mailbox control structures allocated by osf_sys_init() for this mailbox. The function returns a handle to the
created mailbox. Use this handle to add message priority to the mailbox and to send and receive messages from the
mailbox.

Prototype osf_mbx_hndl osf_mbx_create(

CHAR *name_ptr,
UINT8 num_msg,
osf_msg_prio_enum prio)

Inputs *name_ptr (Pointer to) mailbox name string

num_msg Number of messages in message queue

prio Message queue priority

Outputs None

Returns Success = Handle to mailbox structure

Failure = OSF_ERR_FAIL
OSF_ERR_OUT_OF_RESOURCE

Side Effects None

6.5.1.2 osf_mbx_add
If you need to implement message priority, call osf_mbx_add() to add a message priority (and the number of
messages for this priority) to the mailbox you created.

Prototype void osf_mbx_add(

osf_mbx_hndl mbx_hndl,
CHAR *name_ptr,
UINT8 num_msg,
osf_msg_prio_enum prio)

Inputs mbx_hndl Handle to mailbox

*name_ptr (Pointer to) mailbox name string

num_msg Number of messages in message queue

prio Message queue priority

Outputs None

Returns Success = None

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Failure = Assert and never return

Side Effects None

6.5.1.3 osf_msg_header_fill
Before sending a message, you must allocate a buffer (see Section 6.3 User Memory Management) and fill out the
header structure using osf_msg_header_fill().

Prototype void osf_msg_header_fill(

osf_msg_header_struct *hdr_ptr,
UINT32 msg_type,
osf_mbx_hndl recipient_mbx_hndl,
osf_msg_prio_enum recipient_msg_prio,
osf_mbx_hndl sender_mbx_hndl,
osf_msg_prio_enum sender_msg_prio)

Inputs *hdr_ptr (Pointer to) message header to be filled

msg_type Type of message

recipient_ Handle of recipient mailbox

mbx_hndl

recipient_ Priority of recipient message

msg_prio

sender_ Handle of sender mailbox

mbx_hndl

sender_ msg_prio Priority of sender message

Outputs hdr_ptr Pointer to filled message header

Returns Success = None

Failure = OSF_ERR_FAIL
OSF_ERR_OUT_OF_RESOURCE

Side Effects None

6.5.1.4 osf_msg_send
Once the buffer has been allocated and the header structure filled out, use osf_msg_send() to send messages to
another thread at the thread’s mailbox. To prevent you from using the buffer after the message has been sent, OSF
takes over the buffer by overwriting your double pointer to it. If statistics event logging is enabled, osf_msg_send()
logs a statistics event if the number of free message slots for the specified message priority in the mailbox reaches a
new minimum after a message is sent to the mailbox at that priority.
A timeout value is specified for sending messages from the queue. Valid timeout values are:
• OSF_WAIT_NONE: Send and return right away. 1
• OSF_WAIT_FOREVER: Wait indefinitely until the message is sent. Thread is suspended while waiting.
• Finite value: Wait until the message is sent, or the finite timeout period expires. Thread is suspended while
waiting. The valid timeout period is from OSF_WAIT_MIN to OSF_WAIT_MAX timer ticks.

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Prototype PMCFW_ERROR osf_msg_send(

void **msg_pptr
UINT32 wait_option)

Inputs **msg_pptr (Pointer to) pointer to message

wait_option Timeout option

Outputs msg_pptr Pointer to message buffer updated to NULL if message is sent successfully
Pointer unchanged if message send failed

Returns Success = PMC_SUCCESS

Failure = OSF_ERR_TIMEOUT
Assert and never return if wait_option = OSF_WAIT_NONE.

Side Effects None

Note: For PM73207 B005 and earlier releases, osf_msg_send() aborts if the message send or receive fails with this
non-blocking option.
6.5.1.5 Osf_msg_recv
The recipient thread reads the messages from its associated mailbox by using osf_msg_recv(). The messages
are read first in order of priority, then in order of arrival. After processing the information in the message, the recipient
must free the buffer allocated for the message.
A timeout value is specified for receiving messages from the queue. Valid timeout values are:
• OSF_WAIT_NONE: Send or receive and return right away.
• OSF_WAIT_FOREVER: Wait until the message is sent or a message is received. Thread is suspended while
waiting.
• Finite value: Wait until the message is sent or a message is received, or the finite timeout period expires. Thread
is suspended while waiting. Valid timeout period is from OSF_WAIT_MIN to OSF_WAIT_MAX timer ticks.

Prototype PMCFW_ERROR osf_msg_recv(

osf_mbx_hndl recipient_hndl,
void **msg_pptr,
UINT32 wait_option)

Inputs recipient_ hndl Handle of recipient mailbox

**msg_pptr (Pointer to) pointer to message

wait_option Timeout option

Outputs *msg_pptr Message pointer updated to received buffer on successful receive

Message pointer unchanged if message receive failed

Returns Success = PMC_SUCCESS

Failure = OSF_ERR_TIMEOUT

Side Effects None

6.5.2 Data Structures

6.5.2.1 osf_mbx_hndl
OSF returns a handle to the mailbox object, osf_mbx_hndl, when a mailbox has been successfully created:

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typedef void *osf_mbx_hndl;

6.5.2.2 osf_msg_header_struct
All message structures in the system must have osf_msg_header_struct as their first element.

/***************************************************************************
* STRUCTURE: osf_msg_header_struct
* Structure defining the first elements of all application
* inter-task messages.
*
* ELEMENTS:
* msg_type - Message type.
* recipient - Recipient message queue information.
* sender - Sender message queue information.
**************************************************************************/
typedef struct
{
UINT32 msg_type;
osf_mq_info_struct recipient;
osf_mq_info_struct sender;
} osf_msg_header_struct;

osf_msg_header_struct contains all the information required to send and decode a message. If the message is
sent from a thread with a valid mailbox, the recipient can use the sender information to reply to the sender.

6.5.2.3 Osf_mq_info_struct
The sender and recipient information are defined in osf_mq_info_struct:

/***************************************************************************
* STRUCTURE: osf_mq_info_struct
* Structure containing information to identify a message queue.
*
* ELEMENTS:
* mbx_hndl - Handle to mailbox
* msg_prio - Message priority
*
* NOTE:
* - “=” is going to be used to copy sender info to recipient info and
* vice versa.
* - Elements must NOT be an array, have an incomplete type, or be a function.
****************************************************************************/
typedef struct
{
osf_mbx_hndl mbx_hndl;
osf_msg_prio_enum msg_prio;
} osf_mq_info_struct;

6.5.2.4 msg_type
Use this macro to define the message type, msg_type:
OSF_MSG_TYPE_CREATE(module_id, msg_suffix)
Use the following two macros to extract the module and message suffix information from a message type:
OSF_MSG_MODULE_GET(msg_type)
OSF_MSG_SUFFIX_GET(msg_type)

6.5.3 Architecture
ThreadX does not support priority messaging. To implement priority messaging, OSF creates multiple message
queues in each mailbox. One message queue corresponds to a message priority. The message queues are read
based on priority order.
The following figure shows the memory allocation for the thread control structures and the thread stacks.

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Figure 6-4. Messaging Functions Architecture

osf system m ailbox control
Statically allocated in the
structures and param eters
osf_m sg.c file

array of m ailbox control structures, one for each Allocated by OSF in

m ailbox osf_sys_init()

m ailbox m ailbox m ailbox m ailbox

A, A, N, N, Allocated by OSF in
...... osf_m bx_create() and
m essage m essage m essage m essage
queue queue queue queue osf_m bx_add()
priority priority priority priority
norm highest norm highest

To create a mailbox, call osf_mbx_create()first to initialize the mailbox control structure. OSF allocates a
message queue at the specified priority (one of osf_msg_prio_enum) if there is sufficient system memory. If the
mailbox must support more than one message priority, call osf_mbx_add() specifying a different message priority
than that specified in osf_msg_prio_enum. If there is sufficient system memory, OSF allocates memory for the
second message queue and associates it with the previously-created mailbox.

6.6 Logging
OSF provides logging capability with an OSF log and an optional application log. Event logging in the OSF wrapper
APIs is enhanced with logging ThreadX error codes in Microchip Application logs. The logs are circularly indexed so
that the oldest log entries are replaced by the newest log entries.
Log entries include OSF transactions such as message send and receive, buffer allocation, statistics events such as
memory pool reaching new minimum headroom, and fatal events logged before the firmware asserts.
The log entry format is listed as follows.
Table 6-7. Format of Event Log Entry

16-bit 4-bit log event type 9-bit log sub-type 3-bit num words in log
TX_EL_USER_EVENT (osf_log_event_enum) entry
(osf_log_sub_type_enum
(= 4)
)

upper 32-bit of sequence number (always 0)

lower 32-bit of sequence number (increment for each entry)

32-bit currently executing thread pointer (if logging from an interrupt, the thread pointer will be that of the last
executing thread)

32-bit log word 1 (must be in the format [16-bit module ID | 16-bit user defined field])

32-bit log word 2

32-bit log word 3

32-bit log word 4

The application log entry format is listed as follows.

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Table 6-8. Format of Application Log Entry

Word/Bit 31:24 23:16 15:8 7:0

0 Reserved LOG TYPE LOG SEVERITY [15:0]

1 UPPER TIME STAMP

2 LOWER TIME STAMP

3 SEQUENCE NUMBER

4 LOG CODE MODULE-ID LOG CODE USER DEFINED

5 LOG WORD 2

6 LOG WORD 3

7 LOG WORD 4

At compile time, configure the system to use only the OSF log or both the OSF and application logs by calling
osf_sys_init() (log_cfg in osf_cfg_struct). The OSF log size is determined by the size of the “.
Eventlog” section in the linker directive files. Configure the application log size by calling osf_sys_init()
(app_log_size in osf_cfg_struct).
At runtime, enable or disable logging for both logs by configuring the log filters.
OSF provides configuration capability for log filtering based on the event type and log_word1 (applicable to
application log only).
The known set of log words in the system is listed as follows.
Table 6-9. Known Event Logging Codes

Code Description

OSF_LOG_INVALID_PARAMS Invalid input parameter

OSF_LOG_FREE_MEM_EXHAUSTED OSF system memory exhausted

OSF_LOG_FAIL_NUM_POOL_EXCEED_MAX Number of requested memory pool creations exceeds

maximum specified through osf_sys_init().

OSF_LOG_FAIL_MEM_POOL_CREATE Memory pool creation failed

OSF_LOG_MIN_HEADROOM_MEM_POOL New minimum headroom reached for this memory pool.

OSF_LOG_FAIL_MEM_ALLOC Memory allocation failed

OSF_LOG_FAIL_MEM_FREE Memory free failed

OSF_LOG_FAIL_NUM_MBX_EXCEED_MAX Number of requested mailbox creations exceeds maximum

specified through osf_sys_init().

OSF_LOG_FAIL_MBX_CREATE Mailbox creation failed.

OSF_LOG_FAIL_MBX_ADD Mailbox message queue addition failed.

OSF_LOG_INVALID_MSG_PRIO_QUE Message queue priority specified in message header invalid.

OSF_LOG_MIN_HEADROOM_MSG_QUE New minimum headroom reached for this message queue.

OSF_LOG_FAIL_MSG_SEND Message send failed

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...........continued
Code Description

OSF_LOG_FAIL_MSG_RECV Message receive failed

OSF_LOG_UNEXPECTED_EMPTY_MBX Mailbox is unexpected to be empty since mailbox semaphore

get was successful.

OSF_LOG_FAIL_MTX_CREATE Mutex creation failed

OSF_LOG_FAIL_MTX_DELETE Mutex deletion failed

OSF_LOG_FAIL_MTX_GET Mutex get failed

OSF_LOG_FAIL_MTX_PUT Mutex put failed

OSF_LOG_FAIL_SEM_CREATE Semaphore creation failed

OSF_LOG_FAIL_SEM_DELETE Semaphore deletion failed

OSF_LOG_FAIL_SEM_GET Semaphore get failed

OSF_LOG_FAIL_SEM_PUT Semaphore put failed

OSF_LOG_FAIL_NUM_THREAD_EXCEED_MAX Number of requested thread creations exceeds maximum

specified through osf_sys_init().

OSF_LOG_FAIL_THREAD_CREATE Thread creation failed

OSF_LOG_FAIL_THREAD_SLEEP Thread sleep failed

OSF_LOG_FAIL_THREAD_HNDL_SELF Current thread handle invalid

OSF_LOG_FAIL_TMR_CREATE Timer creation failed

OSF_LOG_FAIL_TMR_DELETE Timer deletion failed

OSF_LOG_FAIL_TMR_START Timer start failed

OSF_LOG_FAIL_TMR_STOP Timer stop failed

OSF_LOG_FAIL_TMR_PERIOD_CHANGE Timer period change failed

OSF_LOG_FAIL_VALUE_OUT_OF_RANGE Value out of range.

OSF_LOG_FAIL_UNSUPPORTED_LOG_EVENT Log event is not supported

OSF_LOG_INT_UNEXPECTED_INTERRUPT Interrupt not registered by user.

OSF_LOG_FAIL_TMR_INFO_GET Failed to get timer status

OSF_LOG_FAIL_TMR_CFG_SATURATE User-specified timer period too large, causes saturation.

OSF_LOG_FAIL_LOG_WORD_EXCEED_MAX Number of specified log words exceeds maximum allowable.

6.6.1 External Interface

The OSF supports the following log functions:

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Table 6-10. Logging Functions

Function Description

osf_log_event_filter_set Sets filter for the specified log event(s). The specified event(s) will not
be logged.

Osf_log_event_filter_clear Clears filter for the specified log event(s). The specified event(s) will be
logged.

Osf_log_app_sev_filter_level_set Set global severity level

osf_log_app_sev_filter_level_get Get global severity level

osf_log_word1_filter_set Sets filter base on log_word1 (for use with application events only).

Osf_log_word1_filter_get Gets a copy of the bank of log_word1 filters.

Osf_log_app_event Logs an application event.

Osf_log_fatal_event Logs a fatal error event.

Osf_log_app_ipmi_event Logs an application IPMI event.

Osf_log_app_clear Clears the application log.

Osf_log_app_read Reads an entry from the application log.

Osf_log_app_raw_write Writes a raw entry to the application log.

Osf_log_get_entry_params Get application log parameters.

When you initialize the system using osf_sys_init(), specify whether the optional application log is enabled in
addition to the OSF log (in osf_log_cfg_enum). If the application log is supported, OSF will allocate the specified
amount of memory for the application log if it is available.

6.6.1.1 Osf_log_event_filter_set
Call osf_log_event_filter_set()with the OSF_LOG_FILTER_XXX combinations (defined in osf. H) as required
to configure which events will be logged.

Prototype void osf_log_event_filter_set(

UINT32 events_to_filter)

Inputs events_to_ filter OR of desired OSF_LOG_FILTER_XXX events

Outputs None

Returns Success = None

Failure = None

Side Effects None

6.6.1.7 osf_log_app_event
Use osf_log_app_event() to log application events.

Prototype void osf_log_app_event(

osf_log_sev_enum event_sev
UINT8 num_words,
UINT32 log_code,
UINT32 log_word2,
UINT32 log_word3,
UINT32 log_word4)

Inputs num_words Number of valid log words.

Log_code 32-bit log code in the format:

[16-bit module ID | 16-bit generic]

log_word2 User defined log word

log_word3 User defined log word

log_word4 User defined log word

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Outputs None

Returns Success = None

Failure = Assert and never return

Side Effects None

6.6.1.8 osf_log_fatal_event
Use osf_log_fatal_event() to log fatal error events. If the number of log words (num_words) exceeds the
maximum allowable log words, this function saturates num_words to the maximum number of allowable log words
before logging the event.

Prototype void osf_log_fatal_event(

UINT8 num_words,
UINT32 log_code,
UINT32 log_word2,
UINT32 log_word3,
UINT32 log_word4)

Inputs num_words Number of valid log words.

Log_code 32-bit log code in the format:

[16-bit module ID | 16-bit generic]

log_word2 User defined log word

log_word3 User defined log word

log_word4 User defined log word

Outputs None

Returns Success = None

Failure = None

Side Effects None

6.6.1.9 osf_log_app_ipmi_event
Use osf_log_app_ipmi_event() to log application IPMI events.

Prototype void osf_log_app_ipmi_event(

UINT32 log_code,
UINT8 sensor_type,
UINT8 sensor_num,
UINT8 event_word,
UINT8 event_data1,
UINT8 event_data2,
UINT8 event_data3)

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Inputs log_code 32-bit log code in the format:

[16-bit module ID | 16-bit generic]

sensor_type Sensor Type Code for sensor that generated the event.

Sensor_num Number of sensor that generated the event.

Event_word [Event Dir (bit 7) | Event Type Code (bits 6:0)]

Event Dir: 0b = Assertion event 1b = Deassertion event
Event Type Code: Type of trigger for the event, for example, critical
threshold going high, state asserted, and so on. Also indicates class of
the event. For example, discrete, threshold, or OEM. The Event Type
field is encoded using the Event/Reading Type Code.

Event_data1 Per IPMI Event Request Message Event Data Field Contents for Data 1.

Event_data2 Per IPMI Event Request Message Event Data Field Contents for Data 2.

Event_data3 Per IPMI Event Request Message Event Data Field Contents for Data 3.

Outputs None

Returns Success = None

Failure = Assert and never return

Side Effects None

6.6.1.10 osf_log_app_clear
Call osf_log_app_clear() to clear the application log.

Prototype void osf_log_app_clear(void)

Inputs None

Outputs None

Returns Success = None

Failure = None

Side Effects None

6.6.1.11 osf_log_app_read
Use osf_log_app_read() to read an entry from the application log.
The read is “destructive”, that is, an entry can only be read once.

Prototype PMCFW_ERROR osf_log_app_read(

osf_log_app_entry_struct *entry_ptr,
UINT32 *num_missed_entries_ptr)

Inputs None

Outputs entry_ptr Entry read, if read is successful.

Num_missed_entr Number of unread entries missed since the last read, if read is successful.
ies_ptr

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Returns Success = PMC_SUCCESS

Operating System Functions

• Disabled – No events will be logged.

In the enabled state, events will be filtered as follows:
• All log events (except application events) will be filtered by the log event filter configured by
osf_log_event_filter_set() and osf_log_event_filter_clear().
• Application events (including IPMI events) will be filtered by both the log event filter configured by
osf_log_event_filter_set() and osf_log_event_filter_clear(), and the bank of log word 1 filters
configured by osf_log_word1_filter_set().
The following figure shows the application event filtering using the log word 1 filter bank.

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Figure 6-5. Filtering on Application Event Log Word 1

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6.6.3 Architecture
The OSF log uses the ThreadX Event Analyzer log. All ThreadX-generated log entries are logged into the Event
Analyzer log. OSF-added entries are logged as user-inserted events.
If the application log is enabled, it is allocated by OSF in osf_sys_init(). If you have enabled the application log,
application events (including application IPMI events) that are not filtered out will be directed to both the OSF log and
the application log.
Both logs are a memory block used as a circular buffer where the oldest entries will be overwritten by newer entries.

6.7 Timers
OSF provides the system time and the ability to create, set, change and delete the application timers. The system
time is a 32-bit value which reflects the number of system hardware timer ticks since power up. System time wraps
around when it reaches its maximum. See Section 6.7.3 System Hardware Timer Operation for more detail on
system hardware timer operation and guidelines on setting up the system timer period.
Application timers can be one-shot timers or period timers. The expiration characteristics of a timer include an initial
expiration tick count and a reschedule tick count. When a timer is first started, the first expiry is the initial expiration
tick count. If the reschedule tick count is 0, this is a one-shot timer and the timer will not go off again. If the
reschedule tick count is non-zero, the timer will be reloaded with the reschedule tick count and expire periodically.
The timer expiration characteristics are specified in terms of system timer ticks. However, use the time-to-timer-tick
conversion functions provided by OSF as the underlying system timer resolution may change.
You must manage the memory yourself for timer control structures and for timer creation and deletion.
Note that if you want to restart a one-shot timer, you must perform the following sequence:
1. Stop the timer using osf_tmr_stop().
1. Refresh the timer period through osf_tmr_period_change().
2. Restart the timer again using osf_tmr_start().

6.7.1 External Interface

The OSF supports the following timer functions:
Table 6-11. Timer Functions

Function Description

osf_tmr_create Creates an application timer.

Osf_tmr_delete Deletes an application timer.

Osf_tmr_start Starts a previously created application timer.

Osf_tmr_stop Stops a previously created application timer.

Osf_tmr_period_change Changes the expiration characteristics of a previously created and stopped timer.

Osf_tmr_period_get Gets the expiration characteristics of a previously created timer.

Osf_time_ticks_get Gets the current system time.

Osf_time_diff Calculates the time difference between the two input times. Can handle one
wrap-around between the two times.

Osf_time_ms_to_ticks Converts the input time in milliseconds to the equivalent number of system timer
ticks

osf_time_ticks_to_ms Converts the input system timer ticks to the equivalent time in milliseconds.

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...........continued
Function Description

Osf_time_s_to_ticks Converts the input time in seconds to the equivalent number of 64-bit system
timer ticks

osf_time_ticks_to_s Converts the input 64-bit system timer ticks to the equivalent time in seconds.

6.7.1.1 osf_tmr_create
To create an application timer, allocate a timer control structure, osf_tmr_struct, and pass a pointer to it to
osf_tmr_create(). The timer is in non-active state after creation. User must call osf_tmr_start() to start the
timer.
Note that the initial timer expiry will be (initial_ticks - 1) to (initial_ticks) from the current time. This
is because the next timer expiry will be (initial_ticks) away from the current time but we may be (0) to
(one system timer period) away from the next timer tick. If the initial expiry must be at least N timer ticks away,
initial_ticks should be N+1. E. g. use
osf_time_ms_to_ticks(required time in ms) + 1
instead of
osf_time_ms_to_ticks(required time in ms)
to ensure that the initial timer expiry will be at least (required time in ms) away.

Prototype void osf_tmr_create(

osf_tmr_struct *tmr_ptr,
CHAR *name_ptr,
void (*expiration_function)(UINT32),
UINT32 expiration_input,
UINT32 initial_ticks,
UINT32 reschedule_ticks)

Inputs *tmr_ptr (Pointer to) application timer

*name_ptr (Pointer to) timer name string

*expiration_ (Pointer to) expiration function

function

expiration_ input Expiration input

initial_ ticks Time to first expiry

reschedule_ ticks Option to reload after first expiry

Outputs None

Returns Success = None

Failure = Assert and never return

Returns Success = None

Failure = None

Side Effects None

6.7.1.5 osf_tmr_period_change
Once a timer is created, only the timeout period can be changed. If you want to change a timer expiry function, you
must delete the timer, and create a new one with the new timer expiry function.

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Note that the initial timer expiry will be (initial_ticks - 1) to (initial_ticks) from the current time. This is
because the next timer expiry will be (initial_ticks) from the current time but we may be (0) to (one system
timer period) away from the next timer tick. If the initial expiry must be at least N timer ticks away, initial_ticks
should be N+1. For example, use
osf_time_ms_to_ticks(required time in ms) + 1
instead of
osf_time_ms_to_ticks(required time in ms)
to ensure that the initial timer expiry will be at least (required time in ms) away.

Prototype void osf_tmr_period_change(

osf_tmr_struct *tmr_ptr,
UINT32 initial_ticks,
UINT32 reschedule_ticks)

Inputs *tmr_ptr (Pointer to) application timer

initial_ticks Time to first expiry

reschedule_ ticks Option to reload after first expiry

Outputs None

Returns Success = None

Failure = None

Side Effects None

6.7.1.6 osf_time_period_get

Prototype UINT32 osf_tmr_period_get(

osf_tmr_struct *tmr_ptr)

Inputs *tmr_ptr (Pointer to) application timer

Outputs None

Returns Success = Reschedule expiration period

Failure =

Side Effects None

6.7.1.7 osf_time_ticks_get
The osf_time_ticks_get() function returns the current system tick count.

Prototype UINT32 osf_time_ticks_get(void)

Inputs None

Outputs None

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Returns Success = Number of timer ticks since reset

Failure =

Side Effects None

6.7.1.8 osf_time_diff
Use osf_time_diff()to calculate the time difference between the two 32-bit input times. It can handle one wrap-
around between the two times but cannot differentiate between multiple wrap-arounds and a single wrap-around.

Prototype UINT32 osf_time_diff(

UINT32 time1,
UINT32 time2)

6.7.2 Data Structures

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6.7.2.1 osf_tmr_struct
You must allocate a timer control structure, osf_tmr_struct, to create a timer. The structure is used by OSF
internally.

/***************************************************************
* STRUCTURE: osf_tmr_struct
* OSF timer structure.
*
* ELEMENTS:
* tmr_obj - ThreadX timer structure
* tmr_id - Timer ID, assigned by OSF at creation.
*
***************************************************************/
typedef struc
{
osf_tmr_obj_struct tmr_obj;
UINT16 tmr_id;
} osf_tmr_struct;

6.7.3 System Hardware Timer Operation

OSF uses the SI_TimerInt output signal provided by the MIPS 34Kc hardware timer (based on Count and Compare
registers). When the Count register value matches the Compare register value, the SI_TimerInt signal is triggered.
The SI_TimerInt signal is fed back to the MIPS 34Kc, which in turn executes the system timer interrupt service
routine (ISR). The Count register is left free-running after being reset in osf_sys_init().
If the system is blocked (interrupts disabled) less than a system timer period, the system timer ISR reloads the
Compare register by incrementing the Compare register by one timer period (T). There is therefore no clock slippage
in the system in the sense that the system timer interrupts are always T apart, if the system blockage is always
less than a system timer period. The system timer ISR may be invoked with variable delays after the system timer
interrupts due to the system being blocked for variable duration with different system loading levels, but the variable
delays are always less than T.
In the exception cases, when the system is blocked for a system timer period or longer, the system timer ISR reloads
the Compare register with the current Count register value plus T. This results in slippage in the system clock. The
slip duration is:
(Current Count register value) - (Compare register value for timer interrupt being
serviced) - T
A diagnostic counter is incremented to denote the clock slippage.
Configure the system timer period by calling osf_sys_init() (desired_tmr_period_ms in osf_cfg_struct).
Choose a value for the system timer period that is greater than the maximum system blockage duration in normal
operations. In exception cases, such as firmware downloads and flash memory sector erase when the system will be
blocked longer than a system timer period, and clock slippage will result.

6.8 Semaphores
OSF provides 32-bit counting semaphores including the ability to create, delete, put and get the semaphores.
The semaphore functions are mainly wrappers of the ThreadX semaphores except that getting semaphores with
non-blocking calls and putting semaphores are not expected to fail.
Threads suspended on a semaphore are resumed in FIFO order.
You must manage the memory for the semaphore control structures yourself.

6.8.1 External Interface

The OSF supports the following semaphore functions:

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Table 6-12. Semaphore Functions

Function Description

osf_sem_create Creates a counting semaphore

osf_sem_delete Deletes a counting semaphore

osf_sem_get Gets an instance of the counting semaphore

osf_sem_put Puts an instance of the counting semaphore

osf_sem_count_get Gets the current semaphore count

6.8.1.1 osf_sem_create
To create a counting semaphore, allocate a semaphore control structure, osf_sem_struct, and pass a pointer
to it to osf_sem_create(). You can then get and put the semaphore using the osf_sem_get() and
osf_sem_put() functions.

Prototype void osf_sem_create(

osf_sem_struct *sem_ptr,
CHAR *name_ptr,
UINT32 initial_count)

Inputs *sem_ptr (Pointer to) semaphore

*name_ptr (Pointer to) semaphore name

Initial_count Initial count for semaphore.

Valid range: [0xFFFFFFFFUL]

Outputs None

Returns Success = None

Failure = Assert and never return

Side Effects None

6.8.1.2 osf_sem_delete

Prototype void osf_sem_delete(

osf_sem_struct *sem_ptr)

Inputs *sem_ptr (Pointer to) pre-allocated semaphore

Outputs None

Returns Success = None

Failure = Assert and never return

Side Effects None

6.8.1.3 osf_sem_get
A timeout value is specified for getting semaphores. Valid timeout values are:
• OSF_WAIT_NONE: Get semaphore and return right away.

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• OSF_WAIT_FOREVER: Wait until an instance of the semaphore is available. Thread is suspended while waiting.
• Finite value: Wait until an instance of the semaphore is available, or the finite timeout period expires. Thread is
suspended while waiting. Valid timeout period is from OSF_WAIT_MIN to OSF_WAIT_MAX timer ticks.

Prototype PMCFW_ERROR osf_sem_get(

osf_sem_struct *sem_ptr,
UINT32 wait_option)

Inputs *sem_ptr (Pointer to) pre-allocated semaphore

wait_option Timeout option

Outputs None

Returns Success = PMC_SUCCESS

Failure = OSF_ERR_TIMEOUT

Side Effects None

6.8.1.4 osf_sem_put

Prototype void osf_sem_put(

osf_sem_struct *sem_ptr)

Inputs *sem_ptr (Pointer to) pre-allocated semaphore

Outputs None

Returns Success = None

Failure = Assert and never return

Side Effects None

6.8.1.5 osf_sem_count_get

Prototype UINT32 osf_sem_count_get(

osf_sem_struct *sem_ptr)

Inputs *sem_ptr (Pointer to) pre-allocated semaphore

Outputs None

Returns Success = Current count of this semaphore.

Failure = Assert and never return

Side Effects None

6.8.2 Data Structures

6.8.2.1 osf_sem_struct
You must allocate a semaphore control structure, osf_sem_struct, to create a semaphore. The structure is used
by OSF internally.

/***************************************************************
* STRUCTURE: osf_sem_struct
* OSF semaphore structure.
*

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* ELEMENTS:
* sem_obj - ThreadX semaphore structure
* sem_id - Semaphore ID, assigned by OSF at creation.
*
***************************************************************/
typedef struct{
osf_sem_obj_struct sem_obj;
UINT16 sem_id;
} osf_sem_struct;

6.9 Mutexes
OSF provides the ability to create, delete, put and get mutexes. The mutex functions are mainly wrappers of the
ThreadX mutexes except that getting mutexes with non-blocking calls and putting mutexes are not expected to fail.
OSF mutexes support priority inheritance provided by ThreadX to avoid potential priority inversion. A lower-priority
thread A that owns a mutex will have its priority temporarily raised to that of a higher-priority thread B that wants this
mutex. The priority of thread A will be reverted to the lower priority once thread A releases the mutex.
Threads suspended on a mutex will be resumed by priority resumption. This means the highest priority thread will be
resumed first, and the remaining threads will be resumed in FIFO order.
You must manage the memory for the mutex control structures yourself.

6.9.1 External Interface

The OSF supports the following mutex functions:
Table 6-13. Mutex Functions

Function Description

osf_mtx_create Creates a mutex

osf_mtx_delete Deletes a mutex

osf_mtx_get Obtains exclusive ownership of a mutex

osf_mtx_put Releases ownership of a mutex

6.9.1.1 osf_mtx_create
To create a counting mutex, allocate a mutex control structure, osf_mtx_struct, and pass a pointer to it to
osf_mtx_create(). Use the osf_mtx_get() and osf_mtx_put() functions to get and put the mutex.

Prototype void osf_mtx_create(

osf_mtx_struct *mtx_ptr,
CHAR *name_ptr)

Inputs *mtx_ptr (Pointer to) pre-allocated mutex

*name_ptr (Pointer to) mutex name

Outputs None

Returns Success = None

Failure = Assert and never return

Side Effects None

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6.9.1.2 osf_mtx_delete

Prototype void osf_mtx_delete(

osf_sem_struct *mtx_ptr)

Inputs *mtx_ptr (Pointer to) pre-allocated mutex

Outputs None

Returns Success = None

Failure = Assert and never return

Side Effects None

6.9.1.3 osf_mtx_get
A timeout value is specified for getting mutexes. Valid timeout values are:
• OSF_WAIT_NONE: Get mutex and return right away. Abort if mutex get fails with this non-blocking option.
• OSF_WAIT_FOREVER: Wait until an instance of the mutex is available. Thread is suspended while waiting.
• Finite value: Wait until an instance of the mutex is available, or the finite timeout period expires. Thread is
suspended while waiting. Valid timeout period is from OSF_WAIT_MIN to OSF_WAIT_MAX timer ticks.

Prototype PMCFW_ERROR osf_mtx_get(

osf_mtx_struct *mtx_ptr,
UINT32 wait_option)

Inputs *mtx_ptr (Pointer to) previously-created mutex

wait_option Timeout option

Outputs None

Returns Success = PMC_SUCCESS

Failure = OSF_ERR_TIMEOUT
Assert and never return if wait_option = OSF_WAIT_NONE.

Side Effects None

6.9.1.4 osf_mtx_put

Prototype void osf_mtx_put(

osf_mtx_struct *mtx_ptr)

Inputs *mtx_ptr (Pointer to) previously-created mutex

Outputs None

Returns Success = None

Failure = Assert and never return

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Side Effects None

6.9.2 Data Structures

You must allocate a mutex control structure, osf_mtx_struct, to create a mutex. The structure is used by OSF
internally.

/********************************************************************
* STRUCTURE: osf_mtx_struct
* OSF mutex structure.
*
* ELEMENTS:
* mtx_obj - ThreadX mutex structure
* mtx_id - Mutex ID, assigned by OSF at creation.
*
*********************************************************************/
typedef struct
{
osf_mtx_obj_struct mtx_obj;
UINT16 mtx_id;
} osf_mtx_struct;

6.10 Interrupt Control Framework

MIPS34Kc core works in External Interrupt Controller (EIC) Interrupt mode with the MBIC interrupt controller which
manages up to 120 external interrupt sources and up to 32 NMI sources. The SXP 12G uses a single-level interrupt
dispatcher that dispatches all interrupts including those from the MIPS34kc core.
Figure 6-6. EIC Interrupt Mode

6.10.1 External Interrupt Sources

The SXP 12G uses an integrated interrupt controller inside the MBIC for interrupt processing. The interrupt controller
evaluates interrupt requests from various sources and generates an interrupt vector to the 34Kc processor.
The interrupt controller in the SXP 12G manages 120 external interrupt sources that are arranged in groups of 8 for
mapping to 15 interrupt vectors. See the external interrupt connectivity detail in the following table.
Table 6-14. SXP 12G External Interrupt Sources

SI_INT[5:0] Vector EXT_INT EXT_INT connectivity

Val

1 EXT_INT [ 7: 0] EXT_INT [ 7: 0 ] = MBIC Interrupts [15:8]

2 EXT_INT [ 15 : 8 ] EXT_INT [ 15: 8 ] = MBIC Interrupts [7:0]

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...........continued
SI_INT[5:0] Vector EXT_INT EXT_INT connectivity
Val

3 EXT_INT [ 23 : 16 ] EXT_INT [ 17: 16 ] = {Reserved, PACK1_INT}

4 EXT_INT [ 31 : 24 ] EXT_INT [ 25: 24 ] = {Reserved, PACK1_INT}

5 EXT_INT [ 39 : 32 ] EXT_INT [ 39: 32 ] = { SSS_ECC_ERR_INT[2:0],

SSS_INT[2:0], TXRX1, TXRX0}

6 EXT_INT [ 47 : 40 ] EXT_INT [ 42: 40 ] = {SSPL2, SSPL1, SSPL0}

7 EXT_INT [ 55 : 48 ] EXT_INT [ 50: 48 ] = {SXL2, SXL1, SXL0}

8 EXT_INT [ 63 : 56 ] EXT_INT [ 62: 56 ] = {EPOW_INT, FWS_INT[1:0],

EMIP_ECC_ERR_INT[1:0], EMIP1, EMIP0}

9 EXT_INT [ 71 : 64 ] EXT_INT [ 67: 64 ] = TIMER_INT[3:0]

10 EXT_INT [ 79 : 72 ] EXT_INT [ 73: 72 ] = {TWI_FUNC,TWI_SRSTB}

11 EXT_INT [ 87 : 80 ] EXT_INT [ 83: 80 ] = { MAC_INT, ~INTIB[2:0]}

12 EXT_INT [ 95 : 88 ] EXT_INT [ 91: 88 ] = SGPIO_INT[3:0]

13 EXT_INT [103 : 96 ] EXT_INT [101: 96 ] = {GPIO_INT1, GPIO_INT0,

UART_INT[3:0]}

14 EXT_INT [111 :104 ] EXT_INT [109: 104] = {ECMR_INT, SLICE1, SLICE0, CSU2,
CSU1, CSU0}

15 EXT_INT [119 :112 ] EXT_INT [116: 112] = {MBIC_INT2, MBIC_INT0,

CORR_ECC_INT, Reserved, PACK1_ECC_INT}

6.10.2 SXP 12G Enabled Interrupt

The SXP 12G SDK enables the interrupts in the following table .
Note: pwrmgr_wos_isr is only installed in the WOS sleep mode.
Table 6-15. SXP 12G Enabled Interrupt

Interrupt Source Description INT ID Interrupt Service Routine

PROC_TIMER_VPE0 For OSF Timer 0 osf_tmr_isr

PACK1 For various kinds of PACK event 24 sas_pack_isr

SSS_ECC_ERR_INT0 For SSSF ECC 37 emip_gen_sssf_ecc_int_isr

SSS_ECC_ERR_INT1 For SSSF ECC 38 emip_gen_sssf_ecc_int_isr

SSS_ECC_ERR_INT2 For SSSF ECC 39 emip_gen_sssf_ecc_int_isr

SSPL0 For WOS (COMINIT, COMWAKE) 40 pwrmgr_wos_isr

SSPL1 For WOS (COMINIT, COMWAKE) 41 pwrmgr_wos_isr

SSPL2 For WOS (COMINIT, COMWAKE) 42 pwrmgr_wos_isr

SXL0 For SXL ECC 48 sxl_isr

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Interrupt Source Description INT ID Interrupt Service Routine

SXL1 For SXL ECC 49 sxl_isr

SXL2 For SXL ECC 50 sxl_isr

EMIP0 For EMIP SINT 56 emip_gen_sint_int_isr

EMIP1 For EMIP SINT 57 emip_gen_sint_int_isr

EMIP_ECC_ERR0 For EMIP Error 58 emip_gen_err_int_isr

EMIP_ECC_ERR1 For EMIP Error 59 emip_gen_err_int_isr

FWS0 For FWS Fatal Error 60 emip_fws_fatal_err_int_isr

APP_TIMER0 For App Timer-0 64 app_timer_isr

APP_TIMER1 For APP Timer-1 65 app_timer_isr

APP_TIMER2 For APP Timer-2 66 app_timer_isr

TWI For TWI 0~11 72 twiss_isr

TWI_SRSTB For Slave reset of TWI 0~11 73 twiss_rst_isr

INTIB0 For cable management 80 portmgr_conn_isr

MAC For Ethernet (PM805x devices only) 83 MAC_C_IRQ_Handler

SGPIO0 For SGPIO0 88 sgpio_isr

UART0 For cmdsvr. 96 cmdsvr_uart_isr

GPIO0 For GPIO interrupt. 100 gpio_isr

GPIO1 For GPIO interrupt. 101 gpio_isr

CSU0 For CSU0 (LOCK_LOSS) 104 sas_analog_csu_isr

CSU1 For CSU1 (LOCK_LOSS) 105 sas_analog_csu_isr

CSU2 For CSU2 (LOCK_LOSS) 106 sas_analog_csu_isr

ECMR For various kinds of ECMR Errors. 109 ecmr_isr

PACK1_ECC For PACK ECC error. 112 pack_ecc_isr

6.10.3 External Interface

The OSF supports the following interrupt control functions:
Table 6-16. Interrupt Control Functions

Function Description

osf_int_global_enable Enables all 34 Kc interrupts.

osf_int_global_disable Disables all 34 Kc interrupts

osf_int_global_restore Restores the interrupt enable bit (IE) status to the corresponding bit value of the input.
Use with osf_int_global_disable() to create a critical section.

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6.10.3.1 osf_int_global_enable
osf_int_global_enable() performs atomic writes to the Status(IE) bit to enable all 34Kc core interrupts.

Prototype UINT32 osf_int_global_enable(void)

Inputs None

Outputs None

Returns Original Status register value

Side Effects None

6.10.3.2 osf_int_global_disable
osf_int_global_disable()performs atomic writes to the Status(IE) bit to disable all 34Kc core interrupts.
Notice that the system clock will slip if the system is blocked for longer than a system timer period. See Section
6.7.3 System Hardware Timer Operation for detail.

Prototype UINT32 osf_int_global_disable(void)

Inputs None

Outputs None

Returns Original Status register value

Side Effects None

6.10.3.3 osf_int_global_restore
osf_int_global_restore() performs atomic writes to the Status(IE) bit to enable or disable all 34Kc core
interrupts based on the input value.
Note
If you use osf_int_global_disable() and osf_int_global_restore()to create a critical section, DO NOT
make any OS calls within the critical section.

Prototype UINT32 osf_int_global_restore(

UINT32 ie_bit_val)

Inputs ie_bit_val Input value

Outputs None

Returns Original Status register value

Side Effects None

6.11 MBIC Interrupt Controller Framework

CICINT APIs provide the following functionality:

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Operating System Functions

• Initialize the MBIC Interrupt Controller

• Register interrupt handler for each external interrupt
• Assign the interrupt priority for each interrupt vector
• Dispatch interrupt – When the MIPS 34kc core receives an interrupt it will call each external interrupt handler

6.11.1 External Interrupt Controller API

Table 6-17. External Interrupt API Changes

Function in SXP 12G MBIC/CICINT Notes

void cicint_init(void)

void cicint_int_set( CICINT register callback on EXT_INT [119:0].

UINT8 int_num, cicint_int_callback_fcn_ptr isr_ptr)

void cicint_vec_priority_set(cicint_vec_num_enum 16 hardware priority levels

vec_num, cicint_vec_prio_enum priority_level)

void cicint_int_disable(UINT8 int_num) Disables interrupt with interrupt number int_num.

void cicint_int_enable(UINT8 int_num) Enables interrupt with interrupt number int_num

void cicint_sw_int_set(UINT8 int_num) Triggers the specified interrupt by software

void cicint_sw_int_clear(UINT8 int_num) Clears the specified interrupt that was set by software.

interrupt_handler All interrupts are connected to the MBIC and the

dispatcher is implemented in the CICINT module.

6.11.2 SXP 12G CICINT Interrupt APIs

6.11.2.1 cicint_int_set
This function provides a mechanism for application-level code to register an interrupt service routine (ISR) to handle
one of the 120 possible interrupt sources (EXT_INT [0~119]).

Prototype void cicint_int_set(UINT8 int_num,

cicint_int_callback_fcn_ptr isr_ptr)

Inputs int_num Interrupt number within EXT_INT

isr_ptr Interrupt handler

Outputs None

Returns None

Side Effects None

6.11.2.2 cicint_int_enable
This function enables the given interrupt in the CIC.

Prototype void cicint_int_enable(UINT8 int_num)

Inputs int_num Interrupt number within EXT_INT

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Outputs None

Returns None

Side Effects None

6.11.2.3 cicint_int_disable
This function disables the given interrupt in the CIC. It does not remove the previously installed interrupt handler, if
one was installed.

Prototype void cicint_int_disable(UINT8 int_num)

Inputs int_num Interrupt number within EXT_INT

Outputs None

Returns None

Side Effects None

6.11.2.4 cicint_vec_priority_set
This function provides a mechanism for application-level code to change the default priority level assigned to any one
of the 15 interrupt vectors. One interrupt vector is the summary of 8 number of external interrupt (EXT_INT).

Prototype void cicint_vec_priority_set(

cicint_vec_num_enum vec_num,
cicint_vec_prio_enum priority_level)

Inputs vec_num The interrupt vector number’s priority level to be modified.

priority_level The priority level to assign to the given interrupt vector.

Outputs None

Returns None

Side Effects None

6.11.2.5 cicint_int_status_get
For a given vector number, this function returns its corresponding interrupt status.

Prototype BOOL cicint_int_status_get(UINT8 int_num)

Inputs int_num Interrupt number within EXT_INT.

Outputs None

Returns TRUE If interrupt is pending.

FALSE If interrupt is not pending.

Side Effects None

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Device Drivers

7. Device Drivers
The device drivers provide basic functions for controlling external peripherals. The driver APIs described in this
section are fully tested by Microchip. Use them as-is in your custom code development. Software described in this
section as “examples” may require rework before they can be integrated into your application. The PM73206_04
firmware release provides drivers for:
• FLASH
• TWI
• UART
• GPIO/SGPIO
• Ethernet
• RTC
• Hardware Application Timer
• SPI
This package contains no dedicated GPIO port. Several functional pins are overloaded with GPIO functionality and
can be used in primary function mode or in GPIO mode through firmware control.
Table 7-1. Function-Multiplex Mapping of Peripheral Pins

GPIO Main Function Description Default

Port ID

0 TWI0 GPIO_Instance_0 _Port A ; TWI_SCL[0] Main function

1 TWI0 GPIO_Instance_0 _Port A ; TWI_SDA[0] Main function

2 TWI0 GPIO_Instance_0 _Port A ; TWI_SRSTB[0] Main function

3 TWI1 GPIO_Instance_0 _Port B ; TWI_SCL[1] Main function

4 TWI1 GPIO_Instance_0 _Port B ; TWI_SDA[1] Main function

5 TWI1 GPIO_Instance_0 _Port B ; TWI_SRSTB[1] Main function

6 TWI2 GPIO_Instance_0 _Port C ; TWI_SCL[2] Main function

7 TWI2 GPIO_Instance_0 _Port C ; TWI_SDA[2] Main function

8 TWI2 GPIO_Instance_0 _Port C ; TWI_SRSTB[2] Main function

9 TWI3 GPIO_Instance_0 _Port D ; TWI_SCL[3] Main function

10 TWI3 GPIO_Instance_0 _Port D ; TWI_SDA[3] Main function

11 TWI3 GPIO_Instance_0 _Port D ; TWI_SRSTB[3] Main function

12 TWI4 GPIO_Instance_1 _Port A ; TWI_SCL[4] Main function

13 TWI4 GPIO_Instance_1 _Port A ; TWI_SDA[4] Main function

14 TWI4 GPIO_Instance_1 _Port A ; TWI_SRSTB[4] Main function

15 TWI5 GPIO_Instance_1 _Port B ; TWI_SCL[5] Main function

16 TWI5 GPIO_Instance_1 _Port B ; TWI_SDA[5] Main function

17 TWI5 GPIO_Instance_1 _Port B ; TWI_SRSTB[5] Main function

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...........continued
GPIO Main Function Description Default
Port ID

18 TWI6 GPIO_Instance_1 _Port C ; TWI_SCL[6] Main function

19 TWI6 GPIO_Instance_1 _Port C ; TWI_SDA[6] Main function

20 TWI6 GPIO_Instance_1 _Port C ; TWI_SRSTB[6] Main function

21 TWI7 GPIO_Instance_1 _Port D ; TWI_SCL[7] Main function

22 TWI7 GPIO_Instance_1 _Port D ; TWI_SDA[7] Main function

23 TWI7 GPIO_Instance_1 _Port D ; TWI_SRSTB[7] Main function

24 TWI8/SGPIO0 GPIO_Instance_2_Port A ; SCLOCK[0] / SGPIO

TWI_SCL[8]

25 TWI8/SGPIO0 GPIO_Instance_2_Port A ; SLOAD[0] / SGPIO

TWI_SDA[8]

26 TWI8/SGPIO0 GPIO_Instance_2_Port A ; SDOUT[0] / SGPIO

TWI_SRSTB[8]

27 TWI8/SGPIO0 GPIO_Instance_2_Port A ; SDIN[0] / NA SGPIO

28 TWI9/SGPIO1 GPIO_Instance_2_Port B ; SCLOCK[1] / SGPIO

TWI_SCL[9]

29 TWI9/SGPIO1 GPIO_Instance_2_Port B ; SLOAD[1] / SGPIO

TWI_SDA[9]

30 TWI9/SGPIO1 GPIO_Instance_2_Port B ; SDOUT[1] / SGPIO

TWI_SRSTB[9]

31 TWI9/SGPIO1 GPIO_Instance_2_Port B ; SDIN[1] / NA SGPIO

32 TWI10/SGPIO2 GPIO_Instance_2_Port C ; SCLOCK[2] / SGPIO

TWI_SCL[10]

33 TWI10/SGPIO2 GPIO_Instance_2_Port C ; SLOAD[2] / SGPIO

TWI_SDA[10]

34 TWI10/SGPIO2 GPIO_Instance_2_Port C ; SDOUT[2] / SGPIO

TWI_SRSTB[10]

35 TWI10/SGPIO2 GPIO_Instance_2_Port C ; SDIN[2] / NA SGPIO

36 TWI11/SGPIO3 GPIO_Instance_2_Port D ; SCLOCK[3] / SGPIO

TWI_SCL[11]

37 TWI11/SGPIO3 GPIO_Instance_2_Port D ; SLOAD[3] / SGPIO

TWI_SDA[11]

38 TWI11/SGPIO3 GPIO_Instance_2_Port D ; SDOUT[3] / SGPIO

TWI_SRSTB[11]

39 TWI11/SGPIO3 GPIO_Instance_2_Port D ; SDIN[3] / NA SGPIO

40 UART3 GPIO_Instance_3_Port A ; USOUT[3] [1] GPIO

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...........continued
GPIO Main Function Description Default
Port ID

41 UART3 GPIO_Instance_3_Port A ; URTSB[3] [1] / GPIO

SPI2_D2

42 UART3 GPIO_Instance_3_Port A ; USIN[3] [1] GPIO

43 UART3 GPIO_Instance_3_Port A ; UCTSB[3] [1] [2] / GPIO

SPI2_D3

44 MAC/RMIIB GPIO_Instance_3_Port B ; txd[2] Main function

45 MAC/RMIIB GPIO_Instance_3_Port B ; txd[3] Main function

46 MAC/RMIIB GPIO_Instance_3_Port B ; txer Main function

47 MAC/RMIIB GPIO_Instance_3_Port B ; rxd[2] Main function

48 MAC/RMIIB GPIO_Instance_3_Port B ; rxd[3] Main function

49 MAC/RMIIB GPIO_Instance_3_Port B ; col Main function

50 MAC/RMIIB GPIO_Instance_3_Port B ; crs Main function

51 MAC/RMIIB GPIO_Instance_3_Port C ; txd[0] Main function

52 MAC/RMIIB GPIO_Instance_3_Port C ; txd[1] Main function

53 MAC/RMIIB GPIO_Instance_3_Port C ; rxd[0] Main function

54 MAC/RMIIB GPIO_Instance_3_Port C ; rxd[1] Main function

55 MAC/RMIIB GPIO_Instance_3_Port C ; rx_er Main function

56 MAC/RMIIB GPIO_Instance_3_Port D ; mdio Main function

57 MAC/RMIIB GPIO_Instance_3_Port D ; mdc Main function

58 MAC/RMIIB GPIO_Instance_3_Port D ; tx_en Main function

59 MAC/RMIIB GPIO_Instance_3_Port D ; rx_dv Main function

60 MAC/RMIIB GPIO_Instance_3_Port D ; link Main function

61 MAC/RMIIB GPIO_Instance_3_Port D ; tx_clk_mii Main function

62 MAC/RMIIB GPIO_Instance_3_Port D ; rx_clk_mii Main function

63 UART2 GPIO_Instance_4_Port A ; USOUT[2] [1] / GPIO

SPI2_D0

64 UART2 GPIO_Instance_4_Port A ; URTSB[2] [1] / GPIO

SPI2_D1

65 UART2 GPIO_Instance_4_Port A ; USIN[2] [1] / SPI2_CEB GPIO

66 UART2 GPIO_Instance_4_Port A ; UCTSB[2] [1] / GPIO

SPI2_CLK

67 UART1 GPIO_Instance_4_Port B ; USOUT[1] Main function

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...........continued
GPIO Main Function Description Default
Port ID

68 UART1 GPIO_Instance_4_Port B ; URTSB[1] Main function

69 UART1 GPIO_Instance_4_Port B ; USIN[1] Main function

70 UART1 GPIO_Instance_4_Port B ; UCTSB[1] Main function

71 UART0 GPIO_Instance_4_Port C ; USOUT[0] Main function

72 UART0 GPIO_Instance_4_Port C ; URTSB[0] Main function

73 UART0 GPIO_Instance_4_Port C ; USIN[0] Main function

74 UART0 GPIO_Instance_4_Port C ; UCTSB[0] Main function

75 SPI GPIO_Instance_4_Port D ; SPI_D[0] Main function

76 SPI GPIO_Instance_4_Port D ; SPI_D[1] Main function

77 SPI GPIO_Instance_4_Port D ; SPI_D[2] Main function

78 SPI GPIO_Instance_4_Port D ; SPI_D[3] Main function

79 SPI GPIO_Instance_4_Port D ; SPI_CLK Main function

80 SPI GPIO_Instance_4_Port D ; SPI_CEB Main function

NOTES:
• GPIO Pins 40-43 (muxed with UART3) and 63-66 (muxed with UART2) support GPIO Interrupt mode. Each
group (GPIO Pins 40-43 or GPIO Pins 63-66) of the GPIO interrupt inputs is consolidated into a single interrupt
line connected to the MBIC interrupt controller.
• GPIO Pin 43 (UCTSB[3]) can be configured as AC_GOOD_L signal input when the pin is configured as a GPIO
input and EPOW feature is enabled by setting EPOW_EN bit in EPOW Control Register 0 to the logical one.
• On PM804x devices, GPIO Pins 44-62 (muxed with MAC) are removed, and GPIO APIs will return errors when
accessing GPIO pins 44-62.
These drivers are described in detail in the following sections.

7.1 Flash
The flash driver erases and programs flash memory. The parallel flash driver supports AMD Standard and Intel
Standard CFI command sets. The flash driver defaults to the AMD Standard command set if the flash device does
not support CFI. The SPI flash driver supports Numonyx SPI flash used in the Evaluation Kit.
The firmware download handler (FWDL) controls the piece-wise download of data to the flash in the firmware update
mechanism. It also:
• parses the firmware image header
• calls FLM APIs to erase partitions, to write partition and to compute CRC, write CRC, and image lengths to the
end of a partition.
The Flash Module (FLM) performs initialization, erasing and writing. The FLM only provides write and erase
interfaces since reading from the flash does not require a special sequence. Each function is blocking and does
not return until the operation is complete, or an error has occurred. Any code that requires the flash to be in a state
that is not directly readable is put into a critical section; specifically, initialization, sector-erase and word-write. The
time elapsed within each critical section depends on the specific flash device. In the case of writes, the FLM puts
each word write within a critical section; in this case the priority of the calling thread should be considered if large

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writes are expected. Configure the watchdog timer to accommodate sector-erase time as this is typically much longer
than a word-write time.
The FLM data structure is private to the module and supports a single flash device and a single user of the FLM
module. During initialization, writes, and erases of the flash, ensure that no other threads access the flash and that
no code is run from the flash since unexpected results may occur. If an unexpected result occurs FLM attempts to
recover by resetting the flash memory using its reset sequence and by performing a hardware reset if provided by the
user.
The FLM data structure stores a copy of the partition map as set by the user. The partitions must contain an integer
number of flash sectors. The partition map is defined in the linker command file and its values are passed to FLM
through global variables. The variable names in the linker command file must match those found in flm_device_data.
c. Similarly, these variables and their order must match the partition IDs described by flm_partition_enum. Access
to the flash is restricted to these partitions. The partitions may be write protected by setting the read-only flag of
the partition. By default, they are all writable. Ensure that write protection is enabled in one of the EMA initialization
routines. The Bootloader and the Application Code use two different instantiations of FLM. The Bootloader cannot be
relied upon to set the write protection for the flash partitions.
If a non-CFI parallel flash memory part is being used, the initialization code cannot access the flash sector
information from the device itself. In this case, the parallel flash driver searches through a list of explicitly supported
devices. If it finds one that matches the device, it uses it. Otherwise, it uses a default sector map. This map
consists of 256 x 4096-byte sectors. If very large partitions are set in the linker command file, the erase time will
be extremely long since each sector may be erased multiple times. For example, a 64 Kbytes sector would be
erased 16 times rather than once. The solution is to add the device to the supported devices list. This requires
adding a device data file flm_xxx_data. c and then adding the device to the declarations in flm_loc. h and the
flm_supported_flash_devices_array in flm_device_data. h. Any build and linker files will also need to be updated. A
new file is also required if the flash used is larger than one Mbyte.
Since the FLM module will set the flash into an unreadable state during programming, the FLM code must reside in
RAM, rather than on the flash itself.
Table 7-2. Flash Driver Requirements

Requirement Supported Comments

Support multiple flash Yes Existing code supports programming/updating multiple partitions
partitions in the flash device.

Support AMD and Intel CFI Yes Supports AMD Standard and Intel Standard CFI command sets.
flash AMD Spansion S29GL128 Flash is used in Microchip Evaluation
kit

Support SPI Numonyx flash Yes Numonyx N25Q128 SPI flash is used in the Microchip Evaluation
Kit

Support Winbond SPI flash Yes Supports Winbond W25Q128FW and W25Q32DW parts.

Optional ECC support Yes Supports inline ECC for parallel flash. ECC enabling requires the
support of the Flash Buffer Program command.

Erase Flash Partitions Yes Partition erase currently supported. Flash is allocated in
partitions that can each be erased as a whole (partial partition
erasure is not supported).

Flash download Yes The flash driver operates on buffers supplied through the host-to-
SXP communications path (using SES or other frame formats).

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...........continued
Requirement Supported Comments

EMA execution environment Partial Active flash partitions should only be erased and programmed
(critical regions, interrupts, by the Boot Kernel. EMA flash operations should only write
watchdogs) to the scratch partitions of the flash, and only require small
critical regions around the flash word programming sequence.
Exceptions that occur during flash critical regions must not
access flash for instructions or data (For example, exception
code must be locked in cache or be running from SRAM.).

The following table shows the timing settings for the FLM flash programming/erase operations.
Table 7-3. Timing Settings for Flash Module

Timeout Macro Default Interface Comments

for

Program FLM_PROGRAM_TIMEOUT_US 1000 µs Non-CFI For CFI parallel flash, the

parallel and timing is retrieved from CFI.
SPI

Write FLM_WRITE_BUFFER_TIMEOUT_US 2000 µs Non-CFI For CFI parallel flash, the

buffer parallel and timing is retrieved from CFI.
SPI

Erase FLM_SECTOR_ERASE_POLL_PERIOD 1000 µs Non-CFI Timeout for sector erase is

_US and and 7000 parallel and set to 7 seconds. For CFI
retry times SPI parallel flash, the timing is
FLM_SECTOR_ERASE_POLL_MAX_RE
retrieved from CFI.
TRIES

Erase to FLM_ERASE_SUSPEND_DURATION_U 50 µs CFI, non-CFI This is the Erase to

suspend S Suspend Latency time and
is device specific for CFI
and non-CFI flash. For CFI
flash and non-CFI flash,
it comes from the device
data sheet and needs to
be defined to meet the
device's requirement. For
SPI flash, firmware sends
the command RFSR (Read
Flag Status Register) to
determine when the erase
operation is suspended.

Flash memory sector erase operations take an extremely long time and depend on the device used. During an erase
cycle, the erase operation is interrupted by flash suspend/resume commands every flm_erase_poll_period_ms, so
that data can be read from any non-suspended sector and high priority tasks have a chance to execute. The timing
flm_erase_poll_period_ms is set to 5 ms in the initialization string by default.

7.1.1 Parallel Flash Driver Support for Inline ECC

The memory controller in the SXP 12G (PM805x devices only) supports inline ECC on external parallel flash. When
inline ECC is enabled, the read operation is transparent to firmware and the memory controller handles the memory
address translation from the logical address on the CPU side to the physical address on the flash memory side and
performs the ECC check.
When inline ECC is enabled, firmware is responsible for,

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• Calculating the physical flash sectors to be erased and handling the flash sector erase sequence when erasing
a sector;
• Translating the logical address to the physical address and handling the flash programming sequence on the
flash driver level when programming.

7.1.1.1 Flash Programming Sequence with ECC Enabled

Follow these steps to program Flash with ECC enabled.
1. Program with the Flash Buffer Program command with a 32-byte page boundary.
2. Calculate the physical page address with the 32-byte page boundary (see Figure 7-1).
3. Perform the following Write Procedure:
1. Write unclock cycle 1 to the device.
2. Write unclock cycle 2 to the device.
3. Write the Buffer Program command.
4. Write the Buffer Program Count, including the length of data and ECC.
5. Turn on ECC.
6. Write user data to the controller’s Write Data Buffer Registers.
7. Write the flash physical address to the Buffer Address Register.
8. Write the transfer length of data to the Transfer Register, excluding the length of ECC.
9. Turn off ECC.
10. Write the Buffer Program Confirm.

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Figure 7-1. Data Alignment with In-line ECC

Note
• Logical-to-physical address translation with parallel flash enabled introduces the Flash Partition Map change.
• When programming the flash with ECC enabled, the starting address must be aligned to a 24-byte address
boundary.

7.1.2 External Interface

The flash driver provides the following functions.
Table 7-4. Flash Driver Functions

Function Description

flm_init Initializes the flash device

flm_partition_erase Erases a specified partition in the flash device

flm_partition_write Writes data to the flash device

flm_partition_erased_verify Checks that each word within a partition has the erased value

flm_partition_info_get Returns information about a particular partition.

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Function Description

flm_board_device_reset A user-defined hook that performs a hardware reset of the flash device.

flm_partition_read_only_get Returns read-only flag for a partition.

flm_partition_read_only_set Sets read-only flag for a partition.

fwdl_hdlr Handles piece-wise firmware download.

fwdl_init_hook Hook to handle return code from flm_init().

7.1.2.1 flm_init
Initializes the FLM config structure. flm_init must be called before any other FLM functions are called. Perform the
one time flash module setup, configuration verification, and data initialization for parallel flash or SPI flash based on
the boot device type. Once this is complete the FLM 'object' is constructed and any of the functions to control the
flash can be used. This function can be called multiple times with the same handle without affecting the operation.

Prototype PMCFW_ERROR flm_init(flm_hndl *flm_handle_ptr)

Inputs None

Outputs flm_handle_ptr (pointer to) FLM structure handle.

Returns Success = PMC_SUCCESS

Warning = FLM_ERR_NSUP_FLASH_CMD_INTERFACE

Failure = Never fails.

Side Effects None

7.1.2.2 flm_partition_erase
Erases the specified flash partition. If the specified partition is not already erased, each sector of the partition is
erased in succession. Once the process has completed, the erase is verified by calling flm_partition_erased_verify()
again. This function is blocking and will not return until the erase and verify are complete or there has been an error.
Any valid partition may be erased.
When ECC is enabled, it needs to perform address remapping.

Prototype PMCFW_ERROR flm_partition_erase(

flm_hndl flm_handle,
flm_partition_enum partition_id)

Inputs flm_handle FLM structure handle

partition_id Which partition to erase

Outputs None

Returns Success = PMC_SUCCESS

Failure = FLM_ERR_SECTOR_ERASE_TIMEOUT
FLM_ERR_SECTOR_ERASE_FAILED

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Side Effects None Either failure return code could indicate a partially erased partition.

7.1.2.3 flm_partition_write
Writes data to the flash device. Writes to a flash device are only capable of bringing bits low so the device must
be erased to bring all of the bits high before any writes are performed. It is up to the user to erase the partition
before writing it. Any single valid partition may be written with any data using this function. If the data spans multiple
partitions FLM_ERR_BAD_LENGTH is returned without writing anything. Writes must be an integer number of flash
words (the size of the flash e.g., 16 bits), but can be any number less than or equal to the size of the partition. There
is no checking of the destination partition to see if it has been erased, writes will occur as long as the source data
length fits within the partition. After each word has been written to the flash it is read back for verification. If it does not
match the source word, FLM_ERR_PROG_FAILED is returned.
When ECC is enabled, it needs to do address remapping.

Prototype PMCFW_ERROR flm_partition_write(

flm_hndl flm_handle,
flm_partition_enum partition_id,
UINT32 byte_offset,
UINT32 num_bytes,
UINT8 *src_data_ptr)

Inputs flm_handle FLM structure handle

partition_id The partition to write to

byte_offset Offset into the partition to start writing from

num_bytes Length of data to write in bytes

src_data_ptr Pointer to the source data buffer. This data must be aligned to 16-bit
boundaries.

Outputs None

Returns Success = PMC_SUCCESS

Failure = FLM_ERR_BAD_LENGTH
FLM_ERR_PROG_FAILED

Side Effects None

7.1.2.4 flm_partition_erased_verify
Checks to see if a partition is erased. This function checks each word of the specified partition to ensure that it
matches the erase word (typically 0xFF).
When ECC is enabled, it needs to do address remapping.

Prototype PMCFW_ERROR flm_partition_erased_verify(

flm_hndl flm_handle,
flm_partition_enum partition_id)

Inputs flm_handle FLM structure handle

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partition_id Which partition to verify

Outputs None

Returns Success = PMC_SUCCESS

Failure = FLM_ERR_SECTOR_ERASE_FAILED

Side Effects None

7.1.2.5 flm_partition_info_get
Get information about a particular partition. This function accesses the private FLM data structure and performs some
calculations to return information about a particular partition.

Prototype void flm_partition_info_get (

flm_hndl flm_handle, flm_partition_enum partition_id,
flm_partition_info_struct *partition_info_ptr)

Inputs flm_handle FLM structure handle

partition_id Which partition to query

partition_info_ptr (Pointer to) a partition information structure.

Outputs None

Returns None

Side Effects None

7.1.2.6 flm_board_device_reset
A hook that can be used to perform a hardware reset of the flash. Typically this is board dependent and will use one
of the hardware drivers (e. g., GPIO) to toggle the reset pin of the flash device.

Prototype void flm_board_device_reset (void)

Inputs None

Outputs None

Returns None

Side Effects None

7.1.2.7 flm_partition_read_only_get
This function returns the read-only flag for a particular partition.

Prototype BOOL flm_partition_read_only_get(

flm_hndl flm_handle,
flm_partition_enum partition_id)

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Inputs flm_handle FLM structure handle

partition_id Which partition to query

Outputs None

Returns TRUE Partition is read only

FALSE Partition is writable

Side Effects None

7.1.2.8 flm_partition_read_only_set
This function sets the read-only flag for a particular partition.

Prototype void flm_partition_read_only_set(

flm_hndl flm_handle,
flm_partition_enum partition_id,
BOOL read_only)

Inputs flm_handle FLM structure handle

partition_id Which partition to query

read_only New value for the read_only flag

Outputs None

Returns None

Side Effects None

7.1.2.9 fwdl_hdlr
This function handles piecewise firmware download. The firmware download handler expects data to arrive in
contiguous (consecutive) packets. Each packet is accompanied by data_offset_bytes. The first packet is indicated by
an offset of zero and serves to reset the download process whenever it occurs. The first packet contains the firmware
download header that consists of the 28 bytes of information described in Table 4-1. Once the header is verified,
the destination partition is erased, and the packet data is written to the partition. After each packet is processed,
fwdl_hdlr updates and returns fwdl_status_ptr. This can then be used by upper layer processing to indicate status
and error conditions to the host.
Subsequent packets must have an offset that matches the one expected by fwdl_hdlr or the download is aborted.
After writing the final packet to flash, the CRC is computed by reading the partition up to the expected firmware
length. This value is then compared to the value sent in the firmware download header. If it matches the length of the
image and the CRC are written to the last eight bytes of the partition. After a successful download the partition will be
as shown in the following figure.

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Figure 7-2. Flash Partition Data After a Successful Firmware Download

Firm ware
IMAG E DATA Download Header
is NO T written

PARTITIO N_XXX

Im age length can

be an odd
num ber of bytes
ERASED REG IO N (0xFFs)

IM AG E LENG TH W ritten only if

download
CRC 32 succeeded.

32 bits

To switch over to the new image, a reboot must occur to re-invoke the Bootloader image selection code.

Prototype PMCFW_ERROR fwdl_hdlr(const fwdl_file_hdr_struct ref_file_hdr_ptr,

UINT32 data_offset_bytes,
UINT32 pkt_length_bytes,
UINT8 *data_ptr,
FWDL_STATUS_ENUM *fwdl_status_ptr)

Inputs ref_file_hdr_ptr (pointer to) the reference file header byte array.

data_offset_bytes Offset into the partition in bytes.

pkt_length_bytes Packet length in bytes (this includes the firmware header if

data_offset_bytes = 0). This number must be even except for
the last packet.

data_ptr (pointer to) the firmware data to write. This pointer should be
aligned on a 16-bit boundary. If data_offset_bytes = 0 this will
also include the firmware download header.

Outputs fwdl_status_ptr (pointer to) the firmware download status

Returns PMC_SUCCESS

Return code from FLM Often used to debug when fwdl_status =

FWDL_STATUS_HW_DOWNLOAD_ERR

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Side Effects Turns off interrupts when

programming the flash

7.1.2.10 fwdl_init_hook
Hook to handle the return code from flm_init() called inside fwdl_hdlr().

Prototype void flm_init(PMCFW_ERROR init_rc)

Inputs init_rc Return code from flm_init().

Outputs None

Returns None

Side Effects User-defined

7.1.3 Data Structures

7.1.3.1 flm_partition_info_struct
The flm_partition_info_struct contains information on a particular partition. The start_addr and end_addr fields are set
in the linker command file.

/***************************************************************************
* STRUCTURE: flm_partition_info_struct
* This structure contains information regarding a logical FLASH
* partition. It is populated using flm_partition_info_get().
*
* ELEMENTS:
* offset - Base offset of the partition relative to the start of the
* FLASH. This is the byte offset and is computed by
* subtracting the flash base offset address from start_addr.
* num_words - Number of FLASH words in the partition. Here a FLASH word
* depends on the FLASH device in use. This value is computed
* using (end_addr - start_addr) / sizeof(FLM_WORD).
* start_addr - Start address of the partition relative to the AHB. This
* address is obtained from the linker command file.
* end_addr - End address of the partition relative to the AHB. This
* address is obtained from the linker command file.
* read_only - Read only flag used for partition protection.
*
****************************************************************************/
typedef struct
{
UINT32 start_addr;
UINT32 end_addr;
UINT32 offset;
UINT32 num_words;
BOOL read_only;
} flm_partition_info_struct;

7.1.4 SPI Flash Driver

The SPI flash driver maintains the same APIs as the parallel flash driver.

7.1.4.1 SPI Bus Raw APIs

Three SPI bus raw APIs access the SPI slave device. There are two modes that the memory controller can access in
the SPI device.
• In hardware-assisted mode, the memory controller sends or receives one byte and firmware checks the status.
• In memory-mapped mode, firmware writes one page each time and checks the status. Only an 8B/16B/32B
program is supported. 1/2/3/4 byte access is not supported.

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It is recommended to use memory-mapped mode for write operations and hardware-assisted mode for other
operations.
Table 7-5. SPI Bus Interface Functions

Function Description

spi_hw_assisted_write Sends data in hardware-assisted mode.

spi_hw_assisted_read Receives data in hardware-assisted mode.

spi_mem_mapped_write Sends data in memory-mapped mode.

Dst_ptr (Pointer to) destination.

Data_length Data length in bytes. At most 256 Bytes.

Outputs None

Returns None

Side Effects None

7.1.4.5 spi_mem_mapped_write_write
Sends data in hardware assisted mode. Data is in two buffer sources. Specifically, data1 is the command opCode
and data2 is real data.

Prototype PMCFW_ERROR spi_mem_mapped_write_write(UINT8 bus_id,

UINT8 *src1_ptr,
UINT32 write1_length,
UINT8 *src2_ptr,
UINT32 write2_length)

Inputs bus_id SPI bus ID.

src1_ptr (Pointer to) the first source data pointer.
src1_length Data length in bytes of first source data.

Src2_ptr (Pointer to) the first source data pointer.

Src2_length Data length in bytes of the second source data.

Outputs None

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Returns
PMC_SUCCESS SUCCES
S

SPI_ERR_TIMEOU TIMEOUT
T

Side Effects None

7.1.4.6 spi_mem_mapped_write_read
Sends and receives data in hardware assisted mode.

Prototype PMCFW_ERROR spi_mem_mapped_write_read(UINT8 bus_id,

UINT8 *src_ptr,
UINT32 write_length,
UINT8 *dst_ptr,
UINT32 read_length)

Inputs bus_id SPI bus ID.

src_ptr (Pointer to) source data.
write_length Write data length in bytes.

Dst_ptr (Pointer to) destination.

read_length Read data length in bytes.

Outputs None

Returns
PMC_SUCCESS SUCCES
S

SPI_ERR_TIMEO TIMEOUT
UT

Side Effects None

7.1.4.7 SPI Flash Sector Erasing Procedure

1. Disable global interrupts to stop other threads from accessing the SPI Flash.
2. Send the ‘Write Enable’ command.
3. Send the ‘Sector Erase’ command.
4. It is advisable to periodically allow the other threads an opportunity to process any interrupts that have fired
while the erase is on-going. To do so, send the ‘Erase Suspend’command.
5. Poll the ‘Write in Progress’ bit (WIP) in the SPI Flash ‘Read Status Register’ (RDSR) until it reports ‘Idle,’
indicating that the erase operation has been suspended.
6. Enable global interrupts and sleep for a period of time so that other threads can run.
7. Disable global interrupts to stop others threads again.
8. Send the ‘Erase Resume’ command.
9. Repeat steps 4-8 until the erase has completed.
10. Enable global interrupts.

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7.1.4.8 SPI Flash Sector Programming Procedure

1. Send the Write Enable command using hardware assisted writes.
2. Write the actual data intended in the memory-mapped data buffers. The maximum buffer size supported by the
Numonyx SPI Flash device is 256 bytes.
3. Firmware polls the SPI_MM_STATUS register to confirm that the SPI Controller is in the IDLE state before
issuing the hardware assisted access (Step 4).
4. Send the Read Status command using a hardware-assisted transfer.
5. Repeat Steps 4 until the flash is programmed with the previous write.
6. Repeat Steps 2 to 4 until all data has been programmed.

7.1.4.9 How to customize SPI Flash Driver to support the new model of SPI Flash Memory
Firmware supports Numonyx N25Q128 SPI flash, and Winbond W25Q128FW and W25Q32DW flash parts, refer to
Table 7-2. To support a new SPI flash chip, the following steps should be taken into consideration:
1. Add Flash operation APIs such as get device id, erase sector, write word, write buffer, and chip reset, and so
on. Refer to the corresponding functions in flm_NumonyxSPI.c.
2. Define the corresponding data structures for the new SPI Flash Memory. Refer to structures in
flm_N25Q128_data.c., especially, the following key elements that must be configured properly. See the
instructions in the SPI Flash datasheet:
– device_size -Device Size = 2^N in bytes
– max_multi_byte_write -Maximum number of bytes in a multi-byte program = 2^N
– num_erase_blocks -Number of Erase Block Regions within device
– erase_block_array -Erase Block Region Information
3. Add the device into flm_supported_spi_flash_devices_array[].
4. If a new SPI flash is being used and firmware could not detect it in supported SPI flash device array, firmware
will use N25Q128E SPI flash driver by default. This may cause flash programming error or booting failure.
Make sure the new device is N25Q128E compatible (sector layout/timing/commands/etc), otherwise add new
SPI driver into firmware as described by the above steps.

7.2 TWI
The TWI driver configures the TWI hardware and performs individual TWI transactions. The TWI driver also directly
supports access to peripheral devices and supports the necessary transactions for constructing a complex data-link
protocol for communicating between intelligent TWI-capable systems. The SXP 12G TWI is hardware-based. TWI
hardware is responsible for bus arbitration, handling clock stretching, and performing transactions and interrupts. The
TWI driver needs to initiate transactions, check status, and handle interrupts and bus recovery.
The TWI device driver supports a configurable number of TWI Ports with each port operating either as a master
or slave. In addition, the SXP 12G TWI supports both 10-bit and 7-bit slave addresses and supports corresponding
read/write operations.

7.2.1 External Interface

The TWI driver provides the following functions:
Table 7-6. TWI Driver Functions

Function Description

twi_master_write_10bit Performs a master write transaction with a 10-bit or 7-bit address slave device.

twi_master_read_10bit Performs a master read transaction with a 10-bit or 7-bit address slave device.

twi_master_writeread_10bit Performs a master write and read transaction with a 10-bit or 7-bit address
slave device.

twiss_init Initializes the TWI subsystem. Must be called once before any other TWI
functions can be used.

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...........continued
Function Description

twi_mst_init Initializes a TWI Master port.

twi_slv_init Initializes a TWI Slave port.

twi_slv_offset_width_set Sets the slave offset width for a SXP12G TWI Slave port.

twi_mst_stretch_time_set Sets the extra time that a master must wait before a transaction timeout.

twi_master write Performs a master write transaction.

twi_master_read Performs a master read transaction.

twi_master_writeread Performs a master write and read transaction.

twi_nonthreadx_init Non-ThreadX version of TWI driver.

twi_nonthreadx_master_init Non-ThreadX version of TWI driver.

twi_nonthreadx_master_write Non-ThreadX version of TWI driver.

twi_nonthreadx_master_read Non-ThreadX version of TWI driver.

twi_nonthreadx_master_writeread Non-ThreadX version of TWI driver.

twi_nonthreadx_master_write_10b Non-ThreadX version of TWI driver.

twi_nonthreadx_master_read_10b Non-ThreadX version of TWI driver.

twi_nonthreadx_master_writeread Non-ThreadX version of TWI driver.

_10bit

twi_nonthreadx_slv_init Non-ThreadX version of TWI driver.

twiss_slv_state_machine TWI slave event handler for both ThreadX version and non-ThreadX version

Access to device resources such as transmit and receive buffers is serialized using semaphores shared between
the caller of these API and the TWI ISR. The transmit and receive operations block the thread if the appropriate
semaphore is not available.

7.2.1.1 twi_master_write_10bit
Performs a TWI Master Write transaction with up to 256 bytes of write data. It supports both 7-bit addresses and
10-bit addresses.

Prototype PMCFW_ERROR twi_master_write_10bit(UINT8 port,

UINT16 slv_addr,
UINT8 * tx_msg,
UINT16 tx_len)

Inputs port Port ID

slv_addr 7 or 10-bit TWI slave address

tx_msg (Pointer to) write data

tx_len Number of bytes to write (1 - 256)

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Outputs None

Returns PMC_SUCCESS
TWI3_ERR_MTX_TIMEOUT
TWI3_ERR_UNEXPECTED_INT_SRC
TWI3_ERR_MST_TIMEOUT_RECOVERED
TWI3_ERR_MST_TIMEOUT_UNRECOVERED
TWI3_ERR_TXABRT_7ADDR_NOACK
TWI3_ERR_TXABRT_10ADDR1_NOACK
TWI3_ERR_TXABRT_10ADDR2_NOACK
TWI3_ERR_TXABRT_DATA_NOACK
TWI3_ERR_TXABRT_SBYTE_ACKDET
TWI3_ERR_TXABRT_ARB_LOST

Side Effects None

7.2.1.2 twi_master_read_10bit
Performs a TWI Master Read transaction recovering up to 256 bytes of read data. The calling thread is blocked until
the read operation has completed. It supports both 7-bit addresses and 10-bit addresses.

Prototype PMCFW_ERROR twi_master_read_10bit(UINT8 port,

UINT16 slv_addr,
UINT8 * rx_msg,
UINT16 rx_len)

Inputs port Port ID

slv_addr 7 or 10-bit TWI slave address

rx_msg (Pointer to) location to store the read data

rxlen number of bytes to read (1 - 256)

Outputs rx_msg updated with read data

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Side Effects None

7.2.1.3 twi_master_writeread_10bit
Performs a TWI Master Write-Read transaction writing up to 256 bytes of data and recovering up to 256 bytes of read
data. The calling thread is blocked until the write/read operation has completed. It supports both 7-bit addresses and
10-bit addresses.

Prototype PMCFW_ERROR twi_master_writeread_10bit(UINT8 port,

UINT16 slv_addr,
UINT8 * tx_msg,
UINT16 tx_len,
UINT8 * rx_msg,
UINT16 rx_len)

Inputs port Port ID

slv_addr 7 or 10-bit TWI slave address

tx_msg (Pointer to) location to write data from

tx_len number of bytes to write

rx_msg (Pointer to) location to store the read data

rxlen Number of bytes to read.

Outputs rxmsg updated with read data

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Side Effects None

7.2.1.4 twiss_init
Performs TWI subsystem initialization. This is called once for the entire TWI subsystem.

Prototype void twiss_init(

twiss_div_struct *twiss_div_ptr,
UINT32 glb_cfg)

Inputs twiss_div_ ptr (pointer to) configuration data for the TWI, On SXP 12G, this parameter
is not used.

glb_cfg TWISS global configuration register setting. On SXP 12G, this

parameter is not used.

Outputs None

Returns None

Side Effects None

7.2.1.5 twi_mst_init
Initializes a TWI Master port and allocates system resources used by the TWI driver. This function is called once and
only once for each physical TWI master interface. It must be called before the TWI Master functions can be called.

Prototype void twi_mst_init(

UINT8 port,
twi_mst_callback_fptr mst_callback_fptr,
void *mst_callback_data_ptr,
UINT32 mst_ctl,
UINT32 mst_cfg,
UINT32 mst_int_enb,
UINT32 mst_clk )

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Inputs port TWI port number (0 to TWI_NUM_PORTS – 1)

mst_callback_ fptr Callback function pointer.

mst_callback_data_ Callback data pointer

ptr

mst_ctl Master port control. On the SXP 12G, this parameter is not used.

mst_cfg Master port configuration. On the SXP 12G, this parameter is not used.

mst_int_enb Master port interrupt configuration. On the SXP 12G, this parameter is
not used.

mst_clk Master clock register configuration

Outputs TWI Master registers on the specified port are configured.

Returns Success = None

Failure = None

Side Effects None

7.2.1.6 twi_slv_init
Initializes a TWI Slave interface. This is called once for each physical TWI interface.

Prototype void twi_slv_init(

UINT8 port,
twi_slv_callback_fptr slv_callback_fptr,
void *slv_callback_data_ptr,
UINT32 slv_ctl,
UINT32 slv_int_enb)

Inputs port TWI port number (0 to TWI_NUM_PORTS – 1)

slv_callback_ fptr TWI slave interrupt callback.

slv_callback_ Slave callback data pointer.

data_ptr

slv_ctl Slave port control

-bits [9:0] for slave device address,
-bit [10] for 10bit address flag,
-bit [15] for IPMB Awareness, 1=IPMB_MODE,
-bit[16:31] for callback invoking trigger level, must less than
TWI_SLV_BUF_LEN

slv_int_enb Slave port interrupt configuration. On the SXP 12G, this parameter is
not used.

Outputs TWI Slave registers on the specified port are configured.

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Returns None

Side Effects None

7.2.1.7 twi_slv_offset_width_set
Sets the slave offset width of a SXP12G TWI Slave. This should be called before twi_slv_init() if the slave offset width
needs to be changed.

Prototype void twi_slv_offset_width_set(

UINT8 port,
twi_slv_offset_width_enum slv_offset_width)

Inputs port TWI port number (0 to TWI_NUM_PORTS – 1)

slv_offset_width TWI slv_offset_width

TWI_SLV_1_BYTE_OFFSET_WIDTH = 1
TWI_SLV_2_BYTE_OFFSET_WIDTH = 2,

Outputs TWI Slave registers on the specified port are configured.

Returns None

Side Effects None

7.2.1.8 twi_mst_stretch_time_set
Sets the extra time that a master must wait before a transaction timeout. The default value is 5ms and is set in the
initialization string. This function can be called at any time after twi_mst_init().

Prototype void twi_mst_stretch_time_set (UINT8 port,

UINT32 stretch_time)

Inputs port TWI port number (0 to TWI_NUM_PORTS – 1)

stretch_time The extra time that the master must wait before a transaction timeout.
The unit is ms. The default value is 5.

Outputs None

Returns None

Side Effects None

7.2.1.9 twi_master_write
Performs a TWI Master Write transaction with up to 256 bytes of write data. The calling thread is blocked until the
write operation has completed.

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Prototype PMCFW_ERROR twi_master_write(

UINT8 port,
UINT8 slv_addr,
UINT8 *tx_msg,
UINT16 tx_len)

Inputs port Port ID (0 to TWI_NUM_PORTS – 1)

slv_addr 7-bit TWI slave address to write to.

tx_msg (pointer to) location to write data from

tx_len number of bytes to write (1 – 256)

Outputs None

Side Effects None

7.2.1.10 twi_master_read
Performs a TWI Master read transaction recovering up to 256 bytes of read data. The calling thread is blocked until
the read operation has completed.

Prototype PMCFW_ERROR twi_master_read(

UINT8 port,
UINT8 slv_addr,
UINT8* rx_msg,
UINT16 rx_len)

Inputs port Port ID (0 to TWI_NUM_PORTS – 1)

slv_addr TWI slave address to read from.

rx_msg (pointer to) up to location to write the read data

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rx_len number of bytes to read (1 – 256)

Outputs rx_msg updated with read data

Side Effects None

7.2.1.11 twi_master_writeread
Performs a TWI Master write-read transaction writing up to 256 bytes of data and recovering up to 256 bytes of read
data. The calling thread is blocked until the write/read operation has completed.

Prototype PMCFW_ERROR twi_master_writeread(UINT8 port,

UINT8 slv_addr,
UINT8 * tx_msg,
UINT16 tx_len,
UINT8 * rx_msg,
UINT16 rx_len)

Inputs port Port ID

slv_addr 7-bit TWI slave address

tx_msg (Pointer to) location to write data from

tx_len number of bytes to write (1-256)

rx_msg (Pointer to) location to store the read data

rxlen number of bytes to read(1-256)

Outputs rx_msg updated with read data

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Side Effects None

7.2.1.12 twi_nonthreadx_init
Performs top level TWI initialization.

Prototype void twi_nonthreadx_init(UINT32 glb_cfg)

Inputs glb_cfg TWISS global configuration register setting. On the SXP 12G, this
parameter is not used.

Outputs None

Returns None

Side Effects None

7.2.1.13 twi_nonthreadx_master_init
Performs per-TWI master port initialization. This is called once for each physical TWI master interface.

Prototype VOID twi_nonthreadx_master_init(UINT8 port,

UINT32 mst_ctl,
UINT32 mst_cfg,
UINT32 mst_int_enb,
UINT32 mst_clk )

Inputs port Port ID

Mst_ctl Master port control was obsoleted for the SXP 12G. Set to 0 for backward
compatibility.

Mst_cfg Master port configuration was obsoleted for the SXP 12G. Set to 0 for
backward compatibility

mst_int_enb Master port interrupt configuration was obsoleted for the SXP 12G. Set to 0
for backward compatibility.

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Mst_clk Master clock register configuration. Can be TWI_MST_CLK_400KHZ or

TWI_MST_CLK_100KHZ.

Outputs None

Returns None

Side Effects None

7.2.1.14 twi_nonthreadx_master_write
Performs a TWI Master Write transaction with up to 32 bytes of write data.

Prototype PMCFW_ERROR twi_nonthreadx_master_write(UINT8 port,

UINT8 slv_addr,
UINT8 * tx_msg,
UINT16 tx_len)

Inputs port Port ID

slv_addr 7-bit TWI slave address

tx_msg (Pointer to) write data

tx_len number of bytes to write (1 - 32)

Outputs None

Returns PMC_SUCCESS
TWI3_ERR_MST_TIMEOUT_RECOVERED
TWI3_ERR_MST_TIMEOUT_UNRECOVERED
TWI3_ERR_TXABRT_7ADDR_NOACK
TWI3_ERR_TXABRT_10ADDR1_NOACK
TWI3_ERR_TXABRT_10ADDR2_NOACK
TWI3_ERR_TXABRT_DATA_NOACK
TWI3_ERR_TXABRT_SBYTE_ACKDET
TWI3_ERR_TXABRT_ARB_LOST

Side Effects None

7.2.1.15 twi_nonthreadx_master_read
Performs a TWI Master read transaction recovering up to 32 bytes of read data.

Prototype PMCFW_ERROR twi_nonthreadx_master_read(UINT8 port,

UINT8 slv_addr,
UINT8 * rx_msg,
UINT16 rx_len)

Inputs port Port ID

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slv_addr 7-bit TWI slave address

rx_msg (Pointer to) location to store the read data

rxlen Number of bytes to read (1 - 32)

Outputs rx_msg Updated with read data

Side Effects None

7.2.1.16 twi_nonthreadx_master_writeread
Performs a TWI Master write-read transaction writing up to 32 bytes of data and recovering up to 32 bytes of read
data.

Prototype PMCFW_ERROR twi_nonthreadx_master_writeread(UINT8 port,

UINT8 slv_addr,
UINT8 * tx_msg,
UINT16 tx_len,
UINT8 * rx_msg,
UINT16 rx_len)

Inputs port Port ID

slv_addr 7-bit TWI slave address

tx_msg (Pointer to) location to write data from

tx_len Number of bytes to write

rx_msg (Pointer to) location to store the read data

rxlen Number of bytes to read

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Device Drivers

Outputs rx_msg Updated with read data

Side Effects None

7.2.1.20 twi_nonthreadx_slv_init
Initializes a TWI Slave interface. This is called once for each physical TWI interface.

Prototype void twi_nonthreadx_slv_init(

UINT8 port,
twi_slv_callback_fptr slv_callback_fptr,
void *slv_callback_data_ptr,
UINT32 slv_ctl,
UINT32 slv_int_enb)

Inputs port TWI port number (0 to TWI_NUM_PORTS – 1)

slv_callback_ fptr TWI slave interrupt callback.

slv_callback_ Slave callback data pointer.

data_ptr

slv_ctl Slave port control

-bits [9:0] for slave device address,
-bit [10] for 10bit address flag,
-bit [15] for IPMB Awareness, 1=IPMB_MODE,
-bit[16:31] for callback invoking trigger level, must be less than
TWI_SLV_BUF_LEN

slv_int_enb Slave port interrupt configuration. On the SXP 12G, this parameter is
not used.

Outputs TWI Slave registers on the specified port are configured.

Returns None

Side Effects None

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Device Drivers

7.2.1.21 twiss_slv_state_machine
This function decodes and dispatches handlers for one TWI slave interrupt. It is for both ThreadX and non-ThreadX
functions. TX data and RX data are saved in buffer twi_slv_ptr->data_ptr. Call twi_slv_data_put() to put data into the
buffer. Call twi_slv_data_get() to get RX data from the twi slave buffer. The TWI slave callback function is invoked
when STOP is detected and the trigger flag is TRUE, or when ABORT is detected.

Prototype void twiss_slv_state_machine(UINT8 port)

Inputs port Port ID

Outputs none

Returns none

Side Effects None

7.2.2 TWI Slave Usage

The SXP12G TWI Slave supports two modes.
General Mode: In general mode, the callback function is invoked when any data is written to an offset of which the
value is equal to callback_trigger_level. In an application design, this offset could be used to store a flag or state for
the transaction, for example Transaction Start or, Transaction End, and so on.
Sequence for the Read/Write operation in General mode:
Write by a Master: <Start>+<Slave_Addr>+<W>+<Offset_MSB>+<Offset_LSB>+<Data_To_Slave>
+<Stop>
Read by a Master: <Start>+<Slave_Addr>+<W>+<Offset_MSB>+<Offset_LSB>+<Restart>
+<Slave_Addr>+<R>+<Data_From_Slave>+<Stop>
IPMB Mode: Refer to IPMB Specification [25] for detail. In IPMB mode, the callback function is invoked when the
slave has received more than callback_trigger_level bytes of data. Generally, the callback_trigger_level should be set
as the minimum length of an IPMB frame.
To use a TWI slave, the application needs to:
1. Initialize the TWI slave with function twi_slv_init(), and provide the callback function and callback_trigger_level
as parameters.
2. Use the function twi_slv_data_get() to read data from the slave buffer, and use twi_slv_data_put() to write data
to the slave buffer.
3. Make the callback function as simple as possible since the callback function is invoked in the TWI ISR. In
general, the callback should generate an event that is handled by another thread. An example of this event
and thread method is in the example < fwcs\soc_io\src\ipctwi >.
4. If using “General Mode”, consider implementing protection mechanism for validating transactions, similar to
checksum for IPMB. In a busy system, the TWI slave service routine might not be able to respond to interrupts
in time and this might cause data for different transactions to become concatenated in the TWI slave buffer.

7.3 UART
The UART driver configures the serial port hardware and performs read and write transactions. It supports a
configurable number of UART ports, each of which is controlled independently. For the number of UARTs on the
SEP device you are using, refer to the device-specific Firmware User Manual.

7.3.1 External Interface

The UART driver provides the following functions:

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Device Drivers

Table 7-7. UART Driver Functions

Function Description

uart_init Identifies and initializes the UART

uart_tx Writes a single character to the specified UART

uart_tx_mult Writes a string of characters to the specified UART

uart_rx Reads a single character from the specified UART

uart_nonthreadx_init Identifies and initializes the UART (Non-ThreadX version)

uart_nonthreadx_tx_mult Writes a string of characters to the specified UART (Non-ThreadX version)

uart_nonthreadx_rx Reads a single character from the specified UART (Non-ThreadX version)

7.3.1.1 uart_init
Identifies and initializes the operational capabilities of the UART.

Prototype void uart_init(

UINT8 id,
UINT32 base,
UINT8 data_bits,
UINT8 stop_bits,
uart_parity_enum parity,
uart_baud_enum baud,
BOOL flow_ctrl_en)

Inputs id UART identifier (0 to UART_COUNT-1)

base Base address of the UART

data_bits Number of data bits (5, 6, 7, and 8)

stop_bits Number of stop bits to generate when transmitting. The following data bit
and stop bit combinations are allowed:
data_bits stop_bits
5, 6, 7, 8 1
6, 7, 8 2

parity parity selection

UART_PARITY_NONE
UART_PARITY_EVEN
UART_PARITY_ODD

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Device Drivers

baud baud rate selection

UART_BAUD_2400
UART_BAUD_4800
UART_BAUD_9600
UART_BAUD_19200
UART_BAUD_28800
UART_BAUD_38400
UART_BAUD_57600
UART_BAUD_115200

flow_ctrl_ en TRUE – hardware flow-control enabled

FALSE – hardware flow-control disabled

Outputs None

Returns None

Side Effects None

7.3.1.2 uart_tx
Writes a single character to the specified UART. If the UART has not completed transmitting the previous character,
the calling thread is blocked until the character is transmitted.

Prototype PMCFW_ERROR uart_tx(

UINT8 id,
CHAR data)

Inputs id UART identifier (0 to UART_COUNT-1)

data character to be transmitted

Outputs None

Returns Success = PMC_SUCCESS

Failure = UART_STAT_ERR_BAD_PARAM
UART_STAT_ERR_GENERAL

Side Effects None

7.3.1.3 uart_tx_mult
Writes a string of characters to the specified UART. The calling thread is blocked until the entire string is transmitted.

Prototype PMCFW_ERROR uart_tx(

UINT8 id,
CHAR * d_ptr,
UINT32 len)

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Device Drivers

Inputs id UART identifier (0 to UART_COUNT-1)

d_ptr Pointer to a string of data bytes to be transmitted

len Length (in bytes) of the data string

Outputs None

Returns Success = PMC_SUCCESS

Failure = UART_STAT_ERR_BAD_PARAM
UART_STAT_ERR_GENERAL

Side Effects None

7.3.1.4 uart_rx
Reads a single character from the specified UART. The API returns the character if it is available; otherwise, it
blocks the calling thread for a period defined by UART_RX_FIFO_EMPTY_TIMEOUT_TICKS in uart. h for a received
character to become available. If a character is not available, this function returns a non-zero failure code.

Prototype PMCFW_ERROR uart_rx(

UINT8 id,
CHAR *dptr)

Inputs id UART identifier (0 to UART_COUNT-1)

dptr Pointer to the location to write the character read

Outputs *dptr Character read

Returns Success = PMC_SUCCESS

Failure = UART_STAT_ERR_BAD_PARAM
UART_STAT_ERR_GENERAL
OSF_ERR_TIMEOUT

Side Effects None

7.3.1.5 uart_nonthreadx_init
This function initializes the selected UART device to send and receive data under non–ThreadX conditions.

Prototype void uart _nonthreadx_init(

UINT8 id,
UINT32 base,
UINT8 data_bits,
UINT8 stop_bits,
uart_parity_enum parity,
uart_baud_enum baud,
BOOL flow_ctrl_en)

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Device Drivers

Inputs id UART identifier (0 to UART_COUNT-1)

base Base address of the UART.

data_bits Number of data bits (5, 6, 7, and 8).

stop_bits Number of stop bits to generate when transmitting. The following data
bit and stop bit combinations are allowed:
data_bits stop_bits
5, 6, 7, 8 1
6, 7, 8 2

parity parity selection

UART_PARITY_NONE
UART_PARITY_EVEN
UART_PARITY_ODD

baud baud rate selection

UART_BAUD_2400
UART_BAUD_4800
UART_BAUD_9600
UART_BAUD_19200
UART_BAUD_28800
UART_BAUD_38400
UART_BAUD_57600
UART_BAUD_115200

flow_ctrl_ en TRUE – hardware flow-control enabled.

FALSE – hardware flow-control disabled.

Outputs None

Returns None

Side Effects None

7.3.1.6 uart_nonthreadx_tx_mult
This function sends multiple bytes simultaneously to the selected UART device under non-ThreadX conditions.

Prototype PMCFW_ERROR uart_nonthreadx_tx_multi(

UINT8 id,
CHAR * d_ptr,
UINT32 len)

Inputs id UART identifier (0 to UART_COUNT-1).

d_ptr Pointer to a string of data bytes to be transmitted.

len Length (in bytes) of the data string.

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Device Drivers

Outputs None

Returns Success = PMC_SUCCESS

Failure = UART_STAT_ERR_BAD_PARAM
UART_STAT_ERR_GENERAL

Side Effects None

7.3.1.7 uart_nonthreadx_rx
This function retrieves one byte from the selected UART device under non-ThreadX conditions. The API returns the
character if it is available; otherwise, it returns UART_STAT_ERR_GENERAL.

Prototype PMCFW_ERROR uart _nonthreadx_rx(

UINT8 id,
CHAR *dptr)

Inputs id UART identifier (0 to UART_COUNT-1).

dptr Pointer to the location to write the character read.

Outputs *dptr Character read.

Returns Success = PMC_SUCCESS

Failure = UART_STAT_ERR_BAD_PARAM
UART_STAT_ERR_GENERAL

Side Effects None

7.4 SGPIO
The SXP 12G device provides four SFF-8485 compliant four-pin SGPIO interfaces for GPIO expansion. The firmware
configures each SGPIO output timeslot as a static output, an LED flash output with eight programmable LED flash
patterns, or a link activity status indicator that is generated by the port interface logic. Each SGPIO input timeslot can
also be configured to generate an interrupt.
The length of the bit stream is programmable in units of three timeslots. The firmware also configures the order of
assignment of the slots to the PHYs. These two features provide enough flexibility to support different applications
(e.g., they allow for the exclusion of PHYs attached to initiators and other expanders from the bit stream if needed).
See Section 9.4 LED Control through SGPIO for a complete description of this interface.

7.5 GPIO
In the SXP 12G, all 81 GPIO ports are dual function with other I/O ports. These can be configured as GPIO or main
function ports, see Table 7-1 and Table 8-25. The firmware configures each GPIO pin as input or output.
The GPIO firmware driver provides functions to set up and control the GPIO hardware, and for general GPIO register
read/write operations.

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Device Drivers

Table 7-8. GPIO Operations

Function Description

gpio_reg_write Writes to a GPIO register

gpio_reg_read Reads from a GPIO register

gpio_port_func_selection_cfg Makes the function selection between a GPIO and a main function

gpio_port_cfg Dynamically configures a GPIO port attributes

gpio_port_write Writes the high/low value to a GPIO port

gpio_port_read Reads the high/low status of a GPIO port

7.5.1 gpio_reg_write
Performs a read-modify-write to the specified GPIO register.

Prototype void gpio_reg_write(UINT32 offset, UINT32 reg, UINT8 value, UINT8

mask)

Inputs offset Offset to the GPIO register block.

reg Register to write within the GPIO register block.

value Value to write.

mask The mask of bits to write.

Outputs None

Returns Success = None.

Failure = None.

Side Effects None

7.5.2 gpio_reg_read
Performs a read from the specified GPIO register.

Prototype UINT8 gpio_reg_read(

UINT32 offset,
UINT32 reg)

Inputs offset The offset to the GPIO register block.

reg The register to read within the GPIO register block.

Outputs UINT8 The read value.

Returns Success = None.

Failure = None.

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Device Drivers

Side Effects None

7.5.3 gpio_port_func_selection_cfg
Selects between the GPIO function and the main function.

Prototype void gpio_port_func_selection_cfg (istr_gpio_cfg_new_struct *gpio_cfg_ptr)

Inputs gpio_cfg_ptr (Pointer to) the GPIO configuration parameters that are retrieved from the
initialization string.

Outputs None

Returns None

Side Effects None

7.5.4 gpio_port_cfg
Dynamically configures the GPIO port attributes.

Prototype PMCFW_ERROR gpio_port_cfg (UINT8 port_id,

gpio_mode_enum gpio_mode,
BOOL gpio_output
gpio_isr_callback_fptr gpio_isr_callback_ptr)

Inputs port_id Port ID

gpio_mode 0: output,
1: input;
2: rising edge interrupt (only valid for specific GPIO ports)
3: falling edge interrupt(only valid for specific GPIO ports)
4: high level interrupt(only valid for specific GPIO ports)
5: low level interrupt(only valid for specific GPIO ports)

gpio_output TRUE for high or FALSE for low, when port works as output

gpio_isr_callback_ptr GPIO ISR callback when GPIO mode is 2/3/4/5

Outputs None

Returns PMC_SUCCESS

PMCFW_ERR_INVA Parameters not valid.

LID_PARAMETERS

Side Effects None

7.5.5 gpio_port_write
Writes the high/low value to the GPIO port once the GPIO mode is output.

Prototype PMCFW_ERROR gpio_port_write(UINT8 port_id, UINT8 value)

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Device Drivers

Inputs Port_id Port ID

value Output value

Outputs None

Returns PMC_SUCCESS

PMCFW_ERR_INVA Parameters not valid.

LID_PARAMETERS

Side Effects None

7.5.6 gpio_port_read
Reads the GPIO port once the GPIO mode is input.

Prototype PMCFW_ERROR gpio_port_read(UINT8 port_id, BOOL *output_ptr)

Inputs Port_id Port ID

Output_ptr (Point to) output

Outputs Output_ptr (Point to) output

Returns PMC_SUCCESS

PMCFW_ERR_INVA Parameters not valid.

LID_PARAMETERS

Side Effects None

7.6 Ethernet
Except for the PM8044 and PM8043 devices, the SXP devices provide a 10/100M MAC interface for connecting an
external Ethernet PHY device. The Ethernet driver provides the basic hardware interfacing and packet management
for receiving and transmitting packets. The processing of the actual packets is done by the TCP/IP stack that runs as
a separate thread.
There are APIs for querying MAC statistics and supporting the Micrel Ethernet PHY KSZ8051 used for the SXP 12G
Evaluation Kit.

7.7 Real Time Clock (RTC) Driver

The real time clock is a 50-bit counter that is incremented every 1us and counts to approximately 35 years. Its
primary purpose is for data logging. The CPU can set the counter to any value and it can be read at any time. It must
be configured prior to use. The real time clock does not get reset with a normal soft or hard reset, however, it can be
written, read, or reset through Real Time Clock Control Registers.
To access the RTC, the host sends a vendor-specific SES command and gets a response. Refer to 14.2.3.14 String
Out Diagnostic Command (0x4) for detail.

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Device Drivers

Table 7-9. RTC Driver Functions

Function Description

rtc_reset Resets the RTC

rtc_set Sets the RTC clock count load value

rtc_get Gets the RTC clock count

7.7.1 rtc_reset
This function resets the RTC and loads the clock count load value in the control register.

Prototype void rtc_reset(void)

Inputs None

Outputs None

Returns None

Side Effects None

7.7.2 rtc_set
This sets the RTC clock count load value in the RTC Control register.

Prototype void rtc_set(UINT64 time_us)

Inputs time_us Clock count. Only the lower 50 bits are valid.

Outputs None

Returns None

Side Effects None

7.7.3 rtc_get
This function gets the RTC clock count.

Prototype void rtc_get(UINT64 *time_us_ptr)

Inputs None

Outputs time_us_ptr (Pointer to) clock count in us. Only the lower 50 bits are valid.

Returns None

Side Effects None

7.8 Application Timer Driver

The EXTSS supports four software timers. Each timer has a 32-bit counter and is clocked by a 75-MHz clock allowing
software timer time-out periods of up to 57 seconds. The application software timer is more precise than a 1ms

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Device Drivers

OSF timer. The timer driver provides the APIs for creating hardware timers, start/stop timers, and timing expiration
callbacks.
Upon system reset, all timers are disabled. The software timer can be enabled though the control registers. Once
enabled, the software timer starts counting down. When it reaches 0, it loads one of two values depending on the
timer-operating mode. By default, the timer is in the free-running mode, where the counter wraps to 0xFFFF_FFFF
to allow time to reprogram or disable the timer before another interrupt occurs. In user-defined count mode, the timer
loads the current value of the TimerNLoadCount register.
The user-defined count mode generates a fixed-timed interrupt. The free-running mode generates a single-timed
interrupt.
Select the user-defined count mode by writing 1 to bit 1 of the timer control register.
Select the free-running mode by writing 0 to Bit 1 of the timer control register.
Normal operation of the timer is as follows:
Disable the timer and program its operating mode by writing to its control register.
Load the Timer N LoadCount register – the period in us
Enable the timer.
In both the free-running and user-defined count modes, a timer generates an interrupt when its count changes from
0 to its maximum count value. The interrupt is not generated if the timer is disabled. If the actual interrupt is set, it is
cleared when the timer is disabled.
Table 7-10. Application Timer Driver Functions

Function Description

app_timer_obj_register Registers one application timer instance to one hardware timer.

app_timer_obj_deregister Deregisters one application timer instance from one hardware timer.

app_timer_obj_start Starts one registered application timer instance.

app_timer_obj_stop Stops one registered application timer instance.

7.8.1 app_timer_obj_register
Registers one timer instance to one hardware timer.

Prototype app_timer_obj_struct *app_timer_obj_register(app_timer_id_enum

hw_timer_id,
UINT32 data,
UINT32 time_us,
BOOL repeat_mode,
app_timer_callback_fptr timer_callback_fptr)

Inputs hw_timer_id Hardware timer ID

data Private data of the object

time_us Time in us

repeat_mode Starts repeatedly or starts one time

timer_callback_fpt Callback function when timeout occurs

Outputs None

The MIPS34Kc Hardware Abstraction Layer provides low-level hardware control functions that can be used without
the presence of the operating system.

7.9.1 External Interface

The HAL34Kc module provides the following functions:
Table 7-11. HAL Functions

Function Description

hal_int_global_enable Enables all 34Kc interrupts.

hal_int_global_disable Disables all 34Kc interrupts

hal_int_global_restore Restores the interrupt enable bit (IE) status to the corresponding bit
value of the input. Should be used with hal_int_global_disable() to
create a critical section.

hal_reg_write Writes a 32-bit value to the specified memory-mapped register

hal_reg_read Reads a 32-bit value from the specified memory-mapped register.

hal_time_diff Calculates the time difference between the two input times. Can handle
one wrap-around between the two times.

hal_time_us_to_sysclk Converts the input time in microseconds to the equivalent number of

Returns Success = None

Failure = None

Side Effects None

7.9.1.4 hal_reg_write

Prototype void hal_reg_write(

UINT32 addr,
UINT32 value)

Inputs addr Address to write to

value Value to write to address

Outputs None

Returns Success = None

Failure = None

Side Effects None

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Device Drivers

7.9.1.5 hal_reg_read

Prototype UINT32 hal_reg_read(

UINT32 addr)

Inputs addr Address to write to

Outputs None

Returns Success = Value of register read

Failure =

Side Effects None

7.9.1.6 hal_time_diff
Use hal_time_diff()to calculate the time difference between the two 32-bit input times. It can handle one wrap-
around between the two times but cannot differentiate between multiple wrap-arounds and a single wrap-around.

Prototype UINT32 hal_time_diff(

UINT32 time1,
UINT32 time2)

Device Drivers

Prototype void m34khal_mem_cache_line_create(UINT32 start_addr, UINT32

num_lines)

Inputs start_addr

num_lines

Outputs None

Returns Success = None

Failure = None

Side Effects None

7.9.1.12 m34khal_mem_cache_line_wb_inv
The m34khal_mem_cache_line_wb_inv () function writes back and invalidates the cache line.

Prototype void m34khal_mem_cache_line_wb_inv(UINT32 start_addr, UINT32

num_lines)

Inputs start_addr

num_lines

Outputs None

Returns Success = None

Failure = None

Side Effects None

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Initialization String

8. Initialization String
The initialization string is a data structure that defines the operational configuration for the firmware. The SXP 12G
device provides several sources for the initialization information.

8.1 Flash Memory Initialization String

The flash memory initialization string is in the flash memory device at a fixed sector and address. During system
initialization the main firmware checks which initialization string partition is active from the boot configuration partition.
The checksum of the active data partition is verified first. If it is valid, firmware sets the current initialization string
pointer to this partition. If it is not valid, firmware verifies the inactive data partition. If it is valid, it sets the current
initialization string pointer to the inactive data partition area, and then toggles the active data partition flag in the
boot configuration partition and logs this event. You can query the active data partition information through an SES
command. The flash memory initialization string must exist and be valid for the firmware to be operational.

8.2 SEEPROM Initialization String

Optionally, a portion of the initialization string information may be collected from an external EEPROM over the TWI.
The EEPROM portion of the initialization string is identified using parameters within the flash memory initialization
string. As with the flash memory copy, the EEPROM portion of the image is first verified using the checksum. If it is
valid, the section of the initialization string is read from the EEPROM to add to the operational parameter set.

8.3 Initialization String Format

8.3.1 Flash Memory Initialization String Format

Table 8-1 shows the complete initialization string table format for the SXP 12G devices. The default values apply to
the 68-port devices (that is, SXP 68x12G). When used on a 24, 36 or 48-port device (SXP 24x12G/SXP 24Sx12G,
SXP 36x12G/SXP 36Sx12G and SXP 48x12G), the per-port fields run from 0 to 23, 35, or 47 instead of 0 to 67.
Fields 24 to 67 for 24-port, 36 to 67 for 36-port and 48 to 67 for 48-port device are reserved. In the initialization string
tables, the parameters without highlighting apply to all devices.
Note All reserved fields must be set to zero.
SXP 12G firmware provides default values for configuration parameters. Those parameter values can be adjusted
based on a user’s actual usage and resource conditions, for example, the use of external SRAM for event logging,
increased memory size in the link file for supporting more outstanding commands, and so on. Simply increasing
parameter values to a larger value might cause issues such as firmware asserts due to resource constraints.
When accessing the initialization string, parameters in the initialization string may not have their byte fields on a
boundary that matches the intended data type. To avoid memory alignment issues, the firmware function should read
the parameter as a byte array. For example:
If there is a field named “Field_example” which has a 16-bit value, and it is defined in the Initialization String as
follows.
Offset Description
0x00 Offset_0x00_field
… …
0x03 Field_example_Byte0 (MSB) //Note the offset is 0x03 that isn’t good for a UINT16.
0x04 Field_example_Byte1 (LSB)
There will be a memory alignment issue if “Field_example” is accessed with:
UINT16 Field_example = (UIN16*)&Field_example_Byte0.
The correct operation should be:

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Initialization String

UINT16 Field_example = (Field_example_Byte0 << 8) | Field_example_Byte1

Table 8-1. Initialization String Table

Byte Allocation

0x0000 –0x0036 Device Identification Configuration Block (Table 8-3)

0x0037 – 0x0050 Device Addressing Configuration Block (Table 8-5 )

0x0051 – 0x00FF Topology Discovery Configuration Block ( Table 8-7)

0x0100 – 0x01FF PHY & SGPIO Mapping Configuration Block (Table 8-8)

0x0200 – 0x112F PHY Configuration Block (Table 8-9 and Table 8-2)

0x1130 – 0x127F PHY Connector Configuration Block (Table 8-17 Table 8-11)

0x1280 – 0x129F Additional PHY Event Source Configuration Block ( Table 8-18)

0x12A0 – 0x131F SGPIO Configuration Block (Table 8-19)

0x1320 – 0x132F CMDSVR Configuration and SPS Configuration (Table 8-23 ) and TWI Blocks (Table 8-24)

0x1330 – 0x134F GPIO Configuration Block (Table 8-25 )

0x1350 - 0x135F Pin Drive Strength Ctrl (Table 8-26)

TCP/IP Stack Configuration Block (

0x1360 – 0x13DF Table 69 SXP 12G Initialization String—TCP/IP Stack Configuration)

0x13E0 - 0x13FF EPOW Configuration Block (Table 8-29)

0x1400 - 0x14BF Error Logging Configuration (Table 8-30)

0x14C0 - 0x14DF WOL/WOS Configuration Block (Table 8-31)

0x14E0 – 0x182F Reserved for new features

0x1830 – 0x186F Operating System Configuration Block (Table 8-32)

0x1870 – 0x18AF Protocol Configuration Block (Table 8-34)

0x18B0 – 0x190F EMA Configuration Block (Table 8-36)

0x1910 – 0x191F Redundant Virtual SSP Link Configuration Block (Table 8-38)

0x1920 – 0x192F Disk Qualification, SIA and SAHA Configuration Block (Table 8-39)

0x1930 – 0x193F Disk Spin-Up Configuration Block (Table 8-40)

0x1940 – 0x19DF SSU Configuration Block (Table 8-45)

0x19E0 – 0x19EF Non-I/O Disruptive Soft Reset (NDSR) Configuration Block (Table 8-46)

0x19F0 – 0x1A3F Zoning Configuration Block (Table 8-47)

0x1A40 – 0x1A8F Zoning PHY Group ID Mapping Configuration Block (Table 8-48)

Zone Manager Password and Saving Support Configuration Block (

Table 90 SXP 12G Initialization String—Zone Manager Password and Saving Support
0x1A90 – 0x1ACF Configuration)

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Initialization String

...........continued
Byte Allocation

0x1AD0 – 0x1AFF Virtual SSP/SMP Zoning Configuration Block (Table 8-50)

0x1B00 – 0x2BFF Zoning Permission Table Configuration Block (Table 8-51)

0x2C00 – 0x33FF Reserved (Customer proprietary extension block – 2 Kbytes)

0x3400 – 0x37FF Reserved (Microchip extension block – 1 Kbyte)

0x3800 – 0x3FF7 Patch Table Configuration Block (Table 8-54)

Table 8-2. PHY Configuration Settings

Byte \ Bit 7 6 5 4 3 2 1 0 Default Value Range

0x0230 – Reserved Break Reply Async Invert TX Invert RX No SATA Disable 0x00 Bit Fields
0x025F Enable Recovery PHY
(L_PHY0 Disable
Info)
Max SATA Rate PHY Rate 0x4F PHY rate {1,
2, 3, 4, 6,
7,8,10,11,12,14,15}

Max SATA rate {0,

1, 2, 4}

G4 WITH G4 G3 WITH SSC G3 G2 G2 WITHOUT G1 WITH G1 0xFF

SSC WITHOUT WITHOUT WITH SSC SSC WITHOUT
SSC SSC SSC SSC

TX_ID_FRAME_GAP RX 3 ID TX 3 ID 0xC0
FRAMES FRAMES

TX SSC Reserved 0x00

Down-
Spread
Type

STP Bridge AWT MSB 0x00 0x00–0xFF

STP Bridge AWT LSB 0x00 0x00–0xFF

Connection Policing Timer 0x00 0x00 – 0xFF

Power Disable Broad-cast Reserved STP Align Density SAS Align Density 0x00 STP/SAS ALIGN
Disable Advance change Suppress density  {0, 1, 2}
Supported SATA Sync
Forward

Reserved 0x00

Reserved LOS CTRL SAS LOS REFAMP SAS[4:0] 0x12

RX PEAK Reserved LOS CTRL SATA LOS REFAMP SATA[4:0] 0x09

ENB SATA
0x09
6G

RX PEAK RX PEAK Reserved RX PEAK SAS[2:0] 0x01

ENB SAS1 ENB SAS1
3G 1G5

RX PEAK RX PEAK RX PEAK SATA 6G[5:3] RX PEAK SATA 1G5 3G[2:0] 0x29
ENB SATA ENB SATA
3G 1G5

T PISO AMPLITUDE SAS 1G5 [6:0] 0x36

PRE2 SEL
SAS 1G5

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Initialization String

...........continued
Byte \ Bit 7 6 5 4 3 2 1 0 Default Value Range

T PISO AMPLITUDE SAS 3G [6:0] 0x36

PRE2 SEL
SAS 3G

T PISO AMPLITUDE SAS2 6G [6:0] 0x40

PRE2 SEL
SAS2 6G

T PISO AMPLITUDE SATA 1G5 [6:0] 0x1C

PRE2 SEL
SATA 1G5

T PISO AMPLITUDE SATA 3G [6:0] 0x1C

PRE2 SEL
SATA 3G

T PISO AMPLITUDE SATA 6G [6:0] 0x30

PRE2 SEL
SATA 6G

T PISO T PISO EDGE POSTCURSOR SAS 1G5 [5:0] 0xC0

EDGE DELAY SEL SAS
DELAY 1G5
SEL SATA
1G5

T PISO T PISO EDGE POSTCURSOR SAS 3G [5:0] 0xC0

EDGE DELAY SEL SAS
DELAY 3G
SEL SATA
3G

T PISO T PISO EDGE POSTCURSOR SAS2 6G [5:0] 0x0D

EDGE DELAY SEL
DELAY SAS2 6G
SEL SATA
6G

TRS TXCLK SEL SATA 1G5 POSTCURSOR SATA 1G5 [5:0] 0x00
SSC

TRS_TXCLK SEL SATA 3G POSTCURSOR SATA 3G [5:0] 0x00

SSC

TRS TXCLK SEL SATA 6G SSC POSTCURSOR SATA 6G [5:0] 0x05

Reserved PRECURSOR SAS 1G5[5:0] 0x00

Reserved PRECURSOR SAS 3G [5:0] 0x00

Reserved T PISO PRE2 PRECURSOR SAS2 6G [5:0] 0x40

MODE1 SAS2 6G

Reserved PRECURSOR SATA 1G5 [5:0] 0x00

Reserved PRECURSOR SATA 3G[5:0] 0x00

Reserved T PISO PRE2 PRECURSOR SATA 6G[5:0] 0x40

MODE1 SATA 6G

SAS12G TX Cx BCT PRST Reserved TX BCT EN SAS3 12G 0x44

Reserved
PGA DFLT
BOOST EN

TX C1 NON BCT 0xFF

TX C2 NON BCT 0x33

TX C3 NON BCT 0xF4

TX C1 BCT START POINT 0xFB

TX C2 BCT START POINT 0x33

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Initialization String

...........continued
Byte \ Bit 7 6 5 4 3 2 1 0 Default Value Range

TX C3 BCT START POINT 0xF8

Reserved SAS/SATA 0x00

Buffering
Enable

Reserved SAS 6G/3G SAS 12G Connection SAS SAS 0x02

Buffering Buffering Management Buffering 6G Buffering
Connection
Snoop OAF Early 3G
Management Enable
TMF Accept
Enable Enable Enable

Reserved 0x00

Maximum Frame Count 0x16

Reserved Reserved SATA Buffering SATA 0x02

6G Buffering
3G

Reserved 0x00

Reserved DP FFE M PRELOAD SAS3 12G 0x1F

Reserved Test Threshold 0x0C

0x0260 – Structure content is the same as that for L_PHY0 Info Same as
0x028F L_PHY0
(L_PHY1
Info)

0x0290 – … …
0x0EBF
(L_PHY3
–
L_PHY66
Info)

0x0EC0 – Structure content is the same as that for L_PHY0 Info Same as
0x0EEF L_PHY0
(L_PHY67
Info)

0x0EF0 – Reserved 0x00

0x0112F

0x020C PHY reset PHY reset in progress timeout 0x0F

timeout
0x0F
handling
Enable

Detailed descriptions of each of the blocks within the initialization string table are provided in the following table.
Table 8-3. Initialization String Table—Identification Configuration

Bit/Byte 7 6 5 4 3 2 1 0 Default

0x0000 Reserved For Customer Usage Only 0x00

0x0001 Table Version – Major (Microchip) Table Version - Minor (Microchip) 0x47

Non- Use
strict Default
0x0002 Reserved 0xC0
Check- Ident-
ing ification

0x0003 – 0x0006 Table Revision (vendor-specific) 0x00

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Initialization String

...........continued
Bit/Byte 7 6 5 4 3 2 1 0 Default

0x0007 – 0x000E Manufacturer Information: Vendor ID (8 bytes) “”

0x000F – 0x0001E Manufacturer Information: Product ID (16 bytes) “”

0x001F – 0x0022 Manufacturer Information: Product Revision (4 bytes) “”

0x0023 – 0x002A Manufacturer Information: Component Vendor ID (8 bytes) “”

0x002B Manufacturer Information: Component ID [15:8] 0x00

0x002C Manufacturer Information: Component ID [7:0] 0x00

0x002D Manufacturer Information: Component Revision 0x00

0x002E Reserved 0x00

0x002F – 0x0036 Manufacturer Information: Vendor Specific (8 bytes) 0x00

8.3.1.1 Non-strict Checking Field

If the non-strict checking bit is set, the firmware allows various members of the same device family and device
revisions to use the same initialization string without modification.
Note Firmware may truncate or modify certain parameters, for example, PHY count or subtractive PHY map, to a
smaller number or range depending on the device that the firmware detects.

8.3.1.2 Use Default Identification Field

If this field is set to:
1: The firmware uses the default identification settings shown in the following table when the manufacturer
information is queried.
0: The information stored in the manufacturer information fields is used.
Table 8-4. Default Manufacturer Identification Information

Manufacturer Information Default Value Notes

Field

Vendor ID “Microchip”

Product ID “SXP 24x12G” “SXP 36x12G” 24-port 12G expander 36-port 12G expander
“SXP 48x12G” “SXP 68x12G” 48-port 12G expander 68-port 12G expander
“SXP 24Sx12G” 24-port 12G expander (PM8043)
“SXP 36Sx12G” “Unknown 36-port 12G expander (PM8044)
device”
Unknown device

Product Revision “RevB” Revision B

“RevA” ”UNKN” Revision A Unknown revision

Component Vendor ID “PMCSIERRA”

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Initialization String

...........continued
Manufacturer Information Default Value Notes
Field

Component ID 0x8056 0x8055 SXP 68x12G SXP 48x12G

0x8054 SXP 36x12G
0x8053 SXP 24x12G
0x8044 SXP 36Sx12G
0x8043 SXP 24Sx12G

Component Revision 2 Revision B

0 Revision A

8.3.1.3 Table Version Field (Microchip)

The Table Version field (Microchip) is used to define the version of the default Init String from the Microchip SXP 12G
SDK. For example, for 04.03 version firmware, this field is 0x43.
Firmware checks this Table Version during the initialization phase, if the version of the Active Init String is lower than
the Active Firmware Image, firmware enters Safe mode which permits you to update the Init String with the Microchip
Register GUI.

8.3.1.4 Table Revision Field (Vendor-Specific)

The Table Revision field lets the system integrator assign a number indicating the specific revision for the initialization
string data stored in flash memory. The expander firmware does not use this field. By default, it should be big
endianness.

8.3.1.5 Manufacturer Information Fields

Vendor Identification
The 8-byte vendor identification in the SMP REPORT MANUFACTURER INFORMATION response when the “Use
Default Identification” bit is set to 0.
Product Identification
The 16-byte product identification in the SMP REPORT MANUFACTURER INFORMATION response when the “Use
Default Identification” bit is set to 0.
Product Revision
The 4-byte product revision string in the SMP REPORT MANUFACTURER INFORMATION response when the “Use
Default Identification” bit is set to 0.
Component Vendor Identification
The 8-byte component vendor identification in the SMP REPORT MANUFACTURER INFORMATION response when
the “Use Default Identification” bit is set to 0.
Component Identification
The 2-byte component identification in the SMP REPORT MANUFACTURER INFORMATION response when the
“Use Default Identification” bit is set to 0.
Component Revision
The 1-byte component revision in the SMP REPORT MANUFACTURER INFORMATION response when the “Use
Default Identification” bit is set to 0.
Vendor-Specific String
The 8-byte vendor-specific string the SMP REPORT MANUFACTURER INFORMATION response. This field is
always read when it is queried.

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Initialization String

Table 8-5. Initialization String Table—Device Addressing Configuration

Byte \
7 6 5 4 3 2 1 0 Default Value Range
Bit

ADDRES
0x0037 TWI Serial EEPROM ADDR [7:1] 0xA0
S VALID

TWI Serial
EEPROM Port ID: 0x00 –
0x0038 Reserved TWI Serial EEPROM Port ID 0x00
Offset 0x0B
Width

0x0039 Zone Saved Serial EEPROM ADDR [7:1] Reserved 0xAA

Zone
Saved
0x003A Reserved Serial Zone Saved Serial EEPROM Port ID 0x10
EEPROM
Offset
Width

0x003B SAS_BASE_ADDR [63:56] 0x50

0x003
SAS_BASE_ADDR [55:48] 0x0E
C

0x003
SAS_BASE_ADDR [47:40] 0x00
D

0x003E SAS_BASE_ADDR [39:32] 0x4A

0x003F SAS_BASE_ADDR [31:24] 0xAA

0x0040 SAS_BASE_ADDR [23:16] 0xAA

0x0041 SAS_BASE_ADDR [15:8] 0xAA

SAS_BASE_ADDR [7:N+1] (the bits masked by SAS base address LSB[N:0]

0x0042 0x00
Mask must be 0)

Reserv (PHY_COUNT+
0x0043 SMP SAS address LSB [N:0] 0x7F
ed 1) – 0x7F

Reserv PHY_COUNT –
0x0044 SSP SAS address LSB [N:0] 0x7E
ed 0x7E

Reserv
0x0045 SAS base address LSB[N:0] Mask 0x7F
ed

0x0046 Reserved 0x00

0x0047 Logical SUB_PHY_FLAG (Reserved) 0x00

0x0048 Logical SUB_PHY_FLAG (Reserved) Logical SUB_PHY_FLAG [67:64] 0x00

0x0049 Logical SUB_PHY_FLAG [63:56] 0x00 Bit fields

0x004A Logical SUB_PHY_FLAG [55:48] 0x00 Bit fields

0x004B Logical SUB_PHY_FLAG [47:40] 0x00 Bit fields

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Initialization String

...........continued
Byte \
7 6 5 4 3 2 1 0 Default Value Range
Bit

0x004
Logical SUB_PHY_FLAG [39:32] 0x00 Bit fields
C

0x004
Logical SUB_PHY_FLAG [31:24] 0x00 Bit fields
D

0x004E Logical SUB_PHY_FLAG [23:16] 0x00 Bit fields

0x004F Logical SUB_PHY_FLAG [15:8] 0x00 Bit fields

0x0050 Logical SUB_PHY_FLAG [7:0] 0x0F Bit fields

8.3.1.6 TWI Serial EEPROM Address Field

TWI Serial EEPROM ADDR [7:1] specifies bits 7 to 1 of the serial EEPROM address attached to the TWI port
specified by the TWI Serial EEPROM Port ID field.

8.3.1.7 TWI Serial EEPROM Address Valid Field

This field indicates if the serial EEPROM is available and valid.
If this bit is set to:
0: The serial EEPROM is not accessed.
1: Indicates to the firmware that the serial EEPROM is available – its address is specified by bits 7 to 1 of this field.
Note If the SEEPROM initialization string is invalid, the default serial EEPROM address and port ID are 0xA0 and 0,
respectively.

8.3.1.8 TWI Serial EEPROM Port ID Field

This field specifies the TWI port to which the serial EEPROM is attached.

8.3.1.9 TWI Serial EEPROM Offset Width Field

This field specifies the offset width of the current SEEPROM device at the Port and Address.
0: Offset Width is one byte.
1: Offset Width is two bytes.

8.3.1.10 Zone Saved Serial EEPROM Address Field

Zone Saved Serial EEPROM ADDR [7:1] specifies bits 7 to 1 of the zoning configuration serial EEPROM address
attached to the TWI port specified by the Zone Saved Serial EEPROM Port ID field.

8.3.1.11 Zone Saved Serial EEPROM Port ID Field

This field specifies the TWI port to which the Zone Saved Serial EEPROM is attached.

8.3.1.12 Zone Saved Serial EEPROM Offset Width Field

This field specifies the offset width of the Zone Saved Serial EEPROM device at the Port and Address.
0: Offset Width is one byte.
1: Offset Width is two bytes.

8.3.1.13 SAS Base Address Field

The SAS_BASE_ADDR [63:N] field defines the most significant (63-N) bits of the base address of the SXP 12G
device. The SAS address map of the SXP 12G device in the following table shows the concatenation of the base
address with the valid offsets. The SAS_BASE_ADDR [N:0] bits are reserved and must be set to zero. The definition
of number N is defined in the SAS base address LSB[N:0] Mask field.

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Table 8-6. SAS Address Map

SAS Address Composition Description

[SAS_BASE_ADDR, 0x00] SAS address of the STP Bridge in PHY 0 of the SXP 12G device

[SAS_BASE_ADDR, 0x01] SAS address of the STP Bridge in PHY 1 of the SXP 12G device

[SAS_BASE_ADDR, 0x02] SAS address of the STP Bridge in PHY 2 of the SXP 12G device

: :

[SAS_BASE_ADDR, 0x43] SAS address of the STP Bridge in PHY 67 of the SXP 12G device

SAS address of the SSP virtual port in the SXP 12G device as seen by the
ECMR. By default, the SSP SAS address LSB [N:0] is set to:
[SAS_BASE_ADDR, SSP SAS 0x7E for the PM8056
address LSB [N:0]]
0x3E for the PM8055/PM8054/PM8044
0x1E for the PM8053/PM8043

SAS address of the SXP 12G device. This address also addresses the SMP
function in the SXP. By default, the SMP SAS address LSB [N:0] is set to:
[SAS_BASE_ADDR, SMP SAS 0x7F for the PM8056
address LSB [N:0]]
0x3F for the PM8055/PM8054/PM8044
0x1F for the PM8053/PM8043

8.3.1.14 SMP SAS Address LSB [N:0]

The SMP SAS address LSB [N:0] field defines the least significant (N+1) bits of the SMP SAS address of the SXP
12G device. The value of this field must be set larger than the initialization string SSP SAS address LSB [N:0] field.
The definition of N is defined in the SAS base address LSB[N:0] Mask field.

8.3.1.15 SSP SAS Address LSB [N:0]

The SSP SAS address LSB [N:0] field defines the least significant (N+1) bits of the SSP SAS address of the SXP
12G device. The value of this field must be set less than the value of SMP SAS Address LSB [N:0] field. The
definition of N is defined in the SAS base address LSB[N:0] Mask field.

8.3.1.16 SAS Base Address LSB[N:0] Mask

The SAS base address LSB[N:0] Mask field defines the number of available SAS addresses reserved by an SXP
12G expander for its SSP virtual port, SMP virtual port and all STP bridges. All (N+1) bits from bit 0 to bit N must be
1.
If the value of the SAS base address LSB mask is equal to or less than the value of initialization string field PHY
COUNT, the PHYs with PHY IDs larger than the value of the SAS base address LSB mask or equal to the value
SSP/SMP SAS address LSB[N:0] can`t support SATA drivers. Set the 'no SATA' field in the initialization string for all
PHYs that do not support SATA, otherwise FW will enter minimal safe mode.

8.3.1.17 Logical SUB_PHY_FLAG Field

Each Logical SUB_PHY_FLAG [67:0] bit indicates one logical PHY that performs subtractive routing. The index of a
bit corresponds to the logical.
Table 8-7. Initialization String Table—Topology Discovery Configuration

Byte \ Bit 7 6 5 4 3 2 1 0 Default Value Range

Table to Disable Route Self-

0x0051 table Reserved SSP Target Table Fan-out Expander Reserved Configuring 0x91 Bit Fields
Enable Port Clean-up Expander

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Initialization String

...........continued
Byte \ Bit 7 6 5 4 3 2 1 0 Default Value Range

0x0052 Logical Route Table Entries per PHY [15:8] 0x10

0x00 – 0x1000
0x0053 Logical Route Table Entries per PHY [7:0] 0x00

0x0054 PHY Event Damping Interval [15:8] (in 100us) 0x00

0x00 – 0xFFFF
0x0055 PHY Event Damping Interval [7:0] (in 100us) 0x00

0x01 – PHY_
0x0056 Topology Thread Instances 0x01
COUNT

0x0057 PHY Polling Period (in ms) 0x0a 0x01 – 0xFF

0x0058 Reserved 0x00

0x0059 Reserved 0x00

0x005A Application Level SMP Initiator Maximum Retry Count 0x0A 0x00 – 0xFF

0x005B SATA PHY Validation Count 0x0A 0x0A – 0xFF

Legacy
Bad Open
Global Disk NSCFG Route Expander Wide-port Loop
Destination Reject
0x005C Zoning Qualification Table Compression Route Policing Detect-ion 0x13 Bit Fields
Primitive Retry
Enable Enable Enable Index Enable Enable
Disabled Enable
Disabled

Phy Reset No BC
Report
If Zone FWD if
0x005D Reserved (7:3) Partial 0x05
Phy Info TOPD no
RT(0)
Change change

0x005E –
Reserved (for topology and zoning configuration expansion) 0x00
0x00FF

8.3.1.18 Self-Configuring Expander Field

This bit specifies if the expander is set up as a self-configuring expander. When this bit is set to 0, the expander
reports the presence of a configurable route table.

8.3.1.19 Fan-out Expander Field

This bit indicates to the topology discovery application if the expander is being used as a fan-out expander or an
edge expander.

8.3.1.20 Route Table Cleanup Field

This bit indicates to the topology discovery application whether to clean up the logical route table when a PHY is no
longer active. This configuration bit is valid for non-self-configuring mode. For self-configuring mode, firmware always
cleans up the invalid route table entries.

8.3.1.21 Disable SSP Target Port Field

This bit controls if the expander firmware reports the presence of the virtual SSP target port. Firmware does not
disable the internal virtual PHY, as the virtual SSP Initiator Port is still functional for the DSQ feature.

8.3.1.22 Table-to-Table Enable

This bit controls support for SAS-2 topology discovery. When this bit is:
Set: SAS-2 topology discovery is enabled, and table-to-table connection is allowed in the topology.
Cleared: SAS1.1 discovery is enabled, and table-to-table connection is not allowed in the topology.
See 10.3 Topology Discovery (SAS-2.0) for detail.

8.3.1.23 Logical Route Table Entries per PHY Field

This 16-bit parameter specifies the maximum number of entries allocated in the logical route table per PHY. The
parameter range is 0 to 4096.
Logical route entry is allocated for each PHY (regardless of being connected to a device), of the expanders
discovered. This field limits the total number of expander PHYs discovered from each host expander PHY. Logical

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Initialization String

Route Table Entries for expander PHYs discovered beyond the number defined in this field cannot be added into the
host expander route table.

8.3.1.24 PHY Event Damping Interval Field

This 16-bit field controls the rate at which broadcast primitives are generated and forwarded as a result of detecting
changes in the PHY status. Refer to Section 10.1.1 Architecture, item 10.1.1 Architecture for further information.
This parameter’s unit is 100 μs. The default value is zero, which means damping is disabled.

8.3.1.25 Topology Thread Instances Field

This field specifies the number of simultaneous threads that perform topology discovery. The range of this field is
between 1 and PHY_COUNT.

8.3.1.26 PHY Polling Period Field

This field specifies the interval at which PHYs are polled to determine their status. The interval unit is milliseconds.
The PHYs are polled at each interval. A value of 0 is not allowed.

8.3.1.27 Application Level SMP Initiator Maximum Retry Count Field

This parameter specifies the number of retries the firmware’s application executes when initiating an SMP command
after the command fails. A value of 0 indicates that no retries are initiated when an SMP command fails.

8.3.1.28 SATA PHY Validation Count Field

This parameter specifies the number of polling intervals to validate SATA attached devices.

8.3.1.29 Loop Detection Enable Field

This field specifies if the firmware topology loop detection and disable feature is enabled. This field is applicable if the
expander is self-configuring.
There are two types of loops that are detected:
• sub-tree loops
• attached loops
Attached loops contain the host expander and sub-tree loops do not contain the host expander. These loops must
consist entirely of non-self-configuring expanders (except for the host). Mixed expander-type loops may be detected
but only in a very limited set of cases.
An attached loop is detected when a non-host-child expander is discovered with the same attached SAS address
field as the host's. In this case, the SAS addresses of the host are compared to the parent of the expander being
discovered. The PHYs in the expander with the larger SAS address are disabled – breaking the loop – and topology
discovery is restarted.
A sub-tree loop is detected when the host tries to add a discovered expander to its route table, but that entry is
already there. The parent information for this expander is already in the route table and determines which PHYs to
disable.
In the mixed expander-type topology, loops are detected when copying route tables from a descendent SCFG
expander. Attached loops are detected when the route table being copied contains the host expander. Sub-tree loops
are detected when trying to add the new entries to the host route table, but it already contains the same entry. These
methods work only if the copied tables are correct. The loop requires either a table-to-table expander connection, or a
subtractive loop with no head node. Since the distributed algorithm depends on the spanning tree topology it may not
have configured the tables correctly. In the case of a subtractive loop, it may never converge. For these reasons loop
detection in mixed topologies is unreliable.
PHYs are disabled using the SMP PHY Control Disable function and can be re-enabled with a PHY Control Link or
Hard Reset, or by resetting the expander.

8.3.1.30 Wide-Port Policing Enable Field

This field specifies if the firmware subtractive wide-port policing feature is enabled. When enabled, the firmware
isolates PHYs that violate any one of the following rules:
• The PHY does not have the subtractive attribute but is part of a wide port that has least one PHY with the
subtractive attribute.
• The PHY is subtractive, but is part of a wide port where at least one other PHY is not subtractive.

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• The PHY is subtractive, but there is an existing PHY with the subtractive attribute that is not in a wide port with
this PHY.
• To isolate PHYs, the ECMR entries of the subtractive ports, or non-subtractive ports, or both, upon which the
PHYs had been ready, is invalidated and the LEDs for these PHYs are lit red. Users should remove the cables
immediately if any LEDs are lit red. The PHY can come back after removing the cable. If a PHY is invalidated,
then firmware will report 'no device attached' for the SMP discover request.
Note: Wide-Port Policing is only effective for the PHYs that are connecting expanders.

8.3.1.31 Legacy Expander Route Index Disabled Field

This field turns on (1) or off (0) the EXPANDER ROUTE INDEX field if REPORT GENERAL is set to zero when it
functions as a self-configuring expander.

8.3.1.32 NSCFG Route Table Compression Enable Field

This field turns on (1) or off (0) the route table compression feature when the device is operating in a non-self-
configuring mode.

8.3.1.33 Open Reject Retry Enable Field

When this field is set to:
1: The expander device returns OPEN_REJECT(RETRY) for any connection requests that would otherwise have
resulted in OPEN_REJECT(NO DESTINATION) while the CONFIGURING bit is set to one.
0: The expander device returns OPEN_REJECT(NO DESTINATION) for any connection requests (complies with
SAS1.1)

8.3.1.34 Disk Qualification Enable Field

The field turns on (1) or off (0) the disk-qualification feature on a zoning-capable expander device.

8.3.1.35 Bad Destination Primitive Disabled Field

When this field is set to:
1: The expander device converts all OPEN_REJECT(BAD_DESTINATION) to OPEN_REJECT(NO DESTINATION)
primitives.
0: The expander device does not convert OPEN_REJECT(BAD_DESTINATION) to OPEN_REJECT(NO
DESTINATION) primitives.

8.3.1.36 Global Zoning Enable Field

This field enables (1) or disables (0) the zoning feature of a zoning-capable expander device.
If this field is set to 1, the expander device is configured to be a self-configuring expander device regardless of the
self-configuring expander bit setting.
Setting this bit to 1 enables the zoning capability of the expander device. All zoning-related SMP functions are
supported by the expander device. If this bit is set to zero, the expander device will return an UNKNOWN SMP
FUNCTION response for any zoning-related SMP functions.

8.3.1.37 Report Partial RT

This bit enables the Microchip proprietary topology discovery algorithm between two SXP 12G expanders to speed
up the TOPD process. If this bit is enabled in the SMP initiator, the initiator will set a Microchip-specific bit in its SMP
Report Route Table List request frame (bit 0 in byte 20). If this bit is enabled in the SMP target, the target will check
whether the Microchip-specific bit in its received SMP Report Route Table List request frame (bit 0 in byte 20) is set.
If both bits are set as 1, the SMP target will not report the route table entries of the PHYs that are in the current SMP
connection to the SMP initiator. If this bit is not set, the SMP target still reports all route table entries of all PHYs to
the SMP initiator.

8.3.1.38 No BC FWD if TOPD no change

This bit enables the Microchip proprietary topology discovery improvement. When an expander receives a Broadcast
(Change) primitive from another expander, it will launch a new topology discovery procedure for this expander. By
default, no matter whether there is any new route entry found during this TOPD, the expander will forward this BC to
other PHYs. If this bit is set as “1”, then only when the route table is changed due to any route entry is newly added
or removed, expander will forward this BC to other PHYs, otherwise expander will not forward this BC to other PHYs
to avoid some unnecessary traffic.

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Initialization String

8.3.1.39 PHY Reset If Zone PHY Info Change

A PHY needs to be reset for a zone PHY information change to take effect.
If this field is set to 1, it is enabled and the related PHYs are reset automatically by firmware when zone PHY
information changes.
If this field is set to 0 it is disabled and the related PHYs are not reset automatically by firmware when related zone
PHY information changes. This requires the zone manager to reset the PHYs manually.
Table 8-8. Initialization String Table—PHY and SGPIO Map Configuration

Byte \
7 6 5 4 3 2 1 0 Default Value Range
Bit

1 – [24, 36, 48 or
0x0100 PHY_COUNT 0x44
68]

0x0101 Reserved 0x00

Logical
PHY 0
Reserve 0 – [23, 35, 47 or
map Physical PHY_ID (P_PHY_ID) 0x00
d 67]
(0x010
2)

Logical
PHY 1
Reserve 0 – [23, 35, 47 or
map Physical PHY_ID (P_PHY_ID) 0x01
d 67]
(0x010
3)

... ... ... ...

Logical
PHY
Reserve 0 – [23, 35, 47 or
67 map Physical PHY_ID (P_PHY_ID) 0x43
d 67]
(0x014
5)

0x0146
– Reserved 0x00
0x0151

Logical 0 – [23, 35, 47 or

SGPIO Drive Slot 0x00
PHY 0 67]
map
(0x015 0~16 Bus ID=0;
2- SGPIO Drive 17~ 33 ID=1;
Reserved 0~3
0x0153 Slot Bus ID 34~50 ID=2;
) 51~67 ID=3

Logical 0 – [23, 35, 47 or

SGPIO Drive Slot 0x01
PHY 1 67]
map
(0x015 0~16 Bus ID=0;
4- SGPIO Drive 17~ 33 ID=1;
Reserved BUS ID = {0 ~ 3}
0x0155 Slot Bus ID 34~50 ID=2;
) 51~67 ID=3

... ... ...

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Initialization String

...........continued
Byte \
7 6 5 4 3 2 1 0 Default Value Range
Bit

Logical 0 – [23, 35, 47 or

SGPIO Drive Slot 0x43
PHY 67]
67 map
(0x01D 0~16 Bus ID=0;
8- SGPIO Drive 17~ 33 ID=1;
Reserved 0~3
0x01D Slot Bus ID 34~50 ID=2;
9) 51~67 ID=3

0x01D
A– Reserved 0x00
0x01FF

8.3.1.40 PHY_COUNT Field

The PHY_COUNT field specifies the number of logical PHYs that are enabled. The enabled logical PHY identifiers
(IDs) range from 1 to (PHY_COUNT-1). Values for the PHY_COUNT field range from:
1 to 68 for the SXP 68x12G device
1 to 48 for the SXP 48x12G
1 to 36 for the SXP 36x12G/SXP 36Sx12G
1 to 24 for the SXP 24x12G/SXP 24Sx12G device.
If the value of PHY_COUNT is changed, the fields of the logical subtractive PHY flags and Disk Drive Count may
need to be updated accordingly to match the new PHY_COUNT range.

8.3.1.41 PHY and SGPIO Maps

Starting at offset 0x0102, each logical PHY map specifies a physical PHY identifier with which the logical PHY is
associated. A logical PHY map may specify any one of the up to 68 physical PHYs, in no particular order. However,
no two logical PHYs may map to the same physical PHY. The mapping for logical PHYs 0 to (PHY_COUNT-1) must
be specified.
The SGPIO map provides a mechanism to map between logical PHY identifiers and the SGPIO drive slot. This
mapping starts at offset 0x0152. A logical PHY map may specify any one of the up to 68 SGPIO physical drive slots,
in no particular order. No two logical PHYs may map to the same SGPIO drive slot. The mapping for logical PHYs 0
to (drive slot count - 1) must be specified.

8.3.1.42 SGPIO Drive Slot Bus ID

This field indicates which PHYs are associated with which SGPIO Bus ID.
Table 8-9. SXP 12G Initialization String Table—PHY Configuration Global Setting
Byte \ Bit 7 6 5 4 3 2 1 0 Default Value Range

0x0200 Reserved 0x00 Bit Field

0x0201 Reserved 0x00

0x0202 Reserved 0x00

STP OPEN
0x0203 Reserved 0x01
REJECT AWT Clear

0x0204 TX BCT C1 MAX 0x00

0x0205 TX BCT C1 MIN 0xF6

0x0206 TX BCT C3 MAX 0x00

0x0207 TX BCT C3 MIN 0xED

0x0208 TX BCT VPP MAX 0x40

0x0209 TX BCT VMA MIN 0x06

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Byte \ Bit 7 6 5 4 3 2 1 0 Default Value Range

DP FFE M
0x020A PRELOAD SAS3 Reserved DP FFE M PRELOAD SAS3 12G 0x1F
12G Global Disable

Test Threshold
0x020B – 0x020F Reserved 0x00
Enable

0x0210 TMF Tag0 (MSB) 0xFF

0x0211 TMF Tag0 (LSB) 0xFE

0x0212 TMF Tag1 (MSB) 0xFF

0x0213 TMF Tag1 (LSB) 0xFF

0x0214 SAS Buffering Initiator Retry Timeout (MSB) 0x3A

0x0215 SAS Buffering Initiator Retry Timeout (LSB) 0x98

0x0216 Reserved Xopen Detect En Multi-LUN En 0x00

0x0217 – 0x0219 Reserved 0x00

0x021A Reserved 0x00

SATA Buffering Link

STP open control
0x021B Reserved Reset Error PHY 0x00
disable
Enable

0x021C – 0x022F Reserved 0x00

Phy reset timeout

0x020C Phy reset in progress timeout 0x0f
handling Enable

• The “STP OPEN REJECT AWT Clear” field, when set to 1, tells the expander device to clear the arbitration
wait timer every time it receives an OPEN_REJECT(RETRY) primitive, rather than incrementing the value as it
normally would. This setting is only valid when the PHY is in the STP mode of operation.
• TX BCT Cx MAX and TX BCT Cx MIN(x=1 or 3) fields define the limit (maximal or minimal value) for transmitter
Cx (Cx is coefficient x, x=1 or 3). TX BCT Cx MAX is the product of the Cx maximal value (defined in SAS-3
specification) multiplied by 64, and rounded to the nearest integer. TX BCT Cx MIN is the product of the Cx
minimal value (defined in SAS-3 specification) multiplied by 64, and rounded to the nearest integer.
• TX BCT VPP MAX fields define the maximal peak-to-peak voltage to constrain |C1|+|C2|+|C3|<= TX BCT VPP
MAX
• TX BCT VMA MIN fields define the minimal voltage modulation amplitude to constrain C1+C2+C3>= TX BCT
VMA MIN
• DP FFE M PRELOAD SAS3 12G field defines the preload value for DP_FFE_M_PRELOAD_SAS3_12 when the
initial string field “SAS12G PGA BOOST EN” is set to 1.
Byte \ Bit 7 6 5 4 3 2 1 0 Default Value Range

Break Reply Async Recovery Disable

Reserved Invert TX Invert RX No SATA 0x00 Bit Fields
Enable Disable PHY

0x0230 – 0x025F PHY rate {1, 2,

(L_PHY0 Info) 3, 4, 6,
Max SATA Rate PHY Rate 0x4F 7,8,10,11,12,14,
15} Max SATA
rate {0, 1, 2, 4}

G1
G4 WITH G4 WITHOUT G3 WITHOUT G2 WITH G2 WITHOUT G1 WITH
G3 WITH SSC WITHOUT 0xFF
SSC SSC SSC SSC SSC SSC
SSC

RX 3 ID TX 3 ID
TX_ID_FRAME_GAP 0xC0
FRAMES FRAMES

TX SSC
Down-
Reserved 0x00
Spread
Type

STP Bridge AWT MSB 0x00 0x00–0xFF

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Byte \ Bit 7 6 5 4 3 2 1 0 Default Value Range

STP Bridge AWT LSB 0x00 0x00–0xFF

Connection Policing Timer 0x00 0x00 – 0xFF

Power Disable STP/SAS

Broad-cast
Disable Advance SATA Reserved STP Align Density SAS Align Density 0x00 ALIGN density
change Suppress
Supported Sync Forward  {0, 1, 2}

Reserved 0x00

Reserved LOS CTRL SAS LOS REFAMP SAS[4:0] 0x12

RX PEAK LOS REFAMP SATA[4:0]

ENB SATA Reserved LOS CTRL SATA 0x09
6G 0x09

RX PEAK
RX PEAK ENB
ENB SAS1 Reserved RX PEAK SAS[2:0] 0x01
SAS1 1G5
3G

RX PEAK
RX PEAK ENB
ENB SATA RX PEAK SATA 6G[5:3] RX PEAK SATA 1G5 3G[2:0] 0x29
SATA 1G5
3G

T PISO
PRE2 SEL AMPLITUDE SAS 1G5 [6:0] 0x36
SAS 1G5

T PISO
PRE2 SEL AMPLITUDE SAS 3G [6:0] 0x36
SAS 3G

T PISO
PRE2 SEL AMPLITUDE SAS2 6G [6:0] 0x40
SAS2 6G

T PISO
PRE2 SEL AMPLITUDE SATA 1G5 [6:0] 0x1C
SATA 1G5

T PISO
PRE2 SEL AMPLITUDE SATA 3G [6:0] 0x1C
SATA 3G

T PISO
PRE2 SEL AMPLITUDE SATA 6G [6:0] 0x30
SATA 6G

T PISO
EDGE T PISO EDGE
POSTCURSOR SAS 1G5 [5:0] 0xC0
DELAY SEL DELAY SEL SAS 1G5
SATA 1G5

T PISO
EDGE T PISO EDGE
POSTCURSOR SAS 3G [5:0] 0xC0
DELAY SEL DELAY SEL SAS 3G
SATA 3G

T PISO
EDGE T PISO EDGE
POSTCURSOR SAS2 6G [5:0] 0x0D
DELAY SEL DELAY SEL SAS2 6G
SATA 6G

TRS TXCLK SEL SATA 1G5 SSC POSTCURSOR SATA 1G5 [5:0] 0x00

TRS_TXCLK SEL SATA 3G SSC POSTCURSOR SATA 3G [5:0] 0x00

TRS TXCLK SEL SATA 6G SSC POSTCURSOR SATA 6G [5:0] 0x05

Reserved PRECURSOR SAS 1G5[5:0] 0x00

Reserved PRECURSOR SAS 3G [5:0] 0x00

T PISO PRE2
Reserved PRECURSOR SAS2 6G [5:0] 0x40
MODE1 SAS2 6G

Reserved PRECURSOR SATA 1G5 [5:0] 0x00

Reserved PRECURSOR SATA 3G[5:0] 0x00

T PISO PRE2
Reserved PRECURSOR SATA 6G[5:0] 0x40
MODE1 SATA 6G

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Byte \ Bit 7 6 5 4 3 2 1 0 Default Value Range

SAS12G
TX Cx BCT PRST
PGA Reserved TX BCT EN SAS3 12G Reserved 0x44
DFLT
BOOST EN

TX C1 NON BCT 0xFF

TX C2 NON BCT 0x33

TX C3 NON BCT 0xF4

TX C1 BCT START POINT 0xFB

TX C2 BCT START POINT 0x33

TX C3 BCT START POINT 0xF8

SAS/
SATA
Reserved 0x00
Buffering
Enable

6G/3G
SAS 12G Connection
SAS Buffering SAS
Buffering Connection Management
Reserved OAF Early SAS Buffering 6G Buffering 0x02
Snoop TMF Management
Accept Enable Enable 3G
Enable
Enable

Reserved 0x00

Maximum Frame Count 0x16

SATA
Reserved Reserved SATA Buffering 6G Buffering 0x02
3G

Reserved 0x00

Reserved DP FFE M PRELOAD SAS3 12G 0x1F

Reserved Test Threshold 0x0C

0x0260 – 0x028F Same as

Structure content is the same as that for L_PHY0 Info
(L_PHY1 Info) L_PHY0

0x0290 – 0x0EBF
(L_PHY3 – L_PHY66 … …
Info)

0x0EC0 – 0x0EEF Same as

Structure content is the same as that for L_PHY0 Info
(L_PHY67 Info) L_PHY0

0x0EF0 – 0x0112F Reserved 0x00

PHY reset
timeout
0x020C PHY reset in progress timeout 0x0F
handling
Enable

• DP FFE M PRELOAD SAS3 12G Global Disable field determines if the value of “DP FFE M PRELOAD SAS3
12G” (Table 47) would be used as a global configuration or on a per PHY configuration basis; Value should be
set to ‘1’ for setting this on a per PHY configuration; Value should be set to ‘0’ for global configuration.
• Test Threshold Enable field determines whether to use the “Test Threshold” field (Table 47) in the per PHY
configuration. Value 1 means using the “Test Threshold” field in the per PHY configuration area; Value 0 means
not using it.
• PHY reset handling enable and PHY reset in progress timeout: When ‘PHY reset handling’ is enabled, firmware
starts the PHY reset timer when it receives Link Reset or Hard Reset commands. Firmware monitors the timer
value in port manager to check whether link is ready after Link Reset or Hard Reset. If the link is not ready
within the 'PHY Reset in progress timeout' value, then firmware changes the PHY state to 'UNKNOWN' in SMP
discover response. By default, PHY reset handling is disabled.
• TMF Tag0 is used by SSSF to issue TMF with this tag if it detects that TMF Tag0 is not used by the host.
• TMF Tag1 is used by SSSF to issue TMF with this tag if it detects that TMF Tag 1 is not used by the host
already.

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Note: Host shall not use TMF Tag0 or TMF Tag1 to send the TMF frame to the buffering SAS device. If the host uses
TMF Tag0 or TMF Tag1 to send TMF frame to the buffering SAS device, the RESPONSE of the TMF from host will
have a CRC error.
• The SAS Buffering Initiator Retry Timeout field is used by SSSF to retry connections to the host when SSSF
cannot open the host to send out the frames received from the drive. All frames in the SSSF buffer are dropped
when the retry timeout timer expires. This parameter’s unit is 2 ms.
• Note: The default value should ensure there is enough time for OPENs to be retried in a long cascade of
expanders. You can tune this value based on the actual topology.
• The “STP open control disable” field is used to control whether every STP open request from host is processed
by the SSSF firmware or the hardware. When this bit is set to 0, all STP open requests from the host will be
processed by SSSF firmware. In this mode, hosts could be dynamically switched. When it is set to 1, STP open
requests from the host will be processed by SSSF hardware. In this mode, hosts could be dynamically switched
only when the host issues SMP hard reset to the SATA drives after the host is connected into the system. SATA
performance would be improve in this mode.
• The SATA Buffering Link Reset Error PHY Enable field is used to enable/disable a link reset on a SATA PHY
when a retry timeout occurs or when an I/O timeout is detected by SSSF.
• Set this field to “0” to disable this feature. SSSF resets the PHY when it detects the errors mentioned above.
Set this field to “1” to enable this feature. SSSF waits for the host to detect the situation and to complete the proper
error handling. For example, the host performs a link reset on the drive PHY when it detects an I/O timeout.
• The “Xopen Detect En” field, when set to 1 will enable the xopen deadlock detection and recovery logic. Setting
to 0 will disable the logic.
• The “Multi-LUN En” field when set to 1 will enable the SSSF error handling for multi-LUN devices.
Table 8-10. SXP 12G Initialization String Table—PHY Configuration Per PHY
Value
Byte \ Bit 7 6 5 4 3 2 1 0 Default
Range

Async
Reserved Break Reply Enable Recovery Invert TX Invert RX No SATA Disable PHY 0x00 Bit Fields
Disable

PHY rate
0x0230 – 0x025F {1, 2, 3, 4,
(L_PHY0 Info) 6,
7,8,10,11,
Max SATA Rate PHY Rate 0x4F
12,14,15}
Max SATA
rate {0, 1,
2, 4}

G4
G3 WITHOUT G2 WITH G2 WITHOUT G1 WITH G1 WITHOUT
G4 WITH SSC WITHOUT G3 WITH SSC 0xFF
SSC SSC SSC SSC SSC
SSC

RX 3 ID TX 3 ID
TX_ID_FRAME_GAP 0xC0
FRAMES FRAMES

TX SSC
Down-Spread Reserved 0x00
Type

0x00–
STP Bridge AWT MSB 0x00
0xFF

0x00–
STP Bridge AWT LSB 0x00
0xFF

0x00 –
Connection Policing Timer 0x00
0xFF

Disable STP/SAS
Power Disable Advance Broad-cast change ALIGN
Reserved STP Align Density SAS Align Density 0x00
Supported SATA Sync Suppress density 
Forward {0, 1, 2}

Reserved 0x00

Reserved LOS CTRL SAS LOS REFAMP SAS[4:0] 0x12

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Initialization String

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Value
Byte \ Bit 7 6 5 4 3 2 1 0 Default
Range

RX PEAK LOS REFAMP SATA[4:0]

Reserved LOS CTRL SATA 0x09
ENB SATA 6G 0x09

RX PEAK
RX PEAK
ENB SAS1 Reserved RX PEAK SAS[2:0] 0x01
ENB SAS1 3G
1G5

RX PEAK
RX PEAK
ENB SATA RX PEAK SATA 6G[5:3] RX PEAK SATA 1G5 3G[2:0] 0x29
ENB SATA 3G
1G5

T PISO PRE2
AMPLITUDE SAS 1G5 [6:0] 0x36
SEL SAS 1G5

T PISO PRE2
AMPLITUDE SAS 3G [6:0] 0x36
SEL SAS 3G

T PISO PRE2
AMPLITUDE SAS2 6G [6:0] 0x40
SEL SAS2 6G

T PISO PRE2
SEL SATA AMPLITUDE SATA 1G5 [6:0] 0x1C
1G5

T PISO PRE2
AMPLITUDE SATA 3G [6:0] 0x1C
SEL SATA 3G

T PISO PRE2
AMPLITUDE SATA 6G [6:0] 0x30
SEL SATA 6G

T PISO EDGE
T PISO EDGE DELAY
DELAY SEL POSTCURSOR SAS 1G5 [5:0] 0xC0
SEL SAS 1G5
SATA 1G5

T PISO EDGE
T PISO EDGE DELAY
DELAY SEL POSTCURSOR SAS 3G [5:0] 0xC0
SEL SAS 3G
SATA 3G

T PISO EDGE
T PISO EDGE DELAY
DELAY SEL POSTCURSOR SAS2 6G [5:0] 0x0D
SEL SAS2 6G
SATA 6G

TRS TXCLK SEL SATA 1G5 SSC POSTCURSOR SATA 1G5 [5:0] 0x00

TRS_TXCLK SEL SATA 3G SSC POSTCURSOR SATA 3G [5:0] 0x00

TRS TXCLK SEL SATA 6G SSC POSTCURSOR SATA 6G [5:0] 0x05

Reserved PRECURSOR SAS 1G5[5:0] 0x00

Reserved PRECURSOR SAS 3G [5:0] 0x00

T PISO PRE2 MODE1

Reserved PRECURSOR SAS2 6G [5:0] 0x40
SAS2 6G

Reserved PRECURSOR SATA 1G5 [5:0] 0x00

Reserved PRECURSOR SATA 3G[5:0] 0x00

T PISO PRE2 MODE1

Reserved PRECURSOR SATA 6G[5:0] 0x40
SATA 6G

SAS12G PGA
TX Cx BCT PRST DFLT Reserved TX BCT EN SAS3 12G Reserved 0x44
BOOST EN

TX C1 NON BCT 0xFF

TX C2 NON BCT 0x33

TX C3 NON BCT 0xF4

TX C1 BCT START POINT 0xFB

TX C2 BCT START POINT 0x33

TX C3 BCT START POINT 0xF8

SAS/SATA
Reserved Buffering 0x00
Enable

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Value
Byte \ Bit 7 6 5 4 3 2 1 0 Default
Range

SAS
6G/3G 12G Connection
Buffering SAS Buffering
Management SAS Buffering
Reserved Snoop Connection Management OAF Early SAS Buffering 6G 0x02
3G
TMF Accept Enable Enable
Enable
Enable

Reserved 0x00

Maximum Frame Count 0x16

SATA
Reserved Reserved SATA Buffering 6G 0x02
Buffering 3G

Reserved 0x00

Reserved DP FFE M PRELOAD SAS3 12G 0x1F

Reserved Test Threshold 0x0C

0x0260 – 0x028F Same as

Structure content is the same as that for L_PHY0 Info
(L_PHY1 Info) L_PHY0

0x0290 – 0x0EBF
(L_PHY3 – … …
L_PHY66 Info)

0x0EC0 – 0x0EEF Same as

Structure content is the same as that for L_PHY0 Info
(L_PHY67 Info) L_PHY0

0x0EF0 – 0x0112F Reserved 0x00

PHY reset
timeout
0x020C PHY reset in progress timeout 0x0F
handling
Enable

Each of the PHYs contains the following parameters that can be configured individually.
Note: The values in the tables reflect the hardware reset default and do not necessarily specify any particular
signaling levels.
• The “Disable PHY” field configures PHY n to startup in a disabled state. Normally, the PHY tries to establish a
serial connection. By defaulting to the disabled state, the PHY must be enabled under SMP control for the link to
start.
• The “No SATA” field prevents PHY n from negotiating with a SATA drive. This configures the SSPL
SATA_BRIDGE register bit to logic 0 so that it only uses SAS OOB. No SATA OOB is completed.
• The “Invert TX” field inverts the serial transmit data sent on the transmitter differential pair of PHY n.
• The “Invert RX” field inverts the serial receive data received on the receiver differential pair of PHY n.
• The “Async Recovery Disable” field tells the expander not to support SATA asynchronous signal recovery. When
Async Recovery is enabled, the expander transmits a COMRESET OOB signal after it receives an unexpected
COMINIT OOB signal from a device PHY. When disabled, no COMRESET OOB signal is transmitted when the
expander receives an unsolicited COMINIT OOB sequence.
• The “Break Reply Enable” field controls the PHY capability of responding to received BREAK primitive
sequences with a BREAK_REPLY primitive sequence. When set to:
– 0: Break Reply is disabled
– 1: Break Reply is enabled.
• The “PHY Rate” field specifies the rate that PHY n supports. This field prevents speed negotiation at link rates
not defined in this field. This field is also used by the firmware to report the minimum and maximum rates of the
PHY. The supported PHY Rates are shown in the following table.
Table 8-11. PHY Rate Setting

PHY Rate Setting Description

1 1.5G only

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PHY Rate Setting Description

2 3.0G only

3 Both 1.5G and 3.0G

4 6.0G only

6 Both 3.0G and 6.0G

7 1.5G, 3.0G and 6.0G

8 12.0G

10 3.0G and 12.0G

11 1.5G, 3.0G and 12.0G

12 6.0G and 12.0G

14 3.0G , 6.0G and 12.0G

15 1.5G, 3.0G , 6.0G and 12.0G (default)

Any other value Reserved

Note:
• This field controls SAS 1.1 and the SATA link rate, and controls the SAS 2.0/2.1 link rate with SNW PHY
capability field (initialization string 0x0232 field).
• The “Max SATA Rate” field limits the SATA speed negotiation to the maximum rate as shown in the following
table. If the “Max SATA Rate” exceeds the capability of “PHY Rate”, “Max SATA Rate” is not valid, and the actual
connection PHY rate with SATA drive will be configured by the “PHY Rate” setting only.
• When “PHY Rate” is configured to both 3G and 6G support, and “Max SATA Rate” is configured to 3G, the
firmware does not support the attachment of a 1.5G-only SATA drive.
Table 8-12. Maximum SATA Rate Limit

Max SATA Rate Setting Description

0 The maximum rate is controlled by the PHY Rate Setting and the attached disk
drive

1 up to 1.5G

2 up to 3.0G

4 up to 6.0G (default)

8 TBD

Any other value Reserved

The “G1/G2/G3/G4_WITH_SSC” and “G1/G2/G3/G4_WITHOUT_SSC” fields work with the PHY Rate field to
determine SAS 2/3 spread spectrum clocking support for PHYn in SAS operation mode at PHY rates G1/G2/G3/G4.
Table 8-12 lists the most frequent settings for the supported SAS 2.0/2.1 link rates. For unsupported link rates, the
related SNW3 PHY Capability fields are ignored by firmware and are highlighted in the following table.

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Table 8-13. Settings for Supported SAS 2.0/2.1 Link Rates

PHY RATE[3:0] SNW3 PHY Capabilities

G2 with/
Supported Link Bit 0 Bit 1 Bit 2 Bit 0 without
Rate (1.5G) (3G) (6G) (1.5G) Bit 1 (3G) SSC Bit 0 (1.5G) Bit 1 (3G)

1.5G 1 0 0 0 1[1]

3G 0 1 0 0 1[1]

6G 0 0 1 0 1

12G 0 0 0 1 1

1.5G/3G 1 1 0 0 1[1] 1[1]

1.5G/3G/6G 1 1 1 0 1 1 1

1.5G/3G/6G/12G 1 1 1 1 1 1 1 1

3G/6G 0 1 1 0 1 1

3G/6G/12G 0 1 1 1 1 1 1

6G/12G 0 0 1 1 1 1

• Note [1]:
– For connecting the legacy SAS1 device, the corresponding bits in SNW3 PHY Capabilities are optional.
• The “TX_ID_FRAME_GAP” fields specify the number of SYSCLK cycles between transmissions of two ID
frames. This is only valid when TX_3_ID_FRAMES is set to ‘1’.
• The “TX_3_ID_FRAMES” field specifies whether to enable to transmit 3 identify frames. The value of ‘1’
indicates to enable to transmit three identify frames.
• Notes: When SSSF buffering or connection management is enabled, changing this field will not change the SXP
behaviour.
• The “RX_3_ID_FRAMES” field specifies whether to enable to receive up to 3 identify frames. The value of ‘1’
indicates to enable to receive up to three identify frames.
• The “TX SSC Down-Spread Type” is used to configure the TX SSC TYPE in SNW-3 PHY Capabilities. When set
to:
– 1: Use down-spreading SSC
– 0: Use center-spreading SSC (default)
• The “STP Bridge AWT” field specifies the arbitration wait time to use for the OPEN frame request when
operating the STP bridge mode.
• The “Connection Policing Timer” field specifies the minimum amount of time in milliseconds before BREAK
primitives are sent to the two PHYs comprising the current connection if the link is idle. A value of zero disables
the timer and the sending of the BREAK primitives.
• The “Broadcast change Suppress” field specifies if BROADCAST(CHANGE) primitives are detected only in a
selected number of link states. When this bit is set to 1, the primitives are only detected in a number of states.
When set to 0, it enables the state machine to detect primitives in each state. This bit should be left disabled (0).
• The “Disable Advance SATA Sync Forward Mode” controls how SATA SYNCs are forwarded by the expander.
The expander device contains an algorithm that drops subsequent SATA SYNC primitives in a sequence of two
or more received primitives. This mode should always be enabled and the bit should be set to 0.
• The “Power Disable Supported” controls if expander supports Power disable feature defined in SPL3r6:
– 0: Power disable not supported
– 1: Support power disable
• Notes, if the “Power Disable Supported” is enabled:

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– Set “SAS/SATA buffering enable” to “1”;

– Using “SATA buffering 6G(1) | SATA buffering 3G(0)” and “12G connection management enable(2) | SAS
buffering 6G(1) | SAS buffering 3G(0)” to control SAS/SATA buffering, set or clear these fields to enable or
disable SAS/SATA buffering individually;
– Implement ema_process_power_disable_pin_hook() to control hard drive power control pin.
• The “SAS Align Density” field controls the SAS Align Density Mode which correspondingly determines the Align
Density in the SXL_12G SAS link. The default SAS Align Density Mode is 0 which means High Align Density
disabled and 1 ALIGN every 128 Dwords in the SAS link.
Notes: When SSSF buffering or connection management is enabled, changing this field will not change the SXP
behaviour.
Table 8-14. SAS Align Density Mode

SAS Align SAS Align Density Field in SXL Align Description

Density Mode Density Register

0 0x80 High Align Density disabled and 1 ALIGN every

128 Dwords

1 0x40 High Align Density enabled and 1 ALIGN every

64 Dwords

2 0x20 High Align Density enabled and 1 ALIGN every

32 Dwords

Note:
• The “STP Align Density” field controls the STP Align Density Mode which correspondingly determines the Align
Density in the SXL_6G STP link. The default STP Align Density Mode is 0 which means High Align Density
disabled and 2 ALIGN every 256 Dwords in the STP link.
Table 8-15. STP Align Density Mode

STP Align Density Mode STP Align Density Field in SXL Description
Align Density Register

0 0x100 High Align Density disabled and 2

ALIGN every 256 Dwords

1 0x80 High Align Density enabled and 2

ALIGN every 128 Dwords

2 0x40 High Align Density enabled and

2ALIGN every 64 Dwords

• The “LOS REFAMP SAS/SATA” field selects the LOS threshold

• The “LOS CTRL SAS/SATA” field shifts the threshold by -80mV when set to '1'
• The “RX PEAK SAS/SATA 1G5 3G/SAT 6G” field selects the Rx equalization setting
• The “RX PEAK ENB SAS1 1G5/SAS 3G/SATA 1G5/SATA 3G/SATA 6G” controls the active-low enable for Rx
equalization.
• The “AMPLITUDE SAS 1G5/SAS 3G/SAS2 6G/SATA 1G5/SATA 3G/SATA 6G” field controls amplitude.
• The “T PISO PRE2 SEL SAS 1G5/SAS 3G/SAS2 6G/SATA 1G5/SATA 3G/SATA 6G” fields select between
edge-rate and pre-cursor de-emphasis:
– 0: Edge rate control
– 1: Pre-cursor de-emphasis
• The “T PISO EDGE DELAY SEL SAS 1G5/SAS 3G/SAS2 6G/SATA 1G5/SATA 3G/SATA 6G” fields select the
delay for the edge rate control when T PISO PRE2 SEL * is 0:
– 0: Minimal delay

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– 1: Maximal delay
• The “POSTCURSOR SAS 1G5/SAS 3G/SAS2 6G/SATA 1G5/SATA 3G/SATA 6G” field controls post-cursor
de-emphasis.
• The “PRECURSOR SAS 1G5/SAS 3G/SAS2 6G/SATA 1G5/SATA 3G/SATA 6G” field is used to adjust TX edge
rate when the “T PISO PRE2 SEL x” field = 0.
• The “T PISO PRE2 MODE1 SAS2 6G/SATA 6G” field set to '1' to invert polarity of pre-cursor pre-emphasis.
Effective only when T PISO PRE2 SEL x is 1.
• The “TX BCT EN SAS3 12G” field enables the Tx back-channel negotiation in SAS-3 12G mode
• The “TRS TXCLK SEL SATA 1G5/3G/6G SSC” field selects SATA SSC for the corresponding SATA rate. When
set to:
– 0: No SSC (Default)
– 1: SSC Down-spread
– 3: SSC Center-spread (normally for SAS-2 only)
• The “SAS12G PGA BOOST EN” field provides the per-PHY PGA boost option:
– 1: Enable PGA boosting, DP_FFE_M_PRELOAD_SAS3_12 preload read from the initial string field “DP
FFE M PRELOAD SAS3 12G” in Table 8-10.
– 0: Disable PGA boosting, DP_FFE_M_PRELOAD_SAS3_12 preload is hardware default value(39).
• The “TX Cx BCT PRST DFLT” field is the default Tx coefficient setting for back channel training. The
recommended default preset is SAS Reference 2 regardless of cable length.
Table 8-16. Tx Coefficient Settings

TX_Cx_BCT_PRST_DFLT Description

0 Coefficient setting is user-defined in TX C1 BCT START POINT/ TX C2 BCT

START POINT/ TX C3 BCT START POINT

1 Coefficient setting Reference_1

2 Coefficient setting Reference_2

3 Coefficient setting No Equalization

• The “TX C1 NON BCT” field is set for pre-cursor tap for optical or active cable environments
• The “TX C2 NON BCT” field is set for main tap for optical or active cable environments
• The “TX C3 NON BCT” field is set for post-cursor tap for optical or active cable environments.
• The “TX C1 BCT START POINT” field is the default TX C1 when TX Cx BCT PRST DFLT is set to 0.
• The “TX C2 BCT START POINT” field is the default TX C2 when TX Cx BCT PRST DFLT is set to 0.
• The “TX C3 BCT START POINT” field is the default TX C3 when TX Cx BCT PRST DFLT is set to 0.
Notes:
For legacy operation, AMPLITUDE, PRECURSOR and POSTCURSOR names are used. For SAS3
operation, names changed for C1, C2 and C3, and these are normally automatically adapted unless overridden
by the user.
You can translate the AMP, PRE, POST values into C1, C2, C3 values as follows:
• PRECURSOR = -C1
• AMPLITUDE = -C1+C2-C3
• POSTCUSOR = -C3
Notice how C1 and C3 are negative values:
Where, C1=[-32,0], C3=[-32,0] and C2 = [0,64+C1+C2]
In terms of PRE, AMP and POST, these ranges become:
PRECURSOR=[0,32], AMPLITUDE=[PRECUSOR+POSTCURSOR,64] and POSTCURSOR=[0,32]

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• The SAS/SATA buffering enable field is used to enable or disable the SAS/SATA buffering feature of the PHY
attached to the drive. Setting this field to “0” disables this feature and setting it to “1” enables this feature.
For SATA buffering, it improves the bandwidth utilization only for NCQ commands, but it does not block non-NCQ
commands. SATA buffering should be disabled on PHYs attached to SATA drives that do not support NCQ, as well as
PHYs that are attached to expanders or host HBAs.
Notes: SAS buffering is not supported on subtractive PHYs or to wide port targets.
• The SAS buffering 3G/6G fields are used to enable or disable SAS buffering on 3G/6G drive link rates. Setting
this field to “0” disables SAS buffering on this drive link rate and setting it to “1” enables SAS buffering on this
drive link rate.
Notes:
In SAS buffering mode, if the transfer size of the XFER_RDY frame received from the drive is larger than the effective
SSSF_BUFFER_SIZE, the SSSF splits the frame into several XFER_RDY frames before sending them to the host.
Each frame has a transfer size smaller than or equal to the effective SSSF_BUFFER_SIZE.
• If the attached SAS drive is 6G, the effective SSSF_BUFFER_SIZE is 22K. If the attached SAS drive is 3G, the
effective SSSF_BUFFER_SIZE is 16K.
• The SAS Buffering OAF Early Accept Enable field, when enabled, allows SSSF to accept the OPEN frame
directly from the host instead of waiting for the OPEN_ACCEPT from the drive.
– Set this field to “0” to disable this feature when using multi-initiator environments because the target device
may reject incoming connections when it already has outstanding I/Os for another host.
– Set this field to “1” to enable this feature in single initiator environments for better performance because
this allows SSSF to accept the connection request from the host while it forwards the request to the target
device at the same time.
• The SAS Buffering Snoop TMF field, if enabled, allows SSSF to drop frames in its buffer that are received from
the host when TMF is received, and sends out TMF to the drive in the next connection. Setting this field to
“0” disables this feature and setting it to “1” enables this feature. SSSF snoops the TMF for the following task
management functions:
– ABORT TASK SET
– CLEAR TASK SET
– I_T NEXUS RESET
– LOGICAL UNIT RESET
• The 12G connection management enable field is used to enable or disable the 12G connection management
feature of the PHY attached to a negotiated 12G target. Setting this field to “0” disables this feature and setting it
to “1” enables this feature.
• The 6G/3G connection management enable field is used to enable or disable the connection management
feature of the PHY attached to a negotiated 6G/3G target. Setting this field to “0” disables this feature and
setting it to “1” enables this feature. This functionality will ensure that no more than 25/19 data frames are sent
in the connection from the 6G/3G target to the initiator.
• The SATA buffering 3G/6G fields are used to enable or disable SATA buffering on 3G/6G drive link rates. Setting
this field to “0” disables this feature and setting it to “1” enables SATA buffering on this link rate.
• The maximum frame count field only takes effect if the 12G connection management feature is enabled and the
attached SAS target has negotiated to 12G. For Read data, the value in Maximum frame count field controls
the amount of data that can be transferred during a connection opened by SSSF. The actual transferred frame
count within one connection will not exceed (maximum frame count + 2).For write data, the value specifies
the maximum amount of data that SSSF requests through a XFER RDY frame. If the XFER RDY frame count
requested by the target is less than the value of the maximum frame count, SSSF will use the requested size
from the drive instead. The valid range for this field is from 10 to 64.
• The DP FFE M PRELOAD SAS3 12G field defines the value of “DP FFE M PRELOAD SAS3 12G” based on per
PHY configuration. Only valid when “DP FFE M PRELOAD SAS3 12G Global Disable” set to 1 and “SAS12G
PGA BOOST EN” to 1;
• The Test Threshold field defines the value of “Test Threshold” based on per PHY configuration. Only valid when
“Test Threshold Enable” set to 1;

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Table 8-17. SXP 12G Initialization String Table—PHY Connector Configuration

Byte \ Bit 7 6 5 4 3 2 1 0 Default Value Range

0x1130 FIRST ENCLOSURE CONNECTOR ELEMENT INDEX 0x00 See SPL-2

0x1131 TOTAL NUMBER OF ENCLOSURE CONNECTOR 0x11

0x1132 FIRST VIRTUAL CONNECTOR ELEMENT INDEX 0x11

0x1133-
0x00
0x113F Reserved

0x1140 Reserved PHY 0 Connector Type 0x05 see SES-3

0x1141 PHY 0 Connector Element Index 0x00 see SES-3

0x1142 PHY 0 Connector Physical Link 0x00 see SES-3

PHY 0
PHY 0 Unmanaged
0x1143 Reserved for PHY 0 Connector Info Managed 0x00
Connector Type
Type

... ... 0x00

0x124C Reserved PHY 67 Connector Type 0x05 see SES-3

0x124D PHY 67 Connector Element Index 0x10 see SES-3

0x124E PHY 67 Connector Physical Link 0x03 see SES-3

PHY 67 PHY 67
0x124F Reserved for PHY 67 Connector Info Unmanaged Managed 0x00
Connector Type Type

0x1250 -
0x00
0x127F Reserved

• FIRST ENCLOSURE CONNECTOR ELEMENT INDEX indicates the first index value of connectors that have
CONNECTOR TYPE fields set to 20h to 2Fh. The default is 0.
• TOTAL NUMBER OF ENCLOSURE CONNECTOR indicates the total number of supported drive connectors
and wide connectors.
• FIRST VIRTUAL CONNECTOR ELEMENT INDEX indicates the index value of the first virtual connector (type
2Fh). This index should be one plus the index value of the last internal connector that has CONNECTOR TYPE
fields set to 20h to 2Eh. If there are no internal connectors configured, the default value is one plus the index
value of the last external connector of type 05h. Refer to the Connector Element Index Example in Figure 21 for
the connector element structure. Currently, the SXP12G device is configured to only have one virtual connector.
• The initialization string also includes a provision to support the reporting of SES-3 SAS Connector Elements
on a per PHY basis. The connector elements are described in the SCSI Enclosure Specification [17] while its
SMP reporting structure is documented in the SAS standard [3]. The initialization string table for reporting the
connector information is arranged in ascending order according to the logical PHY ID. Information for up to 68
PHYs may be defined.
• PHY Connector Type indicates the mechanical interface type such as SFF-8644, the value is constant since the
interface is definitive after board design.
• PHY Connector Element Index indicates which connector is to be indexed. The index value depends on the
number of connectors. The Connector Element Index should obey three rules,
– The index value of all connectors, including virtual connector, should be contiguous, and starts from 0.
– The index value of internal connectors that have CONNECTOR TYPE fields set to 20h to 2Eh should be
contiguous.

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– The index value of virtual connector should be one plus the index value of last internal connector that have
CONNECTOR TYPE fields set to 20h to 2Eh.
The following figure shows an example of connector element index settings.
Figure 8-1. Connector Element Index Example

PHY Connector Physical Link indicates the physical link in the connector represented by this element. A
CONNECTOR PHYSICAL LINK field set to FFh indicates that the element represents the entire connector, not just
one physical link in the connector. Physical links in a connector must be numbered starting with zero. If a connector
has only one physical link, the CONNECTOR PHYSICAL LINK field should be set to 00h rather than FFh.
Unmanaged Connector Type field indicates four cable types can be connected, the field is valid when manage type is
set to zero.

00 Passive copper cable

01 Active copper cable

10 Reserved

11 SAS-2.1/3 optical

Managed Type field supports the statically managed mode when set to 0 and the dynamically managed through TWI
when set to 1.

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Table 8-18. SXP 12G Initialization String Table—Additional PHY Event Source Configuration Block

Byte \ Value
Bit 7 6 5 4 3 2 1 0 Default Range

0x1280 Additional PHY event 0 Selector 0x00

0x1281 Additional PHY Event 1 Selector 0x00

0x1282 Additional PHY Event 2 Selector 0x00

0x1283 Additional PHY Event 3 Selector 0x00

0x1284 -
Reserved 0x00
0x129F

• The additional PHY Event 0 selector selects a pre-configuration PHY Event source 0. It impacts the PHY
identifiers.
• The additional PHY Event 1 selector selects a pre-configuration PHY Event source 1. It impacts the PHY
identifiers
• The additional PHY Event 2 selector selects a pre-configuration PHY Event source 2. It impacts the PHY
identifiers
• The additional PHY Event 3 selector selects a pre-configuration PHY Event source 3. It impacts the PHY
identifiers
• Notes: When buffering or connection management is enabled, these events will not be used.
Table 8-19. SXP 12G Initialization String Table—SGPIO Configuration
Byte \ Bit 7 6 5 4 3 2 1 0 Default Value Range

SGPIO
SGPIO
Cascade SGPIO PHY Ready
Cascade Enable
0x12A0 SGPIO Cascade General Purpose Slave Load Pattern Master Indication 0x12

0x12A1 SGPIO Cascade Offset Count Timeslot (MSB)

0x12A2 SGPIO Cascade Offset Count Timeslot (LSB) 0x006C

0x12A3 SGPIO Cascade Total Drive Count (MSB)

(Offset + 3*PhyCount) <=
0x12A4 SGPIO Cascade Total Drive Count (LSB) 0x0048 (3*TotalDriveCount)

0x12A5 SGPIO Cascade General Purpose Output Offset Timeslot (MSB)

0x12A6 SGPIO Cascade General Purpose Output Offset Timeslot (LSB) 0x00A0

0x12A7 SGPIO Cascade Total General Purpose Register Count (MSB)

(Offset + 160) <=
0x12A8 SGPIO Cascade Total General Purpose Register Count (LSB) 0x000A (32*Register Count)

IBPI Enable
0x12A9 Reserved Blink Rate C Flag GPIO Enable 0x01

0x12AA Activity Locate Error 0xA0

0x12AB Stretch Off Stretch On 0x03

0x12AC Force Activity Off Max Activity On 0x48

0x12AD Blink Rate A Blink Rate B 0x00

0x12AE SGPIO PHY Ready Update Rate (in units of 10ms) 0x0A 0x00 – 0xFF

0x12AF SGPIO Update Rate (in units of us) (MSB)

0x12B0 SGPIO Update Rate (in units of us) (LSB) 0x3D09 0x3D09 – 0xFFFF

0x12B1 SGPIO SCLOCK Filter 0x80 0x00 – 0xFF

0x12B2 Reserved Bus Used By Rx GP 0x00 0x00 – 0x03

0x12B3 –
0x12BF Reserved (for SGPIO expansion)

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...........continued

Byte \ Bit 7 6 5 4 3 2 1 0 Default Value Range

0x12C0 –
0x131F Reserved for more 3 configuration instances (customer could use this space to configure) 0x00

8.3.1.43 SGPIO PHY Ready Indication Field

The two bits that make up this field determine which SGPIO SDataOut bit per drive slot is driven using the PHY ready
status. The following table shows the valid values:
Table 8-20. SGPIO PHY Ready Indication Setting

SGPIO PHY Ready Indication Setting SGPIO Bit that Indicates PHY Ready Condition

0 No indication

1 Activity bit

2 Locate bit

3 Error bit

8.3.1.44 SGPIO Cascade Enable Field

This bit enables the cascading of the SGPIO interface with other expanders.

8.3.1.45 SGPIO Cascade Master Field

This field configures the current expander as the master within the cascade chain.

8.3.1.46 SGPIO Cascade General Purpose Slave SLoad Pattern Field

This field specifies the 4-bit general-purpose SLOAD pattern that the slave expander should detect when cascading
is enabled. This field must have a non-zero value when cascading is enabled.

8.3.1.47 SGPIO Cascade Offset Count Timeslot

This field configures the timeslot offset within the cascaded chain of the first SDataOut bit of the current expander
when operating in the normal mode.

8.3.1.48 SGPIO Cascade Total Drive Count Field

This field configures the number of drives within the cascade chain. Each drive slot contains the SGPIO timeslots.

8.3.1.49 SGPIO Cascade General Purpose Output Offset Timeslot Field

This field configures the timeslot offset within the cascaded chain of the first SDataOut bit of the current expander
when operating in the general-purpose mode.

8.3.1.50 SGPIO Cascade Total General Purpose Register Count Field

This field configures the number of general-purpose registers within the cascade chain.

8.3.1.51 IBPI enable flag Field

See the SFF-8489 Specification for the Serial GPIO IBPI (International Blinking Pattern Interpretation) standard.
When IBPI is enabled, the following blink patterns are suggested:
Pattern A field: 0x7, which means 1HZ;
Pattern B field: 0x3, which means 2HZ;
Pattern C field: 0x1, which means 4 HZ;

8.3.1.52 GPIO Enable Field

See SFF-8485 Specification for Serial GPIO (SGPIO) Bus standard.

8.3.1.53 Error Field

See SFF-8485 Specification for Serial GPIO (SGPIO) Bus standard.

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8.3.1.54 Locate Field

See SFF-8485 Specification for Serial GPIO (SGPIO) Bus standard.

8.3.1.55 Activity Field

See SFF-8485 Specification for Serial GPIO (SGPIO) Bus standard.

8.3.1.56 Stretch On Field

See SFF-8485 Specification for Serial GPIO (SGPIO) Bus standard.

8.3.1.57 Stretch Off Field

See SFF-8485 Specification for Serial GPIO (SGPIO) Bus standard.

8.3.1.58 Max Activity On Field

See SFF-8485 Specification for Serial GPIO (SGPIO) Bus standard.

8.3.1.59 Force Activity Off Field

See SFF-8485 Specification for Serial GPIO (SGPIO) Bus standard.

8.3.1.60 Blink Rate A Field

See SFF-8485 Specification for Serial GPIO (SGPIO) Bus standard.

8.3.1.61 Blink Rate B Field

See SFF-8485 Specification for Serial GPIO (SGPIO) Bus standard.

8.3.1.62 Blink Rate C Field

See SFF-8485 Specification for Serial GPIO (SGPIO) Bus standard.

8.3.1.63 SGPIO PHY Ready Update Rate Field

This field determines the rate at which the PHY Ready status is checked. This field has a unit of 10 ms.

8.3.1.64 SGPIO Update Rate Field

This field determines the rate at which SGPIO updates the hardware registers. This field has a unit of 1 us.

8.3.1.65 SGPIO SCLOCK Filter Field

This field specifies the number of consecutive core clock periods (6.7ns) where the SCLK must remain stable before
it is passed by the filter. Setting this field to 0 disables the filtering.

8.3.1.66 Bus used by Rx GP

This field specifies the ID of the bus whose GPIO input stream provides the data source for SMP GPIO READ
requests when operating in general-purpose mode.
Table 8-21. SXP 12G Initialization String—CMDSVR Configuration

Byte \ Value
7 6 5 4 3 2 1 0 Default
Bit Range

0x1320 Reserved CMDSVR UART0 Baud Rate 0x05 0x00 – 0x05

0x1321 Reserved CMDSVR UART1 Baud Rate 0x05 0x00 – 0x05

0x1322 Reserved CMDSVR UART2 Baud Rate 0x05 0x00 – 0x05

0x1323 Reserved CMDSVR UART3 Baud Rate 0x05 0x00 – 0x05

Disable
Fatal Error
CMDSVR UART
0x1324 Handler Reserved(6-3) Expander 0x80 0x00 – 0x03
ID
Enable(7)
phy

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...........continued
Byte \ Value
7 6 5 4 3 2 1 0 Default
Bit Range

Non-
Threadx Interface: 0-1
0x1325 Nonthreadx CMDSVR TWI Port ID 0x04 TWI port ID:
CMDSVR
0-11
Interface

0x1326 Nonthreadx CMDSVR TWI Slave Address 0x5B 0x00-0xFF

Fatal Error Control:0-2

0x1327 Reset Timeout Fatal Error Reset Timeout Value(5:0) 0x3f Value:0x00-0
Control(7:6) x3f

8.3.1.67 CMDSVR UART Baud Rate Field

This field specifies CMDSVR UART interface’s baud rate. The encoding is shown in the following table.
Table 8-22. CMDSVR UART Baud Rate Encoding

CMDSVR UART Baud Rate Field Value CMDSVR UART Baud Rate Field
Value

0 9600 baud

1 19200 baud

2 28800 baud

3 38400 baud

4 57600 baud

5 115200 baud

6–15 Reserved

8.3.1.68 Fatal Error Handler Enable

This field is used to enable/disable the command server fatal error handler.

8.3.1.69 Disable Expander Phy

This field is used to disable expander phy when fatal error occurs.

8.3.1.70 CMDSVR UART ID

This field indicates which UART is active for the command server.

8.3.1.71 Non-Threadx CMDSVR Interface

This field indicates the type of interface for the non-Threadx command server.
Set to 0 for UART interface
Set to 1 for TWI interface.

8.3.1.72 Non-Threadx CMDSVR TWI Port ID

This field specifies TWI Port ID for the non-Threadx command server.

8.3.1.73 Non-Threadx CMDSVR TWI Slave Address

This field specifies the TWI Slave Address for the non-Threadx command server.

8.3.1.74 Fatal Error Reset Timeout Control

This field indicates timing granularity of “Fatal Error Reset Timeout Value” field.

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Set to 0 for seconds; Set to 1 for minutes; Set to 2 for hours and 3 is reserved.

8.3.1.75 Fatal Error Reset Timeout Value

This field specifies the timeout value for the command server to receive a character or the SXP12G will be reset by
the firmware fatal error handler. Setting this timeout value to 0x3F (max value) will disable the timer and the SXP12G
will not be reset allowing the command server to remain available.
Table 8-23. SXP 12G Initialization String—SPS Configuration

Byte \ Value
7 6 5 4 3 2 1 0 Default
Bit Range

SPS Bit
0x1328 Reserved 0x00
Aware Fields

8.3.1.76 SPS Aware Field

The SPS aware field, when set to 1, commands the firmware to poll for SPS devices directly attached to the
expander and to send configuration and/or patch data to the attached SPS devices. The SPS configuration/patch
data must be separately generated and appended to the initialization string data.
Table 8-24. SXP 12G Initialization String—TWI Configuration

Value
Byte/Bit 7 6 5 4 3 2 1 0 Default
Range

0x00 –
0x05
0x1329 TWI Master Stretch Time(ms) 0xFF

TWI Master Speed

0x02
0x132A Reserved Mode

0x132B –
Reserved 0x00
0x132F

8.3.1.77 TWI Master Stretch Time Field

TWI master stretch time is the extra time that a master must wait before a transaction timeout. This field is set for all
12 TWI ports. The unit is ms and the default value is 5.

8.3.1.78 TWI Master Speed Mode Field

This field defines the TWI master speed(400 kbit/s or 100 kbit/s) for all TWI masters. If this field is set as 0x1, then
the TWI master speed is 100 kbit/s. If this field is set as 0x2, then the TWI master speed is 400 kbit/s. All other values
are reserved.
Table 8-25. SXP 12G Initialization String—GPIO Configuration

Value
Byte/Bit 7 6 5 4 3 2 1 0 Default Range

0x1330 TWI_SPI_ON_SGPIO_UART_MUXING CONTROL[31:24] 0x00 Bit fields

0x1331 TWI_SPI_ON_SGPIO_UART_MUXING CONTROL[23:16] 0x00

0x1332 TWI_SPI_ON_SGPIO_UART_MUXING CONTROL[15:8] 0x00

0x1333 TWI_SPI_ON_SGPIO_UART_MUXING CONTROL[7:0] 0x00

0x1334 GPIO_PIN_MUXING_CONTROL0[31:24] 0x00

0x1335 GPIO_PIN_MUXING_CONTROL0[23:16] 0x00

0x1336 GPIO_PIN_MUXING_CONTROL0[15:8] 0x00

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...........continued
Value
Byte/Bit 7 6 5 4 3 2 1 0 Default Range

0x1337 GPIO_PIN_MUXING_CONTROL0[7:0] 0x00

0x1338 GPIO_PIN_MUXING_CONTROL1[31:24] 0x00

0x1339 GPIO_PIN_MUXING_CONTROL1[23:16] 0x00

0x133A GPIO_PIN_MUXING_CONTROL1[15:8] 0x0F

0x133B GPIO_PIN_MUXING_CONTROL1[7:0] 0x00

0x133C GPIO_PIN_MUXING_CONTROL2[31:24] 0x00

0x133D GPIO_PIN_MUXING_CONTROL2[23:16] 0x00

0x133E GPIO_PIN_MUXING_CONTROL2[15:8] 0x00

0x133F GPIO_PIN_MUXING_CONTROL2[7:0] 0x0F

0x1340 -
0x134f Reserved 0x00

8.3.1.79 TWI_SPI_ON_SPGIO_UART_MUXING_CONTROL[31:0]
These fields indicate current function of the GPIO. Value of these fields is written to the EXTSS_APB_PCBI –
TWI_SPI_ON_SGPIO_UART_MUXING_CONTROL register (0xA9000000). Refer to [30] for details.
Bit 10 – EN_EMIP_UART_ON_UART_PORT. 1 for EMIP_UART, 0 for NORMAL_UART.
Bit 9:4 – EN_SPI_ON_UART_PIN. 1 for SPI, 0 for UART.
Bit 3:0 – EN_TWI_ON_SGPIO_PORT. 1 for TWI, 0 for SGPIO.

8.3.1.80 GPIO_PIN_MUXING_CONTROL0[31:0]
These fields indicate the Functional Pin acts as GPIO or Functional Pin. Value of these fields is written to the
EXTSS_APB_PCBI – GPIO_PIN_MUXING_CONTROL0 register (0xA900004C). Refer to [30] for details.
1: Functional Pin act as GPIO.
0: Functional Pin acts as Functional Pin.

8.3.1.81 GPIO_PIN_MUXING_CONTROL1[31:0]
These fields indicate the Functional Pin acts as GPIO or Functional Pin. Value of these fields is written to the
EXTSS_APB_PCBI – GPIO_PIN_MUXING_CONTROL1 register (0xA9000050). Refer to [30] for details.
1: Functional Pin act as GPIO.
0: Functional Pin acts as Functional Pin.

8.3.1.82 GPIO_PIN_MUXING_CONTROL2[31:0]
These fields indicate the Functional Pin acts as GPIO or Functional Pin. Value of these fields is written to the
EXTSS_APB_PCBI – GPIO_PIN_MUXING_CONTROL2 register (0xA9000054). See [30] for details.
1: Functional Pin acts as GPIO.
0: Functional Pin acts as Functional Pin.

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 175

Initialization String

Table 8-26. Pin Drive Strength Control—Pin Configuration

Value
Byte \ Bit 7 6 5 4 3 2 1 0 Default
Range

MISC_OUTPUT TWI_DRIVE_MOD
Reserved
0x1350 S E 0x00 Bit fields

UART_DRIVE_M ETHERNET_D LBI_DRIVE_MOD

SPI_DRIVE_MODE
0x1351 ODE RIVE_MODE E 0x00 Bit fields

0x1352 -
Reserved 0x00
0x135F

8.3.1.83 MISC_OUTPUTS
These 2 bits control the mode pins for outputs or bi-directionals such as INTOB, MIPS_RDY and AVS_ENB.

8.3.1.84 TWI_DRIVE_MODE
These 2 bits control the mode pins for the TWI & SGPIO interface.

8.3.1.85 UART_DRIVE_MODE
These 2 bits control the mode pins for the UART interface.

8.3.1.86 SPI_DRIVE_MODE
These 2 bits control the mode pins for the SPI interface.

8.3.1.87 ETHERNET_DRIVE_MODE
These 2 bits control the mode pins for the Ethernet interface.

8.3.1.88 LBI_DRIVE_MODE
These 2 bits control the entire Local Bus Interface.
Table 8-27. Drive Strength Modes

Mode1 Mode0 Drive Current

00 3mA

01 7mA

10 15mA

11 18mA

Note: The following table is for the PM805x device only.

Table 8-28. SXP 12G Initialization String—TCP/IP Stack Configuration

Value
Byte \ Bit 7 6 5 4 3 2 1 0 Default
Range

0x00 –
0x1360 DHCP ON/OFF 0x00
0x01

0x00 –
0x1361 Local IP[0] 0x0A
0xFF

0x00 –
0x1362 Local IP[1] 0xBC
0xFF

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Initialization String

...........continued
Value
Byte \ Bit 7 6 5 4 3 2 1 0 Default
Range

0x00 –
0x1363 Local IP[2] 0x75
0xFF

0x00 –
0x1364 Local IP[3] 0x50
0xFF

0x00 –
0x1365 Net Mask [0] 0xFF
0xFF

0x00 –
0x1366 Net Mask [1] 0xFF
0xFF

0x00 –
0x1367 Net Mask [2] 0xFC
0xFF

0x00 –
0x1368 Net Mask [3] 0x00
0xFF

0x00 –
0x1369 Gate Way [0] 0x0A
0xFF

0x00 –
0x136A Gate Way [1] 0xBC
0xFF

0x00 –
0x136B Gate Way [2] 0x74
0xFF

0x00 –
0x136C Gate Way [3] 0x01
0xFF

0x00 –
0x136D MAC Addr [0] 0x00
0xFF

0x00 –
0x136E MAC Addr [1] 0xE0
0xFF

0x00 –
0x136F MAC Addr [2] 0x04
0xFF

0x00 –
0x1370 MAC Addr [3] 0xFE
0xFF

0x00 –
0x1371 MAC Addr [4] 0xDC
0xFF

0x00 –
0x1372 MAC Addr [5] 0xBA
0xFF

RMII Negative Auto-

0x1373 Reserved Speed Duplex 0x01 Bit Fields
Disable Polarity neg

0x00 –
0x1374 Ethernet PHY ID 0x01
0x1F

0x00-0x0
0x1375 KEEPALIVE ENABLE 0x00
1

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 177

Initialization String

...........continued
Value
Byte \ Bit 7 6 5 4 3 2 1 0 Default
Range

0x1376 KEEPALIVE TIME(MSB) 0x1C See Note

0x1377 KEEPALIVE TIME(LSB) 0x20 See Note

0x1378 KEEPALIVE INTV(MSB) 0x00 See Note

0x1379 KEEPALIVE INTV(LSB) 0x4B See Note

0x137A KEEPALIVE PROBE CNT 0x05 See Note

0x137B –
Reserved 0x00
0x13DF

The configuration of TCPIP keep alive should satisfy following conditions:

Note 1. KEEPALIVE TIME >= KEEPALIVE INTV * KEEPALIVE PROBE CNT

2. KEEPALIVE TIME is the integer multiple of KEEPALIVE INTV

• DHCP ON/OFF: set 1 to enable DHCP; set 0 to disable DHCP

• Local IP: 4 bytes of the IPv4 address, default 10.188.117.80 for test purposes
• Net Mask: 4 bytes of netmask for a sub-net
• Gate Way: 4 bytes of default gateway IP address
• MAC Addr: 6 bytes of physical MAC address
• Auto-neg: Ethernet PHY auto-negotiation Enable/Disable. Valid values: 0x0(Disable) and 0x1(Enable), default
value: 0x1
• Duplex: Ethernet Duplex mode. Valid values: 0x0(Half duplex mode) and 0x1(Full duplex mode). This field is
valid only when Auto-negotiation is disabled.
• Speed: Ethernet port speed. Valid values: 0x0(10 Mbps) and 0x1(100 Mbps). This field is valid only when
Auto-negotiation is disabled.
• Negative Polarity: Indicates link status logic polarity is negative or positive. Valid values: 0x1(negative logic
polarity) and 0x0(positive logic polarity). Default value is 0x0. Value 0x1: logic low signal to indicate LINK UP,
logic high signal to indicate LINK DOWN. Value 0x0: logic high signal to indicate LINK UP, logic low signal to
indicate LINK DOWN.
• RMII Disable: Selects the operation mode of the MAC. Valid values: 0x0(RMII) and 0x1(MII). Default value is
0x0.
• Ethernet PHY ID: Ethernet PHY device address on RMII MDIO/MDC bus.
• KEEPALIVE ENABLE: Enable/Disable TCP keep connections alive. Valid values: 0x0(Disable) and 0x1(Enable),
default value: 0x0. KEEPALIVE ENABLE enables periodic transmission of probe messages (every 2 hours by
default) on a connection. If the connected party fails to respond to these probe messages, the connection is
considered broken.
• KEEPALIVE TIME: TCP keep alive idle time (before starting sending probes) in seconds. Default value: 0x1c20.
This field is valid only when KEEPALIVE ENABLE is set.
• KEEPALIVE INTV: The interval time between keep alive message probes in seconds. Default value: 0x4B. This
field is valid only when KEEPALIVE ENABLE is set.
• KEEPALIVE PROBE CNT: The maximum number of keep alive probes without any response from the remote
before TCP gives up and aborts the connection. Default value: 0x05. This field is valid only when KEEPALIVE
ENABLE is set.

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 178

Initialization String

Table 8-29. SXP 12G Initialization String—EPOW Configuration

Value
Byte/Bit 7 6 5 4 3 2 1 0 Default
Range

0x13E0 Reserved POLARITY EPOW_EN 0x00

0x13E1 -
Reserved 0x00
0x13EC

0x13ED Reserved Q_PHY[67:64] 0x00

0x13EE Q_PHY[63:56] 0x00

… 0x00

0x13F5 Q_PHY[7:0] 0x00

0x13F6 Reserved 0x00

0x13F7 Reserved N_PHY[67:64] 0x00

0x13F8 N_PHY[63:56] 0x00

… 0x00

0x13FF N_PHY[7:0] 0x00

8.3.1.89 POLARITY
This bit selects the polarity for the AC_GOOD_L signal.
When this bit is set to 0, the AC_GOOD_L signal is active low.
When the bit is set to 1, the AC_GOOD_L signal is active high.

8.3.1.90 EPOW_EN
This bit enables the EPOW feature.

8.3.1.91 Q_PHY
Q_PHY bitmap is used to qualify the EPOW condition. When the EPOW trigger condition is met, at least one of the
PHYs identified by the Q_PHY bitmap is in a PHY ready state.

8.3.1.92 N_PHY
N_PHY bitmap is used to specify the PHYs that transmit NOTIFY (POWER LOSS EXPECTED) when EPOW
conditions are met.
Table 8-30. SXP 12G Initialization String Table—Error LOG Configuration Block

Value
Byte/Bit 7 6 5 4 3 2 1 0 Default
Range

LOG
Flash
Runtime LOG Filter
0x1400 Reserved Saving LOG Filter Count 0x08
Saving Count: 0~16
Enable
Device

Filter Level:
0x1401 LOG Entry Count [19:16] LOG Global Filter Level 0x02
0~5

0x1402 LOG Entry Count [15:8] 0x00 LOG Entry

Count:
0x1403 LOG Entry Count [7:0] 0x80 2~1048575

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Initialization String

...........continued
Value
Byte/Bit 7 6 5 4 3 2 1 0 Default
Range

0x1404 Reserved 0x00

0x1405 Reserved SCFG Log Entry Count[12:8] 0x00 SCFG Log

Entry
0x1406 SCFG Log Entry Count[7:0] 0x10 Count:
2~8192

0x1407 Reserved 0x00

0x1408 Reserved 0x00

0x1409 Reserved 0x00

0x140A Reserved 0x00

0x140B Reserved 0x00

0x140C External RAM LOG Saving Base Address [31:24] 0x98

0x140D External RAM LOG Saving Base Address [23:16] 0x10 Address in
External
0x140E External RAM LOG Saving Base Address [15:8] 0x00 RAM

0x140F External RAM LOG Saving Base Address [7:0] 0x00

0x1410 External RAM SCFG LOG Saving Base Address [31:24] 0x98

0x1411 External RAM SCFG LOG Saving Base Address [23:16] 0x1C Address in
External
0x1412 External RAM SCFG LOG Saving Base Address [15:8] 0x00 RAM

0x1413 External RAM SCFG LOG Saving Base Address [7:0] 0x00

0x1414 Reserved 0x00

0x1415 Reserved 0x00

0x1416 Reserved 0x00

0x1417 Reserved 0x00

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Initialization String

...........continued
Value
Byte/Bit 7 6 5 4 3 2 1 0 Default
Range

Type:
0x00~0x02
LOG Filter Level Reserved LOG Filter Type 0x31
Level:
0x01~0x05

Mask [31:24] 0x00

Mask [23:16] 0xFF

LOG Filter
0 Block Mask [15:8] 0x00
(0x1418 –
0x1420) Mask [7:0] 0x00

Pattern [31:24] 0x00

Pattern [23:16] 0x1F

Pattern [15:8] 0x00

Pattern [7:0] 0x00

0x1421 –
LOG Filter 1~15 Block, same as LOG Filter 0
0x14A7

0x14A8-
Reserved 0x00
0x14BF

8.3.1.93 LOG Runtime Saving Device

This field is to set where the application log is saved at run time. When set to:
• 0: Default, saves log to internal SRAM
• 1: Saves log to external SRAM if there is one.
Note: This field is for the PM805x device only.

8.3.1.94 Flash Saving Enable

This field is to enable the dump of the application log and other information into flash when any Fatal Error happens.
When set to:
• 0: Default. Disables log save to flash memory when fatal error occurs
• 1: Saves log to flash memory when fatal error occurs

8.3.1.95 LOG Filter Count

This field indicates the number of valid application log filter entries that are configured in the initialization string.
Maximum is 16 as implemented in the firmware SDK.

8.3.1.96 LOG Entry Count

This field indicates the number of entries to record the LOG during runtime.
This field contains 20 bits which allows configuring a 1M LOG entry number, that is, 32 MB size maximum. The actual
count depends on the capacity of the RAM.
If you use internal RAM by default, log entry count must be less than
ISTR_INTERNAL_RAM_APP_LOG_ENTRY_MAX=200.

8.3.1.97 SCFG LOG Entry Count

This field indicates the number of entries to record the SCFG LOG in runtime.
This field contains 13 bits that allows configuring 8K SCFG LOG entry number, that is, 256K size maximum. When
the internal RAM mode is used, the maximum SCFG LOG number is 40 entries.

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 181

Initialization String

8.3.1.98 External RAM SCFG LOG Saving Base Address

This field defines the start address in the external RAM to save the self-configure LOG, if the self-configure LOG is
configured to save to external RAM.
Note: This field is for the PM805x device only.

8.3.1.99 LOG Global Filter Level

This field indicates the global filter level, that is, LOG global severity level. It controls whether need to record the log
entry if the log module does not in the LOG filter list.
See 17.2.1 Event Logging Filter Level for each filter level.

8.3.1.100 LOG Filter Type

This field indicates the filter type. The type can be set to Filter OUT, Filter IN and Do not use this filter. See
17.2.1 Event Logging Filter Level for the values.

8.3.1.101 LOG Filter Level

This field indicates the severity level for the filter. It controls whether need to record the log entry if its log module
matches this log filter.
See 17.2.1 Event Logging Filter Level for each filter level.

8.3.1.102 LOG Filter Mask

This field indicates the mask applied to data before pattern matching. The Log Filter Mask can be configured to
0xFF0000.

8.3.1.103 LOG Filter Pattern

This field indicates the pattern to match against. A pattern is defined as (module ID << 16).
See Table 17-6 for module ID configuration.
Table 8-31. SXP 12G Initialization String Table—WOL/WOS Configuration Block

Value
Byte/Bit 7 6 5 4 3 2 1 0 Default Range

Bit
Reserved WOL/WOS enabling 0x00
0x14C0 Fields

0x14C1 Reserved 0x00

0x14C2 WOS_UPSTREAM_PHY_MAP (Reserved) 0x00

WOS_UPSTREAM_PHY_MAP
0x14C3 (Reserved) WOS_UPSTREAM_PHY_MAP [67:64] 0x00

0x14C4 WOS_UPSTREAM_PHY_MAP [63:56] 0x00

0x14C5 WOS_UPSTREAM_PHY_MAP [55:48] 0x00

0x14C6 WOS_UPSTREAM_PHY_MAP [47:40] 0x00

0x14C7 WOS_UPSTREAM_PHY_MAP [39:32] 0x00

0x14C8 WOS_UPSTREAM_PHY_MAP [31:24] 0x00

0x14C9 WOS_UPSTREAM_PHY_MAP [23:16] 0x00

0x14CA WOS_UPSTREAM_PHY_MAP [15:8] 0x00

0x14CB WOS_UPSTREAM_PHY_MAP [7:0] 0x00

0x14CC WOS SLEEP DELAY TIME(ms) (MSB) 0x00

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Initialization String

...........continued
Value
Byte/Bit 7 6 5 4 3 2 1 0 Default Range

…… …… 0x00

0x14CF WOS SLEEP DELAY TIME(ms) (LSB) 0x00

0x14D0 WOS WAKEUP WINDOW TIME(ms) (MSB) 0x00

…… …… 0x00

0x14D3 WOS WAKEUP WINDOW TIME(ms) (LSB) 0x00

0x14D4 WOS WAKEUP BY MIN NUM OF PHY 0x00

0x14D5-0
x14D7 Reserved 0x00

0x14D8 WOL SLEEP DELAY TIME(ms) (MSB) 0x00

…… …… 0x00

0x14DB WOL SLEEP DELAY TIME(ms) (LSB) 0x00

0x14DC-
Reserved
0x14DF 0x00

8.3.1.104 Wake-on-LAN/Wake-on-SAS (WOL/WOS) enabling

This field indicates WOS/WOL is enabled or disabled by default.
• 0: Both WOS and WOL are disabled.
• 1: Only WOS is enabled.
• 2: Only WOL enabled.
• 3: Reserved.
Note:
WOL is supported for the PM805x device only.
8.3.1.105 WOS_UPSTREAM_PHY_MAP
This map defines the logical PHY map of WOS upstream PHYs.
8.3.1.106 WOS SLEEP DELAY TIME
This field indicates the delay from the time all WOS upstream PHYs are down to the time firmware gets ready to
enter sleep mode.
The unit is millisecond (ms).
Note:
The WOS sleep delay time cannot be less than the time for which the SXP PHY becomes READY after waking up,
otherwise the device will enter an endless sleep-wake-sleep loop as the Sleep on SAS condition will be met again
just after waking up. The suggested value can be more than 1 second.
8.3.1.107 WOS WAKEUP WINDOW TIME
This field indicates the delay from the time MIPS is waked up by an interrupt event to the time firmware gets the
interrupt events from enough WOS upstream PHYs (defined by WOS WAKEUP BY MIN NUM OF PHY field) to
wake up the whole device. If firmware fails to get the interrupt events from enough WOS upstream PHYs during this
window, MIPS will enter sleep mode again. The unit is milliseconds (ms).
8.3.1.108 WOS WAKEUP BY MIN NUM OF PHY
This field indicates the minimum number of WOS upstream PHYs that have an interrupt event to wake up the whole
device.

© 2021 Microchip Technology Inc. User Guide DS00004013A-page 183

Initialization String

8.3.1.109 WOL SLEEP DELAY TIME

This field indicates the delay, in milliseconds, from the time firmware receives a WOL SES page of the start command
to the time firmware gets ready to enter sleep mode.
Note:
Firmware uses an application timer to calculate the WOL sleep delay time. Due to the maximum timeout value of the
current application timer being 57266230 us, the valid range for the WOL sleep delay time is 0x0~0xDFB2.
This field is for the PM805x device only.
Table 8-32. SXP 12G Initialization String Table—Operating System Configuration

Value
Byte/Bit 7 6 5 4 3 2 1 0 Default Range

Hard-
ware Heart-
Watch- beat
dog LED
0x1830 Reserved Enable Enable 0x03 Bit Fields

0x00 –
0xFF (0
implies
every
0x1831 SAS Thread Watchdog Kick Interval (in units of 10 messages per interval) 0x64 message)

0x00 –
0xFF (0
disables
0x1832 EMA Thread Peripheral Polling Interval (in units of seconds) 0x01 polling)

0x1833 Reserved 0x00

0x1834 Reserved 0x00

0x02 –
0x1835 Watchdog Block Timeout (in seconds) 0x1C 0x39

0x1836 CS0 Timing Register0 [31:24] 0x00

0x1837 CS0 Timing Register0 [23:16] 0x0b

0x1838 CS0 Timing Register0 [15:8] 0x02

0x1839 CS0 Timing Register0 [7:0] 0x0a

0x183A CS0 Timing Register1 [31:24] 0x06

0x183B CS0 Timing Register1 [23:16] 0x16

0x183C CS0 Timing Register1 [15:8] 0x24

0x183D CS0 Timing Register1 [7:0] 0x04

0x183E CS1 Timing Register0 [31:24] 0x00

0x183F CS1 Timing Register0 [23:16] 0x08

0x1840 CS1 Timing Register0 [15:8] 0x0a

0x1841 CS1 Timing Register0 [7:0] 0x14

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Initialization String

...........continued
Value
Byte/Bit 7 6 5 4 3 2 1 0 Default Range

0x1842 CS1 Timing Register1 [31:24] 0x15

0x1843 CS1 Timing Register1 [23:16] 0x19

0x1844 CS1 Timing Register1 [15:8] 0x32

0x1845 CS1 Timing Register1 [7:0] 0x04

0x1846 –
0x184F Reserved 0x00

0x00 –
0x1850 Command Server Thread Priority 0x0D 0x1F

0x00 –
0x1851 EMA Thread Priority 0x0C 0x1F

0x00 –
0x1852 Port Manager Thread Priority 0x04 0x1F

0x00 –
0x1853 SAS Thread Priority 0x02 0x1F

0x00 –
0x1854 SCSI Thread Priority 0x05 0x1F

0x00 –
0x1855 SGPIO Thread Priority 0x06 0x1F

0x00 –
0x1856 SMP Initiator Thread Priority 0x03 0x1F

0x00 –
0x1857 Watchdog Thread Priority 0x0B 0x1F

0x00 –
0x1858 Serial ATA Host Application Thread Priority 0x09 0x1F

0x00 –
0x1859 SCSI Initiator Application Thread Priority 0x08 0x1F

0x00 –
0x185A Disk Qualification Thread Priority 0x0A 0x1F

0x00 –
0x185B PHY Reset Timer 0x00 0x50

0x00 –
0x185C TCPIP Telnet Server Thread Priority 0x0D 0x1F

0x00 –
0x185D TCPIP Timer Task Thread Priority 0x0A 0x1F

0x00 –
0x185E TCPIP Receive Task Thread Priority 0x0D 0x1F

0x00 –
0x185F SAS connector manager thread priority 0x07 0x1F

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Initialization String

...........continued
Value
Byte/Bit 7 6 5 4 3 2 1 0 Default Range

0x1860 –
0x186F Reserved (for OS configuration expansion) 0x00

8.3.1.110 Heartbeat LED Enable Field

This bit, when enabled, toggles the state of the MIPSRDY pin to provide a heartbeat indication signal. The toggle rate
is fixed at an interval of 1 second.

8.3.1.111 Hardware Watchdog Enable Field

This field toggles the hardware watchdog timer.

8.3.1.112 SAS Thread Watchdog Kick Interval Field

This field commands the SAS thread to kick (reset) the watchdog thread after receiving and processing a certain
number of messages.

8.3.1.113 EMA Thread Peripheral Polling Interval Field

This field specifies the interval, in seconds, in which the peripherals attached to TWI bus 1 are polled when the thread
is not processing any EMA messages. For platforms without any supported device on TWI bus 1, disable the polling
mechanism by setting this field to 0.

8.3.1.114 Watchdog Block Timeout Field

This field specifies the watchdog timeout period in seconds. The actual hardware timeout period is rounded up to the
next highest supported hardware timeout value, as shown in the following table.
Table 8-33. Watchdog Block Timeout Parameter Value and Actual Timeout Period

Watchdog Block Timeout Parameter Value Actual Hardware Watchdog Timeout Period

2 s to 3 s 3.6 s

4 s to 7 s 7.2 s

8 s to 14 s 14.3 s

15 s to 28 s 28.6 s

29 s to 57 s 57.3 s

For example, with a default setting of 28 s, the hardware timeout period used is 28.6 s. This is when the first
watchdog interrupt is asserted if it is not kicked (reset) in time. Firmware then enters Customer Fatal Error Handler.
Refer to section 17.6.1 Customer Fatal Error Handler for details.

8.3.1.115 CS0 Timing Register0 and Timing Register1

The 2 32-bit fields specify the hardware signal timing for interfacing with a non-volatile memory device attached to the
expander device’s chip-select 0 (CS0). The 2 fields will be filled into corresponding Timing Registers (0xbc13_0000,
0xbc13_0020) of the SXP 12G Memory Controller. Refer to SXP 12G Register document for detail.
Note: This field is for the PM805x device only.
The default value is not applicable to the following flash memory that was tested:
M29W128GH. When page mode is used, Tprc(0x1839) needs to be more than 0xc, which is approximately
39(12*3.3) ns.

8.3.1.116 CS1 Timing Register0 and Timing Register1

The 2 32-bit fields specify the hardware signal timing for interfacing with a memory device (e.g. SRAM) attached
to the expander device’s chip-select 1 (CS1). The 2 fields will be filled into corresponding Timing Registers
(0xbc13_0004, 0xbc13_0024) of the SXP 12G Memory Controller. Refer to SXP 12G Register document for detail.

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Initialization String

Note: This field is for the PM805x device only.

8.3.1.117 Thread Priority Fields

The 16-thread priority fields configure the priority of the respective threads running in the firmware. The thread
priorities have a range of 0 to 31, with 0 being the highest priority and 31 being the lowest priority.

8.3.1.118 PHY Reset Timer

When the SXP receives an SMP Link Reset/Hard Reset, it disables the 10ms timer, generates the reset sequence,
waits for a predefined period, and then re-enables the 10ms timer. The PHY Reset Timer field defines the waiting
period. The unit is 10us. The maximum time value is 800us because the SMP command should be handled within
1ms.
Table 8-34. SXP 12G Initialization String Table—Protocol Configuration

Value
Byte/Bit 7 6 5 4 3 2 1 0 Default
Range

0x1870 SAS Supported Initiator Count 0x10 0x01 – 0x10

0x1871 SAS Tasks Per Initiator 0x02 0x01 – 0x02

0x1872 SAS Shared Task Count 0x02 0x01 – 0x02

0x1873 SSP Nexus Loss Time [15:8] 0x00 –

0x07D0
0x1874 SSP Nexus Loss Time [7:0] 0xFFFF

0x1875 SCSI Supported Initiator Count 0x10 0x01 – 0x10

0x1876 STE Maximum Data Size [15:8]

0x0009 0x00 – 0x10
0x1877 STE Maximum Data Size [7:0]

0x1878 SMP Initiator Transmit Retry Count 0x0A 0x00 – 0xFF

0x1879 Reserved 0x00

0x187A SSP Initiator Nexus Timeout [15:8] (ms) 0x01 –

0x09C4
0x187B SSP Initiator Nexus Timeout [7:0] (ms) 0xFFFF

0x187C SSP Initiator Retry Count 0x01 0x00 – 0xFF

0x187D STP Initiator Nexus Timeout [15:8] (ms) 0x01-

0x09C4
0x187E STP Initiator Nexus Timeout [7:0] (ms) 0xFFFF

0x187F SAS frame transmission timeout (milliseconds)[31:24] 0x00

0x1880 SAS frame transmission timeout (milliseconds)[23:16] 0x00

0x1881 SAS frame transmission timeout (milliseconds)[15:8] 0x0b

0x1882 SAS frame transmission timeout (milliseconds)[7:0] 0xB8

0x1883 STP SMP I_T nexus loss time (milliseconds)[15:8] 0x07

0x1884 STP SMP I_T nexus loss time (milliseconds)[7:0] 0xD0

TLR CONTINU
0x1885 Reserved 0x01
CTRL E AWT

0x1886 STP Bus Inactivity time (100 us) [15:8] 0x00

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Initialization String

...........continued
Value
Byte/Bit 7 6 5 4 3 2 1 0 Default
Range

0x1887 STP Bus Inactivity time (100 us) [7:0] 0x00

0x1888 SSP REJECT TO OPEN LIMIT [15:8] (10 us) 0x00

0x1889 SSP REJECT TO OPEN LIMIT [7:0] (10 us) 0x64

0x188A SSP MAXIMUM CONNECT TIME LIMIT [15:8] (100 us) 0x27

0x188B SSP MAXIMUM CONNECT TIME LIMIT [7:0] (100 us) 0x10

0x188C SSP initiator response timeout [15:8] (milliseconds) 0x0f

0x188D SSP initiator response timeout [7:0] (milliseconds) 0xa0

0x188E STP Max Connect Limit time [15:8] (100 us) 0x00

0x188F STP Max Connect Limit time [7:0] (100 us) 0x00

0x1890 STP REJECT TO OPEN LIMIT [15:8] (10 us) 0x00

0x1891 STP REJECT TO OPEN LIMIT [7:0] (10 us) 0x00

0x1892 SAS Open Reject Retry Limit Time (milliseconds)[15:8] 0x03

0x1893 SAS Open Reject Retry Limit Time (milliseconds)[7:0] 0xe8

0x1894 Reject to Open Limit Time on Retry Open: Reserved [15:8] 0x00

0x1896 SMP Initiator Nexus Timeout (milliseconds)[15:8] 0x00

0x1897 SMP Initiator Nexus Timeout (milliseconds)[7:0] 0x14

0x1898 –
Reserved 0x00
0x18AF

8.3.1.119 SAS Supported Initiator Count Field

This field configures the number of simultaneous SSP initiators that the SAS thread supports.
Note: The actual maximum initiator count supported by the SXP 12G is equal to the smaller of either the SAS
Supported Initiator Count Field (this field) or the SCSI Supported Initiator Count Field (Offset 0x1875).
For example, to support 16 initiators, set both this field and the SCSI Supported Initiator Count Field as 0x10.

8.3.1.120 SAS Tasks per Initiator Field

This field configures the number of task resources allocated to each task of the same SSP initiator.

8.3.1.121 SAS Shared Task Count Field

This field configures the number of global task resources allocated to be shared among the SSP initiators.

8.3.1.122 SSP Nexus Loss Time Field

This field configures the maximum time duration before the I_T nexus loss is declared for the SSP target or Initiator
port.

8.3.1.123 SCSI Supported Initiator Count Field

This field configures the maximum number of external SCSI initiators, which means the maximum number of I_T
nexus state machines supported by STE.

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8.3.1.124 STE Maximum Data Size Field

This field configures the maximum supported burst data size within the SAS port thread in blocks of 512 bytes. By
default, this value is set to 0x09, which is 4.5 Kbytes.
Note The current maximum data size supported within the firmware is 32.5 Kbytes.

8.3.1.125 SMP Initiator Transmit Retry Count Field

This field configures the maximum number of retries that the SMP initiator protocol handler attempts after a command
fails.

8.3.1.126 SSP Initiator Nexus Timeout Field

This field specifies the duration (in milliseconds) that the SSP initiator thread waits for a response before declaring a
command transmission failure. This field cannot be set to 0 and must be greater than the SSP Nexus Loss Time.

8.3.1.127 SSP Initiator Retry Count Field

This field specifies the number of retries for sending a command when the transmission fails. The total number of
transmissions is the retry count plus 1.

8.3.1.128 STP Initiator Nexus Timeout Field

This field specifies the duration (in milliseconds) that the STP initiator thread waits for a response before declaring a
command transmission failure. This field cannot be set to 0 and must be greater than the STP SMP I_T Nexus Loss
Time.

8.3.1.129 SAS Frame Transmission Timeout Field

This field specifies the duration (in milliseconds) for each Frame Transmit Request after the connection open/open
retry request is sent. Value of 0 means to disable this timeout.

8.3.1.130 STP SMP I_T Nexus Loss Time Field

This field specifies the duration (in milliseconds) of I_T Nexus Loss Timer for SMP/STP Initiator Port and STP Target
Port in SXP 12G STP/SATA Bridge. Default value is 0x07D0, 2000ms.

8.3.1.131 CONTINUE AWT Field

When set to:
• 1: specifies that the virtual SAS port does not stop the Arbitration Wait Time timer and does not set the
Arbitration Wait Time timer to zero when it receives an OPEN_REJECT (RETRY).
• 0: specifies that the virtual SAS port stops the Arbitration Wait Time timer and sets the Arbitration Wait Time
timer to zero when it receives an OPEN_REJECT (RETRY).

8.3.1.132 TLR CTRL Field

TLR Control field is for determining whether the SSP Command Frame sent by virtual SSP Initiator is compatible to
SAS-2 or to SAS1.1.
When set to:
• 1: Specifies that the SSP Command Frame from the virtual SSP initiator is compatible with SAS-2 and the TLR
CONTROL bits in the SSP Command Frame are set to b01.
• 0: Specifies that the SSP Command Frame from the virtual SSP initiator is still compatible with SAS1.1 and the
TLR CONTROL bits are set to b00.

8.3.1.133 STP Bus Inactivity Time Field

This field specifies the maximum time in 100us increments that an STP target port in SXP 12G can maintain a
connection while transmitting and receiving SATA_SYNC. When this time is exceeded, the STP target port closes this
connection. Default value of 0 in this field specifies that there is no bus inactivity time limit.

8.3.1.134 SSP Reject to Open Limit Timer Field

This field configures the time out value of the port layer reject to open limit timer which applies to a virtual SSP
initiator/target port. Unit is 10us.

8.3.1.135 SSP Maximum Connect Time Limit Timer Field

This field configures the time out value of the port layer maximum connection time limit timer which applies to a virtual
SSP initiator/target port. Unit is 100us.

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Note
It is recommended to configure this timer with a value larger than 1ms since there is an expected tolerance caused
by firmware delay.

8.3.1.136 SSP Initiator Response Timeout

This field specifies the time in one millisecond units that the Virtual SSP target waits for the receipt of a write DATA
frame before aborting the command associated with the frame. A value of 0x0000 specifies that the SSP target
disables the initiator response timeout timer.

8.3.1.137 STP Max Connect Limit time Field

This field specifies the maximum duration of a connection in 100us unit. When the time is exceeded, the STP target
port closes the connection at the next opportunity. A value of 0x0000 specifies that there is no maximum connection
time limit. This field applies to all STP target ports that resides in SXL STP/SATA bridge in all SXP12G PHYs.

8.3.1.138 STP Reject to Open Limit Timer Field

This field specifies the duration (in 10 us) that an STP port must wait to establish a connection with an initiator port on
an I_T nexus after receiving an OPEN_REJECT(RETRY, RESERVED CONTINUE 0, RESERVED CONTINUE 1). A
value of 0x0000 implements a 10us delay before a new connection is established. This field applies to all STP target
ports that reside in the SXL STP/SATA bridge in all SXP12G PHYs.
SAS Open Reject Retry Limit Time Field
This field specifies the time limit (using a 1 ms granularity) that the SXP12G initiator port (including SSP, SMP, and
STP) will retry an OPEN request that receives OPEN_REJECT (RETRY, RESERVED CONTINUE 0, or RESERVED
CONTINUE 1). When the initiator receives continuous OPEN_REJECT(RETRY, RESERVED CONTINUE 0, or
RESERVED CONTINUE 1) and the timer expires, the OPEN is treated as an IT NEXUS loss. A value of 0x0000
disables the timer allowing the SXP12G initiator to retry the OPEN indefinitely.
Reject to Open Limit time on retry open
Setting a bit to one in this bit mask indicates which retry-able OPEN_REJECT types will utilize the SSP Reject to
Open Limit Timer.

8.3.1.139 SMP Initiator Nexus Timeout

This field specifies the maximum duration for which a SMP request is transmitted to the port layer and is in 1ms unit.
When the time exceeds this limit, the SMP transport layer returns message to the originating application and frees
nexus.
Table 8-35. Reject to Open Limit time on retry open

Bit number Name Retry condition

5 Path way block OPEN_REJECT(PATHWAY BLOCKED) is received

4 Time out OPEN is timeout

3 Break BREAK is received

1 No Dest OPEN_REJECT(NO DESTINATION) is received

0 Retry OPEN_REJECT(RETRY) is received

Table 8-36. SXP 12G Initialization String Table—EMA Configuration Block

Value
Byte/Bite 7 6 5 4 3 2 1 0 Default
Range

0x18B0 SES-3 Enclosure Logical Identifier [63:56] 0x00

SES-3 Enclosure Logical Identifier [55:48] 0x00

SES-3 Enclosure Logical Identifier [47:40] 0x00

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...........continued
Value
Byte/Bite 7 6 5 4 3 2 1 0 Default
Range

SES-3 Enclosure Logical Identifier [39:32] 0x00

SES-3 Enclosure Logical Identifier [31:24] 0x00

SES-3 Enclosure Logical Identifier [23:16] 0x00

SES-3 Enclosure Logical Identifier [15:8] 0x00

0x18B7 SES-3 Enclosure Logical Identifier [7:0] 0x00

0x18B8 Disk Drive Count 0x0C 0~0x44

0x18B9 –
Reserved 0x00
0x18BB

0x18BC –
SES-3 Supported Pages 0x7FFFFF
0x18BF

0x18C0
Disk Drive Slot 0~15 0x08~0x17
-0x18CF

0x18D0 –
Disk Drive Slot 16~47 0x18~0x37
0x18EF

0x18F0 -
Disk Drive Slot 48 ~ 67 0x00~ 0x00
0x1903

0x1904
Reserved 0x00
-0x190F

8.3.1.140 SES-3 Enclosure Logical Identifier Field

This field holds the enclosure logical identification that is returned in the SMP REPORT GENERAL Response frame.
See the SAS [4] and SCSI Enclosure [17] standards for information concerning the enclosure logical identifier. If this
field is all zeros, SAS base address is used as a replacement.

8.3.1.141 Disk Drive Count Field

This field indicates the number of disks that have been connected. The maximum value of this field is 0x44. See
Table 14-7.

8.3.1.142 SES-3 Supported Pages Field

This field allows customers to easily configure which SES pages their firmware will advertise support for in SES page
0x0. The values in the field [7:0] are the page codes. See SCSI-3 Enclosure Services Command Set, Chapter 6 in
References [17], for details.
Table 8-37. SES-3 Supported Pages Field

Value
Byte/Bit 7 6 5 4 3 2 1 0 Default
Range

0x18BC Reserved 0x00

0x00 –
0x18BD 0xF4 0xF3 0xF1 0xF0 0x91 0x90 0x86 0x84 0xFF
0xFF

0x00 –
0x18BE 0x83 0x82 0x81 0x80 0x3f 0x0f 0x0e 0x0d 0xFF
0xFF

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...........continued
Value
Byte/Bit 7 6 5 4 3 2 1 0 Default
Range

0x18BF 0x0a 0x07 0x05 0x04 0x03 0x02 0x01 0x00 0xFF 0x000xFF

Note:
1. Page 0x00 (Supported Diagnostic Pages diagnostic page) is always supported. Bit 0 in 0x18BF is ignored.
2. If firmware is configured to support page 0x02 (Enclosure Control/Status diagnostic page) , then page 0x01
(Configuration diagnostic page) should also be supported..

8.3.1.143 Disk Drive Slot Field

This field describes the mapping from the Disk drive slot ID to the logical PHY ID. For example, Disk Drive Slot 0:
0x08 means that logical PHY 8 is mapped to Disk Drive slot 0.
Note:
1. The disk drive slot and the logical PHY should be a one-to-one mapping. So, do not map one logical PHY ID to two
or more disk drive slots.
2. The logical PHY ID mapped to the valid disk drive slot ID (less than the value of Disk Drive Count Field) should be
less than the max PHY count of the board.
Table 8-38. SXP 12G Initialization String Table—Redundant Virtual SSP Link Configuration

Value
Byte/Bit 7 6 5 4 3 2 1 0 Default Range

0x1910 Redundant Virtual SSP Link Map (Reserved) 0x00

Redundant Virtual SSP Link Map Bit

0x1911 (Reserved) Redundant Virtual SSP Link Map [67:64] 0x00 Fields

Bit
0x1912 Redundant Virtual SSP Link Map [63:56] 0x00 Fields

Bit
0x1913 Redundant Virtual SSP Link Map [55:48] 0x00 Fields

Bit
0x1914 Redundant Virtual SSP Link Map [47:40] 0x00 Fields

Bit
0x1915 Redundant Virtual SSP Link Map [39:32] 0x00 Fields

Bit
0x1916 Redundant Virtual SSP Link Map [31:24] 0x00 Fields

Bit
0x1917 Redundant Virtual SSP Link Map [23:16] 0x00 Fields

Bit
0x1918 Redundant Virtual SSP Link Map [15:8] 0x00 Fields

Bit
0x1919 Redundant Virtual SSP Link Map [7:0] 0x00 Fields

0x191A –
0x191F Reserved (for redundant virtual SSP link configuration) 0x00

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8.3.1.144 Redundant Virtual SSP Link Map Field

Each bit in this field specifies one PHY that connects the expanders between two redundant topology branches. Only
the virtual SSP port can be seen across a redundant virtual SSP domain. An example of a topology with a redundant
virtual link is shown in the Figure 8-2.
Figure 8-2. Redundant Virtual SSP Configuration Example

A side B side

Redundant Vssp Redundant Vssp

SAS
1 1

HBA-A 4
Exp-A1 Exp-B1 4
HBA-B
1 1

SPS

SATA

Subtractive Subtractive

SAS
1 1
Exp-A2 Exp-B2
1 1

SPS

Redundant Vssp Redundant Vssp

SATA

In this example, the two HBAs can be set up to detect the presence of the virtual SSP ports on both branches of the
tree and use this redundant (fallback) link to perform enclosure management operations, if required.
Table 8-39. SXP 12G Initialization String—Disk Qualification, SIA, and SAHA Configuration

Byte/Bit 7 6 5 4 3 2 1 0 Default Value Range

0x1920 DSQ Request Minimum Interval (ms) 0x14 0x00 – 0xFF

0x1921 SIA Thread Maximum Retry Count 0x01 0x00 – 0xFF

0x1922 SIA Thread Maximum Simultaneous Application Requests 0x05 0x01 – 0xFF

0x1923 SAHA Thread Maximum Retry Count 0x01 0x00 – 0xFF

0x1924 SAHA Thread Maximum Simultaneous Application Requests 0x01 0x01 – 0xFF

0x1925 SIA Thread Busy Retry Delay (ms) [15:8] 0x00 –

0x0BB8
0x1926 SIA Thread Busy Retry Delay (ms) [7:0] 0xFFFF

0x1927 SAHA Thread Busy Retry Delay (ms) [15:8] 0x00 –

0x0BB8
0x1928 SAHA Thread Busy Retry Delay (ms) [7:0] 0xFFFF

0x1929 DSQ Request Delay Multiplier 0x00 0x00 – 0xFF

0x192A SIA Thread Maximum Simultaneous Requests from DSQ 0x01 0x01 – 0xFF

0x192B SAHA Thread Maximum Simultaneous Requests from DSQ 0x01 0x01 – 0xFF

0x192C
– Reserved
0x192F

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8.3.1.145 DSQ Request Minimum Interval Field

This field specifies the minimum delay interval (in milliseconds) between any two successive requests issued to the
DSQ thread.

8.3.1.146 SIA Thread Maximum Retry Count Field

This field specifies the number of retry attempts the SIA thread executes to complete a SCSI command.

8.3.1.147 SIA Thread Maximum Simultaneous Application Requests Field

This field specifies the maximum number of simultaneous requests that the SIA thread can expect from higher-level
application threads (e.g., DSQ, Cmdsvr, Inter-expander communication over SAS).
Set this value larger than the sum of simultaneous requests from all higher-level applications to ensure enough
resources are allocated or a firmware assert could occur.
For example, the default setting is 5, equal to:
SIA Thread Maximum Simultaneous Requests from DSQ (Configured in this table, default 0x01) +
CMDSVR_MAX_SIMUL_SSP_REQ_NUM (Hard code, default 0x02) + 2 (Reserved for Inter-expander
communication over SAS feature by user).

8.3.1.148 SAHA Thread Maximum Retry Count Field

This field specifies the number of retry attempts the SAHA thread should execute to complete an ATA command.

8.3.1.149 SAHA Thread Maximum Simultaneous Application Requests Field

This field specifies the maximum number of simultaneous requests that the SAHA thread can expect from high-level
application threads (e.g., DSQ).

8.3.1.150 SIA Thread Busy Retry Delay (ms) Field

This field specifies the minimum delay (in milliseconds) the SIA thread should wait before retrying a SCSI command.
This field must be set to a value greater than that of the SSP Initiator Nexus Timeout Field.

8.3.1.151 SAHA Thread Busy Retry Delay (ms) Field

This field specifies the minimum delay (in milliseconds) the SAHA thread should wait before retrying an ATA
command. This field must be set to a value greater than that of the STP Initiator Nexus Timeout Field.
In summary, the SSP/STP Initiator Nexus Timeout, SAS Nexus Loss Time, and SIA/SAHA Thread Busy Retry Delay
parameters must satisfy the following constraint:

SSP/STP initiator nexus time SIA/SAHA initiator thread

SAS nexus loss time < <
out busy retry delay

8.3.1.152 DSQ Request Delay Multiplier

This field specifies the minimum delay (in milliseconds) the PORTMGR thread should wait before it triggers a DSQ
request to the disk attached to the expander PHY when PORTMGR detects that the expander PHY has achieved
PHY RDY in its PHY event polling cycle.
The DSQ Request Delay is in the range from
DSQ Request Delay Multiplier * PHY Polling Period (See Table 8-7) to
(DSQ Request Delay Multiplier +1) * PHY Polling Period.
But the actual observed DSQ Request Delay from PHY achieving PHY RDY to starting DSQ may not be in this range
because there may be some delay between PHY achieving PHY RDY and firmware PORTMGR detecting this event
when SXP 12G tasks are heavy or when SXP 12G subsystem brings up.

8.3.1.153 SIA Thread Maximum Simultaneous Requests from DSQ Field

This field works with the ‘SAHA Thread Maximum Simultaneous Request from DSQ’ field to specify the maximum
number of simultaneous requests that the SIA thread can expect from DSQ threads.

8.3.1.154 SAHA Thread Maximum Simultaneous Requests from DSQ Field

This field works with the ‘SIA Thread Maximum Simultaneous Requests from DSQ’ field to specify the maximum
number of simultaneous requests that the SAHA thread can expect from DSQ threads.

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The maximum number of simultaneous requests from DSQ = Min (SIA Thread Maximum Simultaneous Requests
from DSQ, SAHA Thread Maximum Simultaneous Requests from DSQ).
Table 8-40. Initialization String Table—Disk Spin-Up Configuration

Value
Byte/Bit 7 6 5 4 3 2 1 0 Default
Range

No
SATA SATA Power
Hier-
FIS Spin-up SATA SATA SAS SAS Bit
0x1930 archical Control 0xCB
Broad- Hold Spin-Up Hold Spin-Up Notify Fields
Spin-Up
cast Broad- Enable
cast

0x00 –
0x1931 Reserved Spin-Up Group 0x03
0x03

0x00 –
0x1932 Reserved Spin-Up Initial Delay 0x01
0x07

0x00 –
0x1933 Reserved Spin-Up Interval Delay 0x00
0x07

0x1934 Logical HOST_PHY_FLAG (Reserved) 0x00

0x1935 Logical HOST_PHY_FLAG (Reserved) Logical HOST_PHY_FLAG [67:64] 0x00

0x1936 Logical HOST_PHY_FLAG [63:56] 0x00

0x1937 Logical HOST_PHY_FLAG [55:48] 0x00

0x1938 Logical HOST_PHY_FLAG [47:40] 0x00

0x1939 Logical HOST_PHY_FLAG [39:32] 0x00

0x193A Logical HOST_PHY_FLAG [31:24] 0x00

0x193B Logical HOST_PHY_FLAG [23:16] 0x00

0x193C Logical HOST_PHY_FLAG [15:8] 0x00

0x193D Logical HOST_PHY_FLAG [7:0] 0x00

0x00 –
0x193E Reserved SSU Mode 0x00
0x02

0x193F Power Done Timeout (s) 0x20

8.3.1.155 SAS Spin-Up and SAS NOTIFY Fields

These two fields determine the spinning up of SAS-attached drives. See Table 10-3 for detail.

8.3.1.156 SATA Spin-Up and SATA Hold Fields

These two fields together determine the spin up of SATA-attached drives. See Table 10-2 for detail.

8.3.1.157 Power Control Enable Field

This bit controls the POWER CAPABLE field of the INDENTIFY address frame to be sent. When this bit is set to
1, the POWER CAPABLE field is set to 10b, and the SXP is capable of managing the additional consumption of
power. Otherwise, the POWER CAPABLE field is set to 00b and the SXP is not capable of managing the additional
consumption of power. See [7] for more details.

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8.3.1.158 Hierarchical Spin-Up Field

This bit controls if the spin-up module operates in the staggered spin-up mode or in the hierarchical slave mode.
When set to 1, the hierarchical slave mode is entered; otherwise, the spin-up module operates in the staggered
spin-up mode. See the logical host PHY flags description for more information. When set to 1, SATA Hold needs to
be set 0.

8.3.1.159 No SATA Spin-up Hold Broadcast Field

This bit controls if a BROADCAST(CHANGE) primitive is generated when a SATA drive enters the SATA spin-up hold
state. By default, this bit is set to 1, meaning that a BROADCAST(CHANGE) is not generated when then SATA drive
enters the spin-up hold state. This field is applicable to the default disk spin-up algorithm and the SSU algorithm.

8.3.1.160 SATA FIS Broadcast Field

This bit controls if a BROADCAST(CHANGE) primitive is generated when a SATA drive is spin-up and the FIS
exchange between the expander and the drive is complete. By default, this bit is set to 1, meaning that a
BROADCAST(CHANGE) primitive is generated after FIS is received. This field is applicable to both the default
disk spin-up algorithm and the SSU algorithm.

8.3.1.161 Spin-Up Group Field

The spin-up group field controls the number of drives that are grouped together. The following values for this field are
valid:
Table 8-41. Spin-Up Group Bit Settings

Spin-Up Group Number of Drives (PHYs)

0 1 drive per interval

1 2 drives per interval

2 4 drives per interval

3 6 drives per interval

8.3.1.162 Spin-Up Initial Delay Field

The spin-up initial delay configures the first time interval after system reset before spin-up control starts the drive
spin-up sequence. The following table shows the possible values for this field.
Table 8-42. Spin-Up Initial Delay Settings

Spin-Up Initial Delay Delay Time

0 No delay

1 500 milliseconds

2 1 second

3 2 seconds

4 4 seconds

5 8 seconds

6 16 seconds

7 32 seconds

Notes:
When Spin-up Initial Delay is set to 0, 1, or 2 and Spin-up Interval Delay set to 1 second , it may be observed that the
PHY Ready LEDs of several PHYs are being turned ON at the same time instead of 1s interval delay between them.

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This is due to delayed refresh of LED status. The Disk Spin-up control however, does function as expected and the
disks are spun-up at the right time slot.

8.3.1.163 Spin-Up Interval Delay Field

The spin-up interval delay configures the time between each spin-up interval. The following table shows the possible
values for this field.
Table 8-43. Spin-Up Interval Delay Settings

Spin-Up Interval Delay Delay Time

0 500 milliseconds

1 1 second

2 2 seconds

3 4 seconds

4 8 seconds

5 16 seconds

6 32 seconds

7 64 seconds

8.3.1.164 Logical Host PHY Flags Field

The Logical HOST_PHY_FLAG [67:0] bits each indicate one logical PHY for which the spin-up module awaits the
arrival of the NOTIFY(ENABLE_SPINUP) primitive when the module is configured to run in the hierarchical slave
mode. The arrival of the NOTIFY primitive on any one of the host PHYs causes the spin-up module to spin-up the
drives in the current drive group, advance to the next drive group, and then awaits for the next NOTIFY primitive from
the host PHYs. These flags are not used when the spin-up module is operating in the staggered spin-up mode.

8.3.1.165 SSU Mode Field

The SSU (Staggered Spin-Up) Mode field configures an alternate disk spin-up algorithm. See Table 8-45 for the
SSU configuration. When the SSU mode is enabled or put in standby, the default disk spin-up algorithm is disabled,
regardless of its configuration setting. Descriptions of the SSU Mode bits are provided in the following table.
Table 8-44. SSU Mode Settings

SSU Mode Description

0 SSU algorithm is disabled. The default spin-up algorithm may be used.

1 SSU is enabled. The SSU functionality is initialized based on the configuration data and then
put in standby, awaiting a user-programmable enable call in the firmware to start the spin-up
sequence.

2 SSU is enabled. The functionality is initialized and started the moment the firmware comes out of
a reset. In this mode, the Hierarchical Spin-Up Field must be 0.

3 Reserved

8.3.1.166 Power Done Timeout Field

The Power Done Timeout field specifies the maximum time in one second increments that a power consumer device
is allowed to consume additional power. This timer is started after receiving a PWR_ACK response to a transmitted
PWR_GRANT primitive.

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Table 8-45. SXP 12G Initialization String—Staggered Spin-Up (SSU) Configuration

Byte/Bit 7 6 5 4 3 2 1 0 Default Value Range

0x1940 Power Branch Count 0x00 0x01 – 0x0A

0x01 –
0x1941 Power Branch 0 PHY Count 0x00 PHY_COUNT

0x01 –
0x1942 Power Branch 1 PHY Count 0x00 PHY_COUNT

... ... ... ...

0x01 –
0x194A Power Branch 9 PHY Count 0x00 PHY_COUNT

0x194B–
0x194D Reserved (for SSU) 0x00 0x00

0x194E Initial Timing Delay (in seconds) 0x00 0x00 – 0xFF

0x194F Interval Timing Delay (in seconds) 0x00 0x00 – 0xFF

0x00 –
(PHY_COUNT-
0x1950 Combined PHY List Entry 0 0x00 1)

0x00 –
(PHY_COUNT-
0x1951 Combined PHY List Entry 1 0x00 1)

... ... ... ...

0x00 –
(PHY_COUNT-
0x1993 Combined PHY List Entry 67 0x00 1)

0x1994-0
x199F Reserved

0x19A0 Power Branch 0 Configuration: Peak Power (in Watts) (MSB) 0x00

0x19A1 Power Branch 0 Configuration: Peak Power (in Watts) (LSB) 0x00 0x01 – 0xFFFF

0x19A2 Power Branch 0 Configuration: Per Drive Spin-Up Power (in Watts) 0x00 0x01 – 0xFF

0x19A3 Power Branch 0 Configuration: Per Drive Running Power (in Watts) 0x00 0x01 – 0xFF

0x19A4 Power Branch 0 Configuration: Spin-Up Drive Count Limit 0x00 0x01 – 0xFF

Power Branch 1 Configuration –

0x19A5 –
0x19A9 See definition for Power Branch 0 at offset 0x05D0 – 0x05D4 0x00

Power Branch 2 Configuration –

0x19AA –
0x19AE See definition for Power Branch 0 at offset 0x05D0 – 0x05D4 0x00

Power Branch 3 Configuration –

0x19AF –
0x19B3 See definition for Power Branch 0 at offset 0x05D0 – 0x05D4 0x00

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...........continued
Byte/Bit 7 6 5 4 3 2 1 0 Default Value Range

Power Branch 4 Configuration –

0x19B4 –
0x19B8 See definition for Power Branch 0 at offset 0x05D0 – 0x05D4 0x00

Power Branch 5 Configuration –

0x19B9 –
0x19BD See definition for Power Branch 0 at offset 0x05D0 – 0x05D4 0x00

Power Branch 6 Configuration –

0x19BE –
0x19C2 See definition for Power Branch 0 at offset 0x05D0 – 0x05D4 0x00

Power Branch 7 Configuration –

0x19C3 –
0x19C7 See definition for Power Branch 0 at offset 0x05D0 – 0x05D4 0x00

Power Branch 8 Configuration –

0x19C8 –
0x19CC See definition for Power Branch 0 at offset 0x05D0 – 0x05D4 0x00

Power Branch 9 Configuration –

0x19CD –
0x19D1 See definition for Power Branch 0 at offset 0x05D0 – 0x05D4 0x00

0x19D2 –
0x19DF Reserved (for SSU) 0x00 0x00

8.3.1.167 Power Branch Count Field

This parameter specifies the number of independent power branches available: up to 10 power branches are
supported. Although the default value for this parameter is 0, when SSU is enabled, this field must be set to a
non-zero value.

8.3.1.168 Power Branch X PHY Count Field

These fields, one for each power branch, specify the number of PHYs (or drives) to be spun up per power branch.
The power branch PHY count also indexes into the combined PHY List for a given power branch. The default value
for the branch PHY count field is zero. However, if a branch is enabled, as implied by the branch count field, then its
respective branch PHY count field must be set to a non-zero value.

8.3.1.169 Initial Timing Delay Field

The staggered spin-up algorithm can be deferred from starting immediately after the firmware comes out of a reset
by setting this field to a non-zero value. The delay has a resolution of one second and is applicable to the power
branches in use.

8.3.1.170 Interval Timing Delay Field

The amount of time (in seconds) to wait between successful spin up of groups of drives per power branch is
controlled by this field. This field is applicable to the power branches in use.

8.3.1.171 Combined PHY List Fields

The combined PHY list, starting at offset 0x1950 and ending at offset 0x199F, specifies the list of PHYs that are to
be spun up. The first PHY for power branch 0 resides at offset 0x19A0. Successive PHYs for the same branch are
then appended in sequence to the list. If more than one branch is specified, the PHY list for the second branch is
appended immediately after the last PHY of the first branch, and so on. A PHY cannot reside in more than one power
branch. See Section 10.5.4 Drive (PHY) List Specification for a description and Figure 10-12 for an example of the
PHY List usage.

8.3.1.172 Power Branch X Peak Power Field

The peak power field specifies in Watts the maximum power available for the given branch x.

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8.3.1.173 Power Branch X per Drive Spin-Up Power Field

This field specifies the amount of power in Watts that is needed to spin up one drive from a dead stop to its normal
operating speed. The spin-up power is usually larger than the power needed to sustain a drive’s normal operating
condition.

8.3.1.174 Power Branch X per Drive Running Power Field

This field specifies the amount of power in Watts needed to maintain a drive’s normal operating condition after it has
already been spun up.

8.3.1.175 Power Branch X Spin-Up Drive Count Limit Field

This field limits the number of drives that may be spun up at any given interval per power branch x. The number
of drives that are spun up at any given interval is the minimum of the value specified in this field and the value
determined by the power equation.
Table 8-46. SXP 12G Initialization String Table—Reduced Functionality (RF) and Non-I/O Disruptive Soft
Reset (NDSR) Configuration Block

Value
Byte \ Bit 7 6 5 4 3 2 1 0 Default
Range

NDSR RF Bit
0x19E0 Reserved 0x00
Enable Enable Fields

0x00
0x19E1 INITIAL TIME TO REDUCED FUNCTIONALITY 0x14
-0xFF

0x00 –
0x19E2 MAXIMUM REDUCED FUNCTIONALITY TIME 0x06
0xFF

0x00 –
0x19E3 Flash Erase Poll Period (in units of 1ms) 0x05
0xFF

0x19E4 to 0x19EF Reserved 0x00

8.3.1.176 NDSR Enable Field

This field specifies if the Non-I/O Disruptive Soft Reset (NDSR) [12.2 Non-I/O Disruptive Soft Reset (NDSR)] feature
is enabled. When set to:
1: Enabled. When a soft reset command is received, NDSR is scheduled
0: Disabled. When a soft reset command is received, a hard reset is actually performed.

8.3.1.177 RF Enable Field

This field specifies if the Reduced Functionality (RF) feature is enabled. When set to:
1: Enabled.
0: Disabled.
Note: Set this bit enables user to use reduced functionality when necessary. NDSR uses RF mechanism by default
even if RF is disabled.

8.3.1.178 INITIAL TIME TO REDUCED FUNCTIONALITY Field

This field indicates the minimum period of time, in 100 ms increments, that an expander device waits from the time
it originates a Broadcast (Expander) to when it reduces functionality or sets the NDSR mode. The expander device
should set the default value for the INITIAL TIME TO REDUCED FUNCTIONALITY field to at least 2000 ms (that is,
14h). In a large topology, if one SMP initiator cannot finish issuing an SMP Report General to all expanders in SAS
domain in this time period, this time should be increased.

8.3.1.179 MAXIMUM REDUCED FUNCTIONALITY TIME Field

For reduced functionality mode, this field indicates the maximum time, in seconds, that the expander device can
respond with an OPEN_REJECT (RETRY) to connection requests that map to an expander PHY or to an SMP target

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port that is not accessible during expander device reduced functionality. This NDSR/RF max waiting timer starts after
the reduced functionality delay timer expires.
For NDSR mode, this field indicates how much time, in seconds, is required to complete a soft reset provided in the
SMP Report General command. However, there is no such timer after a soft reset is actually triggered, since software
timer is invalid after the system is reset.

8.3.1.180 Flash Erase Poll Period

The Flash Erase Poll Period field configures the time period when disabling the global interrupt to erase flash sectors.
The sector erasing process is now separated into several erase periods. During each period, the firmware cannot
respond to any interrupts. When the erasing is suspended between two periods, firmware can respond to interrupts.
The unit of this field is milliseconds. When this field is configured to 0, the suspend erase flash feature is disabled,
and the firmware can only respond to interrupts after the whole sector is erased.
Table 8-47. SXP 12G Initialization String—Zoning Configuration Block

Byte/Bit 7 6 5 4 3 2 1 0 Default Value Range

PHY 0 PHY 0 PHY 0

PHY 0 Reques Inside Group
0x19F0 Reserved Source Reserved ted ZPSDS ID 0x07 Bit Fields
Check Inside Persist Persist
ZPSDS ent ent

… … … …

PHY 7 PHY 7 PHY 7

PHY 7 Reques Inside Group
0x19F7 Reserved Source Reserved ted ZPSDS ID 0x07 Bit Fields
Check Inside Persist Persist
ZPSDS ent ent

PHY 8 PHY 8 PHY 8

PHY 8 Reques Inside Group
0x19F8 Reserved Source Reserved ted ZPSDS ID 0x00 Bit Fields
Check Inside Persist Persist
ZPSDS ent ent

… … … …

PHY 67 PHY 67 PHY 67

PHY 67 Reques Inside Group
0x1A33 Reserved Source Reserved ted ZPSDS ID 0x00 Bit Fields
Check Inside Persist Persist
ZPSDS ent ent

0x1A34 –
Reserved 0x00 0x00
0x1A3F

Each byte starting at offset 0x19F0 contains the configuration for one PHY. Although up to 68 PHYs can be
configured, 80 entries are allocated.

8.3.1.181 Source Check Field

The source check field, when set, forces the expander to ensure that the SAS address of the OPEN ADDRESS
frame matches that in the IDENTIFY frame when an attached end device attempts to open a connection.

8.3.1.182 Requested Inside ZPSDS Field

The Requested Inside ZPSDS field establishes the boundary of the ZPSDS. See [4] table 35 for detail.

8.3.1.183 Inside ZPSDS Persistent Field

The Inside ZPSDS Persistent field determines the value of INSIDE ZPSDS bit after a link reset sequence. See [4]
table 35 for detail.

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8.3.1.184 Group ID Persistent Field

The Group ID Persistent field determines the zone group of the PHY after a link reset sequence if the INSIDE ZPSDS
bit is set to zero. See [4] table 36 for detail.
Note: The INSIDE ZPSDS bit is determined from the Requested Inside ZPSDS and Inside ZPSDS Persistent values
exchanged during link reset sequence.
Table 8-48. SXP 12G Initialization String—Zoning PHY Group ID Mapping

Value
Byte/Bit 7 6 5 4 3 2 1 0 Default Range

0x1A40
-
0x00 –
0x1A47 PHY 0 ~ 7’s group ID 0x01 0xFF

0x1A48
-
0x00 –
0x1A4B PHY 8 ~ 11’s group ID 0x00 0xFF

0x1A4C
-
0x00 –
0x1A4F PHY 12 ~ 15’s group ID 0x08 0xFF

0x1A50
-
0x00 –
0x1A53 PHY 16 ~ 19’s group ID 0x09 0xFF

0x1A54
-
0x00 –
0x1A57 PHY 20 ~ 23’s group ID 0x0A 0xFF

0x1A58
-
0x00 –
0x1A5B PHY 24 ~ 27’s group ID 0x0B 0xFF

0x1A5C
-
0x00 –
0x1A5F PHY 28 ~ 31’s group ID 0x0C 0xFF

0x1A60
-
0x00 –
0x1A63 PHY 32 ~ 35’s group ID 0x0D 0xFF

0x1A64
-
0x00 –
0x1A67 PHY 36 ~ 39’s group ID 0x0E 0xFF

0x1A68
-
0x00 –
0x1A6B PHY 40 ~ 43’s group ID 0x0F 0xFF

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...........continued
Value
Byte/Bit 7 6 5 4 3 2 1 0 Default Range

0x1A6C
-
0x00 –
0x1A6F PHY 44 ~ 47’s group ID 0x10 0xFF

0x1A70
-
0x00 –
0x1A73 PHY 48 ~ 51’s group ID 0x11 0xFF

0x1A74
-
0x00 –
0x1A77 PHY 52 ~ 55’s group ID 0x12 0xFF

0x1A78
-
0x00 –
0x1A7B PHY 56 ~ 59’s group ID 0x13 0xFF

0x1A7C
-
0x00 –
0x1A7F PHY 60 ~ 63’s group ID 0x14 0xFF

0x1A80
-
0x00 –
0x1A83 PHY 64 ~ 67’s group ID 0x15 0xFF

0x1A84 -
0x1A8F Reserved 0x00 0x00

Table 8-49. SXP 12G Initialization String—Zone Manager Password and Saving Support Configuration

Value
Byte/bit 7 6 5 4 3 2 1 0 Default
Range

Zone Enable
Zone Zone Zone
PHY Disable
Zoning Manager Permission Manager Zone Information
0x1A90 Reserved Informat Zoning 0x01 Bit Fields
Enable Password Table Save Password Load
ion Save Save
Save Enable Enable Disable
Enable Enable

0x1A91 Zone Manager Default Password Byte 0 0x00 Any

… … … …

0x1AB0 Zone Manager Default Password Byte 31 0x00 Any

0x1AB1 –
Reserved 0x00 0x00
0x1ACF

8.3.1.185 Zoning Enable Field

The field turns on (1) or off (0) the default zoning feature on a zoning capability enabled expander device.
Enabling zoning capability does not necessarily enable zoning on the expander. The SMP function SMP ENABLE
DISABLE ZONING function can be used to enable/disable zoning on the fly.

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By default, the ‘zoning enable’ field is used to enable/disable zoning in an expander device on which zoning capability
is enabled.

8.3.1.186 Zone Manager Password Save Enable Field

The field turns on (1) or off (0) the zone manager password saving support feature on a zoning-capable expander
device.

8.3.1.187 Zone PHY information Save Field

The field turns on (1) or off (0) the zone PHY information saving support feature on a zoning-capable expander
device.

8.3.1.188 Zone Permission Table Save Enable Field

The field turns on (1) or off (0) zone permission table saving support feature on a zoning-capable expander device.

8.3.1.189 Enable Disable Zoning Save Enable Field

The field turns on (1) or off (0) the enable disable zoning saving support feature on a zoning-capable expander
device.

8.3.1.190 Zone Manager Password Disable Field

The field turns on (1) or off (0) the zone manager DISABLED password support feature on a zoning-capable
expander device.
The zone manager DISABLED password (all the 32 bytes are FF) is a well-known value that does not provide
access to any zone manager (for example, zone manager password is disabled). If the Zone Manager Password
Disable Field is set to 1, then the firmware allows the zone manager password to be configured to DISABLED
password (all the 32 bytes are FF) through SMP function CONFIGURE ZONE MANAGER PASSWORD. If the
Zone Manager Password Disable Field is set to 0, it means the zoning expander device does not support the
DISABLED password and the firmware will return a function result of DISABLED PASSWORD NOT SUPPORTED
in the response frame for SMP function CONFIGURE ZONE MANAGER PASSWORD request with the NEW ZONE
MANAGER PASSWORD field set to the DISABLED password. For more details, see [4]10.4.3.24.

8.3.1.191 Zone Information Load Field

The field turns on (1) or off (0) the feature of loading the saved zone information for zoning configuration during
expander power-on if any zone information saving feature is enabled on a zoning-capable expander device.
The saved zoning information is stored in serial EEPROM. The firmware checks the CRC when loading the
saved zone PHY information, the saved zone permission table, or the saved zone manager password. If the CRC
check passes, the firmware uses the saved zoning information to configure the zoning during expander power-on.
Otherwise, the firmware uses the default zoning information which is defined in initialization string to do zoning
configuration.
Note: All zoning-related fields are valid if the Global Zoning Enable bit [0x0058:7] is set to 1. Otherwise the expander
device does not support zoning feature, and the zoning related fields are ignored.

8.3.1.192 Zone Manager Default Password Field

This field consists of 32 bytes which define the default value of Zone Manager Password.
Table 8-50. Virtual SSP/SMP Zoning Configuration

Value
Byte/bit 7 6 5 4 3 2 1 0 Default
Range

0x00 –
0x1AD0 Virtual SSP/SMP PHY’s Group ID 0x01
0xFF

0x1AD1 –
Reserved 0x00 0x00
0x1AFF

8.3.1.193 Group ID Field

The Group ID field contains the zone group to which the PHY belongs. The zone group of the SMP initiator port and
SMP target port in a zoning expander device must be 01h. See [4] 4.9.3.2 for detail.

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Note: Ensure that all the PHYs in an expander port have the same zone PHY information configuration including:
• Requested Inside ZPSDS
• Inside ZPSDS Persistent
• Group ID Persistent
• Group ID
Table 8-51. SXP 12G Initialization String—Zoning Permission Table

Value
Byte/Bit 7 6 5 4 3 2 1 0 Default Range

0x1B00 – Bit
0x1B1F Group 0 Permission Entry Fields

0x1B20 – Bit
0x1B3F Group 1 Permission Entry Fields

… …

0x1C00 –
0x1C1E Group 8 Permission Entry

0x1C1F –
0x1C3D Group 9 Permission Entry

0x1C3F –
0x2B7C Group 10 to Group 252 Permission Entry

Bit
0x2B7D Group 253 Permission Entry Fields

0x2B7E Group 254 Permission Entry

0x2B7F Group 255 Permission Entry

0x2B80 -
0x2BFF Reserved

8.3.1.194 Group Permission Entry

The Zoning Permission Table holds 256 entries, with each entry from 1 bytes to 16 bytes in length. Each entry has
the following format (using entry 0 as an example):
Table 8-52. Zoning Permission Table Entry Format

Byte/B Value
7 6 5 4 3 2 1 0 Default
it Range

0x1B00 Group 0 Permission Entry: groups 7 – 0, P[0, 7-0] 0x02 Bit Fields

0x1B01 Group 0 Permission Entry: groups 15 – 8, P[0, 15-8] 0x00 Bit Fields

0x1B02 Group 0 Permission Entry: groups 23 – 16, P[0, 23-16] 0x00 Bit Fields

0x1B03 Group 0 Permission Entry: groups 31 – 24, P[0, 31-24] 0x00 Bit Fields

0x1B04 Group 0 Permission Entry: groups 39 – 32, P[0, 39-32] 0x00 Bit Fields

0x1B05 Group 0 Permission Entry: groups 47 – 40, P[0, 47-40] 0x00 Bit Fields

0x1B06 Group 0 Permission Entry: groups 55 – 48, P[0, 55-48] 0x00 Bit Fields

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...........continued
Byte/B Value
7 6 5 4 3 2 1 0 Default
it Range

0x1B07 Group 0 Permission Entry: groups 63 – 56, P[0, 63-56] 0x00 Bit Fields

0x1B08 Group 0 Permission Entry: groups 71 – 64, P[0, 71-64] 0x00 Bit Fields

0x1B09 Group 0 Permission Entry: groups 79 – 72, P[0, 79-72] 0x00 Bit Fields

0x1B0
A~
Group 0 Permission Entry: groups 247 – 80, P[0, 2477-80] 0x00 Bit Fields
0x1B1
E

0x1B1
Group 0 Permission Entry: groups 255 – 248, P[0, 255-248] 0x00 Bit Fields
F

Since the zoning group is extended to 256, the normal entry number is 256*256/8 bytes = 8 Kbytes. This occupies
the initialization string space by half. Considering that the zoning permission table is symmetric as described.
The fields in gray can be removed in the firmware initialization string reducing the initialization string space by about
half. Now, Group 0 ~ 7 needs 32 bytes, Group 8~15 needs 31bytes, … Group 247~255 needs 1 bytes. The total
number is (32+31+..+1)*8 bytes = 4224 bytes.
Table 8-53. Zoning Symmetric

Zone Group 0 1 2 3 4 5 6 7 8 9 10 … 254 255 Byte

0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 32

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 32

2 0 1 ZP ZP R R R R ZP ZP ZP ZP ZP ZP 32

3 0 1 ZP ZP R R R R ZP ZP ZP ZP ZP ZP 32

4 0 1 R R R R R R R R R R R R 32

5 0 1 R R R R R R R R R R R R 32

6 0 1 R R R R R R R R R R R R 32

7 0 1 R R R R R R R R R R R R 32

8 0 1 ZP ZP R R R R ZP ZP ZP ZP ZP ZP 31

9 0 1 ZP ZP R R R R ZP ZP ZP ZP ZP ZP 31

10 0 1 ZP ZP R R R R ZP ZP ZP ZP ZP ZP 31

… 0 1 ZP ZP R R R R ZP ZP ZP ZP ZP ZP …

254 0 1 ZP ZP R R R R ZP ZP ZP ZP ZP ZP 1

255 0 1 ZP ZP R R R R ZP ZP ZP ZP ZP ZP 1

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Table 8-54. SXP 12G Initialization String Table--Patch Table

Byte/Bit 7 6 5 4 3 2 1 0 Default Value Range

0x3800 Patch Entry Count [15:8]

0x00 0 – 0x6A
0x3801 Patch Entry Count [7:0]

0x3802 –
Reserved 0x00
0x380F

FW Me-
0x3810 – Device ID Entry
Reserved mory 0x00 Bit Fields
0x3822 Option Enable
Enable

(Patch
Entry 0 Device ID [15:8]
Info) 0x0000 0x8056,

Device ID [7:0]

Revision ID
Reserved Revision ID 0x00 Bit Fields
Option

Repeat Count 0x00 0x00 – 0xFF

Address Increment [15:8] 0x0000 –

0x0000
Address Increment [7:0] 0xFFFF

Address [31:24]

Address [23:16] 0x80000000

0x00000000 –
Address [15:8] 0xFFFFFFFF

Address [7:0]

Mask [31:24]

Mask [23:16]
0x00000000 Any
Mask [15:8]

Mask [7:0]

Value [31:24]

Value [23:16]
0x00000000 Any
Value [15:8]

Value [7:0]

0x3823 –
0x3835 Same as
Same as
(Patch Structure content is the same as that for Patch Entry 0 Patch Entry
Patch Entry 0
Entry 1 0
Info)

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...........continued
Byte/Bit 7 6 5 4 3 2 1 0 Default Value Range

0x3836 –
0x3848 Same as
Same as
(Patch Structure content is the same as that for Patch Entry 0 Patch Entry
Patch Entry 0
Entry 2 0
Info)

0x3849 –
0x3FC7

(Patch ... ... ...

Entries 3
to 103)

0x3FC8
–
0x3FDA Same as
Same as
Structure content is the same as that for Patch Entry 0 Patch Entry
(Patch Patch Entry 0
0
Entry 104
Info)

0x3FDB
–
0x3FED Same as
Same as
Structure content is the same as that for Patch Entry 0 Patch Entry
(Patch Patch Entry 0
0
Entry 105
Info)

0x3FEE
Reserved 0x00
– 0x3FF7

The Initialization String Patch Table lets you patch any address location accessible by the MIPS processor. This
includes the address range 0x80000000 – 0xFFFFFFFF.

8.3.1.195 Patch Entry Count Field

This 16-bit field specifies the number of consecutive entries in the patch table with valid configuration information. A
count value of 0 indicates that none of the entries in the table is to be processed, whereas a count of 106 indicates
that entries in the table are to be processed. Whether an entry is applied is determined by its ‘Entry Enable’ bit. Entry
indices are numbered from 0 to 105.

8.3.1.196 Entry Enable Field

If this field is set to 0, the remaining configuration information for the entry is ignored and the patch not applied.
Otherwise, the entry configuration is processed to determine if the patch can be applied based on the device ID,
device revision, and patch address settings.

8.3.1.197 FW Memory Enable Field

This field enables the patch entry to be applied to the memory range that stores the firmware code
(0xBF000000-0xBF3FFFFF and its cached equivalent 0x9F000000-0x9F3FFFFF). When the address is in the range
of the firmware and the ‘FW Memory Enable’ bit is set to:
0: The patch entry is not applied.
1: The patch entry is applied.

8.3.1.198 Device ID Option Field

The device ID option field specifies which device to apply the patch entry. The following table lists the valid values for
this field.

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Table 8-55. Patch Entry Device ID Option

Device ID Option Condition

0 Apply patch entry to all devices in the family

1 Apply patch entry to only the device matching the value in the Device ID field

2 Apply patch entry to all non-zoning capable (non-GSec) devices

3 Apply patch entry to all zoning-capable (GSec) devices

8.3.1.199 Device ID Field

This field specifies the device ID to apply the patch entry against. The device ID field is used when the ‘Device ID
Option’ field is set to 1.

8.3.1.200 Revision ID Field

The ‘Revision ID’ field specifies the device revision to apply the patch entry against. This field is used with the
‘Revision ID Option’ field. See Table 8-56.

8.3.1.201 Revision ID Option Field

This field specifies the revision of the device to apply the patch entry against, as shown in the following table.
Table 8-56. Patch Entry Revision ID Option

Revision ID Condition
Option

0 Apply patch entry to device revisions

1 Apply patch entry to only the device matching the value in the Revision ID field

2 Apply patch entry to revisions greater than the revision specified by the Revision ID field

3 Apply patch entry to revisions less than the revision specified by the Revision ID field

8.3.1.202 Repeat Count Field

The repeat count field specifies the number of times this patch entry should be applied. For example, when a register
repeats for multiple PHYs, such as 0xA810_0028 + n *0x1000, where n is 0 to 67, to apply the patch entry to the 68
PHYs for register 0xA810_0028, the repeat count is set to 67 and the address increment is set to 0x1000. The actual
number of patch applications is Repeat Count + 1.

8.3.1.203 Address Increment Field

The address increment field specifies the amount the address should be incremented each time the application of the
patch entry is repeated. For example, when a register repeats for multiple PHYs, such 0xA810_0028 + n *0x1000,
where n is 0 to 67, to apply the patch entry to the 68 PHYs for register 0xA810_0028 the repeat count is set to 67 and
the address increment is set to 0x1000.

8.3.1.204 Address Field

The address field specifies the (starting) address to be patched.

8.3.1.205 Mask Field

The mask field specifies the bits in the value field to apply.
When the mask is set to:
0: The equivalent bit in the value field is not modified at the given patch address.
1: The equivalent bit in the value field is applied to the specified address.

8.3.1.206 Value Field

The value field specifies the data, filtered by the mask field, to be written to the patch address.

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8.3.2 Serial EEPROM Initialization String Format

The serial EEPROM initialization string table duplicates many of the parameters that are stored in the table that is
resident in the flash memory. When Serial EEPROM Initialization String Configuration is globally enabled through
the Flash Initialization String Field ‘EEPROM Avail’ in Table 8-5, these duplicated parameters override the equivalent
flash-resident parameters when the EEPROM exists and is valid. The descriptions for each one of the parameters
can be referenced from the flash table. The entire Serial EEPROM initialization string table is shown in Table 8-57.
The addressing configuration block over-rides the flash table equivalent if the serial EEPROM exists. The SGPIO,
disk spin-up, topology configuration, redundant virtual SSP, and SES enclosure blocks may or may not be used,
depending on their respective block valid bit setting in offset 0x1E of the table.
Table 8-57. Serial EEPROM Initialization String Table

Byte Offset Allocation

0x0000 – 0x001D Device Address Configuration Block (Table 8-58)
0x001E – 0x001F Config Block Valid Block (Table 8-59)
0x0020 – 0x002F Topology Discovery Configuration Block (Table 8-60)
0x0030 – 0x003F Disk Spin-Up Configuration Block (Table 8-40 except the different byte offsets)
0x0040 – 0x0055 SGPIO Configuration Block (Table 8-61)
0x0056 – 0x005F Redundant Virtual SSP Link Configuration Block (Table 8-62)
0x0060 – 0x007B SES-3 Enclosure Logical Identification Configuration Block (Table 8-63)
0x0080 – 0x0094 Ethernet Configuration Block (Table 8-64)
0x0098 – 0x00b7 SES-3 subenclosure nickname (Table 8-65)
0x0100 – 0x21BE Saved Zoning Information Block (Table 8-66)

Table 8-58. Serial EEPROM Initialization String Table—Device Address Configuration

Byte \ 7 6 5 4 3 2 1 0 Default
Bit
0x0000 Table Size Byte 1 (MSB) 0x01
0x0001 Table Size Byte 0 (LSB) 0x00
0x0002 Table Revision– Major (Microchip) Table Revision– Minor (Microchip) 0x00
0x0003 Table Revision (vendor-specific) 0x00
–
0x0006
0x0007 Reserved 0x00
0x0008 SAS_BASE_ADDR [63:56] 0x50
0x0009 SAS_BASE_ADDR [55:48] 0x0E
0x000A SAS_BASE_ADDR [47:40] 0x00
0x000B SAS_BASE_ADDR [39:32] 0x4A
0x000C SAS_BASE_ADDR [31:24] 0xAA
0x000D SAS_BASE_ADDR [23:16] 0xAA
0x000E SAS_BASE_ADDR [15:8] 0xAA
0x000F SAS_BASE_ADDR [7:N+1] (the bits masked by SAS base address LSB[N:0] Mask must be 0) 0x00

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...........continued
Byte \ 7 6 5 4 3 2 1 0 Default
Bit
0x0010 Reserve SMP SAS address LSB [N:0] 0x7F
d
0x0011 Reserve SSP SAS address LSB [N:0] 0x7E
d
0x0012 Reserve SAS base address LSB[N:0] Mask 0x7F
d
0x0013 Reserved 0x00
0x0014 Logical SUB_PHY_FLAG (reserved) 0x00
0x0015 Logical SUB PHY FLAG (reserved) Logical SUB_PHY_FLAG[67:64] 0x00
0x0016 Logical SUB_PHY_FLAG [63:56] 0x00
0x0017 Logical SUB_PHY_FLAG [55:48] 0x00
0x0018 Logical SUB_PHY_FLAG [47:40] 0x00
0x0019 Logical SUB_PHY_FLAG [39:32] 0x00
0x001A Logical SUB_PHY_FLAG [31:24] 0x00
0x001B Logical SUB_PHY_FLAG [23:16] 0x00
0x001C Logical SUB_PHY_FLAG [15:8] 0x00
0x001D Logical SUB_PHY_FLAG [7:0] 0x0F

For detailed information on each field, see Table 8-5.

Table 8-59. Serial EEPROM Initialization String Table—Config Valid

Byte\Bit 7 6 5 4 3 2 1 0 Default
0x001E Reserved Ethernet SES Redundant SGPIO Spin-Up Topology 0x00
Info Enclosure VSSP Map
Logical ID
0x001F Reserved 0x00

8.3.2.1 Topology Block Valid Field

When this bit is set to:
1: The 12-byte topology parameters block, residing from offset 0x20 to 0x2B, is read and used in place of its
respective flash-resident counterpart.
0: The block is ignored.

8.3.2.2 Spin-Up Block Valid Field

When this bit is set to:
1: The 15-byte disk spin-up parameters block, residing from offset 0x30 to 0x3E, is read and used in place of its
respective flash-resident counterpart.
0: The block is ignored.

8.3.2.3 SGPIO Block Valid Field

When this bit is set to:
1: The 18-byte SGPIO parameters block, residing from offset 0x40 to 0x51, is read and used in place of its respective
flash-resident counterpart.

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Initialization String

0: The block is ignored.

8.3.2.4 Redundant VSSP Block Valid Field

When this bit is set to:
1: The 10-byte redundant VSSP link map parameter block, residing from offset 0x56 to 0x5F, is read and used in
place of its respective flash-resident counterpart.
0: The block is ignored.

8.3.2.5 SES Enclosure Logical ID Valid Field

When this bit is set to:
1: The 8-byte SES enclosure logical identifier parameter block, residing from offset 0x60 to 0x67, is read and used in
place of its respective flash-resident counterpart.
0: The block is ignored.

8.3.2.6 Ethernet info Block Valid Field

When this bit is set to:
1: The 20-byte Ethernet Info parameter block, residing from offset 0x80 to 0x94, is read and used in place of its
respective flash-resident counterpart.
0: The block is ignored.
Table 8-60. Serial EEPROM Initialization String Table—Topology Discovery Configuration
Value
Byte \ Bit 7 6 5 4 3 2 1 0 Default
Range

Disable Route
Table to Obsolete Self-Configuring
0x0020 SSP Table Fan-out Expander Reserved 0x91 Bit Fields
table Enable (Reserved) Expander
Target Port Clean-up

0x0021 Logical Route Table Entries per PHY [15:8] 0x10

0 – 0x1000
0x0022 Logical Route Table Entries per PHY [7:0] 0x00

0x0023 PHY Event Damping Interval [15:8] (in 100us) 0x00

0 – 0xFFFF
0x0024 PHY Event Damping Interval [7:0] (in 100us) 0x00

0x01 –
0x0025 Topology Thread Instances 0x01 PHY_
COUNT

0x0026 PHY Polling Period (in ms) 0x0A 0x01 – 0xFF

0x0027 Reserved 0x00

0x0028 Reserved 0x00

0x0029 Application Level SMP Initiator Maximum Retry Count 0x0A 0x00 – 0xFF

0x002A SATA PHY Validation Count 0x0A 0x0A – 0xFF

Open NSCFG Legacy

Global Bad Destination Disk Wide-port
Reject Route Table Expander Loop Detection
0x002B Zoning Primitive Qualificatio Policing 0x13 Bit Fields
Retry Compression Route Index Enable
Enable Disabled n Enable Enable
Enable Enable Disabled

0x002C – 0x002F Reserved 0x00

Table 8-61. Serial EEPROM Initialization String Table—SGPIO Configuration

Byte \ Bit 7 6 5 4 3 2 1 0 Default Value Range

SGPIO SGPIO
SGPIO PHY Ready
0x0040 SGPIO Cascade General Purpose Slave SLoad Pattern Cascade Cascade 0x12
Indication
Master Enable

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Initialization String

...........continued

Byte \ Bit 7 6 5 4 3 2 1 0 Default Value Range

0x0041 SGPIO Cascade Offset Count Timeslot(MSB)

0x006C
0x0042 SGPIO Cascade Offset Count Timeslot (LSB)
(Offset + 3*PhyCount) <=
(3*TotalDriveCount)
0x0043 SGPIO Cascade Total Drive Count (MSB)
0x0048
0x0044 SGPIO Cascade Total Drive Count (LSB)

0x0045 SGPIO Cascade General Purpose Output Offset Timeslot (MSB)

0x00A0
0x0046 SGPIO Cascade General Purpose Output Offset Timeslot (LSB)
(Offset + 160) <=
(32*Register Count)
0x0047 SGPIO Cascade Total General Purpose Register Count (MSB)
0x000A
0x0048 SGPIO Cascade Total General Purpose Register Count (LSB)

GPIO Enable
0x0049 Reserved 0x01
flag

0x004A Activity Locate Error 0xA0

0x004B Stretch Off Stretch On 0x03

0x004C Force Activity Off Max Activity On 0x48

0x004D Blink Rate A Blink Rate B 0x00

0x004E SGPIO PHY Ready Update Rate (in units of 10ms) 0x0A 0x00 – 0xFF

0x004F SGPIO Update Rate (in units of us) (MSB)

0x3D09 0x3D09 – 0xFFFF
0x0050 SGPIO Update Rate (in units of us) (LSB)

0x0051 SGPIO SCLOCK Filter 0x80 0x00 – 0xFF

0x0052 –
Reserved (for SGPIO expansion) 0x00
0x0055

Detailed information for each field can be referenced to the description in Table 8-7.
Table 8-62. Serial EEPROM Initialization String Table—Redundant Virtual SSP Link Configuration

Byte/Bit 7 6 5 4 3 2 1 0 Default Value Range

0x0056 Redundant Virtual SSP Link Map (Reserved) 0x00

Redundant Virtual SSP Link Map Redundant Virtual SSP Link Map
0x0057 0x00 Bit Fields
(Reserved) [67:64]

0x0058 Redundant Virtual SSP Link Map [63:56] 0x00 Bit Fields

0x0059 Redundant Virtual SSP Link Map [55:48] 0x00 Bit Fields

0x005A Redundant Virtual SSP Link Map [47:40] 0x00 Bit Fields

0x005B Redundant Virtual SSP Link Map [39:32] 0x00 Bit Fields

0x005C Redundant Virtual SSP Link Map [31:24] 0x00 Bit Fields

0x005D Redundant Virtual SSP Link Map [23:16] 0x00 Bit Fields

0x005E Redundant Virtual SSP Link Map [15:8] 0x00 Bit Fields

0x005F Redundant Virtual SSP Link Map [7:0] 0x00 Bit Fields

Detailed information for each field can be referenced to the description in Table 8-38

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Initialization String

Table 8-63. Serial EEPROM Initialization String Table—SES-3 Enclosure Logical Identification Configuration

Byte/bit 7 6 5 4 3 2 1 0 Default

0x0060 SES-3 Enclosure Logical Identifier [63:56] 0x00

0x0061 SES-3 Enclosure Logical Identifier [55:48] 0x00

0x0062 SES-3 Enclosure Logical Identifier [47:40] 0x00

0x0063 SES-3 Enclosure Logical Identifier [39:32] 0x00

0x0064 SES-3 Enclosure Logical Identifier [31:24] 0x00

0x0065 SES-3 Enclosure Logical Identifier [23:16] 0x00

0x0066 SES-3 Enclosure Logical Identifier [15:8] 0x00

0x0067 SES-3 Enclosure Logical Identifier [7:0] 0x00

0x0068–
Reserved 0x00
0x007B

Detailed information for each field can be referenced to the description in Table 8-36.
Table 8-64. Serial EEPROM Initialization String Table—Ethernet Configuration

Value
Byte/Bit 7 6 5 4 3 2 1 0 Default
Range

0x00 –
0x0080 DHCP ON/OFF 0x00
0x01

0x00 –
0x0081 Local IP[0] 0x0A
0xFF

0x00 –
0x0082 Local IP[1] 0xBC
0xFF

0x00 –
0x0083 Local IP[2] 0x75
0xFF

0x00 –
0x0084 Local IP[3] 0x50
0xFF

0x00 –
0x0085 Net Mask [0] 0xFF
0xFF

0x00 –
0x0086 Net Mask [1] 0xFF
0xFF

0x00 –
0x0087 Net Mask [2] 0xFC
0xFF

0x00 –
0x0088 Net Mask [3] 0x00
0xFF

0x00 –
0x0089 Gate Way [0] 0x0A
0xFF

0x00 –
0x008A Gate Way [1] 0xBC
0xFF

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Initialization String

...........continued
Value
Byte/Bit 7 6 5 4 3 2 1 0 Default
Range

0x00 –
0x008B Gate Way [2] 0x74
0xFF

0x00 –
0x008C Gate Way [3] 0x01
0xFF

0x00 –
0x008D MAC Addr [0] 0x00
0xFF

0x00 –
0x008E MAC Addr [1] 0xE0
0xFF

0x00 –
0x008F MAC Addr [2] 0x04
0xFF

0x00 –
0x0090 MAC Addr [3] 0xFE
0xFF

0x00 –
0x0091 MAC Addr [4] 0xDC
0xFF

0x00 –
0x0092 MAC Addr [5] 0xBA
0xFF

RMII Negative Auto-

0x0093 Reserved Speed Duplex 0x01 Bit Fields
Disable Polarity neg

0x00 –
0x0094 Ethernet PHY ID 0x01
0x1F

0x0095 –
Reserved for Microchip 0x00 0x00
0x00BF

0x00C0 –
Reserved for Customers 0x00 0x00
0x00FB

0x00FC – 0x00 –
CRC for offset 0x0000 ~ 0x00FB 0x00
0x00FF 0xFF

Detailed information for each field can be found in the description in Table 8-38.
Table 8-65. Serial EEPROM Initialization String Table—SES-3 subenclosure nickname

Byte/Bit 7 6 5 4 3 2 1 0 Default

0x0098 SES-3 subenclosure nickname byte 0 0x54

0x0099 SES-3 subenclosure nickname byte 1 0x68

0x009a SES-3 subenclosure nickname byte 2 0x69

0x009b SES-3 subenclosure nickname byte 3 0x73

0x009c SES-3 subenclosure nickname byte 4 0x20

0x009d SES-3 subenclosure nickname byte 5 0x69

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...........continued
Byte/Bit 7 6 5 4 3 2 1 0 Default

0x009e SES-3 subenclosure nickname byte 6 0x73

0x009f SES-3 subenclosure nickname byte 7 0x20

0x00a0 SES-3 subenclosure nickname byte 8 0x53

0x00a1 SES-3 subenclosure nickname byte 9 0x75

0x00a2 SES-3 subenclosure nickname byte 10 0x62

0x00a3 SES-3 subenclosure nickname byte 11 0x65

0x00a4 SES-3 subenclosure nickname byte 12 0x6e

0x00a5 SES-3 subenclosure nickname byte 13 0x63

0x00a6 SES-3 subenclosure nickname byte 14 0x6c

0x00a7 SES-3 subenclosure nickname byte 15 0x6f

0x00a8 SES-3 subenclosure nickname byte 16 0x73

0x00a9 SES-3 subenclosure nickname byte 17 0x75

0x00aa SES-3 subenclosure nickname byte 18 0x72

0x00ab SES-3 subenclosure nickname byte 19 0x65

0x00ac SES-3 subenclosure nickname byte 20 0x20

0x00ad SES-3 subenclosure nickname byte 21 0x4e

0x00ae SES-3 subenclosure nickname byte 22 0x69

0x00af SES-3 subenclosure nickname byte 23 0x63

0x00b0 SES-3 subenclosure nickname byte 24 0x6b

0x00b1 SES-3 subenclosure nickname byte 25 0x6e

0x00b2 SES-3 subenclosure nickname byte 26 0x61

0x00b3 SES-3 subenclosure nickname byte 27 0x6d

0x00b4 SES-3 subenclosure nickname byte 28 0x65

0x00b5 SES-3 subenclosure nickname byte 29 0x20

0x00b6 SES-3 subenclosure nickname byte 30 0x20

0x00b7 SES-3 subenclosure nickname byte 31 0x20

8.3.2.7 Customized Location of Saved Zoning Information Block

When SAS-2 zoning capabilities and the save support for zoning configuration are enabled in the SXP 12G expander,
the SXP 12G firmware requires an 8383-byte block to store the saved zone information in the Serial EEPROM. The
format is shown in Table 8-66.
The Serial EEPROM device used to store the zoning configuration is defined in initialization string. Refer to Table 8-5.
The zoning configuration information in Serial EEPROM device location is now hard coded in the SXP 12G firmware
source code as the following macros:

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• Offset in SEEPROM: SMPSTD_BYTEOFF_ZONE_SAVED_VALUE_DATA

The default value of Offset in SEEPROM is 256 in firmware.
Table 8-66. Serial EEPROM Initialization String Table—Saved Zoning Information Format

Byte/Bit 7 6 5 4 3 2 1 0

Zoning
0 Reserved
Enable

2 Reserved

4 - -
Zone Manager Password
35 - -

36
CRC of Zone Manager Password and Zoning Enable
39

40 Number of PHYs (m <= 69)

41 - Zone PHY Information Descriptor for PHY 0 -

42 - (See Table 8-67) -

… …

… - -
Zone PHY Information Descriptor for PHY m (=68)
40+69*2 = 178 - -

179
CRC of Zone PHY Information Descriptor and Number of PHYs
182

183 Reserved

184
Number of Zone Groups (n=256)
185

186 - Zone Permission Policy Table for Group 0 -

… - (See Table 8-68) -

… …

… - -

256*256/8 + 185 = Zone Permission Policy Table for Group 256

- -
8377

8378
CRC of Zone Permission Table and Number of Zone Groups
8381

8382 Reserved

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Table 8-67. Zone PHY Information Descriptor

Byte/Bit 7 6 5 4 3 2 1 0

ZONE GROUP INSIDE ZPSDS REQUESTED

0 Reserved
PERSISTENT PERSISTENT INSIDE ZPSDS

1 ZONE GROUP

The definitions of the fields in Table 8-66 and Table 8-67 are consistent with the definitions in [4].
Table 8-68. Permission Policy Table for a source group (i.e., s)

Byte/Bit 7 6 5 4 3 2 1 0

0 ZP(s, n-1) ZP(s, n-2) ZP(s, n-3) ZP(s, n-4) ZP(s, n-5) ZP(s, n-6) ZP(s, n-7) ZP(s, n-8)

… …

31 ZP(s,7) ZP(s,6) ZP(s,5) ZP(s,4) ZP(s,3) ZP(s,2) ZP(s,1) ZP(s,0)

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9. Time Services Library

9.1 Watchdog Thread and Watchdog Timer

The Watchdog Thread monitors the health of the threads in the system by sending a message periodically to a list
of threads. It expects a response in return from each of these threads. The Watchdog Thread ceases to reload the
watchdog timer, and lets it expire if either of the following conditions is true:
• Insufficient real time for the watchdog thread to reload the watchdog timer, due to some threads not relinquishing
the CPU for a period greater than the watchdog timer period; or
• Watchdog timer timeout while waiting for a response from one or more of the other threads in the system.
The list of threads to be pinged is configurable; you may even register any threads you develop with the watchdog
timer so that they are pinged. It is not required for a thread or the system to use the watchdog operations. However,
the threads provided by Microchip are designed to respond to a watchdog message if enabled. In order to be pinged
by the watchdog, a thread must:
• Call wdg_user_register() to register its mailbox with the watchdog in the thread’s xxx_init() function called by
tx_application_define();
• Add WDG_NUM_PING_MSG_MAX1 to its mailbox length to accommodate the watchdog ping message; and
• When a watchdog ping message (WDG_MSG_PING) is received, call the wdg_user_msg_hdlr() function to
handle and respond to it.
The hardware watchdog timer is disabled at reset; once enabled it can only be disabled by system reset.
Note The bootloader should not enable the hardware watchdog timer. The application image watchdog thread should
be the only module that enables the hardware watchdog timer.
At system initialization, specify the maximum blocking duration for the system by overwriting the
max_block_duration_ms in the configurable parameter structure returned by wdg_parms_get() (See Sections
9.1.1 External Interface and 9.1.2 Data Structures for detail). The watchdog thread configures the hardware
watchdog timeout period to be the closest hardware watchdog timeout setting that is at least double the maximum
blocking duration specified.
Periodically, the watchdog thread sends a round of pings to all its registered users. If all the users respond with pong
messages within the hardware watchdog timeout period, the system is considered healthy and the watchdog thread
reloads the hardware watchdog timer to prevent it from expiring. The shortest period between two rounds of pings is
less than the hardware watchdog timeout period, which is at least the max_block_duration_ms you specify at system
initialization. The following figure shows the watchdog thread operation.

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Figure 9-1. Watchdog Thread Operation

wdg_m ain() starts

Update lowest watchdog

count if new low is reached

Kick hardware watchdog

Send a ping m essage to

each registered user

Yes

Have all users

responded with pong No
m essage?

Yes

Do som e low-level system

W ait for m essages
m aintenance

Has software ping

period elapsed since
last watchdog kick?

Sleep for (software ping

period - tim e elapsed since
last watchdog kick)

If the watchdog thread does not have enough real time to run, or if one or more users do not respond with pong
messages within a hardware watchdog timeout period, the watchdog thread will not reload the hardware watchdog
timer and allow it to expire. The hardware watchdog timer expiry has two stages.
• After the first hardware timeout period without being reloaded, the watchdog timer NMI interrupt is triggered. The
hardware watchdog timer interrupt service routine calls the watchdog NMI handler or PMCFW_ASSERT macro
which executes the user hook (wdg_nmi_hndl_hook() or pmcfw_assert_function()).
• After another hardware timeout period without being reloaded. The generic watchdog reset sequence is shown
in Figure 9-2.

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Figure 9-2. Watchdog Reset Sequence

hw wdg tim eout period hw wdg tim eout period

tim e

wdg thread kicks hw

interrupt(NM I)
hw wdg tim er

system reset
wdg tim er

Executes:
wdg thread pings all users.
wdg NM I handler
Not all wdg users repond
with pong m essages

In the wdg NMI handler, your firmware may service the hardware watchdog timer interrupt by signaling through an I/O
device and/or save a specific context, before allowing the system reset to take place.

9.1.1 External Interface

The firmware watchdog supports the following functions:
Table 9-1. Watchdog Functions

Function Description

wdg_parms_get Generates a structure of watchdog use-configurable parameters and initializes it with

default values.

wdg_create Allocates OSF resources required by watchdog.

wdg_init Initializes watchdog.

wdg_user_register Register threads to be pinged by watchdog.

wdg_user_msg_hdlr Function used by threads to handle ping messages from watchdog.

wdg_lowest_cnt_get Returns the lowest hardware watchdog count since reset.

wdg_hw_kick Restarts (kicks) the hardware watchdog and clears the hardware watchdog timer
interrupt.

9.1.1.1 wdg_parms_get
wdg_parms_get() generates a structure of configurable watchdog parameters and initializes it with default values.
It also specifies the OSF resources required by watchdog. See Section 9.1.2 Data Structures for further information
on wdg_parms_struct.
Calling sequence restrictions:
• This function should be called in tx_application_define().
• It must be called before any watchdog functions can be used.

Prototype wdg_parms_struct* wdg_parms_get(

osf_sys_cfg_struct *osf_cfg_ptr)

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Inputs osf_cfg_ptr Pointer to OSF system parameter structure.

Outputs osf_cfg_ptr Pointer to OSF system parameter structure, updated with resources
required by watchdog.

Returns Success = Pointer to allocated and initialized watchdog user-configurable

parameter structure.

prio Message priority at which user wants to be pinged.

Outputs None

Returns Success = None

Failure = None

Side Effects None

9.1.1.5 wdg_user_msg_hdlr
Use wdg_user_msg_hdlr() to handle ping messages from the watchdog by responding with a pong message. To
prevent you from using the received watchdog message buffer after it has been processed, this function lets OSF
take over the buffer by overwriting your double pointer to it.

Prototype void wdg_user_msg_hdlr(void **msg_pptr)

Inputs msg_pptr (Pointer to) pointer to received message from watchdog

Outputs None

Returns msg_pptr Pointer to message buffer updated to NULL if message processed

successfully
Pointer unchanged if message processing failed

msg_pptr Pointer to message buffer updated to NULL if message processed

successfully
Pointer unchanged if message processing failed

Side Effects None

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9.1.1.6 wdg_lowest_cnt_get
Use wdg_lowest_cnt_get() to get the lowest hardware watchdog timer count since reset.

Prototype UINT32 wdg_lowest_cnt_get(void)

Inputs None

Outputs None

Returns Success = Lowest hardware watchdog timer count since reset.

Failure =

Side Effects None

9.1.1.7 wdg_hw_kick
Use wdg_hw_kick() to restart the hardware watchdog timer and clear the hardware watchdog timer interrupt. This
prevents the watchdog induced system reset.

Prototype void wdg_hw_kick(void)

Inputs None

Outputs None

Returns Success = None

Failure = None

Side Effects None

9.1.2 Data Structures

9.1.2.1 wdg_parms_struct
The wdg_parms_struct contains the configurable parameters for the watchdog. wdg_parms_get() allocates and
initializes it with default values. You can overwrite the default values before the call to wdg_create(). The default
values are:
• max_block_duration_ms: Maximum time that a thread may be blocked from servicing the watchdog ping by
all other threads/interrupts in the system. The hardware watchdog timeout “hw wdg timeout period” is set by
rounding up to the next higher timeout that the watchdog timer supports. The hardware timeouts are shown in
register document for the SEP being utilized and are based on operating frequency of the device.
For example, for the watchdog running at 75 MHz, if this value is set to 6000 for a watchdog timeout and the next
higher watchdog period is 7.2 seconds.
thread_prio = 16
hw_enabled = TRUE if the preprocessor symbol WDG_ENABLE is defined; FALSE otherwise.

/********************************************************************
* STRUCTURE: wdg_cfg_struct
* ___________________________________________________________________
*
* DESCRIPTION:
* Structure defining user-configurable parameters of watchdog that
* can only be modified before call to wdg_create().
*

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* The default values are set by wdg_parms_get() and users are

* allowed to modify these values before the call to wdg_create().
*
* ELEMENTS:
* max_block_duration_ms - Maximum system blocking duration in
* milliseconds. This should be the
* greater of either 1) the sum of the
* maximum blocking periods for threads
* with priorities higher than watchdog;
* or 2) the greatest blocking period of
* threads with priorities lower than
* watchdog. The minimum allowable value
* is 2000 (since system rebooting time
* is about 2000ms).
* The maximum allowable value is:
* <= (longest watchdog timeout period
* setting)
* for the hardware watchdog timer.

* thread_stack_size - Stack size for thread in bytes

* thread_prio - Watchdog thread priority.
* hw_enabled - TRUE - enable watchdog hardware timer;
* FALSE - do not enable watchdog hardware
* timer
*
*********************************************************************/
typedef struct
{
UINT32 max_block_duration_ms;

UINT32 thread_stack_size;
UINT16 thread_prio;
BOOL hw_enabled;
} wdg_config_struct;

/********************************************************************
* STRUCTURE: wdg_parms_struct
* ___________________________________________________________________
*
* DESCRIPTION:
* Structure defining user-configurable parameters of watchdog.
*
* ELEMENTS:
* config - User configurable parameters that can only be modified
* before call to wdg_create().
*
*********************************************************************/
typedef struct
{
wdg_config_struct config;
} wdg_parms_struct;

9.2 Debug Console/Thread

The debug console thread listens to a configurable UART for incoming commands from a remote console. If the
debug console thread is included in your application image, users will be able to send diagnostic commands to
your embedded application through a UART. A debug console is useful during system integration testing since the
received commands can be used to pull out state information, inject errors or change peripheral register settings.
The debug console’s thread is typically launched at a very low priority to avoid interference with any of the other
threads in the application.

9.2.1 Terminal Interface

By default, the command server thread returns a prompt to a HyperTerminal and displays a menu of known
commands as follows:
Figure 9-3. Command Server Console Trace
0x00000000:0x00>mnu
unknown_cmd

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0x00000000:0x01>menu
menu Menu of commands
help Alias of menu
prompt Prompt on/off
reset Reset MIPS
rd_32 32-bit Read : rd_32 <address> <# of 32 bit words>
wr_32 32-bit Write : wr_32 <address> <data> [<address> <data>, . . . ]
rd_16 16-bit Read : rd_16 <address> <# of 16 bit words>
wr_16 16-bit Write : wr_16 <address> <data> [<address> <data>, . . . ]
rd_8 8-bit Read : rd_8 <address> <# of 8 bit words>
wr_8 8-bit Write : wr_8 <address> <data> [<address> <data>, . . . ]
rd_seeprom 8-bit Read : rd_seeprom <port_id> <device_addr> <offset> <offset_width>
<num of 8 bit words>
wr_seeprom 8-bit Write : wr_seeprom <port_id> <device_addr> <offset> <offset_width>
<data> [<data>, ...]
dwld Download : dwld -fl | -se <offset> <data> [<data>, ...]
log_sev Log severity : log_sev [severity]
(Get/Set: 0 - disable, 1 - highest, 2 - high, 3 - medium, 4 - low, 5 -
lowest)
log_filter Log filter : log_filter [<idx> <mask> <pattern> <type> <severity>]
rd_log Log retrieve : rd_log -fl | -ra <-p | -n <num of entries, default:40>>
dbs Database Read: dbs <page>
ipconfig Show/Config IP : ipconfig [[help]|[dhcp 0 | 1 [ip ip_addr] [nm netmask] [gw
gateway]]]
tftp_dwld TFTP download : tftp_dwld <host> <filename> [a - to activate]
emip EMIP control : emip [[help]|[log emip_id]]
mirror Port mirroring : mirror <on/off> <src_phy_id> [tx_dst_phy_id rx_dst_phy_id]
qinfo Query flash partition information. For internal debug use only
hash_tbl_map_get Retrieve indices of non-zero hash table entries
rd_ecbi ECBI read : rd_ecbi <addr> [<addr>, ...]
wr_ecbi ECBI write : wr_ecbi <addr> <data> [<addr> <data>, ...]
ind_sel Indirect select : ind_sel <table> <data>
ind_ecbi_rd Indirect read : ind_ecbi_rd <addr> [<addr>, ...]
rd_see Read SEEPROM : rd_see <offset> <num of bytes>
update_see Update SEEPROM : update_see [[help]|<cmd> <data> [<data>, ...]]
smp SMP command : smp <data> [<data>, ...]
vhist Vhist capture : vhist <Protocol> <Phy#_List> <capture_length>
<#bin_per_UART_line>
cinfo Cable information : cinfo <connector_id>
version Display firmware versions
status Display status : [sas_phy | sas_link | sas_clr_phy | sas_clr_link]
ssp SSP command : ssp <cmd> [<data>, ...]
logrt_info Retrieve logrt : logrt_info [display | undisplay | dump | undump | list]
phy_mapping Dump logical to physical phy mapping
rx_para_get Capture SAS Rx Parameters : rx_para_get <Phy#_List>
tx_para_get Capture SAS Tx Parameters : tx_para_get <Phy#_List>
err_cnts Dump error counters : err_cnts <Phy#_List> <read/clear>

0x00000000:0x02>prompt
prompt
0x00000000:0x04>

The prompt returned by the command server indicates which server the console is talking to, as well as an
incrementing command number. The server number, 0 in the previous figure, is best defined by a unique number
assigned to your running application. In a SAS expander processor this might be the SAS address assigned to the
SAS expander, which is known to be world-wide-unique.
The prompt is useful when a human user is entering commands. But often the console is at the bottom of a set of
test or diagnostic scripts, in which case the prompt can be disabled making it easier to extract the results of each
command.
The CLI command ‘ind_ecbi_rd’ is expected to be used with the ‘ind_sel’ CLI command to display the table type and
table entry. The following table provides the valid entries for ind_ecbi_rd and ind_sel.
Table 9-2. Valid Entries for Indirect Register Access Through CLI

Table Type Valid Entry Valid Register Offsets

Number

Direct 0-71 0xa,0xb,0xc,0xd,0xe,0xf,0x10,0x11,0x12,0x13

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...........continued
Table Type Valid Entry Valid Register Offsets
Number

Hash 0-4095 0x15,0x16,0x17,0x18

9.2.2 Command Parsing

The command server utilizes stdio lib to retrieve lines of input from the remote console arriving over UART. The
character streams stdin and stdout are redirected to a UART for the command server thread.
Each incoming command is separated by an end-of-line or carriage return character and consists of one or
more words separated by white-space. The first word is used to find the local function correlating to the
command name. This mapping of embedded functions and command names is defined by a table as follows (see
cmdsvr_known_cmds. c):
Figure 9-4. Command Server Command List

const cmdsvr_cmd_def_struct cmdsvr_cmd_set[] =

{
{"menu", " Menu of commands",
cmdsvr_help},
{"help", " Alias of menu", cmdsvr_help},
{"prompt", " Prompt on/off",
cmdsvr_prompt},
{"reset", " Reset MIPS :",
cmdsvr_reset},
{"rd_32", " 32-bit Read : rd_32 <address> <# of 32 bit words>",
cmdsvr_mem_rd_32},
{"wr_32", " 32-bit Write : wr_32 <address> <data> [<address> <data>, . . . ]",
cmdsvr_mem_wr_32},
{"rd_16", " 16-bit Read : rd_16 <address> <# of 16 bit words>",
cmdsvr_mem_rd_16},
{"wr_16", " 16-bit Write : wr_16 <address> <data> [<address> <data>, . . . ]",
cmdsvr_mem_wr_16},
{"rd_8", " 8-bit Read : rd_8 <address> <# of 8 bit words>",
cmdsvr_mem_rd_8},
{"wr_8", " 8-bit Write : wr_8 <address> <data> [<address> <data>, . . . ]",
cmdsvr_mem_wr_8},
{"dwld", " Download : dwld -fl|-se <offset> <hexdata0>. . .
", cmdsvr_dwld},
{"log_sev", " Log severity : log_sev [severity]",
cmdsvr_log_sev},
{"dbs", " Database Read : dbs <page>",
cmdsvr_dbs_rd},
#ifdef EMIP_ENABLE
{"emip", " EMIP control : emip [[help]|[log
emip_id]]", cmdsvr_emip},
#endif
#ifdef TCPIP_ENABLE
{"tftp_dwld"," TFTP download : tftp_dwld <host> <filename> [a - to activate]",
cmdsvr_tftp_dwld},
{"ipconfig", " Show/Config IP : ipconfig [[help]|[dhcp 0 | 1 [ip ip_addr] [nm netmask]
[gw gateway]]]",
cmdsvr_ipconfig},
#endif
{"log_filter","Log filter : log_filter [<idx> <mask> <pattern> <type> <severity>]",
cmdsvr_log_filter},
{"rd_seeprom","Read SEEPROM : rd_seeprom <port_id> <device_addr> <offset>
<offset_width> <num of 8 bit words>",
cmdsvr_rd_seeprom},
{"wr_seeprom","Write SEEPROM : wr_seeprom <port_id> <device_addr> <offset>
<offset_width> <data> [<data>",
cmdsvr_wr_seeprom},
{"rd_log", " Log retrieve : rd_log -fl | -ra <-p | -n <num of entries, default:40>>",
cmdsvr_rd_log},
{"mirror ", " Port mirroring: mirror <on/off> <src_phy_id> [tx_dst_phy_id
rx_dst_phy_id] ",
cmdsvr_port_mirroring},
/* Add additional commands here */
CMDSVR_ADDITIONAL_COMMANDS

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{0, 0, 0}
};

This table must be updated as new commands are added.

All words following the name of the command are forwarded to the registered function for that command. Each of
these functions is an argument interpretation function that receives the list of arguments for that command as per C
main(). (See cmdsvr_mem_rd_wr. c)
Figure 9-5. Example Argument Extraction Function

PMCFW_ERROR cmdsvr_mem_rd_N(CHAR ** args,

UINT8 num_args)
{
UINT32 data;
UINT32 * addr;
UINT32 num;
UINT32 idx;

PMCFW_ASSERT(args, PMCFW_ERR_INVALID_PARAMETERS);

/* extract & check args */

if ((2 != num_args)
|| (PMC_SUCCESS != uartio_strtoul(args[0], &data))
|| (PMC_SUCCESS != uartio_strtoul(args[1], &num))
|| (data & 0x3)
)
{
fputc('\n', stdout);
return PMCFW_ERR_INVALID_PARAMETERS;
}
addr = (UINT32*)data;
for (idx = 0; idx < num; idx++) {
data = addr[idx];
fputs(" 0x", stdout);
uartio_put_hex(data, sizeof(data));
}
fputc('\n', stdout);
return PMC_SUCCESS;
}

9.2.3 Implementation Options

Each argument extraction function has control of stdin and stdout until that function returns so large amounts of data
of specific C-types can be pulled in or pushed out with stdio read() and write() calls embedded within any argument
extraction function.
All argument extraction functions must return PMC_SUCCESS unless there is a problem with the supplied arguments
in which case these functions cannot return PMC_SUCCESS. If the arguments are OK but the command fails, these
argument extraction functions must print a command specific failure string and return PMC_SUCCESS.
For typical commands, command server is only another route for calling an existing firmware routine. In these cases,
it is good practice to name the argument extraction routine cmdsvr_foo() when the underlying routine is foo() and the
command name is also foo, or a shortened version of the function name. This convention allows documentation for
the underlying firmware routine to flow through to users of the command console.
For runtime speed and minimal code size, all of the argument extraction functions should use fputs(), puts(), fputc()
and putc() routines over printf() and sprintf() routines. uartio_strtoul() and uartio_puthex() are available for converting
between hexadecimal numbers and their string representations; uartio_putbool() is also available.

9.2.4 Limitations of Command Server

The cmdsvr debug console is a software mediated console. Interrupts wake up the embedded microprocessor as
characters arrive at a UART port. Depending on the processing load and data rate on the UART port, servicing these
interrupts can saturate the embedded processor, disrupting normal operation. For this reason, any host-side script
or GUI which sits on top of cmdsvr should avoid communicating with the embedded processor unless the system is
quiescent.

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SES pages are a more robust mechanism for retrieving information from the embedded processor. This is the
expected path for passing information between an EMA and the host. cmdsvr provides a simple backdoor for
querying the status of the embedded processor, but has been designed and verified as a debug tool only.

9.2.4.1 Instantiation and Development

The command server is unaware of the underlying transport of stdin and stdout over a UART. Hence, most
commands can be interactively debugged within a debugger, entering the commands within the console pane of
that debugger. Only on the hardware platform does the transport layer have to come into play. When the transport
layer is UART (instead of EJTAG in the debugger) the corresponding UART has to be initialized for use by command
server. In addition, the mapping of stdio through UART also has to be initialized. Two simple examples are provided
—cmdsvr_uart—that demonstrate how the ports and the stdio mapping is preconfigured within tx_application_define,
which also creates the command server thread. A command server thread is also instantiated within the provided
EMA example.
Figure 9-6. Example Command Server Instantiation

PUBLIC void tx_application_define(void *free_mem_ptr)

{
osf_sys_cfg_struct osfcfg;
cmdsvr_parms_struct *cmdsvr_parms_ptr;

/-------------------- Initialize OSF system ----------------------/

memset(&osfcfg, 0x0, sizeof(osf_sys_cfg_struct));
osfcfg. desired_tmr_period_ms = OSF_TMR_PERIOD_MS;
osfcfg. log_cfg = osf_log_cfg_event_log_only;

/* Get the default parameters for the modules */

cmdsvr_parms_ptr = cmdsvr_parms_get(&osfcfg);

/* Update from defaults */

/* Note: no changes required */

/* setup up the OSF */

osf_sys_init(free_mem_ptr, &osfcfg);

/* setup MBIC interrupt controller */

cicint_init();

/* Module Parameter Modifications ---------------------------------*/

/* Modify/override module parameters needed by the xxx_create()
* functions. Thread priorities are overridden here if required.
*/
cmdsvr_parms_ptr->config. thread_priority = 20;

/* Create the module resources */

cmdsvr_create(cmdsvr_parms_ptr);

/* Final initialization of the modules */

cmdsvr_init(cmdsvr_parms_ptr);

} /* tx_application_define() */

9.3 Database
A basic database is provided that can be used to store data that is required during run-time. The SES module would
be the main user of this database; however, any other service in the system can define database pages and access
this resource.

9.3.1 External Interface

The database supports the following functions:

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Table 9-3. Database Functions

Function Description

dbs_parms_get Generates a parameter structure and initializes it with default

values.

dbs_create Allocates database memory and initializes database structures.

dbs_init Initializes database memory.

dbs_page_lock Locks a database page for exclusive read/write access.

dbs_page_unlock Unlocks a previously locked database page.

dbs_entry_read Reads an entry from the database.

dbs_entry_write Writes an entry to the database.

dbs_timestamp_get Returns the timestamp for a database page.

dbs_timestamp_equal Checks if the timestamp on a database page has been updated.

dbs_page_length_get Returns the length of the database page.

dbs_page_data_valid_flag_set Writes the data valid flag on a database page.

dbs_page_data_valid_flag_check Checks the data valid flag on a database page.

dbs_page_valid_check Checks if a database exists.

9.3.1.1 dbs_parms_get
Generates a parameter structure and initializes it with default values.

Prototype dbs_parms_struct* dbs_parms_get(osf_sys_cfg_struct *osf_init);

Inputs osf_init A pointer to an osf_sys_cfg_struct.

Outputs None.

A pointer to a database parameter structure initialized with default

Returns dbs_parms_struct
values

9.3.1.2 dbs_create
Allocates the database memory and initializes database structures.

Prototype void dbs_create(dbs_parms_struct *dbs_parms_ptr);

A pointer to a dbs parameter structure obtained by calling

Inputs dbs_parms_ptr
dbs_parms_create.

Outputs None.

Returns None.

9.3.1.3 dbs_init
Initializes the database using the parameters provided.

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Prototype void dbs_init(dbs_parms_struct *dbs_parms_ptr);

A pointer to a dbs parameter structure obtained by calling

Inputs dbs_parms_ptr
dbs_parms_create.

Outputs None.

Returns None.

This function is currently just a placeholder for future expansion.

9.3.1.4 dbs_page_lock
Locks a database page for exclusive read/write access.

PMCFW_ERROR dbs_page_lock(UINT16 dbs_page,

Prototype
UINT32 wait_option);

Inputs dbs_page The database page to lock.

The time to wait for obtaining the database lock. Refer to

wait_option
osf_mutex_get for all valid wait options.

Outputs None.

Returns PMC_SUCCESS The database lock could be acquired in the time limit set.

OSF_ERR_TIMEOUT The database lock could not be acquired in the time limit set.

The dbs_page_lock function needs to be called before any database read or write access should be performed on
the database to ensure the data integrity.
Several wait options are available for obtaining the lock. Refer to osf_mutex_lock for a list of possible values. Setting
the wait option to OSF_WAIT_FOREVER will not return until the page lock could be acquired.

9.3.1.5 dbs_page_unlock
Unlocks a database page to release exclusive access rights.

Prototype void dbs_page_unlock(UINT16 dbs_page);

Inputs dbs_page The database page to unlock.

Outputs None.

Returns None.

The dbs_page_lock function needs to be called after the database read or write access is completed. If between
the last call of the dbs_page_lock function and the call of the dbs_page_unlock function, at least one write
access took place, the timestamp on the database page is being updated before the page gets unlocked.

9.3.1.6 dbs_entry_read
Reads an entry in a database page.

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void dbs_entry_read(UINT16 dbs_page,

Prototype UINT16 offset,
UINT16 length, UINT8* buffer_ptr);

Inputs dbs_page The database page to access.

offset The byte offset into the database page.

length The number of bytes to read.

Outputs buffer_ptr A pointer to a buffer to store the read data.

Returns None.

Before calling this function, the dbs_page_lock function should be called to ensure an exclusive database access.

9.3.1.7 dbs_entry_write
Writes an entry in a database page.

void dbs_entry_write(UINT16 dbs_page,

UINT16 offset,
Prototype
UINT16 length,
UINT8* const buffer_ptr);

Inputs dbs_page The database page to access.

offset The byte offset into the database page.

length The number of bytes to write.

Outputs buffer_ptr A pointer to a buffer that keeps the write data.

This function returns the allocated size of the database page in bytes.

9.3.1.11 dbs_page_data_valid_flag_set
Writes the data valid flag on a database page.

void dbs_page_data_valid_flag_set(UINT16 dbs_page,

Prototype
BOOL value);

Inputs dbs_page The database page to access.

Outputs value The value to write to the data valid flag on the database page.

Returns None.

The data valid flag on the database page is provided to indicate whether data on a database page has been properly
initialized or not. It is up to you to use this flag and to properly update it.

9.3.1.12 dbs_page_data_valid_flag_check
Checks the data valid flag on a database page.

void dbs_page_data_valid_flag_check(UINT16 dbs_page,

Prototype
BOOL *value_ptr );

Inputs dbs_page The database page to access.

Outputs value_ptr A pointer to a buffer to keep the value of the data valid flag.

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Returns None.

9.3.1.13 dbs_page_valid_check
Checks for a valid database page code.

Prototype BOOL dbs_page_valid_check(UINT16 dbs_page);

Inputs dbs_page The database page to access.

Outputs None.

Returns TRUE, FALSE.

9.4 LED Control through SGPIO

The SXP 12G device implements four SGPIO initiators. The target (usually implemented by a CPLD or FPGA)
typically converts the output serial signal (SDataOut) into multiple parallel LED signals and provides the input signal
(SDataIn) from multiple general inputs. Figure 9-7 shows a typical SGPIO system consisting of one initiator and one
target.
Figure 9-7. SGPIO System Overview

An SGPIO initiator generates the SClock, SLoad, and SDataOut. The signal SClock is the SGPIO system clock
signal. It runs at 100 kHz. The initiator uses the rising edge of SClock to transmit changes in SLoad and SDataOut.
The target uses the rising edge of SClock to transmit changes in SDataIn and the falling edge of SClock to latch
SLoad and SDataOut. The initiator uses the falling edge of SClock to latch SDataIn.
The signal SLoad acts as a control signal, indicating the beginning and end of a bit stream. The clock period during
which SLoad is asserted is the last clock period of a bit stream.
SDataOut carries output bits associated with disk drives. It is intended to control LEDs (for example, activity, locate,
and error LEDs). There are three bits per drive on SDataOut, known as activity, locate and error, as shown in Figure
9-8. You cannot change the order of these three bits within one drive.
The SGPIO target transmits SDataIn. The SDataIn signal carries input bits associated with disk drives. It is intended
to report information such as drive presence detection. There are three bits per drive on SDataIn. Unlike SDataOut,
the meaning of these three bits is undefined in the standard and they are vendor specific.
The following figure shows an example of the four signals on the SGPIO bus. This example shows the information
being transmitted for four drives’ on SDataOut (from initiator to target) and SDataIn (from target to initiator). The

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mapping between the logical drives and SGPIO time slots is determined by configurable settings in the initialization
string.
Figure 9-8. SGPIO Bus Signal Timing

SClock ...
SLoad L0 L1 L2 L3 L0 L1 L2 L3
...
SDataO ut X 0.0 0.1 0.2 1.0 1.1 1.2 2.0 2.1 2.2 3.0 3.1 3.2 0.0 0.1 0.2 ...
SG PIO SG PIO SG PIO SG PIO SG PIO
Drive 0 Drive 1 Drive 2 Drive 3 Drive 0

SDataIn X 0.0 0.1 0.2 1.0 1.1 1.2 2.0 2.1 2.2 3.0 3.1 3.2 0.0 0.1 0.2 ...
SG PIO SG PIO SG PIO SG PIO SG PIO
Drive 0 Drive 1 Drive 2 Drive 3 Drive 0

The PM73206 firmware supports the following most relevant SGPIO features:
• Periodic blinking patterns and activity blinking patterns. By default, the state of the LEDs is updated every 1/64
s.
• SMP functions
• Both normal drive-by-drive basis access and general-purpose bit-by-bit access
• Mapping between logical drives and SGPIO drives, which are then mapped to SGPIO buses and time slots.

9.4.1 Architecture
The firmware that controls the LED blinking patterns over the SGPIO interface consists of two components: LED and
SGPIO.
• The LED component implements the periodic and activity blinking patterns and specifies the mapping of each
LED to a given blinking pattern.
• The SGPIO module provides interfaces to the SGPIO hardware.
Figure 9-9. Structure of the SGPIO Component

SGPIO Com ponent

SG PIO
Array of
Hardware
Activity
Control
Blinking
O bjects

Array of Array of
Periodic LED
Blinking Mask
O bjects O bjects

The SGPIO component consists of the following sub-components, as shown in Figure 9-9:
• The SGPIO Hardware Control block configures the SGPIO hardware, both at startup and while the system is
running. This object also provides functions for register read/write access.
• An array of periodic blinking objects handles the periodic blinking patterns. There is one object per blinking
pattern. There are three periodic blinking objects:
– pblink object 0 is used for blink generator A,
– pblink object 1 is used for blink generator B and

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– pblink object 2 is used for permanent off. Note that to provide the “inverted” blinking pattern (that is, ON
becomes OFF and OFF becomes ON), we don’t need to create a new periodic blinking object. Instead we
use the “inverted” mask provided by the LED mask object to generate the inverted blinking pattern.
• An array of activity blinking objects handles activity blinking. There is one object per PHY.
• An array of LED mask objects is used to map each SGPIO timeslot to a blinking object, either periodic or activity.
There is one LED mask object for every periodic blinking object and for every activity blinking object.

9.4.2 SGPIO Interfaces

The SGPIO firmware component provides two interfaces:
• A low overhead functional interface for register read access.
• A messaging interface for register write access.
This approach serializes writing to SGPIO registers, allowing multiple threads to modify SGPIO settings concurrently.
Note that, depending on system utilization, it is possible for read functions to complete before a previous write has
taken effect. This is shown in the following event sequences:
1. A thread sends a message to the SGPIO thread to perform a write on an SGPIO hardware register.
2. The thread performs a read on the same SGPIO hardware register. This is done through a functional call.
Depending on the state of the system, the read may return the old value.

9.4.3 Periodic Blinking

Periodic blinking is implemented as a state machine that has one 1-bit output. This 1-bit output is the on/off blinking
pattern of one LED. In SFF-8485 revision 0.7[9], there are three periodic blinking patterns, excluding the inverted
blinking pattern, and therefore we need three periodic blinking objects.
Figure 9-10 shows the basic elements that make up one period of the blinking pattern. There are three parameters
that can be configured: offset, duty and period. The units of these elements are in terms of the number of ticks, where
one tick is set to 1/64 sec. During both the offset and remaining periods, the output bit is 0 (that is, off). During the
duty period, the output bit is 1 (that is, on). Both offset and duty (or either one of them) can be zero; however, period
cannot be zero.
Figure 9-10. Basic Elements in One Period

The following examples show some valid combinations of settings:

Example 1: To have the LED permanently turned on, use the following settings:
offset = 0
duty = period = any unsigned non-zero integer

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Example 2: To have the LED permanently turned off, use the following settings:
offset = period = any unsigned non-zero integer
duty = 0
Example 3: To have a 50% duty cycle, on for the first half, period = 3/8 sec, use the following settings:
offset = 0
duty = 0.5 * period
period = (3 / 8) * 64 = 24
The state machine implements the periodic blinking patterns as shown in Figure 9-11.
Figure 9-11. Periodic Blinking Pattern State-Machine

For HP periodic blinking, this state

Start State (Initial State) m achine is assum ed to be run every
1/64 sec.
Entry Actions:
None.

Body Actions:
None.
offset == 0 offset == 0
Exit Actions: AND
AND
None. duty == 0
duty != 0
AND
rem aining expires rem aining != 0
AND
offset != 0 offset == 0
AND
duty != 0

W ait O ffset State W ait Duty State W ait Rem aining State

Entry Actions: offset expires Entry Actions: duty expires Entry Actions:
+ Reset offset AND + Reset duty AND + Reset rem aining
counter. duty != 0 counter. rem aining != 0 counter.
rem aining
Body Actions: Body Actions: Body Actions: does not
+ LED = off. offset does + LED = on. duty does + LED = off. expire
+ Increm ent offset not expire + Increm ent duty not expire + Increm ent
counter by 1. counter by 1. rem aining
counter by 1.
Exit Actions: Exit Actions:
None. None. Exit Actions:
duty expires None.
AND
rem aining == 0 duty expires
offset expires AND AND
AND offset != 0 rem aining == 0
rem aining expires
duty == 0 AND
AND
AND offset == 0
offset expires offset == 0
rem aining == 0
AND AND
duty == 0 duty == 0
AND
rem aining != 0

rem aining expires

AND
offset != 0

9.4.4 Activity Blinking

The first bit of each group of three SDataOut bits associated with a drive is reserved for the activity LED. As its name
indicates, this LED is toggled when activity is detected on a particular drive. The following figure shows the state
machine that implements activity blinking.

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Figure 9-12. Activity Blinking Pattern State-Machine

W ait For Activity State
Start State Activity
(Initial State) == 0 Entry Actions:
Activity
None.
Entry Actions: == 0
None. Activity
Body Actions:
== 1
+ LED = off.
Body Actions:
None. FO RCE ACTIVITY O FF
Exit Actions: counter expires
None. AND
Exit Actions:
None. Local Activity == 0
Activity STRETCH O N
AND
== 1 counter expires
Activity == 0
AND
Activity == 0
Stretch O n State
AND
Entry Actions: STRETCH O FF Force Activity O ff State
+ Reset MAXIMUM
== 0
ACTIVITY O N
counter. Entry Actions:
MAXIMUM
+ Reset STRETCH_O N + Reset FO RCE ACTIVITY
counter. ACTIVITY O N
counter expires O FF counter.
Body Actions: AND + Set local activity = 0.
+ LED = on. MAXIMUM
+ If Activity == 1, reset ACTIVITY O N != 0
AND Body Actions:
STRETCH O N
counter. FO RCE ACTIVITY + LED = off.
O FF != 0
+ Increment STRETCH + Increm ent FO RCE
otherwise O N counter. AND otherwise
STRETCH O N ACTIVITY O FF counter.
+ Increment MAXIMUM
ACTIVITY O N counter does not + If activity == 1, set local
expire
counter. activity = 1.
Exit Actions:
None. Exit Actions:
None.

FO RCE ACTIVITY O FF
STRETCH O N counter expires counter expires
AND AND
Activity == 0 (Local Activity == 1
AND OR
STRETCH O FF != 0 Activity == 1)

Stretch O ff State
STRETCH O FF
Entry Actions: counter expires
STRETCH O FF + Reset STRECH O FF counter. AND
counter expires + Set local activity = 0. (Local Activity == 1
AND
Local Activity == 0 OR
AND Body Actions: Activity == 1)
Activity == 0 + LED = off.
+ Increm ent STRETCH O FF
counter.
+ If activity == 1, set local otherwise
activity = 1.

Exit Actions:
None.

9.4.5 Synchronizing LED Blinking Across Multiple Expanders

The following figure shows a system configuration with multiple expanders. Note that this is not the same as
cascading SGPIOs, since each expander has its own SGPIO target, with a bank of LEDs attached, so the SGPIO
buses are not shared. The challenge in this configuration is to synchronize the LED blinking across expanders, since
allowing the LEDs to blink asynchronously can cause confusion.
Synchronization is achieved by connecting the TPOUT pin of the master expander to the TPIN pin of each slave
expander. Note that TPOUT of the master expander must also be connected to its own TPIN, as these two timers can
be started at different times by the firmware. The TPOUT of the master SXP 12G generates a frame pulse with period
of 10 s and a 50% duty cycle.

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Figure 9-13. Cascaded Expanders

9.4.5.1 Cascading SGPIO Across Multiple Expanders

As shown in the following figure, a cascaded SGPIO system has multiple expanders accessing one SGPIO target
through a shared SGPIO bus (SClock, SLoad, SDataOut and SDataIn). The master expander generates the SClock
and SLoad. In this example, the master expander transmits its data first and then goes to high impedance, allowing
the slave expander to transmit its bit sequence.
Figure 9-14. Cascaded SGPIO Configuration

SGPIO
Target
SXP (contains
(M aster) LEDs)

SClock SClock

SLoad SLoad

SDataOut SDataOut

SDataIn SDataIn

SXP
(Slave)

SClock

SLoad

SDataOut

SDataIn

See Table 8-19 for a description of the initialization string settings necessary for a cascaded SGPIO configuration.

9.5 SXP Diagnostics

This section describes the PM73206 firmware support for the hardware diagnostics capabilities of the SXP 12G
device.

9.5.1 Diagnostics Capabilities

9.5.1.1 PRBS Generation

Pseudo Random Bit Sequence (PRBS) patterns can be generated and inserted into the transmit stream for validating
the electrical performance of the high-speed interface. A PRBS pattern can be inverted before transmission.

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Erroneous PRBS patterns can be sent on any PHY. A receiver can be programmed to accumulate errors and
compare the number of errors against a threshold, generating a report once the threshold is reached.
Note that PRBS patterns are unframed.

9.5.1.2 CJTPAT Generation

Compliant Jitter Test Patterns (CJTPAT) are jitter test patterns sent as payload in SSP DATA frames. A jitter test
pattern is designed to stress the receiver.

9.5.1.3 Programmable Test Pattern Generation

The programmed test patterns which are called as user patterns as well, are transmitted as unframed data.

9.5.1.4 Error Insertion

Code Violation and Disparity errors can be inserted on a transmitted stream, e.g. the test pattern stream of CJTPAT
Pattern, User Pattern or PRBS, for diagnostics purposes. The receiver maintains counters for each type of error.
Monitor these counters during the test.

9.5.1.5 Loopbacks
Three loopback modes are supported in the SXP 12G device:
• Line Side Analog Loop back – Data received is directly looped back to the transmitter
• Line Side Digital Loopback – Data received is looped back in the digital core logic to the transmitter.
• System Side Analog Loopback – Data transmitted is looped back to the receiver.
– When a loopback is configured, errors or patterns can be inserted and results can be monitored.
– In addition, when a port is configured with a connection to an SPS device the following loopbacks are also
available:
• SPS Line Side Metallic Loopback: Data received by the SPS is directly looped back to the transmitter.
• SPS System Side Diagnostics Loopback: Data received by the SPS is looped back for the internal traffic.

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Figure 9-15. SXP 12G Normal Datapath and Diagnostic Datapath

9.5.1.6 Disk Drive Access Test

This feature performs disk access test by issuing INQUIRY requests to SAS disks and IDENTIFY DEVICE requests
to SATA devices.

9.5.1.7 Broadcast Suppression

This feature suppresses the generation of broadcast primitives on a per-PHY basis during diagnostic testing.

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When this feature is enabled on a particular PHY, no broadcasts are generated from that PHY (propagation of
broadcast is unaffected). Multiple PHYs can have broadcasts suppressed simultaneously, but the control mechanism
only allows one PHY to be disabled/enabled at the same time (that is, multiple commands would have to be issued to
enable the feature on multiple PHYs.)

9.5.1.8 Monitoring
The effects of diagnostics operations can be monitored through the counters.
Table 9-4. Diagnostic Counters

Counter Description

PRBS Error Count Number of PRBS bit-errors received in the erroneous PRBS patterns.

CJTPAT Error Count Number of received erroneous CJTPAT patterns.

Usr pattern Error Count Number of received erroneous user-defined patterns.

Disparity Error Count Number of Running Disparity Errors received.

Code Violation Error Count Number of Code Violation Errors received.

CRC Error Count Number of CRC errors happening (due to CJTPAT and others).

In-connection CRC Error Count Number of In-connection CRC errors.

Lost DW Sync Count Lost DW Sync count.

Invalid DW Count Invalid DW count.

Code Violation Error Interval Threshold This threshold is compared to the hardware code violation error count and
a report is generated once it is reached.
When the Code Violation Error Count is read, the firmware will clear the
hardware count that has been accumulated and accumulate the count to a
firmware variable for reporting the Code Violation Error Count.

Disparity Error Interval Threshold This threshold is compared to the hardware disparity error count and a
report is generated once it is reached.
When the Disparity Error Count is read, the firmware will clear the
hardware count that has been accumulated and accumulate the count to a
firmware variable for reporting the Disparity Error Count.

Many of these counts can also be retrieved for the SPS as described later in this section.
Note: To count CJTPAT-generated CRC errors, you can use one of the Microchip-specific SMP Read 0x7A and SMP
Write 0xFA commands. CJTPAT is a pre-defined 8B/10B payload, which means an error can be detected in the
received pattern. Use the following registers to set up the performance counters, including one for test pattern errors.
Table 9-5. Registers for Configuring Performance Counter for CJTPAT Errors

Offset Register

0xA80040B8 +0x40000*A(A=0:33) XCBI:SLICE_TOP(A):SXL(B) - Performance Counter 1 Control

+0x2000*B(A=0:1)

0xA80040BC +0x40000*A(A=0:33) XCBI:SLICE_TOP(A):SXL(B) - Performance Counter 1 Threshold

+0x2000*B(A=0:1)

0xA80040C0 +0x40000*A(A=0:33) XCBI:SLICE_TOP(A):SXL(B) - Performance Counter 1 Count

+0x2000*B(A=0:1)

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9.5.1.9 Eye Capture and BER

To support assessment of signal integrity during system development or in field debugging on the SAS 12G PHY, the
SXP 12G supports eye capture and BER measurement on the SXP 12G PHY.
See section 14.2.3 Supported SES Pages and Limitations for the VHIST CAPTURE SES page.

9.5.1.10 Port Mirroring

Port mirroring is a useful debug feature during the design cycle. Receive and/or transmit data of a PHY can be
mirrored to the transmitters of unused PHYs. All frames, primitives and OOBs are supported however, deletable
primitives may be deleted or inserted. Both optical and electrical modes are supported.
Port mirroring supports four fixed-source PHYs (both receive and transmit) to be mirrored to eight fixed-destination
PHYs. Refer to [29] for physical PHY IDs that support mirroring
Users can enable/disable port mirroring through the command server or PORT MIRRORING SES page. Refer to
section 14.2.3 Supported SES Pages and Limitations for this SES page.

9.5.1.11 SCRAMBLED 0 Pattern

The SXP 12G supports the SCRAMBLED_0 test pattern generator. A 58 Dword (2320 bit) pattern of scrambled 0's
will be transmitted. The scrambler is re-initialized at the beginning of each pattern and the first Dword transmitted in
the pattern is C2D2768Dh.

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9.5.2 Architecture
The diagnostics component programs and accesses Top Level, MABC Port, SSPL and SXL registers to perform the
selected diagnostics operations. It also creates diagnostics reports for the set of counters being monitored.
The following diagram gives an overview of the diagnostics component and its current use scenario.
Figure 9-16. Diagnostics Architecture

9.5.3 Interfaces
The diagnostics component has two main interfaces, listed as follows.
• An SES interface
• An API interface

9.5.3.1 SES Interface

The fundamental processing unit in the diagnostics component is the diagnostics command. A diagnostics command
describes a specific diagnostics operation to be performed by the firmware. Section 9.5.4 Diagnostics Commands
provides a detailed description of the diagnostics commands and their format.
This section explains how multiple diagnostics commands can be grouped in an SES page and sent to the
diagnostics component for processing. SES pages for retrieving diagnostics reports are also described. The following
table lists the format of an SES page that contains multiple diagnostics commands.

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Table 9-6. SES Page Format—Multiple Diagnostics Commands

Bytes/Bits 7 6 5 4 3 2 1 0

0x00

0x01
SES Page Header (5 bytes)
0x02
SCSI Diagnostics Page Code, Length, and so on.
0x03

0x04

0x05

0x06

0x07

0x08

0x09 Diagnostics Command (10 bytes)

0x0A Specifies diagnostics operation detail, e.g. operation type or user data for an operation

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13
Diagnostics Command
0x14

0x15

0x16

0x17

0x18

……

0x80

Section 9.5.5 Diagnostics SES Pages describes the contents of the SES page in detail.
A number of diagnostics commands are sequentially placed in the SES page. The maximum size of the SES page is
128 bytes. This restricts the number of diagnostics commands per SES page to a maximum of 12. The diagnostics
component returns errors for SES pages with non-compliant sizes.

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An SES page that requests a series of diagnostics reports has the following format:
Table 9-7. SES Page Format—Diagnostics Reports

Bytes/Bits 7 6 5 4 3 2 1 0

0x00

0x01

0x02 SES Page Header (6 bytes)

0x03 SCSI Diagnostics Page Code, Length, and so on.

0x04

0x05

0x06

0x07

0x08
Diagnostics Report (7 bytes)
0x09
Details of a report e.g., the report type, error occurred if any, report data
0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10 Diagnostics Report

0x11

0x12

0x13

……

0x80

Section 9.5.5 Diagnostics SES Pages describes the contents of this SES page in detail.
As in the case of the diagnostics commands SES page, there is a size restriction of 128 bytes on the reports SES
page. This restricts the number of diagnostics reports per SES page to a maximum of 17.

9.5.3.2 API Interface

This interface allows a firmware module to perform a single diagnostic operation and retrieve a single diagnostic
report. When using this interface, work directly with diagnostics data structures. The Diagnostics module provides the
following public functions:

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Table 9-8. Diagnostics Module Functions

Function Description

diag_usr_cmd_process Send a diagnostics command to perform the diagnostics operation

specified by the arguments to this function.

diag_report_cmd_process Specify a report and retrieve the desired report as output.

9.5.3.3 diag_usr_cmd_process

Prototype diag_error_enum diag_usr_cmd_process (const diag_usr_cmd_struct * usr_cmd_ptr)

Inputs usr_cmd_ptr Pointer to user command

Outputs None

Return Success = DIAG_SUCCESS

Failure = DIAG_ERR_INVALID_USR_CMD_TYPE
DIAG_ERR_INVALID_USR_CMD_DESC

9.5.3.4 diag_report_cmd_process

Prototype diag_error_enum diag_report_cmd_process ( const diag_usr_cmd_struct * usr_cmd_ptr,

diag_report_struct * report_ptr )

Inputs usr_cmd_ptr Pointer to user command specifying report

Outputs report_ptr Pointer to generated report

Return Success = DIAG_SUCCESS

Failure = DIAG_ERR_INVALID_USR_CMD_TYPE
DIAG_ERR_INVALID_USR_CMD_DESC

9.5.4 Diagnostics Commands

A diagnostics command is the unit of interaction with the diagnostics component for both SES and API interfaces.
It provides a way to specify certain diagnostics action in a structured way. The following set of actions provides
complete control over the diagnostics capabilities of the device.
• Diagnostics setup control - Performs some diagnostics preparation tasks, for example, disabling the ECMR
entry to prevent unexpected frames from passing to the PHY under the test before starting pattern generation,
performing some diagnostic cleanup tasks like enabling ECMR entry and resetting the PHY under test as the
final step of the diagnostic procedure. See 9.5.5 Diagnostics SES Pages for detail.
• Start generated pattern insertion or system-level diagnostics – Generates and inserts patterns continuously.
Available patterns are PRBS, Inverted PRBS, CJTPAT, and user-defined diagnostics patterns.
• Stop pattern insertion or system-level diagnostics – Stops insertion of PRBS, Inverted PRBS, CJTPAT, and
user-defined diagnostics patterns.
• Error Insertion – Inserts one error once. The errors can be an erroneous PRBS pattern, erroneous CJTPAT,
erroneous user-defined diagnostics patterns, Code Violation Errors, or Disparity Errors.
• Enabling Receive – For PRBS, CJTPAT and user-defined diagnostic pattern error accumulation, the receiver
must be programmed.
• Specifying Thresholds – Values of Code Violation Error Interval Threshold, and Disparity Error Interval
Threshold can be specified. It also sets the monitoring period that hardware uses for comparisons. This
period is known as the PMON Period. Internal hardware error counters are reset after each instance of this

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period. Configuring and de-configuring loop-backs – Configures and de-configures one of System Side Analog
Loop-back, Line Side Analog Loop-back, Line Side Digital Loop-back, SPS Line Side Metallic Loop-back, and
SPS System Side Diagnostics Loop-back.
• Resetting Counters – Various error counters and threshold indicators can be reset to restart counting and
comparing.
• Getting Reports – Various error counters and threshold indicators are reported.
A user command can specify any of the previous actions. In addition to the action, the command must specify the
Logical PHY ID of the PHY on which the action is to be performed and user data for the action, if applicable.
An action is specified by a command, which is defined as a combination of a command type and a command
descriptor. A diagnostics command is formed by a bitwise OR of a command type and a command descriptor.

9.5.4.1 Command Type

Command type describes the type of operation. It can contain one of the following values:
Table 9-9. Diagnostics Command Types

Command Type Value Description

DIAG_OPRN_PERFORM 0x00 Perform an operation. For example, setup control,
continuously insert generated test pattern, configure a loop
back, or insert an error.
DIAG_OPRN_STOP 0x20 Stop/de-configure. For example, discontinue inserting a
generated test pattern or de-configure a loop back.
THRESHOLD_SPECIFY 0x40 Specify a threshold for an error count. For example, Disparity
Error Count, or Code Violation Error Count.
RECEIVE_ENABLE 0x60 Enable receiving of a certain kind of pattern on a PHY so that
the received patterns are accounted for. Required for PRBS,
CJTPAT, and User patterns.
DIAG_REPORT_GET 0x80 Get a report. For example, PRBS error count or Lost DW Sync
Count.
ERR_CNT_RESET 0xA0 Reset an error counter.
DIAG_REPORT_GET_SPS 0xC0 Get a report. For example, PRBS error count or Lost DW Sync
Count for SPS.
ERR_CNT_RESET_SPS 0xE0 Reset an error counter for SPS.

9.5.4.2 Command Descriptor

The command descriptor further qualifies the command. For example, for the DIAG_OPRN_STOP command type,
the descriptor specifies which diagnostics operation to stop (such as PRBS generation, CJTPAT, and so on). The
following table lists the possible values for this field.
Table 9-10. Diagnostics Command Descriptors for Command Types DIAG_OPRN_PERFORM,
DIAG_OPRN_STOP, THRESHOLD_SPECIFY and RECEIVE_ENABLE

Command Descriptor Value Description

PRBS 0x00 PRBS patterns

CJTPAT 0x01 CJTPATs

USR_PATTERNS 0x02 User-defined Diagnostics patterns

PRBS_ERR_INSERT 0x08 Erroneous PRBS induced using PRBS error mask

PRBS_INVERT 0x09 Inverted PRBS patterns

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...........continued
Command Descriptor Value Description

CJTPAT_ERR_INSERT 0x0A Erroneous CJTPATs

CODE_VIOL_INSERT 0x0B Code Violation Errors

DISP_ERR_INSERT 0x0C Disparity Errors

LINE_SIDE_ANA_LPBK 0x10 Line Side Analog Loop back

LINE_SIDE_DIG_LPBK 0x11 Line Side Digital Loop back

SYS_SIDE_ANA_LPBK 0x12 System Side Analog Loop back

HDD_DIAG 0x14 SPS and HDD Access test (monitored by SXP, data driven
from HBA)

SXP_SPS_MONITOR 0x15 Monitor SPS from SXP so as to configure it when it goes down

SPS_LINE_SIDE_LPBK(Metallic 0x16 SPS Line Side Loop back (Metallic Loop back)
LPBK)

SPS_SYS_SIDE_LPBK(Diagnostic 0x17 SPS System Side Loop back (Diagnostic Loop back)
LPBK)

SPS_CJTPAT_ERR_INSERT 0x18 SPS CJTPAT Error Insert

SPS_CJTPAT 0x19 Enable/Set SPS CJTPAT pattern

SPS_RESET 0x1A Reset SPS device

BPP_SUPPRESS 0x1C Suppress broadcast

DIAG_SETUP_CTRL 0x1D Diagnostic Setup Control for diagnostic preparation and

cleanup. (used only with DIAG_OPEN_PFEROM)

Table 9-11. Diagnostics Command Descriptors for Command Types DIAG_REPORT_GET and
ERR_CNT_RESET

Command Descriptor Value Description

PRBS_ERR_CNT 0x00 PRBS error count

CODE_VIOL_ERR_CNT 0x01 Code Violation error count

DISP_ERR_CNT 0x02 Disparity error count

CRC_ERR_CNT 0x03 CRC error count

IN_CONN_CRC_ERR_CNT 0x04 In-Connection CRC error count

LOST_DWD_SYNC_CNT 0x05 Lost Dword Sync Count

INVALID_DWD_CNT 0x06 Invalid Dword count

CODE_VIOL_ERR_CNT_THHD 0x09 Code Violation error count and threshold comparison

DISP_ERR_CNT_THHD 0x0A Disparity error count and threshold comparison

SPS_CJTPAT_ERR_CNT 0x0B SPS CJTPAT Error count

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...........continued
Command Descriptor Value Description

CODE_VIOL_ERR_THHD 0x19 Code Violation error interval threshold

DISP_ERR_THHD 0x1A Disparity error interval threshold

HDD_DIAG_REP 0x1B HDD Access test report

9.5.4.3 Valid Type-Descriptor Combinations

A cursory examination of and Table 9-10 reveals that not all combinations of Command Type and Descriptor
make sense. Table 9-11 describes valid combinations of command types and command descriptors, along with the
complete command they specify. User arguments required for certain commands are described in Table 14-65.
Table 9-12. Valid User Command Type-Descriptor Combinations

Command Type Command Descriptor Resultant User Command

PRBS Start inserting PRBS patterns

CJTPAT Start inserting CJTPAT patterns

USR_PATTERNS Start inserting User-defined patterns

PRBS_ERR_INSERT Insert Erroneous PRBS pattern once

PRBS_INVERT Start inserting inverted PRBS patterns

CJTPAT_ERR_INSERT Insert Erroneous CJTPAT pattern once

CODE_VIOL_INSERT Insert Code Violation once

DISP_ERR_INSERT Insert Disparity Error once

LINE_SIDE_ANA_LPBK Configure Line Side Analog Loop back

LINE_SIDE_DIG_LPBK Configure Line Side Digital Loop back

DIAG_OPRN_PERFORM SYS_SIDE_ANA_LPBK Configure System Side Analog Loop back

SPS_LIN_SIDE_MET_LPBK Configure Line Side Metallic Loop back on SPS.

Configure System Side Diagnostic Loop back on

SPS_SYS_DIAG_LPBK
SPS

Start monitoring SPS from SXP to configure it as

SXP_SPS_MONITOR
needed

SPS_CJTPAT Enable/Set CJTPAT pattern on the SPS port

SPS_CJT_PAT_ERR_INSERT Insert CJTPAT errors on SPS port

HDD_DIAG Start HDD access test

BPP_SUPPRESS Suppress broadcast

Diagnostic Setup Control for diagnostic

DIAG_SETUP_CTRL preparation and cleanup. (Used only with
DIAG_OPEN_PFEROM)

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...........continued
Command Type Command Descriptor Resultant User Command

PRBS Stop inserting PRBS patterns

CJTPAT Stop inserting CJTPAT patterns

USR_PATTERNS Stop inserting User-defined patterns

LINE_SIDE_ANA_LPBK De-configure Line Side Analog Loop back

LINE_SIDE_DIG_LPBK De-configure Line Side Digital Loop back

SYS_SIDE_ANA_LPBK De-configure System Side Analog Loop back

DIAG_OPRN_STOP
SPS_LIN_SIDE_MET_LPBK De-configure Line Side Metallic Loop back on
SPS.

De-configure System Side Diagnostic Loop back

SPS_SYS_DIAG_LPBK
on SPS

SXP_SPS_MONITOR Stop monitoring SPS from SXP

SPS_CJTPAT Disable/Unset CJTPAT pattern on the SPS port

BPP_SUPPRESS Suppress broadcast

PRBS Enable receiving and processing PRBS

RECEIVE_ENABLE CJTPAT Enable receiving and processing CJTPATs

USR_PATTERN Enable receiving and processing User patterns

CODE_VIOL_INSERT Specify Code Violation Error Interval Threshold

THRESHOLD_SPECIFY
DISP_ERR_INSERT Specify Disparity Error Interval Threshold

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...........continued
Command Type Command Descriptor Resultant User Command

PRBS_ERR_CNT Get PRBS Error Count report

CODE_VIOL_ERR_CNT Get Code Violation Error Count report

DISP_ERR_CNT Get Disparity Error Count report

CRC_ERR_CNT Get CRC Error Count report

IN_CONN_CRC_ERR_CNT Get In-Connection CRC Error Count report

LOST_DWD_SYNC_CNT Get Lost DWORD Sync Count report

INVALID_DWD_CNT Get Invalid DWORD Count report

DIAG_REPORT_GET Get Code Violation Error Interval Threshold Info

CODE_VIOL_ERR_THHD
DIAG_REPORT_GET_SPS report

DISP_ERR_THHD Get Disparity Error Interval Threshold Info report

Get Code Violation Error Count and Code

CODE_VIOL_ERR_CNT_THHD
Violation Error Interval Threshold Info report

Get Disparity Error Count and Disparity Error

DISP_ERR_CNT_THHD
Interval Threshold Info report

SPS_CJTPAT_ERR_CNT Get SPS CJTPAT error counts

HDD_DIAG_REP Get report of HDD Access test

ALL Get counts and threshold info reports

PRBS_ERR_CNT

CODE_VIOL_ERR_CNT
Any one of this command will reset all SSPL
DISP_ERR_CNT and SXL error counts including PRBS Error
Count, Code Violation Error Count, Disparity Error
CRC_ERR_CNT
Count, CRC Error Count, In-Connection CRC
IN_CONN_CRC_ERR_CNT Error Count, Lost Dword Sync Count, Invalid
Dword Count.
LOST_DWD_SYNC_CNT

ERR_CNT_RESET INVALID_DWD_CNT

ERR_CNT_RESET_SPS CODE_VIOL_ERR_THHD Reset Code Violation Error Interval Threshold Info

DISP_ERR_THHD Reset Disparity Error Interval Threshold Info

Reset Code Violation Error Count and Code

CODE_VIOL_ERR_CNT_THHD
Violation Error Interval Threshold Info

Reset Disparity Error Count and Disparity Error

DISP_ERR_CNT_THHD
Interval Threshold Info

SPS_CJTPAT_ERR_CNT Reset SPS CJTPAT error counts

ALL Reset counts and threshold info register bits

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Note: For readability, the names of the command types and command descriptors are shortened by removing
the common prefix. Each command type above must have the prefix DIAG_BITMSK_USR_CMD_TYP_ and each
command descriptor above must have the prefix DIAG_BITMSK_USR_CMD_DESC_ in the code.

9.5.4.4 Diagnostic Commands with User Arguments

The following table lists the commands that need user arguments and detail on their user arguments.
Table 9-13. Diagnostics Commands with User Arguments

Size in
User Command User Argument Description
bits

The four bytes that must be provided as

Start or Stop Diagnostic Setup Control parameters to call the command.
32
Setup Control words See the parameter definition shown in the Table
9-16.

Two 40-bit user patterns that must be provided to

Start inserting or receive call the command twice with DWord_id 0 and 1
User Pattern 2x40
user-defined patterns respectively. See the parameter definition for each 40-
bit pattern shown in Table 9-19.

A 40-bit mask to change the generated PRBS/user

Insert Erroneous PRBS or pattern to induce errors before it is sent. See the
Error Mask 40
User pattern once parameter definition of 40-bit mask shown in Table
9-20 .

Specifies a code violation pattern that is inserted. It

Code Violation
Insert Code Violation once 10 can have any 10-bit value, for example, 0x032C Table
Pattern
9-21.

The Code Violation Interval Threshold parameter

Specify Code Violation
Threshold 8 specifies the number of allowable code violation errors
Error Interval Threshold
that can be tolerated within the PMON period.

Start/Stop SPS Line Side

Port num 8 SPS port on which to run the loopback.
Metallic Loopback

Start/Stop SPS System

Side Diagnostics Loop Port num 8 SPS port on which to run the loop back
back

Enable SPS CJTPAT

Port num 8 SPS port on which to enable the CJTPAT pattern
pattern

Insert SPS CJTPAT errors Port num 8 SPS port on which to insert errors

9.5.4.5 Diagnostic Commands without User Arguments

The following commands do not take in any arguments.
Table 9-14. Diagnostics Command with No Arguments

User Command

Configure Line Side Analog Loop back

Configure Line Side Digital Loop back

Configure System Side Analog Loop back

De-configure Line Side Analog Loop back

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User Command

De-configure Line Side Digital Loop back

De-configure System Side Analog Loop back

Enable receiving and processing CJTPATs

Enable receiving and processing PRBS

Enable receiving User-defined pattern

Get Error count and Threshold Info reports

Get Code Violation Error Count and Code Violation Error Interval Threshold Info report

Get Code Violation Error Count report

Get Code Violation Error Interval Threshold Info report

Get CRC Error Count report

Get Disparity Error Count and Disparity Error Interval Threshold Info report

Get Disparity Error Count report

Get Disparity Error Interval Threshold Info report

Get In-Connection CRC Error Count report

Get Invalid DWORD Count report

Get Lost DWORD Sync Count report

Get PRBS Error Count report

Get CJTPAT Error Count report

Get User-defined pattern Error Count report

Insert Disparity Error once

Inset erroneous CJTPAT pattern once

Invert PRBS pattern once

Reset Error count and Threshold Info

Reset Code Violation Error Count

Reset Code Violation Error Count and Code Violation Error Interval Threshold Info

Reset Code Violation Error Interval Threshold Info

Reset CRC Error Count

Reset Disparity Error Count

Reset Disparity Error Count and Disparity Error Interval Threshold Info

Reset Disparity Error Interval Threshold Info

Reset In-Connection CRC Error Count

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User Command

Reset Invalid DWORD Count

Reset Lost DWORD Sync Count

Reset PRBS Error Count

Start inserting CJTPAT patterns

Start inserting PRBS patterns

Stop inserting CJTPAT patterns

Stop inserting PRBS patterns

Stop inserting User-defined patterns

HDD Access test

Enable broadcast suppression on a particular PHY

Disable broadcast suppression on a particular PHY

9.5.5 Diagnostics SES Pages

9.5.5.1 SXP Diagnostics Commands Page

The following table lists the format of the SES page used for specifying multiple diagnostics commands:
Table 9-15. SXP Diagnostics Commands Page Format

Bytes/Bits 7 6 5 4 3 2 1 0

0x00 Page Code (0x90)

0x01 Page Code Specific

0x02 MSB
Page Length [n – 3]
0x03 LSB

0x04 User Commands Count

0x05 Command

0x06 Logical PHY ID

0x07

0x08

0x09

0x0A
User Argument Bytes
0x0B

0x0C

0x0D

0x0E

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...........continued
Bytes/Bits 7 6 5 4 3 2 1 0

0x0F Command

0x10 Logical PHY ID

0x11

0x12

0x13

0x14
User Argument Bytes
0x15

0x16

0x17

0x18

……

0x80

Multiple-byte fields in the SES page are in Big Endian byte order. If a multiple-byte integer variable provides a value
of a field, the variable must be entered in Big Endian format.
The Page Code byte must be assigned the value DIAG_SES_PAGE_CODE (0x90).
The Page Code Specific byte is ignored by the Diagnostics component. It is required to comply with the SCSI
Diagnostics Page Header format.
The Page Length field has the number of remaining bytes in the SES page, that is, the number of bytes starting at the
User Commands Count field.
The User Commands Count field contains the number of user commands.
Each command block starts with the Command Type, which is formed by a combination of the values listed in , Table
9-10 and Table 9-11 followed by the logical PHY ID the command applies to and four user arguments. The format of
these arguments depends on the command type. See Table 9-13 for a description of the valid arguments and their
values.
For Diagnostic Setup Control command, the command block is shown in the following table.
Table 9-16. Diagnostic Setup Control Command Block

Bytes/Bits 7 6 5 4 3 2 1 0

0x05+10n ID: Start Setup control

0x06+10n Logical PHY ID

0x07+10n Start/Stop

0x08+10n Diagnostic Pattern Type

0x09+10n Reserved

0x0A+10n Loopback Mode

0x0B+10n Reserved

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Bytes/Bits 7 6 5 4 3 2 1 0

0x0C+10n Reserved

0x0D+10n Reserved

0x0E+10n Reserved

The Start/Stop field specifies diagnostic setup preparation or diagnostic setup cleanup
• 0x01: Diagnostic Setup Preparation. The common preparation task is to disable the ECMR entry for the DUT
PHY.
• 0x00: Diagnostic Setup Cleanup. The common cleanup is to enable the ECMR entry and then do a link reset for
the DUT PHY.
The Diagnostic Pattern Type specifies the test pattern used in the PHY diagnostics. See the additional diagnostics
preparation/cleanup tasks for the specific Pattern Type in the following table.
Table 9-17. Setup Control Actions for Diagnostic Pattern Types

Code Diagnostic Pattern Additional Preparation Additional Cleanup

Type

0x00 PRBS Set Force PHYRDY in SSPL Reset Force PHYRDY in SSPL

0x01 CJTPAT NO NO

0x02 User Pattern NO NO

Reserved - - -

Loopback Mode specifies that line side analog, line side digital or system side analog loopback mode will be used. If
system side analog loopback is specified, firmware forces to override the PHY rate to 12G.
Table 9-18. Setup Control Actions for specific Loopback Pattern Types

Diagnostic Pattern Additional Preparation Additional Cleanup

Type

0x00 NO_LPBK NO No

0x01 LINE_SIDE_ANA_LPB NO NO
K

0x02 LINE_SIDE_DIG_LPBK NO NO

0x03 SYS_SIDE_ANA_LPBK Force PHY rate to 12G in SSPL. Clear operations of forcing
PHY rate.

For insertion of User-defined Patterns, the command block is shown in the following table:
Table 9-19. User-Defined Patterns Command Block

Bytes/Bits 7 6 5 4 3 2 1 0

0x05+10n ID: Start Inserting User Patterns

0x06+10n Logical PHY ID

0x07+10n Bit[7:0] of 1st 10-bit of DWORD

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Bytes/Bits 7 6 5 4 3 2 1 0

0x08+10n Bit[7:0] of 2nd 10-bit of DWORD

0x09+10n Bit[7:0] of 3rd 10-bit of DWORD

0x0A+10n Bit[7:0] of 4th 10-bit of DWORD

0x0B+10n Reserved Bit[9:8] of 2nd 10-bit Reserved Bit[9:8] of 1st 10-bit

0x0C+10n Reserved Bit[9:8] of 4th 10-bit Reserved Bit[9:8] of 3rd 10-bit

0x0D+10n Dword_id (0 or 1)

0x0E+10n Reserved

Note:
The SXP 12G device provides two 40-bit internal registers for user-defined values. Only when the two Dwords are
both set can the user-defined pattern test start. The field DWORD ID is used to specify which Dword is going to be
set. Only value 0 or 1 is valid for this field.
For PRBS and User-defined pattern error generation, the 40-bit user argument is aligned as follows:
Table 9-20. Error Insertion Command Block

Bytes/Bits 7 6 5 4 3 2 1 0

0x05+10n ID: Insert PRBS/User-defined pattern Error once

0x06+10n Logical PHY ID

0x07+10n Bit[7:0] of 1st 10-bit of Error Mask

0x08+10n Bit[7:0] of 2nd 10-bit of Error Mask

0x09+10n Bit[7:0] of 3rd 10-bit of Error Mask

0x0A+10n Bit[7:0] of 4th 10-bit of Error Mask

0x0B+10n Reserved Bit[9:8] of 2nd 10-bit Reserved Bit[9:8] of 1st 10-bit

0x0C+10n Reserved Bit[9:8] of 4th 10-bit Reserved Bit[9:8] of 3rd 10-bit

0x0D+10n Reserved

0x0E+10n Reserved

For Code Violation pattern insertion, the 10-bit user argument is aligned as listed in the following table.
Table 9-21. Code Violation Error Insertion Command Block

Bytes/Bits 7 6 5 4 3 2 1 0

0x05+10n Insert Code Violation once

0x06+10n Logical PHY ID

0x07+10n Bit[9:8] of 10-bit of Error Mask

0x08+10n Bit[7:0] of 10-bit of Error Mask

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Bytes/Bits 7 6 5 4 3 2 1 0

0x09+10n Reserved

0x0A+10n Reserved

0x0B+10n Reserved

0x0C+10n Reserved

0x0D+10n Reserved

0x0E+10n Reserved

For specifying thresholds, the threshold value and optional user value of PMON Period are aligned as shown in the
following table.
Table 9-22. PMON Period and Threshold Value

Bytes/Bits 7 6 5 4 3 2 1 0

0x05+10n ID: Specify Thresholds

0x06+10n Logical PHY ID

0x07+10n 8-bit Threshold

0x08+10n MSB

0x09+10n [Optional] 24-bit PMON Period

0x0A+10n LSB

0x0B+10n

0x0C+10n
Reserved
0x0D+10n

0x0E+10n

The firmware ignores the argument bytes for the other command types. The PMON period specifies the number of
150-MHz clock cycles. As such, each count has a duration of ~6.7 ns. The minimum valid value for the PMON period
is 0x000012 and the maximum value is 0xFFFFFEor approximately 112 ms. Setting the PMON period to 0xFFFFFF
disables the PMON timer.

9.5.5.2 SXP Diagnostics Reports SES Page

The following table shows the format of the SES page.
Table 9-23. SXP Diagnostics Reports SES Page Format

Bytes/Bit 7 6 5 4 3 2 1 0

0x00 Page Code (0x90)

0x01 Page Code Specific

0x02 MSB
Page Length [n – 3]
0x03 LSB

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Bytes/Bit 7 6 5 4 3 2 1 0

0x04 User Commands Count

0x05 Response Count

0x06 Command

0x07 Logical PHY ID

0x08 User Command Processing Status

0x09

0x0A
Response Data Bytes
0x0B

0x0C

0x0D Command

0x0E Logical PHY ID

0x0F User Command Process Status

0x10

0x11
Response Data Bytes
0x12

0x13

……

0x80

Multiple-byte fields of this SES page are in Big Endian byte order.
The Page Code byte should have the value DIAG_SES_PAGE_CODE (0x90).
The Page Code Specific byte is ignored by the Diagnostics API and is provided only for compliance with the SCSI
Diagnostics Page Header format.
The Page Length contains the number of bytes starting from User Commands Count field until the end of the SES
page.
User Commands Count is a copy of the corresponding field in the matching user command’s SES page sent earlier.
The Response Count is the number of reports in this SES page.
After the Response Count field, the reports follow. Each report block starts with the Command Type, which matches
the Command Type sent in the matching User Commands SES page. The logical PHY ID is next, followed by the
User Command Processing Status. Valid values for this field are listed in the following table.
Table 9-24. Command Processing Status Values

Value Status Constant

0x00 DIAG_USR_CMD_PROC_STATUS_SUCCESS

0x01 DIAG_USR_CMD_PROC_STATUS_INVALID_COMMAND

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Value Status Constant

0x02 DIAG_USR_CMD_PROC_STATUS_SYS_FAIL

0x03 DIAG_USR_CMD_PROC_STATUS_NOT_IN_DBG_MODE

The format of the Response Data Bytes depends on the command type. If the User Command Processing Status
field indicates DIAG_USR_CMD_PROC_STATUS_INVALID_COMMAND error, the report data consists of one byte
indicating the part of the command with the error. The following table lists the possible values.
Table 9-25. Invalid Command Part Values

Value Invalid Command Part Value

0x00 DIAG_INVALID_USR_CMD_TYPE

0x01 DIAG_INVALID_USR_CMD_DESC

0x02 DIAG_INVALID_USR_ARGS

If errors were not detected, the report data is one of the following:
• Threshold reports use a one-byte Boolean value that indicates if a threshold was reached. A value of 0x00
means NO and 0x01 means YES.

Bytes/Bits 7 6 5 4 3 2 1 0

0x06+7n Command

0x07+7n Logical PHY ID

0x08+7n User Command Processing Status

0x09+7n YES / NO, or, Bad User Command Part Identifier

0x0A+7n

0x0B+7n Not used

0x0C+7n

• The PRBS error count, CRC Error Count and In-connection CRC Error Count are provided in the first two
response bytes.

Bytes/Bits 7 6 5 4 3 2 1 0

0x06+7n Command

0x07+7n Logical PHY ID

0x08+7n User Command Processing Status

0x09+7n
Error Count
0x0A+7n

0x0B+7n
Not used
0x0C+7n

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• Disparity Error Count, Code Violation Count, Invalid DWORD count and Lost DWORD Synchronization count
are provided by four response bytes

Bytes/Bits 7 6 5 4 3 2 1 0

0x06+7n Command

0x07+7n Logical PHY ID

0x08+7n User Command Processing Status

0x09+7n

0x0A+7n
Error Count
0x0B+7n

0x0C+7n

• SPS Error counts (for SPS configured ports) for Invalid Dword, Disparity Error, Loss of Dword Sync, Code
Violation, SSPL PHY Reset Failed Count, and SSPL Code Violation Error Count are returned by 4 response
bytes.

Bytes/Bits 7 6 5 4 3 2 1 0

0x06+7n Command

0x07+7n Logical PHY ID

0x08+7n User Command Processing Status

0x09+7n

0x0A+7n
Error Count
0x0B+7n

0x0C+7n

9.5.5.3 Relationship between Commands and Reports

When using the SES interface into the Diagnostics module, you can also issue composite DIAG_REPORT_GET
commands to retrieve multiple reports. Composite command descriptor options for the DIAG_REPORT_GET
command are listed in the following table.
Table 9-26. Composite DIAG_REPORT_GET Command Descriptors

Command Descriptor Results in

CODE_VIOL_ERR_CNT
CODE_VIOL_ERR_CNT_THHD
CODE_VIOL_ERR_THHD

DISP_ERR_CNT
DISP_ERR_CNT_THHD
DISP_ERR_THHD

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Command Descriptor Results in

PRBS_ERR_CNT

CODE_VIOL_ERR_CNT

CODE_VIOL_ERR_THHD

DISP_ERR_CNT

ALL DISP_ERR_THHD

CRC_ERR_CNT

IN_CONN_CRC_ERR_CNT

LOST_DWD_SYNC_CNT

INVALID_DWD_CNT

9.5.5.4 Diagnostic Commands Guidelines

The following steps are general guidelines to help you determine the order of the commands sent to the firmware:
Note:
• Multiple diagnostic operations performed on the same PHY should be ordered to avoid erroneous results. This
applies to both the SES and API interfaces.
• For the SES Page Interface, the order in which commands appear in the SES page is the processing order.
1. Before performing the diagnostic test, perform the Diagnostic Setup Control procedure. After performing
setup control, patterns can be transmitted.
2. Perform a receive enable after patterns reach the PHY receiver.
3. If a PHY is required to transmit what it received, configure a line side analog loopback or line side
digital loopback. If a PHY is required to receive what it transmitted, configure a system side analog loop
back. If error count threshold information is required, the thresholds should be specified before errors are
inserted. This avoids any erroneous or unexpected results.
4. Before inserting patterns and errors, or inverting PRBS and CJTPAT patterns to induce errors, reset the
error counters to ensure that the error counts and the thresholds are affected only by the commands.
5. Insert patterns and errors to induce errors or check data integrity.
6. Retrieve error count reports and threshold-reached reports before the receiver stops and the error counts
or threshold information registers are reset.
7. De-configure loop back before stopping pattern and error insertion. This avoids forming any potential
internal active link within an expander PHY.
8. Reset error count and threshold information registers.
9. Perform the diagnostic setup control for PHY diagnostic cleanup.

9.5.6 Logical Division of Diagnostics Operations – Transmitter and Receiver Sides

The diagnostics operations scenario is divided into two logical parts – transmitter side and receiver side. On the
transmitter side, patterns are generated and errors are inserted. The receiver side receives the patterns and errors.
The divisions are logical, as the transmitter and receiver PHYs shown can be on the same SXP device. Also, system
side analog loop back can be configured on the same PHY to make it receive its own generated and inserted
patterns or errors.
The following figure is an overview of how diagnostics operations are organized and performed using diagnostics
commands. It shows which diagnostics commands are used on the transmitter side and which are used on the
receiver side. Note that the diagram does not imply any specific ordering. It also shows typical choices of loop-back
configurations.

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Figure 9-17. Logical Division of Diagnostics Operations

Transm itter Receiver
Side Side

Insert Patterns Enable Receive

Insert Errors Specify

Thresholds

Stop Inserting
Diagnostics Diagnostics
Patterns Reset Counters
Com m ands Com m ands
SES Page SES Page
System Side Retrieve
Loop back Reports

Line Side Loop

backs

Diagnostics
Reports
SES Page

Diagnostics Module Diagnostics Module

Top MABC Top MABC

SSPL SXL SSPL SXL
Level Port Level Port
Regs Regs Regs Regs
Regs Regs Regs Regs

System Side Line Side

Loop back Loop backs

Transm itter Phy Rx Tx Rx Tx Receiver Phy

The following figure shows the Logical Division when an SPS device is also involved in the port operations.

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Figure 9-18. Diagnostics Operations Involving SXP and SPS

SXP

TX RX .

SXP System Side Loop Back

SPS RX TX

SDPA

SPS System Side Digital Loop Back

TX RX

Drive SPS and Drive Diag Test

9.5.7 Examples

9.5.7.1 SES Page Examples

In this example, there is a connection between PHYs 8 and 12 on an SXP 12G device. In this example we:
• Specify a code violation error interval threshold of 10
• Set the PMON Period of 0xFFFFFE (the maximum) on PHY 8
• Insert two code violation errors on PHY 8
• Get the reports to check the code violation error count.
• Get the reports to check if the threshold was reached on PHY 12.
The diagnostics commands that need to be specified are:
• Specify Code Violation Error Interval Threshold -
The command is DIAG_BITMSK_USR_CMD_TYP_THRESHOLD_SPECIFY |
DIAG_BITMSK_USR_CMD_DESC_CODE_VIOL_INSERT (4B h)
• Insert Code Violation Error - The command is DIAG_BITMSK_USR_CMD_TYP_ DIAG_OPRN_PERFORM |
DIAG_BITMSK_USR_CMD_DESC_CODE_VIOL_INSERT (0B h)
• Insert Code Violation Error
• Get Code Violation Error Count and Code Violation Error Interval Threshold
info reports - The command is DIAG_BITMSK_USR_CMD_TYP_DIAG_REPORT_GET |
DIAG_BITMSK_USR_CMD_DESC_CODE_VIOL_ERR_CNT_THHD (89 h)
The following table shows an example of the resulting User Commands SES page:

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Table 9-27. User Commands SES Page Format

Bytes Field Value

0x00 Page Code 0x90

0x01 Page Code Specific Don’t care

0x02 Page Length MSB 0x00

0x03 Page Length LSB 0x19

0x04 User Commands Count 0x04

0x05 Command 0x4B

0x06 Logical PHY ID 0x08

0x07 Threshold 0x0A

0x08 PMON Period Byte 2 0xFF

0x09 PMON Period Byte 1 0xFF

0x0A PMON Period Byte 0 0xFE

0x0B Unused Don’t care

0x0C Unused Don’t care

0x0D Unused Don’t care

0x0E Unused Don’t care

0x0F Command 0x0B

0x10 Logical PHY ID 0x08

0x11 Unused Don’t care

0x12 Unused Don’t care

0x13 Unused Don’t care

0x14 Unused Don’t care

0x15 Unused Don’t care

0x16 Unused Don’t care

0x17 Unused Don’t care

0x18 Unused Don’t care

0x19 Command 0x0B

0x1A Logical PHY ID 0x08

0x1B Unused Don’t care

0x1C Unused Don’t care

0x1D Unused Don’t care

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Bytes Field Value

0x1E Unused Don’t care

0x1F Unused Don’t care

0x20 Unused Don’t care

0x21 Unused Don’t care

0x22 Unused Don’t care

0x23 Command 0x89

0x24 Logical PHY ID 0x0C

0x25 Unused Don’t care

0x26 Unused Don’t care

0x27 Unused Don’t care

0x28 Unused Don’t care

0x29 Unused Don’t care

0x2A Unused Don’t care

0x2B Unused Don’t care

0x2C Unused Don’t care

The following table shows an example of a Report SES page:

Table 9-28. Report SES Page Format

Bytes Field Value

0x00 Page Code 0x90

0x01 Page Code Specific Don’t care

0x02 Page Length MSB 0x00

0x03 Page Length LSB 0x10

0x04 User Commands Count 0x04

0x05 Response Count 0x02

0x06 Command 0x81

0x07 Logical PHY ID 0x0C

0x08 Command Processing Status 0x00

0x09 Code Violation Error Count Byte 3 0x00

0x0A Code Violation Error Count Byte 2 0x00

0x0B Code Violation Error Count Byte 1 0x00

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Bytes Field Value

0x0C Code Violation Error Count Byte 0 0x02

0x0D Command 0x99

0x0E Logical PHY ID 0x0C

0x0F Command Processing Status 0x00

0x10 Threshold Reached? 0x00

0x11 Unused Don’t care

0x12 Unused Don’t care

0x13 Unused Don’t care

9.6 IPMB

9.6.1 General Description

The firmware provides a mechanism to query non-intelligent peripheral devices to manage the enclosures through
TWI interfaces. The TWI interface is also extended to support IPMB commands to communicate with intelligent
devices within the enclosure that use such commands. The IPMB module provides a thin layer of API on which
additional platform management capabilities can be built.

9.6.2 Implementation
The firmware IPMB module passes the user-supplied standard-compliant commands and responses almost
transparently, without decoding any of the parameters within the messages. The only exception is the calculation
of the connection header and message checksums, which are determined internally by the firmware IPMB module.
For example, the firmware does not keep track of the LUN or sequence numbers.

9.6.2.1 Module Dependencies

The IPMB module relies on the TWI driver to transport IPMB commands and responses. As such the IPMB module
is a thin layer of firmware that simply takes in user-specified IPMB commands, calculates the appropriate checksums,
sends the commands through the TWI interface, and waits for the responses. The IPMB command and response
formats are defined in the IPMB standard and are reproduced in the following tables.
Table 9-29. IPMB Node-to-Node Request Message Format

Byte Assignment Description

0 rsSA Responder’s 7-bit (TWI) slave address located from bits 7 to 1. Bit 0 is 0.
Connection header

1 netFn / rsLUN Net function (even) and responder’s logical unit number

2 ChkSum Header checksum. This field is calculated by the IPMB module and can be left at
a value of 0.

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Byte Assignment Description

3 rqSA Requestor’s 7-bit (TWI) address located from bits 7 to 1. Bit 0 is 0.

4 rqSeq / rqLUN Requestor’s sequence number and requestor’s logical unit number

5 cmd

6 Data Zero or more data bytes, denoted by N.

6+N ChkSum Command checksum. This field is calculated by the IPMB module and can be
left at a value of 0.

Table 9-30. IPMB Node-to-Node Response Message Format

Byte Assignment Description

0 rqSA Requester’s 7-bit (TWI) slave address located from bits 7 to 1. Bit 0 is 0.
Connection header

1 netFn / rqLUN Net function (odd) and requester’s logical unit number

2 ChkSum Header checksum. This field is calculated by the IPMB module and can be left at
a value of 0.

3 rsSA Responder’s 7-bit (TWI) address located from bits 7 to 1. Bit 0 is 0.

4 rqSeq / rsLUN Requestor’s sequence number and responder’s logical unit number

5 cmd

6 Completion
code

7 Data Zero or more response data bytes, denoted by N.

7+N ChkSum Command checksum. This field is calculated by the IPMB module and can be
left at a value of 0.

9.6.2.2 Firmware API

The following APIs can initialize, send IPMB commands, and receive IPMB responses:

void twi_ipmb_init(UINT8 port_id, twi_mst_callback_fptr

Prototype mst_callback_fptr, void *mst_callback_data_ptr, UINT32 mst_ctl, UINT32
mst_cfg, UINT32 mst_int_enb, UINT32 mst_clk, UINT8 twi_slv_addr);

Inputs port_id The TWI port identification (0 – 11).

mst_callback_fptr Pointer to a function called out from the TWI master ISR.

Pointer to a data buffer returned by the TWI master ISR during the
mst_callback_data_ptr
call out.

mst_ctl A 32-bit integer containing the TWI master control fields.

mst_cfg A 32-bit integer containing the TWI master configuration fields.

mst_int_enb A 32-bit integer containing the TWI master interface enable bits.

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mst_clk A 32-bit integer containing the TWI master clock setting.

twi_slv_addr The TWI device address when operating as an IPMB slave.

Outputs None.

Returns None.

PMCFW_ERROR twi_ipmb_read(UINT8 port_id, UINT8 *read_buffer_ptr, UINT8

Prototype
read_buffer_nb_byte);

Inputs port_id The TWI port identification (0 – 11).

Pointer to a buffer containing the response message of the format

read_buffer_ptr
as shown in Table 9-30.

The length of buffer in bytes pointed to by the parameter

read_buffer_nb_byte
read_buffer_ptr.

Outputs Data read. Data is returned in the buffer pointed to by read_buffer_ptr.

Returns PMC_SUCCESS Function executed successfully.

PMCFW_ERR_TIMER_FAILED Timed out in acquiring TWI slave port mutex.

PMCFW_ERROR twi_ipmb_write(UINT8 port_id, UINT8 *write_buffer_ptr, UINT8

Prototype
write_buffer_nb_byte);

Inputs port_id The TWI port identification (0 – 11).

Pointer to a buffer containing the request message of the

write_buffer_ptr
format as shown in Table 9-29.

The length of the request message in bytes pointed to by the

write_buffer_nb_byte
parameter write_buffer_ptr.

Outputs None.

Returns PMC_SUCCESS Function executed successfully.

TWI_ERR_MASTER_TIMEOUT Timed out in acquiring TWI port mutex.

TWI_ERR_MST_FIRMWARE_TIMEOU
Firmware timed out on transaction.
T

TWI_ERR_MST_PORT_NACK No response from target TWI device.

TWI_ERR_MST_ARBLOST Arbitration lost error.

PMCFW_ERROR twi_ipmb_write_read(UINT8 port_id, UINT8 *write_buffer_ptr,

Prototype UINT8 write_buffer_nb_byte, UINT8 *readbuffer_ptr, UINT8
read_buffer_nb_byte);

Inputs port_id The TWI port identification (0 – 11).

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Pointer to a buffer containing the request message of the

write_buffer_ptr
format as shown in Table 9-29.

The length of the request message in bytes pointed to by the

write_buffer_nb_byte
parameter write_buffer_ptr.

Pointer to a buffer containing the response message of the

read_buffer_ptr
format as shown in Table 9-30.

The length of buffer in bytes pointed to by the parameter

read_buffer_nb_byte
read_buffer_ptr.

Outputs Data read. Data is returned in the buffer pointed to by read_buffer_ptr.

Returns PMC_SUCCESS Function executed successfully.

TWI_ERR_MASTER_TIMEOUT Timed out in acquiring TWI port mutex.

TWI_ERR_MST_FIRMWARE_TIMEOU
T Firmware timed out on transaction.
PMCFW_ERR_TIMER_FAILED

TWI_ERR_MST_PORT_NACK No response from target TWI device.

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Port Manager Component

10.3.1.1 Populating Routing Table Entries from Adjacent Self-Configuring Expander

The Microchip proprietary Distributed Topology Discovery (a.k.a. TOPD) algorithm needs to obtain all valid routing
table entries from each adjacent SAS 2.0 expander. This is done using the SMP Report Expander Route Table List
command. In a large topology, for example, a topology with 4000 entries in the SAS domain, populating all routing
entries in the adjacent expander routing table takes a long time (e.g. 100 ms) and occupies the SAS bandwidth.
To speed up this process, the TOPD algorithm was modified so that the SXP12G requests only routing entries
without redundant destination routing entry information from the adjacent expander.
Figure 10-2. Expander Route Table in SAS-2.0 Topology

In the example topology in Figure 10-2, both the hash table of expander CC and the hash table of expander DD
contain full topology information. If expander CC performs TOPD for expander DD through port M-N, expander CC
does not need the red hash entries from expander DD’s hash table since expander CC already has them. It is the
same when expander DD performs TOPD for expander CC. To eliminate the unnecessary reporting of redundant
entries, an improvement was made so that the expander does not report its route table list entries for the PHYs in the
current TOPD SMP connection. This improvement greatly reduces the number of SMP Report Expander Route Table
List commands during the TOPD procedure.

10.3.1.2 Skip populating Upper or Lower 48 PHY BITMAP without other Expanders Attached
The PHY BIT MAP field indicates the Routed SAS address to be routed to each PHYs (each bit represents a PHY).
The SAS-2 and SPL specifications define the PHY BITMAP as 48 bits. The PM805x expander family can support up
to 68 ports. Thus, to report the 68-bit PHY bit map for a routed SAS address, the TOPD master needs to issue two
SMP Report Expander Route Table List Functions:
• One with STARTING PHY IDENTIFIER ‘0’ for the lower bitmap 0-47
• And the other with STARTING PHY IDENTIFIER ‘48’ for the upper bitmap above 48.
If the destination PHYs for all routed SAS Addresses are within the lower bitmap 0-47, TOPD master actually does
not necessarily populate the expander routing descriptors with STARTING PHY IDENTIFIER ‘48’ since all returned
descriptors with all zero PHY BIT MAP. Correspondingly, if the destination PHYs for all routed SAS Addresses are
within the upper bitmap 48-95, the TOPD master does not necessarily populate the descriptors with STARTING PHY
IDENTIFIER ‘0’.
In the SXP 12G firmware, the TOPD master determines if populating the routed SAS addresses is done from the
adjacent self-configuration expander in the lower bitmap, in the upper bitmap, or in both.

10.3.2 SAS-2 Allowed Connections

The SAS-2 standard defines one port of the SAS-2 expander, the enclosure universal port, which supports table-to-
table attachment using the same external connector.

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Figure 10-3. SAS-2 Allowed Connections

Table-to-table enabled Expander: The SAS-2 self-configuring expander with table-to-table enabled, like the SXP 12G
expander working with the enhanced distributed discovery algorithm.
No Table-to-Table support Expander: The SAS 1.1 expander (self-configuring or non-self-configuring expander) or the
SAS-2 self-configuring expander with table-to-table disabled or not supported.
Connection#1: Does not allow table-to-table connections for a non-table-to-table supported expander device with this
connection type.
Connection#2: Does not allow table port connection of a non table-to-table supported expander device with this
connection type. If SXP 12G expander works with SXP3G legacy distributed discovery algorithm by disabling table-
to-table support in initialization string, the conn#2 is allowed.
Connection#3/#4/#5: Table-to-table support is allowed.
If the connection is not supported, the LED for the expander PHYs is lit RED indicating a wrong connection.

10.3.3 Supported Expander Self-configuring Mode

Table 10-1. Supported Expander Self-configuration Mode

SXP 12G Expander Self- Self-configuring Table to Table Supported Supported

Configuring Mode Expander Bit Enable Bit Connection Topology
Mode Examples

(I) Non Self-configuring Expander 0 X (0 or 1) SAS1.1 T-S and Model#1

S-S

(II) SAS1.1 Self-configuring 1 0 SAS1.1 T-S and Model#1

expander with SXP3G legacy S-S
distributed discovery algorithm

(III) SAS-2 Self-configuring 1 1 SAS-2 Allowed Model#2, #3

expander with the enhanced Connections
distributed discovery algorithm

Note:

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See the SXP 12G Initialization String Table – Topology Discovery Configuration for the definition of a self-configuring
expander bit and table to table enable bit.

10.3.4 Typical SAS Topologies with SXP 12G Expanders

Figure 10-4. Typical Usage Models

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Figure 10-5. Typical Usage Modes (cont.)

Model#1: SXP 12G expander is attached to the existing SAS1.1 Topology with SAS1.1 Self-configuring Mode or
non-self-configuring Mode.
Mode#2: Full SAS-2 Expander topology and the SXP 12G in SAS-2 Self-configuring Mode with table-to-table
enabled.
Mode#3: SAS-2 Expander attached SAS1.1 sub-topology with T/S/U to S connections.
Mode#4: An example of a restricted topology since there is one forbidden connection between SAS-2 JBOD#D (with
SAS-2 Self-configuring with table-to-table enabled) and SAS1.1 JBOD#C.
Note:
Although only several daisy-chain SAS topologies are listed in this section, the SXP 12G expander supports SAS1.1
FANOUT topology.

10.3.5 Loop Topology Detection and Resolution

• NOTIFY(ENABLE_SPINUP) primitives – for SAS-connected links on which power control is not enabled or
supported
• PWR_GRANT primitives – for SAS-connected links on which power control is enabled
• LINK or HARD RESETs – for the specified links
Inputs to the module consist of both static configuration data loaded from the initialization string and the dynamic
events that are triggered either by a timer, the arrival of an SMP PHY control command, a change in the status of any
one of the PHYs, or Power Control Primitives (PWR_REQ, PWR_DONE) received.
The three events that can trigger the operation of the disk spin-up module include:
• PHY event: A PHY event occurs when there is a change in the status of a PHY. The PHY state changes
include :
– PHY changing to ready
– PHY changing to not ready
– PHY attaining the SATA spin-up hold state
– PHY receiving the NOTIFY(ENABLE_SPINUP) primitive
– PHY receiving the Power Control Primitive, that is, PWR_REQ or PWR_DONE when both SXP PHY and
the attached SAS device are Power Capable (10b) in Table 121, [7].
The port manager thread polls the PHYs to determine their status. If a change in the PHY’s status is detected, the
spin-up module’s PHY event handler is invoked through a callback. Depending on the initialization string settings, the
handler routine either ignores the event or marks the PHY to check when its PHY-grouping is due for processing.
• Timer event: At regular intervals, the port manager thread invokes the spin-up module’s timer event handler.
During this callback, the drive grouping is cycled and the various PHYs’ status within the current drive group is
examined to determine if further processing is warranted on the particular PHYs.
• SMP PHY control event: The spin-up module, when set to execute SMP PHY control reset commands,
generates the LINK or HARD RESET on the specified PHYs, regardless of the attached device type. The
SMP module assists in this function by terminating the SMP PHY control command and saving the reset status
until at which time the status is read by the spin-up module. The spin-up module polls the SMP PHY reset flags
at each interval timer period and executes the resets as stipulated.

10.4.2 Control
During initialization of the disk spin-up module, the disk spin-up configuration is read from the initialization string and
the mode of operation is determined. In particular, the following settings are specified:
• The default spin-up algorithm is disabled when the Staggered Spin-Up (SSU) algorithm is enabled or put in
stand-by.
• Hierarchical slave spin-up operation enable/disable settings and the hierarchical host PHYs selection. By
default, the hierarchical master must operate in the staggered spin-up mode.
• SATA device handling is determined by the SATA_SPINUP and SATA_HOLD fields, as shown in the following
table. The timer delay parameters are not applicable when the module is configured to run in the hierarchical
slave mode.
Table 10-2. SATA Disk Spin-Up Confirmation

SATA_SPINUP SATA_HOLD Description

0 0 SATA drives can complete speed negotiation immediately after the serial
link resets (that is, after a hot plug event). A link or hard reset must be
generated on the link within the specified 10 ms. The spin-up module is not
involved for this configuration.

0 1 SATA drives are prevented from completing speed negotiation after

COMRESET. Speed negotiation is only allowed to complete after the SMP
performs a LINK RESET or HARD RESET on the PHY, spinning up the
drive. This configuration is compliant with the SAS specification. The spin-
up module is not involved for this configuration.

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...........continued
SATA_SPINUP SATA_HOLD Description

1 0 SATA drives are prevented from completing speed negotiation after

COMRESET. The spin-up module schedules SATA spin-up events based
on the spin group, initial delay and interval delay. When a link enters the
SATA hold state, the spin-up module triggers the specified reset at the
appropriate interval time.

1 1 An SMP PHY control command operation must be performed by a host

to mark the PHY for spinning up. The spin-up module triggers the LINK
RESET or HARD RESET at the appropriate interval time only if the link
is marked for either a LINK or a HARD RESET. The reset is performed
regardless of the PHY status or attached device type (that is, SAS versus
SATA). If a SATA drive is attached to the PHY of interest, it is prevented
from completing speed negotiations after COMRESET.

Note:
Similarly, the SAS_SPINUP and SAS_NOTIFY fields in the initialization string control how SAS disks should be spun
up. See the following table. The initial delay and interval timer period are not valid when the module is configured to
operate in the hierarchical slave mode.
Table 10-3. SAS Disk Spin-Up Confirmation

SAS_SPINUP SAS_NOTIFY Description

0 0 The spin-up module does not generate NOTIFY primitives. No SAS

drives are spun up.
When the Power Capable (10b) in both SXP PHY and the attached SAS
device is enabled, SXP Firmware will not handle the Power Request
(PWR_REQ) from the SAS device, and not grant the Power to the SAS
device as well.

0 1 The spin-up module generates NOTIFY primitives on the SAS links. The
SAS drives are spun up simultaneously.
When the Power Capable in both SXP PHY and the attached SAS device
is enabled, SXP Firmware will reply the Power Request (PWR_REQ)
from the SAS device with PWR_GRANT immediately.

1 0 Reserved. Unused.

1 1 When the drives are being checked during the appropriate interval time,
the spin-up module generates
- PWR_GRANT to the SAS end device that requires power thru
PWR_REQ, when both SXP PHY and the attached SAS end device are
Power Capable;
- NOTIFY primitives to the SAS end device when neither SXP PHY nor
the attached SAS end device is Power Capable.

The shaded row in each of the two tables above indicates the recommended default configuration.
As an example, consider a setting that consists of an interval period of 8 seconds and an initial delay of 2 seconds
with a 6-drive group. The following table shows the PHYs (drives) that are spun up at each interval period for the first
60 seconds of the spin-up sequence.

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Table 10-4. PHY Spin-Up Sequence Example

Time 0 2 10 18 26 34 42 50 58 66 74 …

PHYs None 0-5 6 - 11 12 - 17 18 - 23 24 -29 30 - 35 36 - 41 42 - 47 48 - 53 54 - …

spun 59
up

The spin-up sequence repeats every 96 seconds plus the 2-second initial delay offset. If a drive is inserted/hot-
plugged after the firmware starts, the drive is spun-up at the next interval period whenever the group it belongs to is
scheduled for processing.

10.4.3 Modes of Operation

An expander operates in one of two states: Staggered or hierarchical. In the staggered mode of operation, each
expander independently controls the drives that are directly connected to it. The host can also assist the spin-up
process for SATA drives, as described in the initialization string configuration.
The hierarchical spin-up configuration is a special case where one expander is designated as the hierarchical
master and the remaining expanders in the topology tree are considered hierarchical slaves. The hierarchical master
typically has a drive grouping consisting of one drive. For each timer period, the master “spins up” a group of PHYs,
rotates to the next group, and awaits the next interval timer period expiry. The slave expanders do not use the
spin-up timer. These expanders wait for a NOTIFY primitive from the hierarchical host, spins up the drives from the
current drive group, advance to the next group, and then wait for the next NOTIFY primitive before repeating the
whole process. During the spinning up of a group of drives, a slave might implicitly forward the NOTIFY primitive to
the downstream expanders, if any. The following figures shows an example of the effect of the hierarchical spin-up
feature for several successive intervals starting from interval timer period T0. Note that the spin-up interval timer
period is typically a few seconds.
Figure 10-9. Hierarchical Spin-Up

Expander
T 0 / T 4 / ... (hierarchical host)

T 3 / T 7 / T 11 / ...
T 2 / T 6 / T 10 / ...
T 1 / T 5 / T 9 / ...

Expander (slave 1) Expander (slave 2) Expander (slave 3)

T 1 / T 9 / ... T 5 / T 13 / ... T 2 / T 6 / T 10 / ... T 3 / T 7 / T 11 / ...

B C E
D

In the previous figure, the hierarchical host expander generates NOTIFY primitives for drive group A at intervals T0,
T4, T8, and so on. Slave Expander 1 receives NOTIFY primitives at interval T1, T5, T9, et cetera. Because this slave
expander is controlling two drive groups, it spins up the B group during the interval T1 and the C group during interval
T5. At timer interval T9, the NOTIFY primitives are again sent to the drive group B, and T13 for drive group C. Only
one drive group can be spun up in any given interval timer period. The process repeats indefinitely.
The following example further shows the effect of drive grouping and wide-port connections between the expanders
on the hierarchical spin-up configuration.
Consider the case of a hierarchical spin-up configuration shown in the following figure. The SXP 12G expanders are
configured as hierarchical slaves with two drives per group. There is a 4-PHY wide-port connecting the SXP 12G
expander to each one of the expanders. As a hierarchical master, the SXP 12G is configured to have a PHY grouping
of 1 PHY per group.

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Figure 10-10. Hierarchical Spin-Up Topology Example

Assume a processing interval of 8 seconds. The following table shows the storage blade, and the drives within that
blade, that are spun-up at each timer interval for the first 120 seconds.
Table 10-5. Hierarchical Drive Spin-Up Example (Wide-Port)

Time 2 10 18 26 34 42 50 58 66 72 80 88 96 104 112 120

Blade B0: B0: B0: B0: B1: B1: B1: B1: B2: B2: B2: B2: B3: B3: B3: B3:
& D0 D2 D4 D6 D0 D2 D4 D6 D0 D2 D4 D6 D0 D2 D4 D6
Drive D1 D3 D5 D7 D1 D3 D5 D7 D1 D3 D5 D7 D1 D3 D5 D7
s

Consider that, based on the results of Table 10-5, there is a four-PHY wide-port connecting each storage blade to
the SXP expander. Because the SXP expander only generates one NOTIFY(ENABLE_SPINUP) primitive per PHY at
each interval period due to the drive/PHY group setting, it takes four periods to span each wide-port. Each storage
blade receives four NOTIFY(ENABLE_SPINUP) primitives in succession, each one separated by the interval delay
from the others. This results in four drive groups in each blade being spun up before the next blade is processed. As
a counter example, if the blades were connected to the SXP 12G device using a narrow port, the spin-up sequence is
shown in the following table:
Table 10-6. Hierarchical Drive Spin-Up Example (Narrow Port)

Time 2 10 18 26 34 42 50 58 66 72 80 88 96 104 112 120

SPINUP_INIT_READY This state indicates that the drive is spinning, but not necessarily accessible. If a SATA
device is attached, the PHY is in the SATA SPINUP Hold state and must be reset for
the PHY to reach a ready state. In the case of SAS attached, this state indicates
that periodic NOTIFY (ENABLE SPINUP) primitives are not currently being issued to
the drive. However, a SAS drive will be accessible in this state. Transitioning to the
spin-up spinning state will not require additional power since the drive spindle is already
spinning.

The state transition is controlled by five states. They are listed in the following table.
Table 10-8. SSU Events

Event Description

PHY Ready This event occurs when the PHY has reached the SP15: SAS PHY_Ready state

SATA Spinup Hold This event occurs when the PHY has reached the SP26: SATA_Spinup Hold state

PHY Initialization This event will cause a drive to begin spinning if it isn’t already. For SATA drives, this
requires a PHY reset sequence; for SAS it requires the transmission of a NOTIFY(ENABLE
SPINUP) primitive.

PHY Not Ready This event occurs when a PHY has reached the SP0: OOB_COMINIT state

Drive Powered Off This event occurs when the disk drive is powered off

Notes:
• In this user manual, when there is a Drive Hot-Plug event or the drive is removed, the drive loses its power
supply unless the context explicitly indicates otherwise.

10.5.1 The Power Budget Equation

The algorithm can be summarized by the following power equation:

D Spin − able = ((PTotal − PRun × D Run − PSpin × D Spin )> PSpin _ req )? TRUE : FALSE
,
Where,
DSpin-able indicates whether a disk can be spun up in the current interval; PTotal is the total power available in Watts;
PRun is the power required to keep one drive in the normal operating/spinning state; DRun is the number of drives that
are currently running/spinning; PSpin is the power required (in Watts) to spin up a drive from a dead stop state;
DSpin is the number of drives that are currently spinning up;
PSpin_req is the power required (in Watts) to spin up a drive from its current state. If its current status is a dead stop
state, then PSpin_req = PSpin; if its current status is a spinning state, then PSpin_req equals to PSpin_req = (PSpin - DRun).
Another parameter is DMax, which indicates the maximum number of drives that is allowed to spin up at any interval.
This equation simply states whether a disk can be spun up at any interval is determined by the power supply output,
the number of drives that are currently in spinning state and spinning up state, the amount of power required to spin
up one drive and the current state of the disk (dead stop state or spinning state).The total power available is guided
by the enclosure design, whereas the drives’ running and spinning power requirements are determined by the disk
drives themselves.
In addition, the time interval delay between spinning up successive groups of drives is drive-dependent because it
takes a finite amount of time for the drives to reach their normal operational spin speed. For the disk with SAS-3
power control enabled, after SXP sends PWR_GRANT to the disk, the disk is deemed to move to spinup state; when
SXP receives PWR_DONE from the disk, firmware considers the disk coming to the normal running/spinning state.

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10.5.2 Example
The best way to show the SSU algorithm with an example. Consider this situation with the following specifications:
• Power supply output is 105 Watts (that is, PTotal)
• Power to spin up one drive is 25 Watts (that is, PSpin)
• Power to keep one drive in normal operating condition is 15 Watts (that is, PRun)
• There are 6 drives, specified in the following priority (highest first) order: 4, 5, 6, 7, 12, 13
• Each drive requires a total of 20 seconds to attain a stable spindle speed
• Six drives are plugged in prior to the expander powering up
• You want to limit the number of drives to be spun up at any interval to 3
• You want to delay the spin-up sequence by 5 seconds from reset
The following table summarizes the power allocation and the number of drives that can be spun-up at each specific
time interval.
Table 10-9. SSU Spin-Up Sequence Example

Time DRun DSpin-num Consumed Available Power Drive (PHY) Notes

(s) Power (W) (W) Spinning Up

0 0 3 0 105 None Expander coming out of a

reset.

5 0 3 0 105 4, 5, 6 Spin up 3 drives.

25 3 2 3x15=45 105-45=60 Watts 7, 12 Spin up 2 drives.

45 5 1 5x15=75 105-75=30 Watts 13 Spin up 1 drive.

65 6 0 6x15=90 105-90=15 None Six drives spinning and

attain operational spindle
speed.

73 5 1 5x15=75 105-75=30 None Drive on PHY 6 removed

85 5 1 5x15=75 105-75=30 None No un-spun drives left.

88 5 1 5x15=75 105-75=30 None Drive on PHY 6 re-inserted.

Spin-up of this PHY does not
occur until the next interval
at t=105 seconds.

105 5 1 5x15=75 105-75=30 6 Spin up drive on PHY 6.

125 6 0 6x15=90 105-90=15 None Drives reach operational

spindle speed.

Notes:
• It is assumed that the disk spinup time is less than the interval time, but if the disk spinup time is not less than
the interval time, firmware can also handle it correctly.
The spin-up sequence starts on the fifth second mark. You spin up three drives as this is what the power equation
permits. Note that the power supply can actually handle four drives spinning up at this instant; however, you have
artificially limited the spin-able drive count to three. There are currently no spinning drives.
At the 25th second mark, the previous three drives have already reached their normal operating condition. We are
currently consuming 45 Watts of power to keep the drives spinning. The remaining 60 Watts enable you to spin up 2
more drives in this interval.
At the 45th second mark you have five drives spinning normally and are consuming a total of 75 Watts of power. The
remaining 30 Watts of power can spin up one more drive.

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By the 65th second mark, the six drives are spinning normally. The total power consumption is 90 Watts, leaving 15
Watts to spare.
Consider the case where you physically remove the drive attached to PHY 6 at the 73-second mark. The available
power and consumed power are immediately recalculated. On the following spin-up interval at t=85s, there is no drive
left to spin up. The remaining five drives are still spinning. You then re-insert the drive at t=88s. The drive is then
spun-up again at the 105th second mark, which is the next valid spin-up timer interval. By the 125th second, the six
drives are spinning normally.
In this particular example, the hot plug events did not occur until after the drives were initially been spun up. The
following example shows the effect of priority ordering when a drive with a higher priority is inserted during the initial
spin-up sequence. The specified PHY list is the same as in the previous example. However, this time the drive on
PHY 6 is not initially attached.
Power Branch PHY List: 4, 5, 6, 7, 12, 13 Initial Drives attached on PHYs: 4, 5, 7, 12, 13 (no drive on PHY 6) Drive
Hot-plugged: Drive on PHY 6 at t=15 seconds
Table 10-10. SSU Spin-Up Sequence with Pre-emption Example

Time DRun DSpin-num Consumed Available Drive (PHY) Notes

(s) Power (W) Power (W) Spinning-Up

0 0 3 0 105 None Expander coming out of a

reset.

5 0 3 0 105 4, 5, 7 Spin up 3 drives

15 N/A N/A N/A N/A N/A Drive inserted on PHY 6

25 3 2 3x15=45 105-45=60 6, 12 Spin up two drives. Inserted

drive on PHY 6, with a
higher priority, pushes drive on
PHY 13 to the next group.
Otherwise, the drive oh PHY
13 would have been spun up
at this interval.

45 5 1 5x15=75 105-75=30 13 Spin up one drive

65 6 0 6x15=90 105-90=15 None Six drives spinning

Notes:
Supposed disk spinup time is less than interval time, but if disk spinup time is not less than interval time, Firmware
can also handle it correctly.

10.5.3 Modes of Operation

The SSU algorithm can be placed in any one of 3 modes as shown in the following table.
Table 10-11. SSU Algorithm Operating Modes

SSU Mode Description

Disabled SSU algorithm is disabled. Disk spin-up operation depends on the default spin-up
configuration settings.

Stand-by The SSU algorithm initializes using the configuration information, but does not actually spin-
up any disk drive.

Enabled The SSU algorithm starts spinning up disk drives based on the power equation and the PHY
list after a programmable initial delay.

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When the SSU algorithm is disabled, the settings in the default spin-up configuration determine the expander’s disk
spin-up operation.
Alternatively, the SSU algorithm can be put in stand-by. In this mode, the algorithm initializes itself with the
configuration parameters but does not actually spin-up any attached disk drives. You must add firmware code
to start the spin-up sequence by calling the function portmgr_ssu_enable(). This puts the algorithm in the
enabled state. The disk spin-up operation occurs either after the initial delay timer expiry or after a call to
portmgr_ssu_enable(), whichever is later.
In the enabled state, the SSU algorithm spins up disk drives based on the power equation(s) and the PHY
configuration.

10.5.4 Drive (PHY) List Specification

As indicated in the previous two examples, the current SSU algorithm implementation in firmware contains more than
just the power equation. You must specify the list of PHYs or drives. Implicit in the PHY list is the drive spin-up
priority. Drives specified at the front of the list have higher priorities than drives at the end of the list. Each power
branch has its own PHY list.
Space is allocated for specifying up to 68 PHYs in the SSU configuration space (within the initialization string)
and is shared between the power branches. Because the power branches may have different PHY list lengths, the
combined PHY list contains a concatenation of the PHY list for each power branch, with the first power branch
starting at offset 0 of the combined list. PHYs can be specified in any order, but not shared between two or more
power branches. See the following table for an example. Only the power branches that are used must be specified.
Slots between two power branches must be used.
Figure 10-12. SSU Power Branch PHY List Example

10.5.5 Drive Hot-Plugging

The implied PHY list priority means that when a drive is inserted that has a higher priority than those in the current
PHY group, spinning up the newly inserted drive takes precedence on the next valid timer interval. The drives in the
current group are also adjusted.

10.5.6 Programming Hooks

To assist in the spin-up synchronization between expanders, several programmable application interface functions
are added to the SSU firmware module. They are listed in the following table.
Table 10-12. Programming Hooks

Hook Name Description

portmgr_spinup_spin_state_overwrit Provides a mechanism for a user to add firmware code to initialize the SSU
e() sequence with a specified list of drives that are currently spinning.

portmgr_spinup_phy_spin_status_ge Returns the spinup information of a specified PHY.

t()

portmgr_spinup_user_callback() Callback mechanism where you can attach additional firmware to handle
situations where the power budget is exceeded while there are still drives left
to be spun up. It is in the SSU module file portmgr_spinup.c

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...........continued
Hook Name Description

portmgr_ssu_enable() These functions can start and stop the SSU algorithm during run-time if
firmware code is added to make use of them.
portmgr_ssu_disable()

portmgr_spinup_is_drive_present() The default return value of this hook is FALSE. If the user wants to skip
the SSU delay for drives that are already spinning, two power variables are
required to be implemented to assist in the power status check. For example:
POWER_STATUS_V: Indicates current power status (1: Power is on; 0:
Power is off).
POWER_EVENT_I: Indicates if power status has changed (1: Changed; 0:
Not changed).
The hook should return FALSE except when current power is on
(POWER_STATUS_V = 1) and the power status has not been changed
(POWER_EVENT_I = 0).

10.5.7 Limitations and Assumptions

The current implementation limitations of the SSU algorithm are as follows:
• Drives cannot be shared between two or more power branches
• Once a drive is disconnected from the expander, and if the hook function
portmgr_spinup_is_drive_present() is not implemented, it is assumed that the drive is spun down
• SPS devices must not have rate snooping enabled when using the SSU algorithm to spin-up disk drives
attached to an SXP 12G expander through SPS devices. The rate snooping feature of the SPS device can
cause the expander to mistakenly identify the presence of a PHY Not Ready event, which can confuse the SSU
algorithm into detecting that that there are fewer drives being spun-up at a given time than there actually are.
Consequently, the algorithm may attempt to spin-up more disk drives than allowed by the power budget at the
next spin-up interval.

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Disk Qualification

11. Disk Qualification

This section describes the firmware function that qualifies the disk drives based on the identification information that
they return.

11.1 What is Disk Qualification?

The Disk Qualification Application (DSQ) selectively prevents access to SAS and/or SATA drives directly attached
to the expander, based on a number of selectable criteria. Drives can be excluded from participating in the system
based on characteristics such as the particular drive manufacturer or version, the SPC-4 standard version it conforms
to, or the supported link rate. A disk drive that passes qualification is reported to initiators (e.g., HBAs) during the
discovery process. Similarly, a drive that fails the disk qualification process has its presence masked and the PHY
on the expander to which it is attached disabled; the HBA never detects the presence of an unqualified drive. Disk
drives that are not supported based on certain customizable criteria are not allowed into the topology, even if they are
physically connected.

11.2 Devices Supporting the Disk Qualification Feature

The disk qualification feature is supported by the SXP 12G devices

11.3 Qualification Metrics

Drives are qualified based on the responses they provide during the initial query when the drive insertion is detected.
For SAS drives, the SCSI INQUIRY response dictates if a drive is qualified. SATA drives are qualified based on their
responses to the ATA IDENTIFY DEVICE command.
At the top level, a user-defined hook is provided to parse the response from the drive and take the appropriate
actions. In the example hook, the PHY connected to the non-qualified device is disabled, thereby removing the
device from the directly attached table. At this point, you must replace the drive with a qualified one, and then
re-enable the PHY through SMP PHY CONTROL. The Disk Qualification application is re-triggered, but this time the
drive is qualified and treated normally.
Possible use models of this feature include:
• You can assemble a list of qualified drives and choose not to interoperate with any others, reducing the risk of
encountering potential issues that were not encountered during the in-house expander qualification process.
• You can assemble a list of non-qualified drives that are known to cause issues and choose to disqualify them
before they can affect the rest of the system.
A SAS drive is qualified after the INQUIRY response is received from the transport layer according to the flowchart
shown in the following figure.
• Note that the attached device must be a disk as indicated by the INQUIRY response fields:
– Peripheral Qualifier (Byte 0, Bits 7:5)= 000b
– Peripheral device type (Byte 0, Bits 4:0)= 0x00 (Direct access block device), or 0x0e (Simplified direct-
access device)
• In the hook, if this criterion is not met, the attached device will pass disk qualification with the reason being
DSQ_REASON_NOT_DRIVE. The PHY is not disabled.

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Disk Qualification

Figure 11-1. SAS Disk Qualification Process

Response received from transport layer

Service response =
Set reason = DSQ_REASON_CMD_INCOMPLETE
TASK COMPLETE?

SCSI status code = Set reason =

GOOD_STATUS? DSQ_REASON_CMD_STATUS_NOT_GOOD

INQUIRY response length >= Set reason =

36 bytes? DSQ_REASON_CMD_INQ_RSP_TOO_SHORT

Peripheral device type = 0

(direct access block device)?

Peripheral device type = 0xE

Set reason = DSQ_REASON_CMD_NOT_DRIVE
(simplified direct access device)?

Peripheral device qualifier = 0?

SCSI version = 3(SPC), 4(SPC-2), or Set reason =

5(SPC-3)? DSQ_REASON_STD_NON_COMPLIANCE

Set reason =
Disable PHY
DSQ_REASON_STD_COMPLIANT

DSQ PASSED DSQ FAILED

Note that when a drive fails the disk qualification process, its attached PHY is disabled by the firmware for all cases
except when the firmware cannot establish a command-response sequence with the drive.
A SATA disk drive is qualified based on its response to the ATA IDENTIFY DEVICE command, as shown in the
following figure.
Figure 11-2. SATA Disk Qualification Process
Response received from transport layer

Service response = Set reason =

SUCCESS? DSQ_REASON _CM D_INCOM PLETE

Device =
ATA device?

Set reason = M ajor version num ber = Set reason =

DSQ _REASON _NOT_DRIVE 0(reserved)? DSQ _REASON _STD_NON_COM PLIANCE

M ajor version num ber = Set reason =

0xFFFF(reserved)? DSQ _REASON _STD_NON_COM PLIANCE

Supports ATA /ATAPI-4?

Y Set reason =
DSQ _REASON _STD_NON_COM PLIANCE

Supports ATA /ATAPI-7?

Set reason =
Disable PHY
DSQ_REASON_STD_COM PLIANT

DSQ PASSED DSQ FAILED

Similar to the SAS disk qualification procedure, if the firmware cannot establish a valid command-response sequence
with the disk drive, it does not disable the PHY even though the qualification process has failed.
Additionally, if the device type reported in the ATA IDENTIFY DEVICE response is not an ATA device, the firmware
reports a PASSED status. When the firmware cannot determine if the attached device is ATA-compliant, there is
not enough information for qualification purposes. The firmware allows the device to pass disk qualification with the
reason code set to DSQ_REASON_NOT_DRIVE. The PHY is not disabled so that when a disk drive is inserted, it
may then be qualified.

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Disk Qualification

Once a PHY is disabled as a result of detecting an unsupported disk drive, the PHY can only be re-enabled by
sending it an SMP PHY CONTROL (RESET) command. It is assumed that the unsupported drive is removed and a
different (compliant) drive is inserted.
DSQ provides a function to enable/disable disk qualification. This function is called by:
• DSQ initialization, to enable/disable disk qualification based on the initialization string setting (all enabled / all
disabled).
• SMP, upon receipt of an SMP PHY CONTROL command with the “PHY OPERATION” field set to the reserved
code 0xaa or 0xab for disabling or enabling DSQ respectively.

11.4 Disk Qualification Status

The disk qualification procedure returns two codes: a pass/fail status code and a reason code. The values assigned
to the codes are shown in the following table. Both codes must be processed to determine if a particular disk drive
passes the qualification process.
Firmware provides a way for users to poll the SXP 12G for disk qualification status and reasons using the proprietary
SMP DSQ Status command.
When DSQ is enabled, the DSQ status and the reason code are retained to a PHY until a new DSQ process is
performed on this PHY.
Table 11-1. Disk Qualification Completion Codes

Code Value Description

Name

passed TRUE Disk drive may be valid; check reason code

FALSE Disk drive does not meet qualification

requirement

reason DSQ_REASON_UNINITIALIZED (0) DSQ has not been performed on this PHY yet.

DSQ_REASON_DISABLED (1) DSQ is disabled on this PHY.

DSQ_REASON_PENDING (2) A new disk qualification request for this PHY is

pending

DSQ_REASON_SATA_AFFILIATED (3) SATA drive is affiliated with another host.

DSQ_REASON_CMD_INCOMPLETE (8) Unable to receive response from disk drive

DSQ_REASON_CMD_STATUS_NOT_GOOD (9) SCSI INQUIRY response is not a

GOOD_STATUS

DSQ_REASON_STD_NON_COMPLIANCE (10) Disk drive does not conform to standard

DSQ_REASON_STD_COMPLIANT (11) Disk drive conforms to standard

DSQ_REASON_NOT_DRIVE (12) Device is not a disk drive

DSQ_REASON_CMD_INQ_RSP_TOO_SHORT (13) Invalid response received; length too short

11.5 Disk Qualification Thread Dependencies

To support the DSQ application, additional modules are added and/or modified to implement the necessary initiator
functionality for querying both SAS and SATA drives. These components include:
• SCSI Initiator Application Layer (SIA)

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Disk Qualification

• Serial ATA Host Application Layer (SAHA)

• SSP Initiator and STP Initiator Transport Layer, an extension of the existing SAS port component
These generic layers are completely decoupled from the Disk Qualification application and can be used in a
standalone fashion.

11.5.1 Command Flow

A disk qualification request originates from the port manager (PORTMGR) module after a drive is successfully
detected and spun-up. The DSQ thread, in turn, makes use of either the SCSI Initiator Application thread to initiate
a SCSI INQUIRY command or the Serial ATA Host Application thread to generate the required ATA command
to the targeted disk drive. The response from the drive is then parsed and filtered by the respective helper
application before the results are returned to the DSQ thread. Using these results, the DSQ thread determines if
the targeted drive passes the qualification process and updates the PORTMGR thread with the status. Graphically,
the dependencies between the various firmware applications and threads are shown in the following figure.
Figure 11-3. Disk Qualification Thread Dependencies

PO RTMG R

disk qualification
request & response

DSQ

SCSI request & response ATA/ATAPI request & response

SIA SAHA

SSP Initiator request & response STP Initiator request & response

SAS Transport

11.6 Customization
The qualification criteria shown in Figure 11-1 and Figure 11-2 ensure that an attached disk drive is compliant with its
associated standard. However, additional qualification criteria, such as drive manufacturer or model number, can be
added. For customers with full access to the firmware source code, the additional criteria can be added by modifying
the file dsq_hook_default.c.
Customers can also customize the DSQ result handler with the result handler hook routine in dsq_hook_default.c.
The default DSQ failure handling method includes the following:
• Firmware disables the PHY attached to the disqualified drive in dsq_hook_disk_qualify_result_hdlr() when the
DSQ result fails with reason code not equal to DSQ_REASON_CMD_INCOMPLETE.
• When the SMP Initiator queries the expander PHY information with SMP Discover/Discover List function,
Firmware hides the PHY attached to the disqualified Drive with “No device attached” in the SMP response.

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Reduced Functionality and Non-I/O Disruptive Soft ...

12. Reduced Functionality and Non-I/O Disruptive Soft Reset

Reduced Functionality (RF) is a SAS-2 feature. According to the SAS-2 specification, the expander has reduced
functionality for a period of time if it experiences reduced performance.
Non-I/O disruptive soft reset (NDSR) is a feature that is not described in the SAS-2 specification. If this feature is
enabled, only a soft reset is needed after upgrading the firmware (or after any other action that requires system
reset). During the soft reset, the I/O transactions passing through the expander are not impacted, and the SSP/SMP
connection request from Host or other Management Application client to the SXP virtual SSP/SMP Port will be reject
with OPEN_REJECT (RETRY) till SXP firmware reboots successfully.
Considering SXP cannot handle SMP/SES command within the reboot time (around 80ms), if the unresponsive time
causes the SMP/SES failure in the Host application, we would suggest enabling NDSR function in SXP so that SXP
firmware notifies Host with Broadcast (Expander) that the SXP enters Reduced Functionality Mode before NDSR
reboot starts.
Optionally, if Host can tolerate the unresponsive time in the SXP virtual SMP/SSP port, you can disable the SXP RF
and NDSR function through Firmware Initialization String ‘RF enable’ and ‘NDSR enable’ fields in Table 8-46.
Figure 12-1. Reduced Functionality and NDSR

In Figure 12-1, “1” means SSP/SMP requests to the expander virtual port, and “2” means I/O traffic that passes
through the expander ports excluding its own virtual port. When doing NDSR reset, the expander only rejects the
SMP/SSP/STP open request to its own virtual PHY, while the request through the expander ports can continue
without any disruption.

12.1 Reduced Functionality (RF)

12.1.1 RF State Machine

RF mode is implemented as in the following state machine. The firmware should periodically invoke
rf_state_machine() to run the state machine for RF mode. The RF state machine consists of the following three
states:
• RF_IDEL: Expander is running in normal mode
• RF_SCHEDULE: Expander is preparing to enter RF mode
• RF_EXECUTE: Expander is running in RF mode
The state transition is shown in the following figure.

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Figure 12-2. Reduced Functionality State Machine

The state machine starts from RF_IDLE state after rf_init() is called, and enters RF_SCHEDULE state when
rf_schedule() is called. After entering RF_SCHEDULE state, the expander device:
1. Sends Broadcast (Expander) on all physical PHYs to indicate that it must have reduced functionality for a
period of time.
2. Initializes the initial_time_to_rf timer to the value indicated by the INITIAL REDUCED FUNCTIONALITY field in
the initialization string, and starts the timer.
3. After initial_time_to_rf timer expires, the expander enters RF_EXECUTE state, disables PACK, initializes
the max_rf_time timer to the value indicated by the MAXIMUM REDUCED FUNCTIONALITY TIME field in
initialization string, and starts the timer. All SSP/SMP/STP traffic to the virtual PHY is now responded with
OPEN REJECT(RETRY).
4. After max_rf_time timer expires, the expander reenters RF_IDLE state, enables PACK, and originates a
Broadcast (Change) on each expander PHY. SSP/SMP/STP traffic now can normally go to the virtual PHY.
The interface for triggering Expander to enter the RF mode is defined as the API rf_schedule()as follows.

Prototype BOOL rf_schedule(NDSR_RF_MODE_ENUM mode)

Inputs Mode RF or NDSR mode

Outputs None.

Returns TRUE Scheduled successfully

FALSE It is already scheduled

RF mode is not explicitly used in alpha release by default. To enter RF mode, application can invoke this routine.
When rf_schedule(NDSR_RF_NDSR_MODE) is called, NDSR is scheduled.

12.1.2 SMP Initiator

After one PHY receives a Broadcast (Expander) primitive, the SXP issues an SMP REPORT GENERAL to its
neighbor expander that is attached to the PHY in the sub-topology. The SAS-2 Topology Discovery Master identifies
whether this expander is in RFmode or not. If the neighbor expander is in RF mode, the expander initializes the RF

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delay time with the value of TIME TO REDUCED FUNCTIONALITY field, and initializes the RF max waiting time with
the value of MAXIMUM REDUCED FUNCTIONALITY TIME field in the response frame of SMP REPORT GENERAL.
Before RF delay time expires, SSP Initiator in host should manage to terminate any SSP traffic with the neighbor
Expander. After the timer for RF delay time expires, the expander starts the max waiting timer until the max waiting
timer expires. During the waiting period, the SXP will delay to process PHY events in the wide port until the max wait
timer expires or a Broadcast (Change) is received in the wide port to the neighbor expander.
Once the SMP initiator receives a Broadcast (Change) from its neighbor expander, which means that the neighbor
expander has ended the RF mode and has come back to full functionality, the SMP initiator can immediately trigger a
new topology discovery process for its neighbor SXP.

12.2 Non-I/O Disruptive Soft Reset (NDSR)

Firmware in the expander needs to be updated from time to time. After upgrading, a reset is needed to re-load
the new firmware. Normally it requires that all I/Os in the system be stopped during the reset process. The NDSR
requires only a soft reset after upgrading and I/O transactions routed through the expander will not be impacted
during the reset.

12.2.1 Overview
The NDSR mechanism is similar to the one provided in RF mode. As a result, the NDSR uses the same state
machine and the same rf_schedule API from RF to enter into NDSR mode. The NDSR process can be separated
into three steps:
1. After the expander receives a soft reset command from the SES string out page or command server, the
expander sends NDSR event notification Broadcast (Expander) to all initiators in the SAS domain before a soft
reset is triggered in the register if NDSR enable field is set in initialization string. It then starts the first timer
for NDSR delay. The timeout value is the same one as configured for reduced functionality, the initial reduced
functionality timer.
2. During the NDSR delay interval, the expander still functions normally. After the delay ends, the firmware saves
some necessary information about the running-time environment and triggers the reset register. It then initiates
the NDSR reset process. Host initiators should terminate the SSP/SMP transactions to this virtual expander
port.
3. The expander responds to any SSP/SMP request to the expander’s virtual port with OPEN_REJECT (RETRY)
if host sends a new request. The firmware then is reloaded and re-initialized. The firmware does not re-
initialize the expander routing table or its hardware registers related to ECMR, SXL, and SSPL. This ensures
that the I/O traffics that go through the expander ports (except for the expander’s own virtual port) are not
disrupted. The firmware then sends Broadcast (Change) and goes again into normal state.
The following behavior is expected during the NDSR process:
• The routing table and its hardware registers related to ECMR, MABC, SXL and SSPL are not re-initialized, so
there is no link reset or hard reset for each PHY after soft reset.
• Existing connections through ECMR are not disrupted and new connections through ECMR can be created.
• Any type of broadcast primitive is not forwarded.
• Any SSP/SMP request to the expander virtual port is responded to with an OPEN_REJECT (RETRY) primitive.
• The hardware event indications are kept in the registers.
• The firmware uses the snapshot of the state/configuration that it took prior to the reset to bring it back up in the
same state.

12.2.2 NDSR Process

12.2.2.1 Bootloader Process

The bootloader checks the last reset reason in the hardware register to determine if the last reset was a soft reset.
If it was, the POST test is skipped to ensure the saved data section is not cleared, and the main firmware is loaded
directly.

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12.2.2.2 Firmware Load Process

The main firmware validates the saved data section, and evaluates the reset type before it initializes the hardware
during boot-up. If the reset is a soft reset, the firmware skips the hardware initialization including ECMR, MABC,
SSPL and SXL, and loads the necessary data from the reserved space in RAM so that the system can keep running
with the previous configuration and settings.
A handshake mechanism was added for EMIP firmware updates. The SXP 12G SDK first loads the new EMIP
firmware to the alternative partition of the memory. It notifies the EMIP firmware that is currently running, to move to
a known good state. EMIP is reset to jump to the updated EMIP firmware for executing. The firmware then sends a
Broadcast (Change).
If the saved data fails CRC checking, firmware cannot load the data as it may be incorrect. Currently, a
PMCFW_ASSERT is called to enter a minimal system so that the outstanding I/O traffic can continue, while the
host can still have an out-of-band method to control the expander.

12.2.2.3 Soft Reset Process

The soft reset uses the same mechanism as reduced functionality, as shown in the following figure except that there
is no second timer (max waiting time) for the period of time not responding to an open request with OPEN_REJECT
(RETRY). Once the reset process completes, firmware immediately sends out a Broadcast (Change) to announce
that it is now in normal state. The MAXIMUM REDUCED FUNCTIONALITY TIME Field in the initialization string is
indicated in the SMP REPORT GENERAL response and indicates how much time is allowed for a soft reset. This
value must be a little longer than the actual soft reset time, which makes host estimate the reduced functionality
duration. In the SXP 12G NDSR soft reset phase, the firmware reboot time is greatly reduced compared with the one
when doing hard reset.
Before the initial delay timer expires, the expander waits to receive the other SMP initiators (including the expander
and host) to issue an SMP REPORT GENERAL request. The reduced functionality bit is set in the REPORT
GENERAL response frame and the host should stop an open request to that expander’s virtual PHY after it detects
which expander is in RF or NDSR mode.
After the delay timer expires, firmware disables the pack to reject new SMP/SSP traffic to its virtual PHY, and global
interrupt is disabled, so from then on, no new events can be processed. Firmware disables the TWI slaves, saves the
necessary data to the reserved space, and triggers a soft reset to the MIPS core.
Figure 12-3. NDSR Soft Reset Process

12.2.2.4 Saved Data

In the SXP 12G firmware SDK, most of the necessary data that needs to be kept is now put in a fixed space,
starting from the address of imem_mem2_cached, which can be modified in the link script. For example, logical
route table data, ECMR hash management data, zoning data and so on, are put into a special section, called
ndsr_bss0, ndsr_bss1 and ndsr_bss_last section. The locations in RAM of these sections are fixed, starting from
imem_mem2_cached. After a soft reset, the firmware can still use the data from this location. The data has CRC
protection.

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If more data needs to be kept for NDSR in application code, the data can be added at the end of ndsr_data
instruction, before the ndsr_data_last_addr element. The start address of imem_mem2_cached may need be
adjusted to accommodate more data.
Figure 12-4. NDSR Save Data Layout

12.2.2.5 Initialization String Fields Classification

When the SXP 12G initialization string is updated, a reset is required to allow the new initialization setting to take
effect. However, not all the fields updated in the initialization string are required for a hard reset. If only specific fields
are updated, a soft reset is enough. The following table describes when a hard reset is required after the settings are
changed.
Note: If the value of the initialization string fields that require for a hard reset is changed and a soft reset is triggered
instead of a hard reset, some abnormal behavior might occur. However, in some cases after a soft reset, changes
for some fields in those blocks that are not related to the hardware settings also might take effect. Therefore, it is
recommended that if fields that require a hard reset are changed, a hard reset is triggered.

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Table 12-1. Init String Fields Classification

Need Hard Reset

Byte Offset Allocation to take effect

0x0000 – 0x0036 Device Identification Configuration Block No

0x0037 – 0x0050 Device Addressing Configuration Block Yes

0x0051 – 0x00FF Topology Discovery Configuration Block No

0x0100 – 0x01FF PHY & SGPIO Mapping Configuration Block No

0x0200 – 0x112F PHY Configuration Block Yes

0x1130 – 0x127F PHY Connector Configuration Block Yes

0x1280 – 0x129F Additional PHY Event Source Configuration Block No

0x12A0 – 0x131F SGPIO Configuration Block No

0x1320 – 0x132F CMDSVR UART and SPS Configuration and TWI Blocks No

0x1330 – 0x134F GPIO Configuration Block No

0x1350 - 0x135F Pin Drive Strength Ctrl Block No

0x1360 – 0x13DF TCP/IP Stack Configuration Block No

0x13E0 - 0x13FF EPOW Configuration Block No

0x1400 - 0x14BF Error Logging Configuration No

0x14C0 - 0x14DF WOL/WOS Configuration Block No

0x14E0 – 0x182F Reserved for new features

0x1830 – 0x186F Operating System Configuration Block No

0x1870 – 0x18AF Protocol Configuration Block No

0x18B0 – 0x190F EMA Configuration Block No

0x1910 – 0x191F Redundant Virtual SSP Link Configuration Block No

0x1920 – 0x192F Disk Qualification SIA and SAHA Configuration Block No

0x1930 – 0x193F Disk Spin-Up Configuration Block Yes

0x1940 – 0x19DF SSU Configuration Block Yes

0x19E0 – 0x19EF Non-I/O Disruptive Soft Reset (NDSR) Configuration Block No

0x19F0 – 0x1A3F Zoning Configuration Block Yes

0x1A40 – 0x1A8F Zoning PHY Group ID Mapping Configuration Block Yes

0x1A90 – 0x1ACF Zone Manager Password and Saving Support Configuration Block Yes

0x1AD0 – 0x1AFF Virtual SSP/SMP Zoning Configuration Block Yes

0x1B00 – 0x2BFF Zoning Permission Table Configuration Block Yes

0x2C00 – 0x33FF Reserved (Customer proprietary extension block – 2 Kbytes)

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...........continued
Need Hard Reset
Byte Offset Allocation to take effect

0x3400 – 0x37FF Reserved (Microchip extension block – 1016 bytes)

0x3800 – 0x3FF7 Patch Table Configuration Block No

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Zoning

13. Zoning
The SXP 12G zoning implementation is compliant with the SAS 2.1/3.0 specification for port-based zoning. The
SXP 12G zoning capability restricts communication between devices in different zoned domains. In zoning mode,
certain PHYs are marked as being in a zoned domain or not. Zones are based on an access permission table that
determines the access permissions between different groups of devices. Groups that have access to each other
constitute a zone.
The device supports up to 256 groups. The SMP commands necessary to program group IDs in-band and setup the
access permission table are also supported. Legacy expanders that do not support zoning can be cascaded outside
the zoning fabric boundary and inherit the group assignment of the PHY to which it is attached. The device zoning is
designed to be transparent to the end devices and legacy expanders.
Other supported security features include detection of SAS address spoofing on the OPEN address frames and
broadcast storm prevention.

13.1 What is Zoning?

Zoning is a feature that lets the fabric segregate traffic among the various devices within the fabric. This need arises
as SAS is gaining interest for use in small storage area networks (SAN) and requires features that are currently
afforded by Fibre Channel and Ethernet’s virtual LAN.
The port-based zoning mechanism is simply an aggregation of some number of PHYs into a group with a particular
set of data routing and topology management routing attributes. A zone is determined by the groups that comprise
it and the access privileges between the groups. A zoning domain’s boundary is marked by PHYs with an INSIDE
ZPSDS (zoned portion of a service delivery subsystem) attribute.
Figure 13-1. Zoning Domain

A physical domain may contain several zones. Figure 13-1 shows an example of this. If group 11 has access to group
13, then group 11 and 13 comprise one virtual zone. Similarly, if group 12 and 14 can access one another, these two
groups comprise a separate virtual zone that share the same physical topology with group 11 and 13. Note that the
traffic between the two zones does not cross.

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Zoning

Enabling zoning in a particular application provides the following advantages:

• Data separation – Zoning allows the separation of data and management traffic between mutually-exclusive
virtual domains to ensure some level of privacy and transparency. This is necessary in a SAN environment
where mutually-exclusive sets of users and disk storage data pass through the same hardware. There is a
special need to ensure that traffic is properly constrained within its designated domain and that management
traffic from one domain does not affect the performance of another domain.
• Cost savings – There is no need for a separate hardware setup to isolate customer data for privacy concerns, as
the zoning feature set allows for parallel virtual topologies within one physical topology. The same firmware and
configuration can be used in both zoning and non-zoning environments, thus reducing variation in inventory and
maintenance.
• Flexibility – The PM73206 firmware permits the system administrator to dynamically allocate resources between
different virtual zones. Resources can be re-allocated from one virtual zone to another according to usage
requirements. The SXP 12G can also be reconfigured to a degenerated state where there is only one zone (that
is, SAS 1.1 topology). In essence, the expander operates like a normal non-zoning-capable device.
The SXP 12G devices and their associated PM73206 firmware component implement many additional functions to
support the zoning features. These features are described in further detail in the next sections.

13.2 Zone PHY Information

To support the port-based zoning, the zone PHY information is defined in SAS-3. The zone PHY information consists
of the fields described in the table that follows. See [4], Section 4.9.3 for more detail on zone PHY information.
Table 13-1. Zone PHY Information

Recommended
Bit/Field Description
Default

INSIDE ZPSDS Indicates if the PHY is inside or on the boundary of a ZPSDS N/A See Note

REQUESTED INSIDE
Used to establish the boundary of the ZPSDS 0
ZPSDS

INSIDE ZPSDS Used to determine the value of the INSIDE ZPSDS bit after a
0
PERSISTENT link reset sequence

ZONE GROUP Used to determine the zone group of the PHY after a link reset
0
PERSISTENT sequence if the INSIDE ZPSDS bit is set to zero

ZONE GROUP The zone group to which the PHY belongs 00h

Note: The INSIDE ZPSDS bit is determined from the values exchanged during the link reset sequence.

The INSIDE ZPSDS bit indicates if the PHY is inside or on the boundary of a ZPSDS. The REQUESTED INSIDE
ZPSDS bit determines the values of zone PHY information fields after a link reset sequence. See [4], Section 4.9.4
for detail.
The INSIDE ZPSDS PERSISTENT bit determines the value of the INSIDE ZPSDS bit after a link reset sequence.
See [4], Section 4.9.4 for detail.
The ZONE GROUP PERSISTENT bit determines the method of determining the zone group of the PHY after a link
reset. See [4], Section 4.9.4 for detail.
The zone group field contains the zone group to which the PHY belongs. See [4], Section 4.9.3 for detail.
Note
• The method of detecting that a new SATA device has been inserted is outside the scope of the SPL standard
and firmware does not implement it.

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Zoning

13.3 Access Permissions

A major part of the zoning feature set is its dynamic group access permission. The access permission is a matrix
that determines if one or more groups have access privilege to another group or set of groups, and vice-versa. If the
access privilege between two groups, say X and Y, is denoted as P[X,Y], then the privilege definition is as shown in
the following table.
Table 13-2. Zoning Access Permission Definition

P[X,Y] Access Permission

0 Device members in Group X cannot access those in Group Y

1 Device members in Group X may access those in Group Y

The permission is symmetrical. That is, P[X,Y] is the same as P[Y,X]. Members within the same group may or may
not be given permission to access one another. The following permissions are also valid:
• P[X,X] = 0
• P[X,X] = 1
Extending this concept further to encompass all 256 possible groups’ yields the permission matrix.
Table 13-3. Zone Permission Table

Destination Source Zone Group (that is, s)

Zone Group 0 1 0 4 to 7 0
(that is, d)

0 0 1 0 0 0

1 1 1 1 1 1

2 to 3 0 1 ZP[s = 2 to 3, d = 2 to 3] Reserved ZP[s = 8 to (z-1), d = 2 to 3]

4 to 7 0 1 Reserved Reserved Reserved

8 to (z-1) 0 1 ZP[s = 2 to 3, d = 8 to (z-1)] Reserved ZP[s = 8 to (z-1), d = 8 to (z-1)]

Note:
1. Shading identifies configurable zone groups.
2. All reserved ZP bits must be set to zero (for example, bits ZP[4 to 7, 4 to (z-1)] are set to zero).
3. The number of zone groups (that is, z) is reported in NUMBER OF ZONE GROUPS field in the REPORT
GENERAL response (see [4] section, 10.4.3.4).

Note: Group 0 cannot access any other group other than Group 1. On the other hand, Group 1 has visibility to every
group. Group 4 to 7 are reserved. PHYs in all the left zone groups have access to PHYs in the zone groups indicated
by the zone permission table. Group 2 and Group 3 are defined as special groups for management. See [4], Section
4.9.3.2 for detail.

13.4 INSIDE ZPSDS versus Not INSIDE ZPSDS

A PHY can be classified as inside ZPSDS or not inside ZPSDS. The INSIDE ZPSDS property of a PHY is determined
from the values exchanged during the link reset sequence. If the INSIDE ZPSDS is set to 1 after the link reset
sequence, the PHY resides within the zoning boundary, and the PHY’s zone group ID is also set to 1.PHYs with
INSIDE ZPSDS set to 1 also support additional fields within the IDENTIFY and OPEN ADDRESS frames to control
access permissions.

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PHYs with INSIDE ZPSDS set to 0 delimit the zoning boundary and to connect to legacy expanders and end devices.
See [4], Section 4.9 for detail.

13.5 Source Check

As a measure against device SAS address spoofing, each PHY can be validated to ensure that the device’s SAS
address in the IDENTIFY frame matches the address it uses in the OPEN ADDRESS frames. If the SAS addresses
do not match, the OPEN_REQUEST is denied. This feature can be turned on or off on a per-PHY basis. By default,
source check is turned off.

13.6 Broadcast Processing

In a zoning expander device with zoning enabled, the firmware processes Broadcast as defined in SAS-2.
The BPP determines the source zone group(s) of the Broadcast as follows:
• If the BPP receives a Broadcast Event Notify request from an expander logical PHY (that is, a zoning expander
logical PHY received a BROADCAST), then the Broadcast has a single source zone group set to the zone group
of that expander PHY; or
• If the BPP receives a message from the management device server indicating that the management device
server received an SMP ZONED BROADCAST request from an SMP initiator port that has access to zone
group 3, then the Broadcast has each of the source zone groups specified in the SMP ZONED BROADCAST
request.
The BPP forwards the Broadcast to each expander port other than the one on which the Broadcast was received
(that is, the expander port that received the BROADCAST or SMP ZONED BROADCAST request) if:
• The Broadcast is not a Broadcast (Zone Activate) and any of the source zone groups have access to the zone
group of the expander port;
• The Broadcast is a Broadcast (Zone Activate), the BPP is in a locked zoning expander device, the INSIDE
ZPSDS bit is set to one, and the source zone group has access to zone group 2.
• The Broadcast is a Broadcast (Zone Activate), the BPP is not in a locked zoning expander device, and any of
the source zone groups have access to the zone group of the expander port.
To forward a Broadcast to an expander port:
• If the expander port’s INSIDE ZPSDS bit is set to one, the BPP requests that the SMP initiator port establish
a connection on one PHY in the expander port to the SMP target port of the attached expander device and
transmits an SMP ZONED BROADCAST request specifying the source zone group(s).
• If the expander port’s INSIDE ZPSDS bit is set to zero, the BPP sends a Transmit Broadcast message to one
PHY in the expander port, causing it to transmit a BROADCAST.
See [4] Section 4.9.5 for detail.

13.7 Zone Manager

A ZPSDS has a zone manager responsible for its configuration. The zone manager may have access to an end
device with a SAS port that has a zone group (see [4], Section 4.9.3.2) that can access zone group 2, or may have
access to one or more zoning expander devices through providing correct zone manager password.
Physical presence detection is another mechanism that allows management access to a ZPSDS defined in SAS-2.
The SXP 12G currently does not support this feature.
The zone manager can configure the ZPSDS on the fly through SMP functions for zoning. See Section 13.10 Zoning
Configuration On The Fly for more about zone configuration.
See [4], Section 4.9 for detail on the Zone Manager.

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13.8 Zone Information Type

In a zoning expander device, the zone information mainly consists of the zoning enable/disable status, zone PHY
information for each PHY, zone permission table and the zone manager password.
The firmware must maintain the current values of all zone information. For zoning enable/disable status, zone PHY
information, and the zone permission table, the firmware must also maintain the shadow values. There is no shadow
value for the zone manager password.
If saving support is enabled, the firmware must also maintain the saved value of the zone information selectively.
That means support or lack of support for saved values for one setting does not imply support or lack of support for
saved values for any other setting.
The zone manger can access the ZPSDS by being attached to an end device with a SAS port whose zone group has
access to zone group 2, or being directly attached to the expander devices in the ZPSDS through sideband interface.
See [4], Section 4.9.1 for more detail.
The default values of the zone information are defined in initialization string. See Table 13-4.

13.9 Zoning Configuration after System Power-on

After system power-on, the firmware configures the zoning functionality for the expander device according to the
initialization string settings.
The Zone Information Load bit in the initialization string determines the source of zone information for zoning
configuration. If the zone information load is set to 0, the expander device sets the current value to the default value
no matter if there are any saved values supported. If the zone information load is set to 1, the expander device sets
the current value to the saved value, if any, or the default value, if there is no saved value supported. If the firmware
detects an error (that is, CRC error) during the loading of the saved values, the default values are loaded instead.
You can get specific detail of the default values from the initialization string settings. However, the following table
briefly summarizes the default out-of-the-box configuration.
Table 13-4. Default Zoning Configuration

Element Default Configuration

Zone Permission Table Group 0 can access only group 1, that is, P[0, 1] = 1. Group 1 can access all other
groups, that is, P[1, 0 .. 255] = 1. The remaining permissions are all set to 0.

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...........continued
Element Default Configuration

Zone PHY Information PHY 0 to 7 are with REQUESTED INSIDE ZPSDS bit, INSIDE ZPSDS PERSISTENT
bit, and GROUP ID PERSISTENT bit set to 1, and Zone Group ID set to 1; The virtual
SSP/SMP port is assigned to group 1. The remaining PHYs are with REQUESTED
INSIDE ZPSDS bit, INSIDE ZPSDS PERSISTENT bit, and GROUP ID PERSISTENT
bit set to 0.
PHY 8 to 11 Zone Group ID set to 0;
PHY 12 to 15 Zone Group ID set to 8;
PHY 16 to 19 Zone Group ID set to 9;
PHY 20 to 23 Zone Group ID set to 10;
PHY 24 to 27 Zone Group ID set to 11;
PHY 28 to 31 Zone Group ID set to 12;
PHY 32 to 35 Zone Group ID set to 13;
PHY 36 to 39 Zone Group ID set to 14;
PHY 40 to 43 Zone Group ID set to 15;
PHY 44 to 47 Zone Group ID set to 16;
PHY 48 to 51 Zone Group ID set to 17;
PHY 52 to 55 Zone Group ID set to 18;
PHY 56 to 59 Zone Group ID set to 19;
PHY 60 to 63 Zone Group ID set to 20;
PHY 64 to 67 Zone Group ID set to 21;

Enable/Disable Zoning Disabled

Status

Zone Information Saved Saved value support disabled for zoning enable/disable status, zone PHY information
Value Support and Zone for each PHY, zone permission table and zone manager password;
Information Load
After power on, the expander device set the current value to the saved value, if any, or
the default value, if there is no saved value supported.

Zone Manager Password ZERO. Well-known value that provides access to any zone manager
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000

Source check This feature is disabled for all PHYs.

13.10 Zoning Configuration On The Fly

Zoning expander devices implement a lock to coordinate zoning configuration by zone manager(s).
There are four steps in the zone configuration process:
• Lock (see [4], Section 4.9.6.2)
• Load (see [4], Section 4.9.6.3)
• Activate (see [4], Section 4.9.6.4)
• Unlock (see [4], Section 4.9.6.5).

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The management device server in a zoning expander device only accepts SMP zone configuration function requests,
SMP ZONE ACTIVATE requests, and SMP ZONE UNLOCK requests while it is locked, and only accepts SMP zone
configuration function requests from the zone manager that locked the zoning expander device (that is, the active
zone manager). SMP zone configuration functions change zoning expander shadow values. When changes are
complete, the zone manager activates the changes and the zoning expander device sets the zoning expander current
values equal to the zoning expander shadow values. The zone manager then unlocks the zoning expander devices.
For a ZPSDS to function correctly, all zoning expander devices within the ZPSDS are required to have identical
values in their zone permission tables. To change zone permission tables, a zone manager device locks all zoning
expander devices in a ZPSDS.
To change zone PHY information, a zone manager locks only the zoning expander devices containing the PHYs to be
changed.
If the zone lock inactivity timer expires, then the zoning expander device performs the unlock step. The zoning
expander device is unlocked and the zoning expander shadow values are not activated. If the zone lock inactivity
timer is active, and an NDSR[12.2 Non-I/O Disruptive Soft Reset (NDSR)] is expected to be triggered, unlock the
zoning expander device first before the triggering.
For more detail about zoning configuration, see [4], Section 4.9.6 and [4], Section 10.4.3.

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14. Protocol Stack Library

This section describes the library of protocol stacks provided by the PM73206_04 firmware. The protocol stack library
is intended to be used as-is in the development of your EMA. In most cases, you do not need to modify these
functions.
The following figure shows the SAS protocol layers involved in communication with the virtual SMP and SSP ports
implemented by the PM73206_04 firmware in the expander device. The PM73206_04 firmware implements the
SSP and SMP transport layer, SAS port layer and portions of the SSP and SMP link layers, through the SAS Port
component.
Figure 14-1. SAS Protocol Layers
Im plem ented in Firm ware

Im plem ented in Hardware

SES
SES
Com ponent SM P
STE Com ponent
Com ponent

SCSI application layer Managem ent application layer

SAS Port
SSP transport layer Com ponent SMP transport layer

SAS port layer

SSP link layer SMP link layer

SAS link layer

SXL

SAS phy layer PHY

SAS physical layer SERDES

The following tables outline the components of the Protocol Stack Library that are included in the PM73206_04
firmware.
Table 14-1. Protocol Stack Library Components—SES/SCSI

Layer Component

Enclosure Management Application

Application
SCSI Enclosure Services Protocol Implementation

SXP-specific SES pages

SCSI Target Emulator SCSI Protocol (SPC) Protocol Implementation

SAS-specific SCSI mode pages

Serial SCSI Protocol SSP Target

(SSP) Transport Layer
SSP Initiator

Table 14-2. Protocol Stack Library Components—SMP

Layer Component

SMP Application Layer SMP Initiator

SMP target

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...........continued
Layer Component

SMP Transport Layer SMP Initiator

Table 14-3. Protocol Stack Library Components—Port Layer

Layer Component

SSP/SMP Port Layer Port Layer

14.1 SAS Port Component

This section describes the high-level architectural design of the SAS Port Component, a SAS 1.1 compliant SAS
Port that consists of a single PHY (narrow port). The SAS Port Component is used by the following applications to
interface with the SAS Service Delivery Subsystem.
• SMP Initiator Applications such as an SMP Topology Master
• SMP Target Applications
• SSP Initiator Applications such as SIA and SAHA in support of the Disk Qualification feature
• SSP Target Applications such as a SCSI application performing enclosure services
The following figure shows the sub-components that make up the SAS Port component and their interaction.
Figure 14-2. SAS Port Component Architecture

SIA (SCSI) SAHA SMP SCSI

Initiator Initiator Initiator Target
Application Application Application Application

SMP
Target
Application

Functional
Interface

SAS Port Com m on

Transport Layer O bject
Com ponent (SAS 1.1: ST_T, MT_IP, MT_TP)
Fram ework
(O S, buffer
pools, etc)

Port Layer O bject

(SAS 1.1: PL_O C, PL_PM, SSP, SMP)

High Priority
Event Q ueue

PACK_LT Device Driver O bject

(SAS 1.1: Interface to SL,XL)

SAS Port Thread

As shown in the previous diagram, the SMP Initiator, SSP Target, SSP Initiator, and STP Initiator applications send
ingress Serial Management Protocol and SCSI Transport Protocol Messages to the Transport Layer which converts
the requests into SMP or SSP/STP SAS frames. The SAS frames are sent to the Port Layer where they are queued
for transmission on a specific connection. The Port Layer opens the required connections and transmits the queued
frames.
In the other direction, the SAS connections in the Port Layer are opened remotely by other SAS endpoints in
the network. Received egress frames are passed from the Port Layer to the Transport Layer where they are

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assembled into SAS Management Protocol or SCSI Transport Protocol messages for transmission to their respective
applications.
The SMP Target application operates within the SAS Port thread. When an SMP Request frame is received by
the Port Layer, a blocking functional call is made to the SMP Target Application for processing. The SMP Target
application returns an SMP Response frame for transmission back into the connection. The Port Layer effectively
blocks while the SMP Target application is processing an SMP request and the SAS Port remains in the connected
state throughout the entire process.

14.2 SCSI Enclosure Services (SES)

This section describes the library of protocol stacks provided by the firmware. The protocol stack library is intended to
be used as-is in the development of your EMA. In most cases (with the exception of the SES module which is usually
very application specific), you will not need to modify these functions.

14.2.1 SCSI Enclosure Services (SES)

SCSI enclosure services are the services that establish the mechanical environment, electrical environment, and
external indicators and controls for the proper operation and maintenance of devices within an enclosure. The SES
data is transported ‘in-band’ to and from the application client.
The firmware provides a set of standard SES pages that the EMA uses as input to direct the configuration and
monitoring of peripheral devices. It also defines Microchip vendor-specific pages for monitoring the device, and
provides for vendor-specific pages that you may define as needed for your system.
The content of the standard pages is well defined; however, which fields on each page are supported, is application
dependent and needs to be determined specifically on a case-by-case basis.
The standard SES pages give the EMA control over peripheral devices. There are two basic types of SES pages:
control pages that configure the peripherals, and status pages that monitor the peripherals.
The SES pages are accessed through the SCSI commands SEND DIAGNOSTICS (control pages) and RECEIVE
DIAGNOSTIC RESULTS (status pages). Note that a particular page code may be used for both a control page
and a status page; which page is actually accessed depends on whether the page code is sent in the RETRIEVE
DIAGNOSTIC RESULTS command or the SEND DIAGNOSTIC command.
If there is any disagreement between this manual and the SES standards, the SES standards should take
precedence.

14.2.2 SES Implementation on the SEP

In order to add new SES pages to the existing code base and to understand the limitations of the SES module, a
quick overview on how SES is implemented and how it ties together with the DBS database module and the rest of
the enclosure management is required.
Two groups of SES pages can be differentiated:
• SES pages that need to exchange data with the rest of the enclosure management application. Both control and
status pages can belong to this group. For instance, when the request for data for a status page request cannot
be immediately serviced, as would be the case when accessing slow sensor elements, the data is periodically
stored in the database and ready to be retrieved when the SES request comes in. Vice versa, when incoming
control information cannot be immediately processed or needs to be stored until updated, the SES page data
would store its payload in the DBS database.
• SES pages that do not need to exchange data with the rest of the enclosure management application. This can
be static SES status pages that are defined at compile time, or SES control pages that can be immediately
acted upon and do not need to retain the received data. This group of SES pages could also utilize the
database; however to minimize RAM space on the device and to simplify the design, the use of the database
can be avoided.
The current SES implementation fully supports the latter type of SES pages; the former type is supported as far as
the data transfer to and from the database goes.

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14.2.3 Supported SES Pages and Limitations

The SES module along with the EMA example supplied is intended to provide a basic framework that needs to be
expanded depending on the particular needs of your enclosure. Some of the pages provided are fully implemented,
while others only store and retrieve data on the expander device but do not act upon the data due to hardware
limitations on the evaluation Kit. The following table summarizes the supported SES pages and the extent to which
they are implemented.
The following table summarizes supported SES pages. If the page code in an enclosure service request command
does not appear in the list, the SXP responds to the request with sense code set as UNSUPPORTED ENCLOSURE
FUNCTION.
Table 14-4. SES Pages

Page Code Page Name Control/Status

0x0 Supported Diagnostic Pages diagnostic page Status

0x1 Configuration diagnostic page Status

0x2 Enclosure Control diagnostic page Control

Enclosure Status diagnostic page Status

0x3 Help Text diagnostic page Status

0x4 String Out diagnostic page Control

String In diagnostic page Status

0x5 Threshold Out diagnostic page Control

Threshold In diagnostic page Status

0x7 Element Descriptor diagnostic page Status

0xA Additional Element Status diagnostic page Status

0xD Supported SES Diagnostic Pages diagnostic page Status

0xE Download Microcode Control diagnostic page Control

Download Microcode Status diagnostic page Status

0xF Subenclosure Nickname Control diagnostic page Control

Subenclosure Nickname Status diagnostic page Status

0x3F Protocol-Specific Diagnostics (SAS) Control

0x80 EMM System Log Page Status

0x81 SES Delay Test page Control

0x82 SXP Firmware Status Page Status

0x83 PHY Analog Setting Control Page Control

PHY Analog Setting Status Page Status

0x84 Vhist Capture Control Page Control

Vhist Capture Status Page Status

0x86 Port Mirroring Control Page Control

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...........continued
Page Code Page Name Control/Status

Port Mirroring Status Page Status

0x90 SXP Diagnostics Control Page Control

SXP Diagnostics Status Page Status

0x91 FWDL Partition Control Page Control

FWDL Partition Status Page Status

0xF0 SXP TWIPT Command Send Control

SXP TWIPT Command Receive Status

0xF1 SXP TWIPT Configuration Send Control

SXP TWIPT Configuration Receive Status

0xF2 Reserved Control

Reserved Status

0xF3 SSSF PHY Configuration Page Control

SSSF PHY Status Page Status

0xF4 Fatal Error Event Log Control Page Control

Fatal Error Event Log Retrieval Page Status

14.2.3.1 Supported Diagnostics Page (0x00)

This page allows the host application to determine what page types are supported by the expander device. This
page contains a list of all diagnostic page codes implemented by the enclosure services device in ascending order
beginning with PAGE CODE 0x00.
Table 14-5. Supported Diagnostics Page Format

Component Name Bytes Field Name

Page Header 0 Page Code (0x00)

1 Reserved (0x00)

2-3 (MSB)
Page Length (n-3) (LSB)

Supported Pages 4-n Supported Pages – a list of page codes

14.2.3.2 Configuration Diagnostic Page (0x01)

The Configuration diagnostic page describes every item that could possibly be ‘contained’ in an enclosure. Every
item that has been listed in the Configuration diagnostic page has a corresponding entry in the Enclosure Status
diagnostic and Enclosure Control diagnostic pages, as well as the SES threshold pages.
The Enclosure Descriptor section of the Configuration diagnostic page contains a number of fields that require
description. These fields are designed to allow the enclosure services processor to communicate information to the
host application regarding the state of the enclosure as a whole.

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Table 14-6. Configuration Diagnostic Page Format

Component Name Bytes Field Name

Page Header 0 Page Code (0x01)

1 Number of sub enclosures (0x00)

2-3 (MSB)
Page Length (n-3) (LSB)

Generation Code 4-7 Generation Code (0x00 0x00 0x00 0x00)

Enclosure Descriptor Header 8 Reserved # of Enclosure

Services Processes

9 Sub-Enclosure ID (0x00)

10 Num. Element Types (T)

11 Enclosure Descriptor Len (m)

Enclosure Descriptor 12-19 Enclosure Logical Identifier

20-27 Enclosure Vendor Identification

28-43 Product Identification

44-47 Product Revision Level

48-(11+m) Vendor Specific Information

Type Descriptor Header List (4 bytes) Type descriptor header (1st element type)

….

(4 bytes) Type descriptor header (Tth element type)

Type Descriptor Text variable Type descriptor text (1st element type)

….

Last byte = n Type descriptor text (Tth element type)

14.2.3.3 Generation Code

The generation number is used in systems where the physical configuration of the system can lchange while the
system is operating. A change in this number indicates to the host that the Configuration diagnostic page has
changed and that it must read that page before attempting to interpret any other page. The enclosure supported by
this SES implementation does not support this concept, and the generation number must always be zero and not
incremented.
A non-zero generation code received by the SEP causes a check condition with a sense key of “ILLEGAL
REQUEST”, an ASC and an ASCQ of “Enclosure Services Transfer Refused”.

14.2.3.4 Enclosure Descriptor Header

Number of Enclosure Services Processes: This field indicates the number of enclosure services processes
supported by the enclosure. For the case of this implementation, the number of processes is 1.
Sub-Enclosure ID: This field must always be zero.

14.2.3.5 Enclosure Descriptor

Enclosure Logical Identifier: SAS base address is used for replacement if this field is set to zero.

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Enclosure Vendor Identification: The Enclosure Vendor Identification is an eight-byte string.

Product Identification: The Product Identification is a sixteen-byte string.
Product Revision Level: The Product Revision Level is a four-byte code indicating the revision level of the product.
The four bytes refer to the firmware release revision number. Each release of firmware is assigned a unique revision
number.
Vendor Specific Information: This 52 byte-long field is used to convey storage enclosure specific information. The
content of this field is entirely user-defined and is filled with test data only.

Offset (Bytes) Contents

1 – 52 Test data

14.2.3.6 Type Descriptor Headers

The type descriptor header list defines the element types that is being monitored by the firmware, indicates the
number of each element type contained within each page, and finally indicates the length of the text field for that
element type. Each header consists of four bytes:

Bits 7 6 5 4 3 2 1 0
Bytes

0 Element Type

1 Number of Possible Elements

2 Sub-Enclosure Identifier (0x00)

3 Type Descriptor Text Length

The element types and numbers of each type reported on the SES page are listed in the following table.
Table 14-7. Supported SES Element List

Type Code Element Type Count

0x17 Array Device 12 – See Note 2 and 3

0x02 Power Supply 2

0x03 Cooling Element 4

0x04 Temperature Sensor 4

0x12 Voltage 1

0x06 Audible Alarm 1

0x07 ES Electronics 1

0x0E Enclosure 1

0x18 SAS Expander 1

0x19 SAS Connector 12

Note
1. The elements and number of elements are arbitrarily chosen for the SES module and need to be aligned to the
specific enclosure targeted.

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2. Array Device Count is configured through the initialization string field Disk Drive Count in Table 8-36. The
mapping between the Array Device element and the SXP Logical PHY is configurable in the table. In the
default initialization string setting, 12 drives are mapped to PHY8~PHY19 respectively.
3. The maximum number of Disk Drive Count, is restricted by the MACRO SES_SXP_MAX_PHYS_CNT in the
header file fwcs\ses\inc\ses.h and SXP’s PHY_COUNT. The SES_SXP_MAX_PHYS_CNT is defined as 68,
which is the maximum number of PHYs for the SXP12G device family.

14.2.3.7 Type Descriptor Text

The other components of the Configuration diagnostic page that are vendor specific are the Type Descriptor Text
Strings for the element types supported. The strings that are used in the example SES implementation are:

Element Type Bytes Type Descriptor String

Device 16 “Array Device ”+0

Power Supply 16 “Power Supply ”+0

Cooling Module 16 “Cooling Fan ”+0

Temperature Sensor 16 “Temp. Sensor ”+0

Voltage 16 “Voltage ” + 0

Audible Alarm 16 “Buzzer ”+0

ES Electronics 16 “EMM ”+0

Enclosure 16 “Enclosure ”+0

SAS Expander 16 “Expander ”+0

SAS Connector 16 “Connector ”+0

14.2.3.8 SES Enclosure Control Diagnostic Page (0x02)

The Enclosure Control diagnostic page allows the host to request the expander device to carry out certain
‘commands’.
The Enclosure Control diagnostic page’s Page Length has to be exactly the same as the Enclosure Status diagnostic
page’s Page Length. Otherwise, a check condition with a sense key of “ILLEGAL REQUEST”, an ASC and an ASCQ
of “Enclosure Services Transfer Refused” will be returned by the SEP.
Table 14-8. Enclosure Control Diagnostic Page Format

Component Name Bytes Field Name

0 Page Code (0x02)

1 System Control Byte

Page Header
2-3 (MSB)
Page Length (n-3) (LSB)

Generation Code 4-7 Generation Code (0x00 0x00 0x00 0x00)

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...........continued
Component Name Bytes Field Name

8-11 Overall Control (1st element type)

12-15 Element Control (1st element of 1st element type)

….

(4 bytes) Element Control (last element of 1st element type)

Element Control
(4 bytes) Overall Control (2nd element type)

(4 bytes) Element Control (1st element of 2nd element type)

….

n-3 to n Element Control (last element of last element type)

The following table documents the byte offsets (starting from zero) of elements in Table 14-7 within the SES
enclosure control page.
Table 14-9. Element Offsets in Enclosure Control Page

Device Element Offset

Overall Drive Control 8 (0x8)

Individual Drive Control 12 (0xC)

Overall PS Control 60 (0x3C)

Individual PS Control 64 (0x40)

Overall Fan Control 72 (0x48)

Individual Fan Control 76 (0x4C)

Overall Temp Sensor Control 92 (0x5C)

Individual Temp Sensor Control 96 (0x60)

Overall Voltage Sensor Control 112 (0x70)

Individual Voltage Sensor Control 116 (0x74)

Overall Alarm Control 120 (0x78)

Individual Alarm Control 124 (0x7C)

Overall SEP Control 128 (0x80)

Individual SEP Control 132 (0x84)

Overall Enclosure Control 136 (0x88)

Individual Enclosure Control 140 (0x8C)

Overall Expander Control 144 (0x90)

Individual Expander Control 148 (0x94)

Overall Connector Control 152 (0x98)

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...........continued
Device Element Offset

Individual Connector Control 156 (0x9C)

Table 14-10. Enclosure Control Page: System Control Byte

Bit 7 6 5 4 3 2 1 0

Purpose Reserved Info Non-Crit Crit Unrecov

The System Control Byte is defined as a way for the host to indicate an overall status condition to the expander.
Info: The Informational condition bit (Info) may be set to one by the host to indicate the presence of an information
condition. The information condition is not an error and does not reduce the capabilities of the devices in the
enclosure. Transmitting an Enclosure Control diagnostic page with the Info bit set to zero does not clear the bit in the
enclosure when returned by the Enclosure Status diagnostic page.
Non-Crit: The Non-Critical condition bit (Non-Crit) may be set to one by the host to indicate the presence of a
non-critical condition. A non-critical condition is when one or more elements inside the enclosure have failed or are
operating outside of their specifications, but the condition does not affect the normal operation of the enclosure. A
condition determined by the SES F/W overrides this bit.
Crit: The Critical condition bit (Crit) may be set to one by the host to indicate the presence of a critical condition.
A critical condition is when one or more elements inside the enclosure have failed or are operating outside of their
specifications, and the condition affects the normal operation of the enclosure. A condition determined by the SES
F/W overrides this bit.
Unrecov: The Unrecoverable condition bit (Unrecov) may be set to one by the host to indicate the presence of an
unrecoverable condition. A condition determined by the SES F/W overrides this bit.
Note: Currently none of the above bits are being processed by the EMA and the SES enclosure control page will
simply set these values in the database. A request for an SES enclosure status page will return the settings for these
bits
The format of the CONTROL INFORMATION field for a device element type in the Enclosure Control diagnostic
page is defined in . Note: Only “RQST IDENT”, “RQST FAULT” and “DEVICE OFF” bits of the device element are
implemented in the SDK.
Table 14-11. Device Element for Enclosure Control Diagnostic Page

Byte \ Bit 7 6 5 4 3 2 1 0

0x00 Common Control

0x01 Reserved

RQST DO NOT RQST RQST RQST RQST

0x02 Reserved Reserved
ACTIVE REMOVE MISSING INSERT REMOVE IDENT

RQST DEVICE ENABLE ENABLE

0x03 Reserved Reserved
FAULT OFF BYP A BYP B

The request identify bit (RQST IDENT) is set to request that the device slot be identified by changing the blink pattern
for the SGPIO LOCATE bit. When the RQST IDENT bit is cleared, the visual indication is not present.
The request fault indication (RQST FAULT) bit set to one specifies that the device slot be identified by a visual
indication that a fault is present in the device. When the RQST FAULT bit is cleared, the fault indication is cleared if
the indication is not also set by the device or enclosure services process.
The DEVICE OFF bit is set to request that the device be turned off. When the DEVICE OFF bit is cleared, the device
may turn on if all other prerequisites are met.

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Other fields are not used.

When zoning is enabled on an expander device, if the SELECT bit is set to one for any device attached to the
expander PHY for which the SAS initiator port performing the SEND DIAGNOSTIC command does not have access
according to the zone permission table, then the enclosure services process terminates the SEND DIAGNOSTIC
command with CHECK CONDITION status. The sense key is set to ILLEGAL REQUEST, and the additional sense
code is set to INVALID FIELD IN PARAMETER LIST.
Table 14-12. Enclosure Control Page: Common Control Byte for All Element Types

Bit 7 6 5 4 3 2 1 0

Meaning Select PrdFail Disable Rst Swap Reserved

Select: When set to one, the control information for this element will be acted upon.
PrdFail: When set to one, the predicted failure indicator (if one exists) will be activated. This bit is ignored when
handling all element types.
Disable: When set to one, the element is disabled. This bit is ignored when handling all element types.
Rst Swap: When set to one, the swap status for this element will be set to zero.
Note:
• Currently only the ‘Select’ bit is processed. All other bits are simply set in the database. A request for a SES
enclosure status page will return the settings for these bits.

14.2.3.9 Field Definitions for All Element Types

Table 14-13. Enclosure Control Page: Array Device Element

7 6 5 4 3 2 1 0

0 COMMON CONTROL

1 Rqst OK Rqst Rsvd Rqst Hot Rqst Cons Rqst in Crit Rqst in Rqst Rqst R/R
Device Spare Check Array Failed Rebuild/ Abort
Array Remap

2 Active Do Not Reserved Rqst Insert Rqst Rmv Rqst Ident Reserved
Remove

3 Rqst Fault Device Off Enable Enable

Reserved Reserved
Byp A Byp B

In the Common Control byte, Select, PrdFail, Rst Swap bits are supported. Rqst OK: When set to one, the HDD
status LED blinks in the Drive Online pattern. When set to zero, the blink pattern is de-activated.
Rqst Rsvd Device, Rqst Hot Spare, Rqst Cons Check, Rqst in Crit Array, and Rqst in Failed Array: The value
of the Request Reserved Device bit, the Request Hot Spare bit, the Request Consistency Check In Progress bit, the
Request in Critical Array bit and the Request in Failed Array bit will have no effect. The SES F/W maintains a copy of
these bits as status and returns the copy to the host when requested through the Enclosure Status diagnostic page.
Rqst Rebuild/Remap: When set to one, the HDD status LED blinks in the Drive Rebuilding pattern. When set to
zero, the blink pattern is de-activated.
Rqst R/R Abort: When set to one, the HDD status LED blinks the Rebuild Abort pattern. When set to zero, the blink
pattern is de-activated.
Active: This bit has no effect since the enclosure does not drive the HDD activity LED.
Do Not Remove: The value of this bit will have no effect. The SES F/W maintains a copy of this bit as status and
returns the copy to the host when requested through the Enclosure Status diagnostic page.
Rqst Insert: This bit has no effect.

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Rqst Rmv, Rqst Ident: When either the Request Removal or Request Identify bit is set to one, the HDD status LED
blinks the Drive Identify/Prepare for Removal pattern. When set to zero, the blink pattern is de-activated.
Rqst Fault: When set to one, the HDD status LED blinks the Drive Failed pattern. When set to zero, the blink pattern
is de-activated.
Device Off, Enable Byp A, and Enable Byp B: These bits will have no effect.
Note:
• Currently only the ‘Select’ bit is processed. All other bits are simply set in the database. A request for a SES
enclosure status page will return the settings for these bits.
Table 14-14. Enclosure Control Page: Power Supply Element

7 6 5 4 3 2 1 0

0 COMMON CONTROL

1 Rqst Ident Reserved

3 Reserved Rqst Fail Rqst On Reserved

In the Common Control byte, only the Select bit is supported.

Rqst Ident, and Rqst Fail: These bits are only written to the database.
Rqst On: When set to one, the PS is switched on or remains switched on. When set to zero, the PS will be switched
off in 3 minutes. This 3-minute delay is added to let a host have enough time to flush all commands to drives and
stop any further I/O. Note: This bit is only implemented in Overall Control field, so power supplies cannot be turned
off individually.
Note:
• Currently only the ‘Select’ bit is processed. All other bits are simply set in the database. A request for a SES
enclosure status page will return the settings for these bits.
Table 14-15. Enclosure Control Page: Cooling Element

7 6 5 4 3 2 1 0

0 COMMON CONTROL

1 Rqst Ident Reserved

3 Reserved Rqst Fail Rqst On Reserved Requested Speed Code

In the Common Control byte, only the Select is supported.

Rqst Ident, Rqst Fail, and Rqst On: These bits are only written to the database.
Requested Speed Code:
The speed control is global to all fans, so the EMM only deals with the speed setting in the overall fan element type
field. There are three possible speed settings for the fans. The following values are implemented:

Requested Speed Code Fan Speed

000b Reserved

001b Low

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...........continued
Requested Speed Code Fan Speed

100b Medium

111b High

The requested speeds will only be activated if they are the same or higher than that required by the current ambient
temperature.
Note:
• Currently only the ‘Select’ bit is processed. All other bits are simply set in the database. A request for a SES
enclosure status page will return the settings for these bits.
Table 14-16. Enclosure Control Page: Temperature Sensor Element

7 6 5 4 3 2 1 0

0 COMMON CONTROL

1 Rqst Ident

2 Reserved

In the Common Control byte, only the Select bit is supported.

Rqst Ident, Rqst Fail: These bits are only written to the database.
Note:
• Currently only the ‘Select’ bit is processed. All other bits are simply set in the database. A request for a SES
enclosure status page will return the settings for these bits.
Table 14-17. Enclosure Control Page: Voltage Sensor Element

7 6 5 4 3 2 1 0

0 COMMON CONTROL

1 Rqst Ident Rqst Fail Reserved

2 Reserved

In the Common Control byte, only the Select bit is supported.

7 6 5 4 3 2 1 0

0 COMMON CONTROL

1 Rqst Ident Reserved

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...........continued
7 6 5 4 3 2 1 0

3 Reserved Set Mute Reserved Set Remind Info Non-Crit Crit Unrecov

In the Common Control byte, only the Select bit is supported.

Rqst Ident, Rqst Fail: These bits are only written to database.
Set Mute: When set to one, this bit causes the audible alarm to be muted until the next alarm event occurs. It must
have precedence over the tone urgency control bits.
Set Remind: This bit is not implemented and has no effect.
Info: This bit is not implemented and has no effect.
Non-Crit: If set to one, a non-critical tone is emitted in this state if it is not muted and if there is no existing critical
condition. If set to zero, the alarm stops emitting the non-critical tone if there is no existing non-critical condition.
Crit: If set to one, a critical tone is emitted in this state if it is not muted. If set to zero, the alarm stops emitting the
critical tone if there is no existing critical condition or non-critical condition.
Unrecov: This bit is not implemented and has no effect.
Note:
• Currently only the ‘Select’ bit is processed. All other bits are simply set in the database. A request for a SES
enclosure status page will return the settings for these bits.
Table 14-19. Enclosure Control Page: ES Electronics Element

7 6 5 4 3 2 1 0

0 COMMON CONTROL

1 Rqst Ident Reserved

2 Reserved Select
Element

3 Reserved

In the Common Control byte, only the Select is supported.

Rqst Ident, Rqst Fail: These bits are only written to the database.
Select Element: This bit will have no effect.
Note:
• Currently only the ‘Select’ bit is processed. All other bits are simply set in the database. A request for a SES
enclosure status page will return the settings for these bits.
Table 14-20. Enclosure Control Page: Enclosure Element

7 6 5 4 3 2 1 0

0 COMMON CONTROL

1 Rqst Ident Reserved

2 Reserved

3 Reserved Rqst Rqst

Failure Warning

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In the Common Control byte, only the Select is supported.

Rqst Ident: If set to one, the shelf status LED will blink an identify pattern. If set to zero, the firmware stops the
identify pattern.
Rqst Failure: If set to one, the shelf status LED will blink a fault pattern. If set to zero, the firmware stops the fault
pattern.
Rqst Warning: If set to one, the shelf status LED will blink a warning pattern. If set to zero, the firmware stops the
warning pattern.
Power Cycle Request, Power Cycle Delay: These bits are not implemented and have no effect.
Note:
• Currently only the ‘Select’ bit is processed. All other bits are simply set in the database. A request for a SES
enclosure status page will return the settings for these bits.
Table 14-21. Enclosure Control Page: Expander Element

7 6 5 4 3 2 1 0

0 COMMON CONTROL

1 Rqst Ident Rqst Fail

2 Reserved

In the Common Control byte, only the Select is supported.

Rqst Ident: If set to one, the shelf status LED will blink an identify pattern. If set to zero, the firmware stops the
identify pattern.
Rqst Fail: This bit is only written to the database.
Note:
• Currently only the ‘Select’ bit is processed. All other bits are simply set in the database. A request for a SES
enclosure status page will return the settings for these bits.
Table 14-22. Enclosure Control Page: Connector Type Element

7 6 5 4 3 2 1 0

0 COMMON CONTROL

1 Rqst Ident

2 Reserved

3 Reserved Rqst Fail Reserved

In the Common Control byte only the Select is supported.

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14.2.3.10 SES Enclosure Status Diagnostic Page (0x02)

The Enclosure Status diagnostic page returns status information for each of the elements identified by the
Configuration diagnostic page. The status page is read by the RECEIVE DIAGNOSTIC RESULTS command. The
following table describes the format of SES Enclosure Status Diagnostic page.
Table 14-23. Enclosure Status Page Format

Component Name Bytes Field Name

0 Page Code (0x02)

1 System Status Byte

Page Header
2-3 (MSB)
Page Length (n-3) (LSB)

Generation Code 4-7 Generation Code (0x00 0x00 0x00 0x00)

8-11 Overall Status (1st element type)

12-15 Element Status (1st element of 1st element type)

….

(4 bytes) Element Status (last element of 1st element type)

Element Status
(4 bytes) Overall Status (2nd element type)

(4 bytes) Element Status (1st element of 2nd element type)

….

n-3 to n Element Status (last element of last element type)

The following table documents the byte offsets (starting from zero) for elements on the enclosure status page.
Table 14-24. Element Offsets in Enclosure Status Page

Element Type Offset

Overall Drive Control 8 (0x8)

Individual Drive Control 12 (0xC)

Overall PS Control 60 (0x3C)

Individual PS Control 64 (0x40)

Overall Fan Control 72 (0x48)

Individual Fan Control 76 (0x4C)

Overall Temp Sensor Control 92 (0x5C)

Individual Temp Sensor Control 96 (0x60)

Overall Voltage Control 112 (0x70)

Individual Voltage Sensor Control 116 (0x74)

Overall Alarm Control 120 (0x78)

Individual Alarm Control 124 (0x7C)

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...........continued
Element Type Offset

Overall SEP Control 128 (0x80)

Individual SEP Control 132 (0x84)

Overall Enclosure Control 136 (0x88)

Individual Enclosure Control 140 (0x8C)

Overall Expander Control 144 (0x90)

Individual Expander Control 148 (0x94)

Overall Connector Control 152 (0x98)

Individual Connector Control 156 (0x9C)

Table 14-25. Enclosure Status Page: System Status Byte

Bit/Byte 7 6 5 4 3 2 1 0

Purpose Reserved Invop Info Non-Crit Crit Unrecov

Invop: This is set to one by the SES F/W when returning the first Enclosure Status diagnostic page following receipt
of an invalid Enclosure Control diagnostic page.
Info: This bit is set to one in the Enclosure Status diagnostic page after the firmware detects an information condition
in the enclosure. The bit is also set to one if it has been set in the previous Enclosure Control diagnostic page. This
bit is set to zero on a per-initiator basis.
Non-Crit: This bit is set to one in the Enclosure Status diagnostic page after the firmware detects a non-critical
condition in the enclosure. It is also set to one if it has been set to one in the previous Enclosure Control diagnostic
page. The bit is only set to zero if there is no locally detected non-critical condition, and it has not been set to one by
an Enclosure Control diagnostic page.
Crit: This bit is set to one in the Enclosure Status diagnostic page after the firmware detects a critical condition in the
enclosure. It is also set to one if it has been set to one in the previous Enclosure Control diagnostic page. The bit is
only set to zero if there is no locally detected critical condition, and it has not been set to one by an Enclosure Control
diagnostic page.
Unrecov: This bit is set to one in the Enclosure Status diagnostic page after the firmware detects an unrecoverable
condition in the enclosure, and is only set to zero if there is no locally detected unrecoverable condition.
Note:
• Currently only the INVOP bit is processed. None of the other bits are being set by the EMA; the SES enclosure
status page will simply return the values stored in the database. An SES enclosure control page can set
writeable bits in the database.
The format of the STATUS INFORMATION field for a device element type in the Enclosure Status diagnostic page is
defined in the following table. Only the “RQST IDENT”, “RQST FAULT” and “DEVICE OFF” bits of the device element
are implemented in this release, and only 12 devices elements are supported. These are mapped to logic PHY 8 –
logic PHY 19.
Table 14-26. Enclosure Status Page: Common Status Byte for All Element Types

Bit/Byte 7 6 5 4 3 2 1 0

Meaning Reserved PrdFail Reserved Swap Status Code

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PrdFail: When set to one, this bit indicates that the element has the capability of predicting failure and that failure has
been predicted. The bit may additionally be set to one by the corresponding bit in the Enclosure Control diagnostic
page.
Swap: When set to one, this bit indicates that an element has been removed and reinserted in the location indicated.
This bit is set to zero only by a corresponding reset swap bit in the Enclosure Control diagnostic page. The enclosure
services process must maintain one SWAP bit for each I_T nexus. The SDK supports the Swap bit and RST_SWAP
bits for Array Device Elements. The implementation of RST_SWAP and SWAP bits for each I_T Nexus is described
as follows:
• When powered on, all drives are considered to do one hotplug action; SWAP bit is reported as ‘1’ for each
initiator.
• When one initiator sends the enclosure control page with RST_SWAP ‘1’, the SWAP bit is cleared for the
corresponding I_T nexus only.
• When drive is swapped, the port manager thread can detect this event and updates the SWAP status to all I_T
nexuses.
Status Code: The status code indicates the overall operating status of the element.
Table 14-27. Status Code

Status Code Name Condition

0x00 Unsupported No status detection available for this element

0x01 OK Element is present and no error conditions are recorded

0x02 Critical Critical Condition is detected

0x03 Non-Critical Non-Critical condition is detected

0x04 Unrecoverable Unrecoverable condition is detected

0x05 Not Installed Element is not installed in enclosure

0x06 Unknown Sensor has failed or status is unavailable

0x07 Not Available Element is installed and has no recorded errors, but has not been
‘switched on’

Note:
• Currently none of the above bits are being set by the EMA; the SES enclosure status page simply returns values
stored in the database. An SES enclosure control page can set writeable bits in the database.

14.2.3.11 Field Definitions for All Element Types

Table 14-28. Enclosure Status Page: Array Device Element

Bit/Byte 7 6 5 4 3 2 1 0

0 COMMON STATUS

1 OK Rsvd Hot Spare Cons In Crit In Failed Rebuild/ R/R Abort

Device Check Array Array Remap

2 App Client Do Not Enclosure Enclosure Ready to Rmv Ident Report

Bypassed Remove Bypassed Bypassed Insert
A A B

3 App Client Fault Fault Device Off Bypassed Bypassed Device Device
Bypassed Sensed requested A B Bypassed A Bypassed
B B

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In the Common Status byte, the PrdFail, SWAP and Status Code bits are supported OK: The OK bit is set to one
when the HDD status LED is blinking the Drive Online pattern. It is set to zero when the blink pattern is de-activated.
Rsvd Device, Hot Spare, Cons Check, In Crit Array, and In Failed Array: The Reserved Device bit, Hot Spare bit,
Consistency Check in Progress bit, In Critical Array bit, and In Failed Array bit are copied from the latest Enclosure
Control diagnostic page received by the firmware.
Rebuild/Remap: The Rebuild/Remap bit is set to one when the HDD status LED is blinking the Drive Rebuilding
pattern. It is set to zero when the blink pattern is de-activated.
R/R Abort: The Rebuild/Remap Abort bit is set to one when HDD status LED is blinking the Rebuild Abort pattern. It
is set to zero when the blink pattern is de-activated.
App Client Bypassed A, App Client Bypassed B, Enclosure Bypassed A, and Enclosure Bypassed B: These
bits are not supported and must always be set to zero.
Do Not Remove: This bit is copied from the latest Enclosure Control diagnostic page received by the firmware.
Ready to Insert: This bit must always be set to zero.
Rmv: When set to one, this bit indicates that the HDD status LED is currently blinking the Drive Identify/Prepare for
Removal pattern. It is set to zero when the blink pattern is de-activated.
Ident: When set to one, this bit indicates that the HDD status LED is currently blinking the Drive Identify/Prepare for
Removal. It is set to zero when the blink pattern is de-activated.
Report: This bit must always be set to zero.
Fault Sensed: This bit must always be set to zero.
Fault Requested: When set to one, this bit indicates that the HDD status LED is currently blinking the Drive Failed
pattern. It is set to zero when the blink pattern is de-activated.
Device Off: This bit must always be set to zero.
Bypassed A, and Bypassed B: This bit must always be set to zero.
Device Bypassed A, and Device Bypassed B: These bits are not supported in the SCSI enclosure and must
always be set to zero.
Table 14-29. Array Device Element Status Code Summary

Supported Status Code Values Meaning Field Events

OK Device is present No corresponding fields

NOT INSTALLED Device is not present No corresponding fields

Note:
• Currently none of the above bits are being set by the EMA and the SES enclosure status page will simply return
the values stored in the database. An SES enclosure control page can set writeable bits in the database.
Table 14-30. Enclosure Status Page: Power Element

Bit/Byte 7 6 5 4 3 2 1 0

0 COMMON STATUS

1 Ident Reserved

2 Reserved DC Over DC Under DC Over Reserved

Voltage Voltage Current

3 Hot Swap Fail Rqsted On OFF Overtmp Temp AC Fail DC Fail

Fail Warn

In the Common Status byte, Status Code and SWAP bit are supported.

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Ident: This bit is not supported and must always be set to zero.
DC Over-Voltage, DC Under-Voltage: These two bits are mapped to the OV/UV bit of the PS/Fan module interface
register set. They are set to one when the firmware detects that the OV/UV bit is set to one. They are set to zero
when the OV/UV bit is set to zero.
DC Over-Current: This is mapped to the OC bit of the PS/Fan module interface register set. It is set to one when the
firmware detects that the OC bit is set to one. It is set to zero when the OC bit is set to zero.
Over-Temperature Fail: This is mapped to the OTP bit of the PS/Fan module interface register set. It is set to one
when the firmware detects that the OTP bit is set to one. It is set to zero when the OTP bit is set to zero.
Temperature Warning: This fault condition is determined internally within the power supply. It is not separately
indicated to the EMM and hence cannot be reported separately. This bit must always be set to zero.
DC Fail: This is mapped to the POK bit of the PS/Fan module interface register set. It is set to one when the firmware
detects that the POK bit is set to zero. It is set to zero when the OC bit is set to one.
AC Fail: This bit is mapped to the VIN_GOOD bit of the PS/Fan module interface register set. It is set to one when
the firmware detects that the VIN_GOOD bit is set to zero. It is set to zero when the VIN_GOOD bit is set to one.
Hot Swap: This bit is set to one when element is replaced without power off. It is set to zero when element
replacement doesn’t happen.
Fail: This is set to one when any of the DC Over-Voltage, DC Under-Voltage, DC Over-Current, Over-Temperature
Fail, DC Fail and AC Fail bits are set to one. It is also set to one if the firmware fails to communicate with the PS/Fan
module interface register set. It is set to zero when none of these bits is set to one.
Rqsted On: This bit must be cleared when the power supply is not installed and set when the power supply is
installed.
Off: When set this bit indicates that the power supply is not providing power. This can occur because the PS is not
installed in the slot.
Table 14-31. Power Element Status Code Summary

Supported Status Code Values Meaning Field Events

OK PS is present and reports no Fail = 0

errors
Off = 0
Rqsted On = 1

CRITICAL PS is present and reports an Fail = 1

operating error
Off = 0
Rqsted On = 1

NOT INSTALLED PS is not present Fail = 0

Off = 1
Rqsted On = 0

Bit/Byte 7 6 5 4 3 2 1 0

0 COMMON STATUS

1 Ident Reserved (MSB)

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...........continued
Bit/Byte 7 6 5 4 3 2 1 0

2 Actual Fan Speed (LSB)

3 Reserved Fail Rqsted On Off Reserved Actual Speed Code

In the Common Status byte, the Status Code bits are supported.
Ident: This bit is not supported and must always be set to zero.
Actual Fan Speed: This is the fan speed in revolutions per minute (RPM) multiplied by 10.
Hot Swap: This bit is set to one when element is replaced without power off. It is set to zero when element
replacement doesn’t happen.
Fail: When set to one, this bit indicates that the Fail indicator is active. This can occur as a result of a locally detected
Fan failure.
Rqsted On: When set to one, this bit indicates that the fan has been requested to turn on by the host setting the
corresponding control bit. This bit must always be set to zero because this control bit is not implemented.
Off: When set to one this bit indicates that the fan is not operational.
Actual Speed Code: This field indicates the detected speed of the cooling element.
Table 14-33. Cooling Element Status Code Summary

Speed Code Fan Speed

000b Fan Stopped

001b Low Speed

100b Medium Speed

111b High Speed

Supported Status Code Values Meaning Field Events

OK Fan is present and reports no errors Fail = 0 Off = 0

CRITICAL Fan is present and reports an operating error Fail = 1 Off = 0

NOT INSTALLED Fan is not present Fail = 0 Off = 1

Note:
• Currently none of the above bits are set by the EMA; the SES enclosure status page simply returns values
stored in the database. A SES enclosure control page can set writeable bits in the database.
Table 14-34. Enclosure Status Page: Temperature Sensor Element

Bit/Byte 7 6 5 4 3 2 1 0

0 COMMON STATUS

1 Ident Fail Reserved

2 Temperature

3 Reserved OT Failure OT UT Failure UT

Warning Warning

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In the Common Status byte, the Status Code bit is supported.

Ident: This bit is not supported and must always be set to zero.
Fail: When set to one, this bit indicates that the Fail indicator is active. This can occur as a result of a locally detected
temperature failure.
Temperature: This field indicates the current temperature (with an offset of 20oC)
OT Failure: When set to one, this bit indicates that the temperature has exceeded the high critical threshold.
OT Warning: When set to one, this bit indicates that the temperature has exceeded the high warning threshold.
UT Failure: When set to one, this bit indicates that the temperature has dropped below the low critical threshold.
UT Warning: When set to one, this bit indicates that the temperature has dropped below the low warning threshold.
Table 14-35. Temperature Sensor Element Status Code Summary

Supported Status Code Values Meaning Field Events

OK Temperature is within normal operating OT, UT Fail = 0 OT, UT

region Warn = 0

NON-CRITICAL Temperature is outside warning limits, but OT, UT Fail = 0 OT or UT

inside critical limits Warn = 1

NOT INSTALLED Temperature sensor is not present No corresponding fields

UNNKOWN The temperature sensor itself has failed OT, UT Fail = 0 OT, UT
Warn = 0

CRITICAL Temperature is outside critical limits OT or UT Fail = 1 OT, UT

Warn = 0

Note:
Currently only a value for temperature sensor 1 is set by the EMA in the database. The SES enclosure status page
will simply return the values stored in the database. A SES enclosure control page can set writeable bits in the
database.
Table 14-36. Enclosure Status Page: Voltage Sensor Element

Bit/Byte 7 6 5 4 3 2 1 0

0 COMMON STATUS

1 Ident Fail WARN WARN CRIT CRIT

Reserved
OVER UNDER OVER UNDER

2 (MSB)
VOLTAGE
3 (LSB)

In the Common Status byte, the Status Code bit is supported.

Ident: When set to one, this bit indicates that the Identify indicator is active. Currently, it only indicates the value
stored in the database.
Fail: When set to one, this bit indicates that the Fail indicator is active. Currently, it only indicates the value stored in
the database.

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Table 14-37. Voltage Sensor Element Status Code Summary

Supported Status Meaning Field Events

Code Values

OK Voltage is within normal operating region WARN OVER, UNDER Fail = 0 CRIT
OVER, UNDER = 0

NON-CRITICAL Voltage is outside warning limits, but inside critical WARN OVER or UNDER Fail = 1 CRIT
limits OVER, UNDER = 0

NOT INSTALLED Voltage sensor is not present No corresponding fields

UNKNOWN The voltage sensor itself has failed WARN OVER, UNDER Fail = 0 CRIT
OVER, UNDER = 0

CRITICAL Voltage is outside critical limits WARN OVER, UNDER Fail = 0 CRIT
OVER or UNDER = 1

Note:
The SES enclosure status page will simply return the values stored in the database. A SES enclosure control page
can set writeable bits in the database.
Table 14-38. Enclosure Status Page: Audible Alarm Element

Bit/Byte 7 6 5 4 3 2 1 0

0 COMMON STATUS

1 Ident Fail Reserved

2 Reserved

3 Rqst Mute Muted Reserved Remind Info Non-Crit Crit Unrecov

In the Common Status byte, the Status Code bits are supported.
Ident: This bit is not supported and must always be set to zero.
Fail: When set to one, this bit indicates that the Fail indicator is active. This can occur as a result of a locally detected
alarm failure.
Rqst Mute: This bit is copied from the latest Enclosure Control diagnostic page received by the firmware.
Muted: When set to one, this bit indicates that the audible alarm is in the muted state. No sound is emitted when in
this state.
Remind: This bit must always be set to zero.
Info: This bit must always be set to zero.
Non-Crit: This bit indicates the alarm is emitting a non-critical tone if it is not muted.
Crit: This bit indicates the alarm is emitting a critical tone if it is not muted.
Unrecov: This bit must always be set to zero.
Table 14-39. Audible Alarm Element Status Code Summary

Supported Status Code Values Meaning Field Events

OK The Buzzer is present (The Buzzer should No corresponding fields

always be present in the SEP)

Note:

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• Currently none of the above bits are being set by the EMA and the SES enclosure status page will simply return
the values stored in the database. An SES enclosure control page can set writeable bits in the database.
Table 14-40. Enclosure Status Page: ES Electronics Element

Bit/Byte 7 6 5 4 3 2 1 0

0 COMMON STATUS

1 Ident Fail Reserved

2 Reserved Report

3 Hot Swap Reserved

Supported Status Code Values Meaning Field Events

OK The SEP is installed and operating correctly Report = 1

CRITICAL The SEP is not functioning correctly Report = 0

NOT INSTALLED The SEP is not installed Report = 0

NOT AVAILABLE The SEP is in Bootloader and is not fully functional N/A

Bit/Byte 7 6 5 4 3 2 1 0

0 COMMON STATUS

1 Ident Reserved

2 Time Until Power Cycle Failure Warning

Indication Indication

3 Requested Power Off Duration Failure Warning

Requested Requested

In the Common Status byte, the Status Code bits are supported.
Ident: This bit is set to one if the Shelf Status LED is blinking the identify pattern; it is set to zero otherwise.
Failure Indication: This bit is set to one if the firmware has detected a critical condition and the shelf status LED is
blinking a fault pattern; it is set to zero otherwise.

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Warning Indication: This bit is set to one if the firmware has detected a non-critical condition and the shelf status
LED is blinking a warning pattern; it is set to zero otherwise.
Failure Requested: This bit is copied from the latest Enclosure Status diagnostic page received by the firmware.
Warning Requested: This bit is copied from the latest Enclosure Status diagnostic page received by the firmware.
Time Until Power Cycle, Requested Power off Duration: These bits are not implemented.
Note:
Currently, none of the above bits are being set by the EMA and the SES enclosure status page will simply return the
values stored in the database. An SES enclosure control page can set writeable bits in the database.
Table 14-43. Enclosure Status Page: Expander Element

Bit/Byte 7 6 5 4 3 2 1 0

0 COMMON STATUS

Ident Fail

2 Reserved

3 Reserved

In the Common Status byte, Status Code bit is supported.

Ident: This bit is not supported and must always be set to zero.
Fail: This bit is not supported and must always be set to zero.
Note:
Currently none of the above bits are being set by the EMA and the SES enclosure status page will simply return the
values stored in the database. An SES enclosure control page can set writeable bits in the database.
Table 14-44. Enclosure Status Page: Connector Type Element

Bit/Byte 7 6 5 4 3 2 1 0

0 Reserved PrdFail Reserved Swap Status Code

1 Ident Connector Type

2 Connector Physical Link

3 Reserved Fail Reserved

Ident: This bit is not supported and must always be set to zero.
Fail: This bit is not supported and must always be set to zero
Connector Type: This field explains what the connector type is, such as SFF-8644.
Connector Physical link: This field indicates the physical link in the connector represented by this element.
Note: Currently none of the above bits are being set by the EMA and the SES enclosure status page will simply
return the values stored in the database. An SES enclosure control page can set writeable bits in the database

14.2.3.12 Help Text Diagnostic Page (0x3)

Table 14-45. Help Text Diagnostic Page

Bit/Byte 7 6 5 4 3 2 1 0

0 PAGE CODE (0x03)

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Bit/Byte 7 6 5 4 3 2 1 0

1 Obsolete

2 PAGE LENGTH (n-3) (MSB)

3 PAGE LENGTH (n-3) (LSB)

4-n PRIMARY SUBENCLOSURE HELP TEXT

The fields in this page are defined as:

• PRIMARY SUBENCLOSURE HELP TEXT: Contains a text string describing the corrective actions to perform on
the primary subenclosure. It contains “Hello World Help” in the default SDK.

14.2.3.13 String In Diagnostic Command (0x4)

When asked for a String In diagnostic page the SEP will return application download status, and tag data. Fields
containing current test data can be freely defined by the user.
Table 14-46. String In Diagnostic Page Format

Component Name Bytes Field Name

0 Page Code (0x04)

Page Header 1 Sub-Enclosure Identifier (0x00)

2-3 (MSB) Page Length (n-3) (LSB)

4 Firmware Download Status

5-23 Test data

24-31 Tag Data Identify String

Vendor Specific
32 Tag Data Length

33-132 Tag Data

133-241 Test data

Table 14-47. String In Diagnostic Page: Firmware Download Status Field

Byte 3 Byte 2 Byte 1 Byte 0

Reserved Download Status: this field indicates the status of the firmware download.
0x00: Ready for download 0x01: Download in progress, no error 0x02: Image header
incorrect 0x03: Packet offset incorrect 0x04: Image CRC incorrect 0x05: Mismatch of
image length sent and length in of the download header 0x06: Hardware errors, such as
wrong packet CRC from expander 0x07: Download completes, but pending on a reboot
command from host in order to run the new image.

Tag Data: Tag Data Identify String has the following format:
“Tag Data” (8 bytes) Tag Data Length = 100 Tag Data (100 bytes)

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Table 14-48. String In Diagnostic Page: Tag Data Field

Component Bytes Notes

User defined 0 - 97

Tag Data Checksum 98-99

14.2.3.14 String Out Diagnostic Command (0x4)

The host uses the String Out diagnostic page to download applications or perform in-band diagnostic commands.
Table 14-49. String Out Diagnostic Page Format

Component Name Bytes Field Name

0 Page Code (0x04)

1 Sub-Enclosure Identifier (0x00)

Page Header
2-3 (MSB)
Page Length (n-3) (LSB)

4 Command
Vendor Specific
5-n User Data

The format of the pages is a command code followed, where relevant, by data.
Table 14-50. String Out Diagnostic Commands

Command Purpose Data Notes

0x01 Download Firmware image binary EMA prepares application area, copies data into
Firmware data flash memory, but does not reboot.
New firmware takes effect on next power-on-reset
or reboot command.

0x02 Reboot 01: soft-reset This command causes the SEP to perform a soft-
reset or hard-reset depending on the data field. A
02: hard-reset
sample of soft-reset:
Pmc_scsi –scsi –x 1d 10 00 00 06 00 –o 04 00 00
02 02 01
This command causes the SEP to perform a soft-
reset or hard-reset depending on the data field. A
sample of hard-reset:
pmc_scsi –scsi –x 1d 10 00 00 06 00 –o 04 00 00
02 02 02

0x20 Download Tag 100 bytes of Tag Data Data copied to RAM
Data

0x27 Set Time of day Time in 4 byte format LSB Set time in EMM for the timestamp used for error
clock byte first logging.

0x28 Clear Error Log None Error log stored in RAM is erased.

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Command Purpose Data Notes

0x40 Log Control Byte 1: Filter index Adjust log filtering for application log logging.
Function osf_log_word1_filter_set() is called with
Bytes 2-5: Mask
the parameters specified in the data.
Bytes 6 - 9: Pattern
Bytes 10 - 13: Type

Download Firmware: Upon receipt of the first firmware download command, the firmware verifies the binary image
header included in the first download packet. This image is then downloaded in a series of packets using the
“Firmware Download” command. New firmware image will not be executed until the next enclosure power cycle or
reboot. Each frame of firmware data is preceded by the offset of the current packet of data in the first four bytes
(bytes 5-8 of each string out: Firmware Download page). Details of host tools that generate the string out pages can
be found in Section 19.1.1 Host API.
Reboot: Firmware will return command status before reboot. After the reboot firmware will check for the cause of the
reboot. If new firmware image is downloaded previously, it will validate the CRC-32 of the new image. If the validation
is successful, it will switch to and start executing the new image.
Download Tag Data: Tag data can be used to uniquely identify a particular enclosure. This information is currently
stored in the database RAM on the SEP and will be reported in String In diagnostic page.
Table 14-51. String Out Diagnostic Page: Tag Data Format

Component Bytes Notes

Tag data 0 – 95 Test data.

Tag Data Checksum 96 - 99

Set Timestamp: The host sets the timestamp (seconds) and firmware configures the RTC counter accordingly.
Clear Error Log: Firmware will reset all the error log related pointers, effectively clearing the applications log.

14.2.3.15 Threshold In Diagnostic Command (0x5)

The threshold pages allow a host application to configure and examine the threshold values for those element types
that support the concept of thresholds. The page length needs to be identical to the configuration and enclosure
status/control page.
Table 14-52. Threshold In Diagnostic Page Format

Component Name Bytes Field Name

0 Page Code (0x05)

1 Reserved (000b) Invop Reserved (0000b)

Page Header
2-3 (MSB)
Page Length (n-3) (LSB)

Generation Code 4-7 Generation Code (00h 00h 00h 00h)

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Component Name Bytes Field Name

8-11 Overall Threshold (1st element type)

12-15 Element Threshold (1st element of 1st element type)

….

(4 bytes) Element Threshold (last element of 1st element type)

Element Status
(4 bytes) Overall Threshold (2nd element type)

(4 bytes) Element Threshold (1st element of 2nd element type)

….

n-3 to n Element Threshold (last element of last element type)

Invop: This is set to one by the SES F/W when returning the first Threshold In diagnostic page following receipt of an
invalid Threshold Out diagnostic page.
Table 14-53. Threshold In Diagnostic Page: Data Format for All Element Types

Bits
7 6 5 4 3 2 1 0
Bytes

0 High Critical Threshold

1 High Warning Threshold

2 Low Warning Threshold

3 Low Critical Threshold

Every instance of each element type has an entry in the threshold pages. There is also a summary entry for each
element type.
Only the temperature sensor element type uses thresholds in an SEP. All other elements will report NULL data in
their entries in Threshold In diagnostic page and will ignore any data sent in Threshold Out diagnostic page.
• TEMPERATURE SENSOR ELEMENT: The temperature sensor element reports the four temperature thresholds
high and low, warning and critical in the Threshold In diagnostic page. In the Threshold In diagnostic page, the
Overall Threshold entries of the temperature sensor element are not supported.
The default temperature threshold values measured in degrees Celsius are as follow (with an offset of 20oC):
• High Critical: 50oC.
• High Warning: 40oC.
• Low Warning: 10oC.
• Low Critical: 0oC.
The above values are in decimal and must be programmed as hex when reported in SES.

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14.2.3.16 Threshold Out Diagnostic Command (0x5)

Table 14-54. Threshold Out Diagnostic Page Format

Component Name Bytes Field Name

0 Page Code (0x05)

1 Reserved (0x00)
Page Header
2-3 (MSB)
Page Length (n-3) (LSB)

Generation Code 4-7 Generation Code (0x00 0x00 0x00 0x00)

8-11 Overall Threshold (1st element type)

12-15 Element Threshold (1st element of 1st element type)

….

(4 bytes) Element Threshold (last element of 1st element type)

Element Status
(4 bytes) Overall Threshold (2nd element type)

(4 bytes) Element Threshold (1st element of 2nd element type)

….

n-3 to n Element Threshold (last element of last element type)

SEP accepts new values for thresholds only for temperature sensor elements in the Threshold Out diagnostic page.
It must not accept new values for high/low critical thresholds. New values for high warnings must not be higher
than the default high warning, and new values for low warning must not be lower than the default low warning.
In the Threshold Out diagnostic page, the Individual Threshold entries of the temperature sensor element are not
supported. In other words, all the sensors in the enclosure share the same set of thresholds.

14.2.3.17 Element descriptor Status Diagnostic Page (0x07)

Table 14-55. Element Descriptor Status Page Format

Component Name Bytes Field Name

0 Page Code (0x07)

1 Reserved
Page Header
2-3 (MSB)
Page Length (n-3) (LSB)

Generation Code 4-7 Generation Code (0x00 0x00 0x00 0x00)

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Component Name Bytes Field Name

8- variable Overall Descriptor (1st element type)

Variable -
variable Element Descriptor (1st element of 1st element type)

Variable -
variable Element Descriptor (last element of 1st element type)

Variable -
variable Overall Descriptor (2nd element type)

Variable -
variable Element Descriptor (1st element of 2nd element type)

Variable -n Element Descriptor (last element of last element type)

Table 14-56. Overall Descriptor Format and Element Descriptor Format

Component Name Bytes Field Name

0 Reserved

1 Reserved
Header
2-3 (MSB)
Page Length (m-3) (LSB)

Descriptor 4-m ASCII string

14.2.3.18 Device Element Status Diagnostic Page (0x0A)

Table 14-57. Device Element Status Page Format

Component Name Bytes Field Name

0 Page Code (0x0A)

1 Reserved
Page Header
2-3 (MSB)
Page Length (n-3) (LSB)

Generation Code 4-7 Generation Code (0x00 0x00 0x00 0x00)

8-n Additional Element Status descriptor

Currently this page supports three additional element status descriptors: Drive descriptor, ES Electronics and SAS
Expander descriptor.
Table 14-58. Additional Element Status Descriptor with EIP Bit

Byte\Bit 7 6 5 4 3 2 1 0

0 Invalid Reserved EIP(1b) Protocol Identifier

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Byte\Bit 7 6 5 4 3 2 1 0

1 Additional Element Status Descriptor Length

2 Reserved EIIOE

3 Element Index

4
Protocol-specific information
x

Invalid: This bit is set 1 when the content of protocol-specific information is invalid.
EIP: This bit is set 1 to indicate the element index is present, only supports EIP is set to 1.
Protocol Identifier: The value reports the identification of the device protocol.
EIIOE: The EIIOE (Element Index Includes Overall Elements) field indicates if the position includes overall status
elements. An EIIOE bit set to one indicates that the ELEMENT INDEX field in table is based on the position in
the status descriptor list of the Enclosure Status diagnostic page including overall status elements and the OTHER
ELEMENT INDEX fields. An EIIOE bit set to zero indicates that the ELEMENT INDEX field is based on the position in
the status descriptor list of the Enclosure Status diagnostic page excluding overall status elements.
Element Index: The value indicates which descriptor is describing.
Table 14-59. Protocol-Specific Information with Drive Descriptor

Zx 7 6 5 4 3 2 1 0

0 Number Of PHY Descriptors

1 Descriptor Type(00b) Reserved Not All PHYs

2 Reserved

3 Device Slot Number

4
PHY Descriptor (first)
31

.. ….

z-27
PHY Descriptor (last)
z

Number of PHY Descriptors: This field reports how many PHYs are described.
Descriptor Type: This field must be set to 00 for drive descriptor.
Not All PHYs: This field indicates all PHYs of the SATA or SAS device should be described or not.
Device Slot Number: This field indicates the device slot number.
Table 14-60. PHY Descriptor Detail

Byte\Bit 7 6 5 4 3 2 1 0

0 Reserved Device Type Reserved

1 Reserved

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Byte\Bit 7 6 5 4 3 2 1 0

SSP STP SMP

2 Reserved Initiator Initiator Initiator Reserved
Port Port Port

SATA Port SSP STP SMP SATA

3 Reserved
Selector Target Port Target Port Target Port Device

4
Attached SAS Address
11

12
SAS Address
19

20 PHY Identifier

21
Reserved
27

Table 14-61. Protocol-Specific Information with SAS Expander Descriptor

Byte\Bit 7 6 5 4 3 2 1 0

0 Number Of Expander PHY Descriptors

1 Descriptor Type(01b) Reserved

2
Reserved
3

4
SAS Address
11

12
Expander PHY Descriptor (first)
13

… ……

y-1
Expander PHY Descriptor (last)
y

Number of Expander PHY Descriptors: This field reports how many expander PHYs are described.
Descriptor Type: This field must be set to 01 for SAS Expander descriptor.
SAS Address: This field indicates the SAS address of expander.
Table 14-62. Expander PHY Descriptor

Byte\Bit 7 6 5 4 3 2 1 0

0 Connector Element Index

1 Other Element Index

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Connector Element Index: This field indexes the mechanical connector number.
Other Element Index: The field indexes the array device element.

14.2.3.19 Supported Diagnostics Page (0x0D)

This page allows the host application to determine what page types are supported by the expander device in the
range of 0x1 ~ 0x2F.
Table 14-63. Supported Diagnostics Page Format

Component Name Bytes Field Name

Page Header 0 Page Code (0x0D)

1 Reserved (0x00)

2-3 (MSB)
Page Length (n-3) (LSB)

Supported Pages 4-n Supported Pages – a list of page codes in range of 0x1 ~
0x2F

14.2.3.20 Download Microcode Control Diagnostic Page(0x0E)

Table 14-64. Download Microcode Control Diagnostic Page

Byte \ Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (0x0E)

1 Reserved(0x00)

2 PAGE LENGTH (n-3) (MSB)

3 PAGE LENGTH (n-3) (LSB)

4 Generation Code

7 Generation Code

8 Download Microcode Mode

9 Reserved

10 Reserved

11 Buffer ID

12 Buffer Offset(MSB)

13 Buffer Offset

14 Buffer Offset

15 Buffer Offset(LSB)

16-19 Microcode Image Length(MSB)

17 Microcode Image Length

18 Microcode Image Length

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Byte \ Bit 7 6 5 4 3 2 1 0

19 Microcode Image Length(LSB)

20 Microcode Data Length(m-23)(MSB)

21 Microcode Data Length(m-23)

22 Microcode Data Length(m-23)

23 Microcode Data Length(m-23)(LSB)

24 Microcode Data

… …

m Microcode Data

m+1 PAD(if needed)

… PAD(if needed)

n PAD(if needed)

Download Microcode Mode: SXP firmware support the following three modes.
• Mode 0x07: Download microcode with offsets, save, and activate.
• Mode 0x0E: Download microcode with offsets, save, and defer activation.
• Mode 0x0F: Activate deferred microcode. The page will cause a reset of SXP, and new microcode will be
executed.
Buffer Offset: the current offset in bytes within the firmware image.
Microcode Image Length: the total number of bytes in the firmware image.
Microcode Data Length: the number of bytes in the Microcode Data field.
PAD: fill the field so that the total length of the page is a multiple of four bytes.

14.2.3.21 Download Microcode Status Diagnostic Page (0x0E)

Table 14-65. Download Microcode Status Diagnostic Page

7 6 5 4 3 2 1 0

0 PAGE CODE (0x0E)

1 Reserved(0x00)

2 PAGE LENGTH (n-3) (MSB)

3 PAGE LENGTH (n-3) (LSB)

4 Generation Code(0x00)

7 Generation Code(0x00)

8 Download microcode status descriptor (See the following table)

… …

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Table 14-66. Download Microcode Status Descriptor

Byte \ Bit 7 6 5 4 3 2 1 0

0 Reserved(0x00)

1 Subenclosure Identifier(0x00)

2 Subenclosure Download Microcode Status

3 Subenclosure Download Microcode Additional Status(0x00)

4 Subenclosure Download Microcode Maximum Size (MSB)

… …

7 Subenclosure Download Microcode Maximum Size (LSB)

8 Reserved

9 Reserved

10 Reserved

11 Subenclosure Download Microcode Expected Buffer ID

12 Subenclosure Download Microcode Expected Buffer Offset(MSB)

… …

15 Subenclosure Download Microcode Expected Buffer Offset(LSB)

Subenclosure Download Microcode Status: the status of download microcode operation. Firmware may return one of
the following values, depending on the Download Microcode Control diagnostic page and the download operation.
00h: No download microcode operation in progress.
01h: Download in progress.
10h: Download complete with no error, and firmware begins using new microcode after returning this page.
11h: Download complete with no error, and firmware begins using new microcode after the next hard reset or power
on.
13h: Download complete with no error, firmware begins using new microcode after hard reset, power on, or
processing a Download Microcode Control diagnostic page specifying the Activate Deferred Microcode mode.
80h: Error in one or more of the Download Microcode Control diagnostic page fields, new microcode discarded.
81h: CRC checksum error, new microcode discarded.
84h: Internal error in the download microcode operation.
85h: Try to activate the deferred microcode when there is no deferred microcode.

14.2.3.22 Subenclosure Nickname Control Diagnostics Page (0x0F)

This page allows the host application to transmit a text string to the enclosure service process to serve as the
nickname for the specified subenclosure.

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Table 14-67. Subenclosure Nickname control Diagnostics Page Format

Component Name Bytes Field Name

Page Header 0 Page Code (0x0F)

1 Subenclosure Identifier

2–3 (MSB)
Page Length (n-3) (LSB)

Generation Code 4–7 Generation Code (0x00 0x00 0x00 0x00)

Subenclosure Nickname 8~39 ASCII String

14.2.3.23 Subenclosure Nickname Status Diagnostics Page (0x0F)

The Subenclosure Nickname Status diagnostic page returns the nicknames of each subenclosure to the host. The
status page is read by the RECEIVE DIAGNOSTIC RESULTS command. The following table describes the format of
SES Nickname Status Diagnostic page.
Table 14-68. Subenclosure Nickname Status Diagnostics Page Format

Component Name Bytes Field Name

Page Header 0 Page Code (0x0F)

1 Number of secondary Subenclosures

2–3 (MSB)
Page Length (n–3) (LSB)

Generation Code 4–7 Generation Code (0x00 0x00 0x00 0x00)

Subenclosure nickname status descriptor (primary

8~47 subenclosure)

Subenclosure Nickname n–39 ~ n Subenclosure nickname status descriptor (last subenclosure)

The NUMBER OF SECONDARY SUBENCLOSURES field indicates the number of secondary subenclosure
nickname status descriptor values that are included, not including the primary subenclosure. The NUMBER
OF SECONDARYSUBENCLOSURES field must be set to the same value as the NUMBER OF SECONDARY
SUBENCLOSURES field in the Configuration Diagnostic Page.
Table 14-69. Subenclosure Nickname Status Descriptor Format

Component Name Bytes Field Name

Page Header 0 Reserved

1 Subenclosure Identifier

2 Subenclosure Enclosure Nickname status

Generation Code 3 Subenclosure Enclosure Nickname additional status

Reserved 4–5 Reserved (0x00, 0x00)

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Component Name Bytes Field Name

(MSB)
6–7 SUBENCLOSURE NICKNAME LANGUAGE CODE (LSB)

8–39 Subenclosure Nickname

The SUBENCLOSURE IDENTIFIER field indicates the subenclosure to which the subenclosure nickname status
descriptor applies.
The SUBENCLOSURE NICKNAME STATUS field indicates the status of nickname operations for the subenclosure
and is defined in the following table. After reporting a non-zero value, the enclosure services process must set
the SUBENCLOSURE NICKNAME STATUS field to 00h and set the SUBENCLOSURE NICKNAME ADDITIONAL
STATUS field to 00h.
Table 14-70. Subenclosure Nickname Status Field

Code Description

0x00 No errors

0x80 Error in one or more of the Subenclosure Nickname Control diagnostic page fields. The SUBENCLOSURE
NICKNAME ADDITIONAL STATUS field must be set to the offset of the lowest byte of the field in the
Subenclosure Nickname Control Diagnostic Page that has an error.

0x81 Internal error. The nickname is lost.

0x82 Internal error. The previous nickname preserved.

All Reserved
others

14.2.3.24 SXP-Specific Diagnostics Page for SAS (0x3F)

The diagnostics page for SAS (page code 0x3F) conforms to the format in [3]. The page currently only supports the
CJTPAT/JTPAT/Scrambled_0 option for the PHY TEST PATTERN field. The PHY IDENTIFIER field accepts values in
the range of 0x00 to (PHY_COUNT- 1) set in the initialization string.

14.2.3.25 EMM System Event Log Retrieval Page (0x80)

The RECEIVE DIAGNOSTIC RESULTS command with a vendor specific page code of 0x80 returns the EMM system
event log. The Event log is in binary format and is passed from the SEP using RECEIVE DIAGNOSTIC RESULTS
Command with a page code of 0x80.
For a SAS transport layer, the maximum size of a packet, including all headers, is 1K bytes. For an FC transport
layer, the maximum size of a packet, not including the FC header, is 2K bytes (or the configured FC frame size). No
pre-processing on the log is required, all relevant data is already compiled into this packet. Each entry is 16 bytes
long with a timestamp included.
Note that reading the event log through the System Event Log Retrieval Page is destructive and the host needs to
make sure to store this information after retrieval. Some events associated with retrieving the log may themselves be
included in the log information.

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Table 14-71. EMM System Event Log Retrieval Page Format

Component Bytes Field

Page Header 0 Page code (0x80)

1 Reserved (0x00)

2–3 (MSB)
Page Length (n-3) (LSB)

Event/Error Log Header 4–31 General Enclosure Information

Event/Error Log Data 32–n Event Log data

When the SEP receives the event log retrieval command, it will prepare for event log retrieval by taking a snapshot
of the current event log to avoid interfering with the normal I/O operations. At this time the firmware will construct the
event log header and send it with the packet.
EMM Event Log Header
The data that is retrieved from the SEP is stored in a single file. The file must consist of a header followed by the
application firmware in a binary format. The event log header and data are displayed in the following table:
Table 14-72. EMM Event Log Header Format

Byte Offset Data Description

Event/Error Log Header 4–11 ASCII Vendor ID

12 HEX Product ID

13 HEX Hardware Rev

14–17 ASCII Firmware Rev

18–19 HEX Event Log Length

20–23 HEX Event Log checksum

24–31 HEX Reserved

Event/Error Log Data 32–n HEX Event Log data

Vendor ID: The Vendor ID is an 8-byte string and “VENDOR” is used to identify the log.
Product ID: The Product ID is used to check the product’s log and see what enclosure it came from. This field
currently reports 0x03.
Hardware Rev: The Hardware Rev is used to identify which hardware generated the log.
Firmware Rev: The Firmware Rev is used to identify this firmware’s revision.
Event Log Length: The length of the error log data returned through this page, which does not include header bytes.
Event Log Checksum: The event log checksum is the 32-bit sum of all event log data, which does not include
header bytes. The checksum is generated like the Tag Data Checksum.
Log Entry Format: IPMI events are reported in IPMI format, non-IPMI events are reported in an IPMI like format.

14.2.3.26 SES Delay Test Page (0x81)

This page causes a delay in the response to the host. It is for testing purposes.

Protocol Stack Library

Table 14-73. SES Delay Test Page

Byte/Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (0x81)

1 Reserved(0x00)

2 PAGE LENGTH (n–3) (MSB)

3 PAGE LENGTH (n–3) (LSB)

4 Delay Time (ms) (MSB)

5 Delay Time (ms) (LSB)

The fields in this page are defined as:

• Delay Time: Number of ms for the delay.

14.2.3.27 SXP Firmware Status Page (0x82)

Table 14-74. SXP Firmware Status Page

20-23 Inactive Data Image Revision Number

24-27 EEPROM Data Image Revision Number

28-31 Bootloader Image Revision Number

32 EMIP Microcode Revision(MSB)

33 EMIP Microcode Revision

34 EMIP Microcode Revision

Protocol Stack Library

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Byte \ Bit 7 6 5 4 3 2 1 0

35 EMIP Microcode Revision(LSB)

36 BCT Microcode Revision(MSB)

37 BCT Microcode Revision

38 BCT Microcode Revision

39 BCT Microcode Revision(LSB)

40-43 Watchdog Reload Value

44-47 Watchdog Lowest Value

48-51 Application Log Start Address

52-55 Application Log Length

The fields in this page are defined as:

• Active/Inactive Firmware Image Partition ID: The partition number of the active/inactive image.
• Active/Inactive Data Image Partition ID: The partition number of the active/inactive data.
• Image Valid: Indicates whether the image is valid or not. If set to:
– 1: The partition contains a valid image with correct CRC value.
– 0: The partition contains either an invalid image with incorrect CRC value or an incomplete image which is
unsafe for ECC while accessing the partition.
• Active/Inactive Firmware Image Revision Number: The revision number of the active/Inactive firmware image.
The revision number is set to 0xffffffff if the Image Valid is 0.
• Active/Inactive Data Image Revision Number: The revision number of the active/Inactive data image. The
revision number is set to 0xfffffffff if the Image Valid is 0.
• EEPROM Data Image Revision Number: Retrieves the initialization string table revision number from the
EEPROM if enabling EEPROM initialization string. Otherwise, the revision number is set to 0xffffffff. By default
the revision info uses big endianness.
• Bootloader Image Revision Number: The revision number of the bootloader, default value is 0xffffffff.
• EMIP Microcode Revision: EMIP Microcode version. The bits[23:16] is the major number, the bits[15:8] is the
minor number and the bits[7:0] is the subminor number.
• BCT Microcode Revision: BCT Microcode version, the Bits [31:16] are unused. The bits[15:14] is the major
number, the bits[13:8] is the minor number and the bits[7:0] is the subminor number.
• Watchdog Reload Value: Hardware watchdog timer reload count.
• Watchdog Lowest Value: Lowest hardware watchdog counter value since reset. The lower the value, the higher
the system loading.
• Application Log Start Address: Get the applications log start address.
• Application Log Length: Get the applications log start length.

14.2.3.28 PHY Analog Setting Control Page (0x83)

The SES PHY Analog Setting Control page provides the interface for the host application to adjust the PHY Analog
Settings for the SXP PHYs. The page supports the following maximum number of PHY Analog Setting Descriptors:
• 68 for the PM8056
• 48 for the PM8055
• 36 for the PM8054 and the PM8044
• 24 for the PM8053 and the PM8043
1. The page format is defined in L (LINK RESET) to reset the PHY.

Protocol Stack Library

2. and the PHY Analog Setting Descriptor is defined in Table 14-76. Firmware configures the PHY analog setting
for the PHY according to the parameters in the each descriptor. The analog setting sequence is as follows:
3. Firmware disables the PHY in both the MTSB and SSPL.
4. Firmware applies the analog settings to the MTSB and SSPL registers accordingly.
5. If the ENABLE_PHY bit in the descriptor is ‘1’, firmware then automatically enables the MTSB and SSPL in the
corresponding PHY. Otherwise, the PHY stays in PHY disabled state until the host application can issue SMP
PHY CONTROL (LINK RESET) to reset the PHY.
Table 14-75. PHY Analog Setting Page Format

Byte\Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (83h)

1 Reserved

2 (MSB)
PAGE LENGTH (33*n)
3 (LSB)

4 (MSB)
PHY 0 ANALOG SETTING DESCRIPTOR
36 (LSB)

...

33*n-29 (MSB)
PHY n-1 ANALOG SETTING DESCRIPTOR
33*n+3 (LSB)

Table 14-76. PHY Analog Setting Descriptor Format

Byte\Bit 7 6 5 4 3 2 1 0

ENABLE_
0 PHY ID
PHY

1 Reserved

SNW3_SS
2 PHY RATE
C_TYPE

G4_W_SS G4_WO_S G3_W_SS G3_WO_S G2_W_SS G2_WO_S G1_W_SS G1_WO_S

3
C SC C SC C SC C SC

LOS
4 Reserved CTRL LOS REFAMP_SAS
SAS

RX PEAK LOS
5 ENB SATA Reserved CTRL LOS REFAMP SATA
6G SATA

RX PEAK RX PEAK
6 ENB ENB Reserved RX PEAK SAS
SAS1 3G SAS1 1G5

RX PEAK RX PEAK
7 ENB SATA ENB SATA RX PEAK SATA 6G RX PEAK SATA 1G5 3G
3G 1G5

Protocol Stack Library

...........continued
Byte\Bit 7 6 5 4 3 2 1 0

T PISO
8 PRE2 SEL AMPLITUDE SAS 1G5
SAS 1G5

T PISO
9 PRE2 SEL AMPLITUDE SAS 3G
SAS 3G

T PISO
10 PRE2 SEL AMPLITUDE SAS2 6G
SAS2 6G

T PISO
11 PRE2 SEL AMPLITUDE SATA 1G5
SATA 1G5

T PISO
12 PRE2 SEL AMPLITUDE SATA 3G
SATA 3G

T PISO
13 PRE2 SEL AMPLITUDE SATA 6G
SATA 6G

T PISO T PISO
EDGE EDGE
14 DELAY DELAY POSTCURSOR SAS 1G5
SEL SATA SEL SAS
1G5 1G5

T PISO T PISO
EDGE EDGE
15 DELAY DELAY POSTCURSOR SAS 3G
SEL SATA SEL SAS
3G 3G

T PISO T PISO
EDGE EDGE
16 DELAY DELAY POSTCURSOR SAS2 6G
SEL SATA SEL SAS2
6G 6G

TRS TXCLK SEL SATA

17 POSTCURSOR SATA 1G5
1G5 SSC

TRS TXCLK SEL SATA

18 POSTCURSOR SATA 3G
3G SSC

TRS TXCLK SEL SATA

19 POSTCURSOR SATA 6G
6G SSC

20 Reserved PRECURSOR SAS 1G5

21 Reserved PRECURSOR SAS 3G

Protocol Stack Library

...........continued
Byte\Bit 7 6 5 4 3 2 1 0

T PISO
PRE2
22 Reserved PRECURSOR SAS2 6G
MODE1
SAS2 6G

23 Reserved PRECURSOR SATA 1G5

24 Reserved PRECURSOR SATA 3G

T PISO
PRE2
25 Reserved MODE1 PRECURSOR SATA 6G
SATA
6G(6)

SAS12G
TX BCT
PGA TX Cx BCT PRST
26 Reserved EN SAS3 Reserved
BOOST DFLT
12G
EN

27 TX C1 NON BCT

28 TX C2 NON BCT

29 TX C3 NON BCT

30 TX C1 BCT START POINT

31 TX C2 BCT START POINT

32 TX C3 BCT START POINT

PHY ID: Specifies the PHY to which the PHY analog setting in this descriptor will be applied.
ENABLE_PHY: If this bit in the descriptor is ‘1’, firmware automatically enables the corresponding PHY. Otherwise,
the PHY stays in PHY disabled state until the host application can issue SMP PHY CONTROL (LINK RESET) to
reset the PHY.
SNW3_SSC_TYPE: Indicates the SNW3 PHY capability SSC type. See SPL2r05 Table 53 SNW-3 PHY capabilities.
PHY RATE: Sets the PHY rate to 12G, 6G, 3G and 1.5G. See Table 8-11.
G4_W_SSC, G4_WO_SSC, G3_W_SSC, G3_WO_SSC, G2_W_SSC, G2_WO_SSC, G1_W_SSC,G1_WO_SSC:
See Table 8-12 and refer SPL2r05 Table 8-16 SNW-3 PHY capabilities.
OTHERS: The other fields have the same definition.

14.2.3.29 PHY Analog Setting Status Page (0x83)

1. The SES PHY Analog Setting Status page provides the interface for the host application to retrieve the PHY
Analog Settings for the SXP PHYs. The page format is the same as the PHY Analog Setting Control Page
described in L (LINK RESET) to reset the PHY.

14.2.3.30 Vhist Capture Control Page (0x84)

Table 14-77. Vhist Capture Control Page

Byte \ Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (0x84)

1 Reserved(0x00)

Protocol Stack Library

...........continued
Byte \ Bit 7 6 5 4 3 2 1 0

2 PAGE LENGTH (n-3) (MSB)

3 PAGE LENGTH (n-3) (LSB)

4 Force restart

5 Logical PHY Bit Map MSB

6 Logical PHY Bit Map

7 Logical PHY Bit Map

8 Logical PHY Bit Map

9 Logical PHY Bit Map

10 Logical PHY Bit Map

11 Logical PHY Bit Map

12 Logical PHY Bit Map

13 Logical PHY Bit Map

14 Logical PHY Bit Map LSB

15 Sample points MSB

16 Sample points

17 Sample points

18 Sample points

19 Sample points LSB

The fields in this page are defined as:

• Force restart: Since each Vhist Capture process contains 1 control page and 8 Vhist capture status pages, each
Vhist capture status page is related to a data collecting step. If the former process is not done, firmware will not
permit another Vhist capture process if this bit is set to 0 in a normal case. If this bit is set to 1, firmware will
force a restart of another Vhist capture process and drop the former process, if one exists.
• Logic PHY Bit Map: This field contains 10 bytes like the logic PHY Bit Map used in elsewhere. The number of
valid bits is the same as the number of PHYs contained or retained by the init-string setting.
• Sample Points: Control sample points for Vhist capture.

14.2.3.31 Vhist Capture Status Page (0x84)

Table 14-78. Vhist Capture Status Page

Byte \ Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (0x84)

1 Reserved(0x00)

2 PAGE LENGTH (n-3) (MSB)

3 PAGE LENGTH (n-3) (LSB)

Protocol Stack Library

...........continued
Byte \ Bit 7 6 5 4 3 2 1 0

4 Vhist Capture Status

5 PHY Count

6 Wait Time MSB

7 Wait Time

8 Wait Time

9 Wait Time LSB

10-75 PHY Descriptor 0

PHY Descriptor 1

PHY Descriptor 2

Last PHY Descriptor

The fields in this page are defined as:

• Vhist capture status:
– Bit 3-0: Data status
• 0x00: Data ready
• 0x01: Capture in progress
• 0x02: No data (in this case, the status page will contain no fields following it in the table)
– Bit 7-4: Report status page times for this control page, value is from 1 to 8.
• PHY Count: Indicates how many PHYs perform Vhist capture.
• Wait Time: Time left until current data collecting step, unit is ms. Wait at least this time, then send a/another
Vhist capture status page.
• PHY Descriptor: Contains Vhist capture data. See the following table for detail.
Table 14-79. Vhist Capture PHY Descriptor

Byte \ Bit 7 6 5 4 3 2 1 0

0 Logical PHY ID

1 Bin Data Valid

2-9 Bin Descriptor 0

10-17 Bin Descriptor 1

18-25 Bin Descriptor 2

26-33 Bin Descriptor 3

34-41 Bin Descriptor 4

42-49 Bin Descriptor 5

50-57 Bin Descriptor 6

58-65 Bin Descriptor 7

Protocol Stack Library

The fields in this page are defined as:

• Logical PHY ID: Logical PHY number.
• Bin Data Valid:
– Bit 0: Indicates whether this bin data is valid
• 0x00: Data is not valid
• 0x01: Data is valid
– Bit 2-1: If data is not valid, indicate the reason.
• 0x00: PHY is not in ready state
• 0x01: Hardware fails
• 0x02/0x03: Reserved
• Bin Descriptor: Contains Vhist capture data for just a bin, refer to the following for detail.
Table 14-80. Vhist Capture Bin Descriptor

Byte \ Bit 7 6 5 4 3 2 1 0

0 Expected bin num

1 Read back bin num

2 overflow

3 Bin value MSB

4 Bin value

5 Bin value

6 Bin value

7 Bin value LSB

The fields in this page are defined as:

• Expected bin num: Expected bin number. This is set by firmware.
• Read back bin num: Bin number read back for hardware. User should check whether this value equals the
expected bin number.
• Overflow: Indicates whether overflow occurs when performing Vhist capture for this bin.
• Bin value: Bin value for this bin.

14.2.3.32 Port Mirroring Control Page (0x86)

Use this page to enable or disable the port mirroring function.
Table 14-81. Port Mirroring Control Page

Byte \ Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (0x86)

1 Reserved(0x00)

2 PAGE LENGTH (n-3) (MSB)

3 PAGE LENGTH (n-3) (LSB)

4 Enable

5 Port Mirroring PHY Descriptor count

6-9 Port Mirroring PHY Descriptor 0

Protocol Stack Library

...........continued
Byte \ Bit 7 6 5 4 3 2 1 0

(4*n+6) – Port Mirroring PHY Descriptor n (n <=3)

(4*n+9)

The fields in this page are defined as:

• Enable: Enable/disable port mirroring on logical PHY IDs in all port mirroring PHY descriptors. 1 = Enable, 0 =
Disable.
• Port Mirroring PHY Descriptor Count: Specify the number of port mirroring PHY descriptors to configure, range
is 0~4.
• Port Mirroring PHY Descriptor: Specify the source logical PHY ID and destination logical PHY IDs to configure.
In the SXP 12G, only the source logical PHY ID is used. The destination logical PHY IDs are ignored. Refer to
Table 14-83.

14.2.3.33 Port Mirroring Status Page (0x86)

Table 14-82. Port Mirroring Status Page

Byte \ Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (0x86)

1 Reserved(0x00)

2 PAGE LENGTH (n-3) (MSB)

3 PAGE LENGTH (n-3) (LSB)

4 Port Mirroring PHY Descriptor count

5-8 Port Mirroring PHY Descriptor 0

(4*n+5) – Port Mirroring PHY Descriptor n (n <=3)

(4*n+8)

• Port Mirroring PHY Descriptor Count: Reports the number of port mirroring PHY descriptors.
• Port Mirroring PHY Descriptor: Reports the source logical PHY ID and the destination logical PHY IDs
configured. Refer to the following table.
Table 14-83. Port Mirroring PHY Descriptor

Byte \ Bit 7 6 5 4 3 2 1 0

0 Source Logical PHY ID

1 Destination Logical PHY ID 1

2 Destination Logical PHY ID 2

3 Reserved

• Source Logical PHY ID: In the control page, this field specifies which PHY has port mirroring enabled. In the
status page, this field reports which PHY has port mirroring is enabled.
• Destination Logical PHY ID 1: Reports which TX PHYs the source logical PHY ID is mirrored to.
• Destination Logical PHY ID 2: Reports which RX PHYs the source logical PHY ID is mirrored to.

Protocol Stack Library

14.2.3.34 SXP Diagnostics Commands Page (0x90)

See Section 9.5.5 Diagnostics SES Pages for a description of this page, within the context of the SXP diagnostics
module.

14.2.3.35 SXP Diagnostics Reports SES Page (0x90)

See Section 9.5.5 Diagnostics SES Pages for a description of this page, within the context of the SXP diagnostics
module.

14.2.3.36 FWDL Partition Control Page (0x91)

Flash contains bootloader, image0, image1 space, data0, data1 partitions and bootcfg partition. The page provides a
way for host to toggle the active images and data in bootcfg partition.
Active image/data flag is saved in first and second byte of bootcfg partition, the first byte is used for the image while
the second byte is used for the data.
Table 14-84. FWDL Partition Control Diagnostic Page Format

Byte\Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (91h)

1 RESERVRD

2 (MSB) (LSB)
PAGE LENGTH (n - 3)
3

4 TOGGLE ACTIVE IMAGE PARTITION

5 TOGGLE ACTIVE DATA PARTITION

TOGGLE ACTIVE IMAGE PARTITION: Decide whether to switch between image0 and image1.
TOGGLE ACTIVE DATA PARTITION: Decide whether to switch between data0 and data1.
The following table lists how toggle active data or image partition byte affects the value written to the bootcfg
partition:
Table 14-85. Active Flag in Bootcfg Partition

IMAGE TOGGLE DATA TOGGLE Image Byte in Data Byte in bootcfg

Image
BYTE BYTE bootcfg partition partition

1 0 XOR Keep original

Images/DATA are 0 1 Keep original XOR

valid 1 1 XOR XOR

0 0 Keep original Keep original

Images/DATAs are
X X Keep original Keep original
invalid (CRC fail)

14.2.3.37 FWDL Partition Status Page (0x91)

Table 14-86. FWDL Partition Status Diagnostic Page Format

Byte\Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (91h)

1 RESERVRD

Protocol Stack Library

...........continued
Byte\Bit 7 6 5 4 3 2 1 0

2 (MSB) (LSB)
PAGE LENGTH (n - 3)
3

4 ACTIVE IMGFLAG

5 ACTIVE DATAFLAG

6 IMAGE0 CRC STATUS

7 IMAGE1 CRC STATUS

8 DATA0 CRC STATUS

9 DATA1 CRC STATUS

14.2.3.38 SXP TWI-Pass-Through Pages

The following four pages provide a closed-form expander firmware solution that allows for an arbitrary set of TWI
devices attached to the expander to be controlled and monitored by another SCSI device. Two of these pages
configure the TWI ports and report transaction statistics since the last configuration of TWI ports.

14.2.3.39 Error Handling for TWI-Pass-Through Pages

If the expander firmware cannot successfully interpret a detected TWIPT page, the expander replies to the host with
INVALID FIELD IN PARAMETER LIST.
If the expander firmware does not support a TWIPT page, the expander replies to the host with UNSUPPORTED
ENCLOSURE FUNCTION.

14.2.3.40 General TWIPT Page Behavior

• At most only one successful TWI frame is generated: write, read, or write/read per detected TWIPT Command
Send page. Additional retry pages on NACK or failed arbitration are not counted as successful TWI pages.
• Requested bytes are written before reading any requested bytes. This is done through a single write/read page.
• The TWI clock rate is set to the supported value nearest to the requested value. For example, requesting
440 kHz may result in a 400 kHz operation, and requesting 120 kHz may correspondingly result in a 100 kHz
operation. The TWIPT target rounds down.
• Firmware and TWI port hardware is reconfigured on the detection of each valid TWIPT Configuration page.

14.2.3.41 SXP-TWI Pass-Through Command Send Page (0xF0)

Table 14-87. TWIPT Command Send Page

Byte \ Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (default 0xF0)

1 Reserved

2 PAGE LENGTH (n+4) (MSB)

3 PAGE LENGTH (n+4) (LSB)

4 Reserved PORT NUMBER

5 SLAVE ADDRESS

6 WRITE LENGTH

7 READ LENGTH

Protocol Stack Library

...........continued
Byte \ Bit 7 6 5 4 3 2 1 0

n+8 WRITE DATA [n]

The fields in the page are defined as:

• PORT NUMBER is the specific TWI port to perform master cycles on.
• SLAVE ADDRESS is a 7-bit TWI slave address followed by a R/W bit in bit position 0, which is ignored. The
value in bit position 7 is transmitted first, bit 1 last.
• WRITE LENGTH contains the number of bytes to write. If too few WRITE DATA bytes in comparison to WRITE
LENGTH are presented, the page is not interpreted. If additional WRITE DATA bytes in comparison to WRITE
LENGTH are presented, these bytes are ignored.
• READ LENGTH is the number of bytes to read, after the requested bytes are written.
• Each WRITE DATA byte is treated as a big-endian value where the most significant bit is the first bit sent on the
TWI bus.
• WRITE DATA byte n is the nth byte that is sent in a TWI frame.

14.2.3.42 SXP-TWI Pass-Through Data Receive Page (0xF0)

Table 14-88. TWIPT Data Receive Page

Byte \ Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (default 0xF0)

1 Reserved

2 PAGE LENGTH (n+1) (MSB)

3 PAGE LENGTH (n+1) (LSB)

4 RESULT

n+5 READ DATA [n]

The fields in the page are described in the following list:

• RESULT returns a 0 on a successful TWI operation, 1 on a timeout and 2 on a NACK.
• READ DATA n is the nth byte that was received in a TWI frame.
• Each READ byte is a big-endian value where the most significant bit is the first bit received on the TWI bus.
• The number of READ DATA bytes in the page matches the READ LENGTH in the most recent valid TWIPT
Command Send page.

14.2.3.43 SXP-TWI Pass-Through Configuration Send Page (0xF1)

Table 14-89. TWIPT Configuration Send Page

Byte \ Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (default 0xF1)

1 Reserved

2 PAGE LENGTH (8+8*n) (MSB)

3 PAGE LENGTH (8+8*n) (LSB)

4 TIMEOUT (MSB)

5 ...

Protocol Stack Library

...........continued
Byte \ Bit 7 6 5 4 3 2 1 0

6 ...

7 TIMEOUT (LSB)

8 RETRIES

9 PORT COUNT

10 Reserved

11 Reserved

12+8*n PORT n RATE (MSB)

13+8*n ...

14+8*n ...

15+8*n PORT n RATE (LSB)

16+8*n PORT n RESET

17+8*n Reserved

18+8*n Reserved

19+8*n Reserved

The fields in the page are described in the following list:

• RETRIES is the number of automatic retries before declaring failure. If the value specified is too large the page
fails to interpret.
• TWI port configuration parameters for ports above PORT COUNT in a TWIPT Configuration page are ignored.
• TIMEOUT is the number of microseconds before aborting an attempted read or write due to arbitration failure. If
an unsupported value is specified, the page fails to interpret.
• PORT n RESET is a request to assert a TWI RESET pin on TWI port n for PORT n RESET milliseconds. If an
unsupported value is specified, the page fails to interpret.
• PORT n RATE is the desired TWI clock rate, in kHz. If an unsupported value is specified, the page fails to
interpret.
• PORT COUNT is the number of TWI ports on the SES target. If this value does not match PORT COUNT in a
TWIPT Configuration Receive Diagnostic page, the page fails to interpret.

14.2.3.44 SXP-TWI Pass-Through Configuration Receive Page (0xF1)

Table 14-90. TWIPT Configuration Receive Page

Byte \ Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (default 0xF1)

1 Reserved

2 PAGE LENGTH (20+4*n) (MSB)

3 PAGE LENGTH (20+4*n) (LSB)

4 TIMEOUT (MSB)

5 ...

Protocol Stack Library

...........continued
Byte \ Bit 7 6 5 4 3 2 1 0

6 ...

7 TIMEOUT (LSB)

8 IDENTIFIER

9 FORMAT VERSION

10 MAX RETRIES

11 PORT COUNT

12 MAX READ LENGTH

13 MAX WRITE LENGTH

14 MAX RESET

15 Reserved

16 MAX RATE (MSB)

17 ...

18 ...

19 MAX RATE (LSB)

20 MAX TIMEOUT (MSB)

21 ...

22 ...

23 MAX TIMEOUT (LSB)

24+4*n PORT n RATE (MSB)

25+4*n ...

26+4*n ...

27+4*n PORT n RATE (LSB)

The fields in the page have the following meaning and behavior:
• TIMEOUT reports the current timeout setting.
• IDENTIFIER returns 1
• FORMAT VERSION returns 1
• MAX RETRIES returns the maximum possible number of retries before abandoning a single TWI frame.
• MAX WRITE LENGTH returns the maximum possible number of bytes written in a single TWI frame.
• MAX READ LENGTH returns the maximum possible number of bytes read in a single TWI frame.
• PORT COUNT returns the total number of TWI ports on this SES target.
• MAX RATE returns the maximum supported TWI clock speed supported in a TWIPT Configuration Send
Diagnostic frame.
• MAX RESET returns the maximum length of a RESET pulse supported in a TWIPT Configuration Send
Diagnostic frame.

Protocol Stack Library

• MAX TIMEOUT returns the maximum timeout value supported in a TWIPT Configuration Send Diagnostic
frame.
• PORT n RATE reports the current TWI clock rate for port n.

14.2.3.45 SSSF PHY Configuration Page (0xF3)

The SSSF PHY configuration SES page provides the interface for the host application to adjust SSSF PHY
configurations for each SXP PHY. This SES page consists of two parts just like the SSSF PHY Configurations in
the initstring (see Table 8-9) which consists of the global SSSF PHY Configuration and the per PHY SSSF PHY
Configuration. Table 14-91 SSSF PHY Configuration Page Format also defines the global SSSF PHY Configuration.
Table 14-92 SSSF PHY Configuration Descriptor Format defines the per PHY SSSF PHY Configuration. Firmware
configures the SSSF PHY configurations dynamically according to the parameters in global SSSF PHY configuration
and in each SSSF PHY Configuration descriptor. This page supports the maximum number of SXP PHY descriptors,
that is, 68 for the PM8056, 48 for the PM8055, 36 for the PM8054, 36 for the PM8044, 24 for the PM8053 and 24 for
the PM8043.
Table 14-91. SSSF PHY Configuration Page Format

Byte\Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (F3h)

1 RESERVED

2 (MSB)
PAGE LENGTH (16*8*n)
3 (LSB)

Per PHY Global

4 RESERVED Setting Setting
Valid Valid

5 (MSB) (LSB)
TMF Tag0
6

7 (MSB) (LSB)
TMF Tag1
8

9 (MSB) (LSB)
The SAS Buffering Initiator Retry Timeout
10

Xopen Multi- LUN

11 RESERVED
Detect En En

12 RESERVED

13 RESERVED

14 RESERVED

15 RESERVED

SATA
Buffering
16 RESERVED RESERVED Link Reset
Error PHY
Enable

17 RESERVED

Protocol Stack Library

...........continued
Byte\Bit 7 6 5 4 3 2 1 0

18 RESERVED

19 RESERVED

20 RESERVED

21 RESERVED

22 RESERVED

23 RESERVED

24 RESERVED

25 RESERVED

26 RESERVED

27 RESERVED

28 RESERVED

29 RESERVED

30 (MSB)
SSSF PHY 0 CONFIGURATION DESCRIPTOR
37 (LSB)

...

30+8*n (MSB)
SSSF PHY n–1 CONFIGURATION DESCRIPTOR
30+8*n+7 (LSB)

Global setting Valid: This bit indicates whether the global setting is valid. If it is valid, the global settings are applied
to each PHY specified by each SSSF PHY configuration descriptor.
Per phy setting Valid: This bit indicates whether the per PHY setting is valid. If it is valid, each per PHY setting is
applied to the PHY specified by the SSSF PHY configuration descriptor.
For other fields, refer to the related field in Table 8-9. They have the same usage.
Table 14-92. SSSF PHY Configuration Descriptor Format

Byte\Bit 7 6 5 4 3 2 1 0

Take effect
0 immediatel PHY ID
y

SAS/SATA
1 RESERVED Uncorrectable ECC control Buffering
Enable

Protocol Stack Library

...........continued
Byte\Bit 7 6 5 4 3 2 1 0

12G
6G/3G SAS
SAS Connectio
Connection Buffering SAS SAS
Buffering n
2 RESERVED Manageme OAF Early Buffering Buffering
Snoop Managem
nt Accept 6G 3G
TMF ent
Enable enable
Enable

3 RESERVED

4 Maximum Frame Count

SATA SATA
5 RESERVED Buffering Buffering
6G 3G

6 RESERVED

7 RESERVED

PHY_ID: This field specifies the PHY ID to be configured with the global and per PHY SSSF PHY configurations.
Uncorrectable ECC control: This field controls the SXP’s handling of the PHY with an uncorrectable error in the
buffer RAM:
• 0x0: General PHY configuration. The configuration fields are valid for the special PHY ID;
• 0x1: Scan the corresponding PHY’s buffer RAM. This can be used when the corresponding PHY’s buffer RAM
has detected an uncorrectable ECC error. The HOST can use the SES SSSF page (See Table 14-94) to poll the
scan result. The other configuration fields are invalid when this control field is set to 0x1;
• 0x2: Clear the uncorrectable SSSF ECC error flag on the corresponding PHY. This can be used when the
corresponding PHY’s buffer ram has detected an uncorrectable ECC error. The other configuration fields are
invalid when this control field is set to 0x2;
• 0x3: Reset EMIP for the corresponding PHY. This can be used when the corresponding PHY’s EMIP has
detected an uncorrectable ECC error. The other configuration fields are invalid since this control field is set to
0x3;
• 0x4: Clear the SXL uncorrectable ECC error flag on the corresponding PHY. This can be used when the
corresponding PHY’s SXL has detected an uncorrectable ECC error. The other configuration fields are invalid
since this control field is set to 0x4;
• 0x5-0x7: Reserved.;
Take effect immediately: This bit indicates whether to take the SSSF PHY configurations in the SES page effect
immediately on this PHY. If this bit in the descriptor is ‘1’, firmware automatically triggers a link reset on this PHY.
Otherwise, the SSSF PHY configurations in the SES page will be not taken effect until a PHY NOT READY event
is detected on this phy. Please note that in topologies where expander attached drives are part of a RAID volume,
dynamically enabling/disabling buffering will cause link reset which could lead to loss of RAID volumes. Hence, it is
not recommended to dynamically enable or disable buffering in such scenarios.
For other fields, refer to the related field. They have the same usage.

Protocol Stack Library

Value
Defau
Byte \ Bit 7 6 5 4 3 2 1 0 Rang
lt
e

Async
Break Reply Recover Invert Invert No Disable Bit
Reserved 0x00
Enable y TX RX SATA PHY Fields
Disable

PHY
rate
0x0230 – {1, 2,
0x025F 3, 4,
(L_PHY0 6,
Info) 7,8,10
Max SATA Rate PHY Rate 0x4F ,11,12
,14,15
} Max
SATA
rate
{0, 1,
2, 4}

G4
G4 G3 G2 G2 G1 G1
WITHO
WITH G3 WITH SSC WITHO WITH WITHO WITH WITHO 0xFF
UT
SSC UT SSC SSC UT SSC SSC UT SSC
SSC

RX 3
TX 3 ID
ID
TX_ID_FRAME_GAP FRAME 0xC0
FRAM
S
ES

TX SSC
Down-
Reserved 0x00
Spread
Type

0x00–
STP Bridge AWT MSB 0x00
0xFF

0x00–
STP Bridge AWT LSB 0x00
0xFF

0x00
Connection Policing Timer 0x00 –
0xFF

STP/S
Disable AS
Power Advanc ALIG
Broad-cast
Disable e SATA Reserve STP Align N
change SAS Align Density 0x00
Support Sync d Density densit
Suppress
ed Forwar y
d {0, 1,
2}

Reserved 0x00

Protocol Stack Library

...........continued
Value
Defau
Byte \ Bit 7 6 5 4 3 2 1 0 Rang
lt
e

LOS CTRL
Reserved LOS REFAMP SAS[4:0] 0x12
SAS

RX
PEAK LOS REFAMP SATA[4:0]
Reserv LOS CTRL
ENB 0x09
ed SATA 0x09
SATA
6G

RX RX
PEAK PEAK
ENB ENB Reserved RX PEAK SAS[2:0] 0x01
SAS1 SAS1
3G 1G5

RX RX
PEAK PEAK
ENB ENB RX PEAK SATA 6G[5:3] RX PEAK SATA 1G5 3G[2:0] 0x29
SATA SATA
3G 1G5

T PISO
PRE2
SEL AMPLITUDE SAS 1G5 [6:0] 0x36
SAS
1G5

T PISO
PRE2
AMPLITUDE SAS 3G [6:0] 0x36
SEL
SAS 3G

T PISO
PRE2
SEL AMPLITUDE SAS2 6G [6:0] 0x40
SAS2
6G

T PISO
PRE2
SEL AMPLITUDE SATA 1G5 [6:0] 0x1C
SATA
1G5

T PISO
PRE2
SEL AMPLITUDE SATA 3G [6:0] 0x1C
SATA
3G

T PISO
PRE2
SEL AMPLITUDE SATA 6G [6:0] 0x30
SATA
6G

Protocol Stack Library

...........continued
Value
Defau
Byte \ Bit 7 6 5 4 3 2 1 0 Rang
lt
e

T PISO
EDGE
T PISO EDGE
DELAY
DELAY SEL POSTCURSOR SAS 1G5 [5:0] 0xC0
SEL
SAS 1G5
SATA
1G5

T PISO
EDGE
T PISO EDGE
DELAY
DELAY SEL POSTCURSOR SAS 3G [5:0] 0xC0
SEL
SAS 3G
SATA
3G

T PISO
EDGE
T PISO EDGE
DELAY
DELAY SEL POSTCURSOR SAS2 6G [5:0] 0x0D
SEL
SAS2 6G
SATA
6G

TRS TXCLK SEL SATA

POSTCURSOR SATA 1G5 [5:0] 0x00
1G5 SSC

TRS_TXCLK SEL SATA

POSTCURSOR SATA 3G [5:0] 0x00
3G SSC

TRS TXCLK SEL SATA

POSTCURSOR SATA 6G [5:0] 0x05
6G SSC

Reserved PRECURSOR SAS 1G5[5:0] 0x00

Reserved PRECURSOR SAS 3G [5:0] 0x00

T PISO PRE2
Reserve
MODE1 SAS2 PRECURSOR SAS2 6G [5:0] 0x40
d
6G

Reserved PRECURSOR SATA 1G5 [5:0] 0x00

Reserved PRECURSOR SATA 3G[5:0] 0x00

T PISO PRE2
Reserve
MODE1 SATA PRECURSOR SATA 6G[5:0] 0x40
d
6G

SAS12G
PGA TX Cx BCT Reserve TX BCT EN SAS3
Reserved 0x44
BOOST PRST DFLT d 12G
EN

TX C1 NON BCT 0xFF

TX C2 NON BCT 0x33

TX C3 NON BCT 0xF4

Protocol Stack Library

...........continued
Value
Defau
Byte \ Bit 7 6 5 4 3 2 1 0 Rang
lt
e

TX C1 BCT START POINT 0xFB

TX C2 BCT START POINT 0x33

TX C3 BCT START POINT 0xF8

SAS/
SATA
Reserved 0x00
Buffering
Enable

SAS
SAS 12G
Bufferi 6G/3G
Buffering Connection SAS
ng SAS
Reserve Connection OAF Managemen Buffering
Snoop Buffering 0x02
d Management Early t
TMF 6G 3G
Accept
Enabl Enable Enable
Enable
e

Reserved 0x00

Maximum Frame Count 0x16

SATA
SATA
Reserved Reserved Buffering 0x02
Buffering 6G
3G

Reserved 0x00

Reserve
DP FFE M PRELOAD SAS3 12G 0x1F
d

Reserved Test Threshold 0x0C

0x0260 – Same
0x028F as
Structure content is the same as that for L_PHY0 Info
(L_PHY1 L_PH
Info) Y0

0x0290 –
0x0EBF
(L_PHY3 – … …
L_PHY66
Info)

0x0EC0 – Same
0x0EEF as
Structure content is the same as that for L_PHY0 Info
(L_PHY67 L_PH
Info) Y0

0x0EF0 –
Reserved 0x00
0x0112F

Protocol Stack Library

...........continued
Value
Defau
Byte \ Bit 7 6 5 4 3 2 1 0 Rang
lt
e

PHY
reset PHY reset in progress timeout
0x020C timeout 0x0F
handling 0x0F
Enable

14.2.3.46 SSSF PHY Status Page (0xF3)

The SSSF PHY Status SES page provides the interface for the host application to get SSSF PHY status for all SXP
PHYs, that is, 68 for the PM8056, 48 for the PM8055, 36 for the PM8054, 36 for the PM8044, 24 for the PM8053 and
24 for the PM8043.
Table 14-93. SSSF PHY Status Page Format

Byte\Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (F3h)

1 RESERVED

2
PAGE LENGTH (8*phy count)
3

Table 14-94. SSSF PHY Status Descriptor Format

7 6 5 4 3 2 1 0

RESERVE
0 PHY ID
D

1 SXL Link rate SSPL Link rate

2 RESERVED Buffer ram scan state PHY working mode

3 Maximum Frame Count

Multi- Host SXL

Multi-Host SSSF ram EMIP
A/A Xopen uncorrecta
4 RESERVED A/A Xopen RSVD uncorrecta uncorrectab
Deadlock ble ecc
Detect ble ecc le ecc error
Detect error

SSSF split
5 RESERVED
mode

6 Multi-Host A/A Xopen Deadlock Hit Count[15:8]

7 Multi-Host A/A Xopen Deadlock Hit Count[7:0]

PHY_ID: This field specifies the PHY ID of the SSSF PHY status Descriptor.
SSPL Link rate: This field indicates the PHY link rate in SSPL layer.
SXL Link rate: This field indicates the PHY link rate in SXL layer.
PHY working mode: This field indicates the current working mode of this PHY:
• 0x0: IDLE/Bypass mode;

Protocol Stack Library

• 0x1: BCT mode;

• 0x2: SAS buffering mode;
• 0x3: SATA buffering mode;
• 0x4: Error mode: Detected uncorrectable SSSF/EMIP/SXL ECC error;
• 0x5-0x7: Reserved.
• Buffer RAM scan state: This field indicates the scan state of the buffering RAM:
• 0x0: The scanning is not in progress;
• 0x1: The scanning is in progress;
• 0x2: The result of last scan is FAIL. The buffer RAM has an error;
• 0x3: The result of last scan is PASS;
• 0x4-0x7: Reserved.
EMIP uncorrectable ECC error: This field indicates whether the EMIP RAM detected an uncorrectable ECC error:
• 0x0: No uncorrectable EMIP ECC error;
• 0x1: Detected uncorrectable EMIP ECC error;
SXL uncorrectable ECC error: This field indicates whether the SXL detected an uncorrectable ECC error:
• 0x0: No uncorrectable SXL ECC error;
• 0x1: Detected uncorrectable SXL ECC error;
SSSF uncorrectable ECC error: This field indicates whether the SSSF detected an uncorrectable ECC error:
• 0x0: No uncorrectable SSSF ECC error;
• 0x1: Detected uncorrectable SSSF ECC error;
Maximum Frame Count: This field indicates the maximum frame count setting of the attached 12G SAS target if the
12G connection management feature is enabled and the attached SAS target has negotiated to 12G.
Multi-Host A/A (Active-Active) Xopen Detect: This bit indicates whether the cross open case occurs in the drive
link of the corresponding PHY during the Multi-Host Active-Active access to the drive with SAS buffering enabled. ‘1’
means this cross-open case has been detected; ‘0’ means not detected.
Multi-Host A/A (Active-Active) Xopen Deadlock Detect: This bit indicates whether the cross open deadlock
happens in the drive link during the Multi-Host Active-Active access.
Multi-Host A/A (Active-Active) Xopen Deadlock Hit Count[15:0]: This field provides the count of drive link cross-
open deadlock hits. The count value increments each time deadlock being detected and will saturate hitting the max
value of 65535.

14.2.3.47 Fatal Error Event Log Control Page (0xF4)

The SEND DIAGNOSTIC command with a vendor specific page code of 0xF4 allows the host application to operate
the Fatal Error Event Log section.
Table 14-95. Fatal Error Event Log Control Page Format

Byte \ Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (0xF4)

1 Reserved

2 (MSB)
Page Length (8)
3 (LSB)

4 Log Operation Code

Protocol Stack Library

...........continued
Byte \ Bit 7 6 5 4 3 2 1 0

6 Reserved

10 Parameters

The fields in this page are defined as:

• Log Operation Code: The Fatal Error Event Log operation code executed in the SES service processor.
• Parameters: The parameters associated with the Log Operation Code for the log operation.
Table 14-96. Log Operation Code and Parameters

Log Log Operation

Operation Name Parameters Description
Code

0 NOP N/A Do nothing and return “OK”

SET START Set the log read start offset, it will be increased
OFFSET automatically when the log is retrieved by the “Fatal
Error Event Log Retrieve Page” until it’s at the end of
log partition. If it’s at the end of log section, it will be
Start Offset
wrapped to 0 when the host retrieves the log the next
1 (32 bit, 4-byte time.
alignment)
The host should set the START OFFSET if the current
Start Offset in firmware is unexpected. The START
OFFSET will be returned by “Fatal Error Event Log
Retrieve Page”.

CLEAR LOG Clear “Fatal Error Event Log” section, the partition will
be erased. The host may clear the fatal error log once
the log has been retrieved. This operation is destructive.
2 N/A
Before the log is cleared, the host should save the log
into its storage soace. After this operation the log in
flash will be erased permanently.

3 ~ 255 Reserved N/A Reserved

14.2.3.48 Fatal Error Event Log Retrieval Page (0xF4)

The RECEIVE DIAGNOSTIC RESULTS command with a vendor specific page code of 0xF4 returns the fatal error
event log. The event log is in binary format and is passed from the SEP using RECEIVE DIAGNOSTIC RESULTS
Command with a page code of 0xF4.
For a SAS transport layer, the maximum size of a packet, including all headers, is 1K bytes. For an FC transport
layer, the maximum size of a packet, not including the FC header, is 2K bytes (or the configured FC frame size). No
pre-processing on the log is required, all relevant data is already compiled into this packet. The minimum size of a
request should be 20 bytes.

Protocol Stack Library

Note that reading the fatal error event log through the Fatal Error Event Log Retrieval Page is non-destructive.
The host needs to make sure to store this information after retrieval and before the log is cleared. Some events
associated with retrieving the log may themselves be included in the log information.
Table 14-97. Fatal Error Event Log Retrieval Page Format

Byte \ Bit 7 6 5 4 3 2 1 0

0 PAGE CODE (0xF4)

1 Reserved Dirty

2 (MSB)
Page Length (n–3)
3 (LSB)

4 (MSB)
Log Start Offset
7 (LSB)

8 (MSB)
Log Total Size
11 (LSB)

12
Reserved
19

20
Log Data
n

The fields in this page are defined as:

• Dirty: If the Start Offset in firmware has never reached the end of the log section, this bit is 1, otherwise this bit is
0 (zero).
• After firmware boots up this bit will be reset to 1. Use this bit to check whether the log is a new log that has
not been retrieved before. Due to the following reasons this bit is only for reference. Do not use this bit to judge
whether all logs are retrieved:
• Once firmware boots up this bit will be reset to 1
• Even if the host only retrieves the last log section, this bit will be 0 (zero) no matter the rest log is retrieved or not
• Log Start Offset: The Start Offset of the Fatal Error Log section where the log data in this page is retrieved. This
is not applicable if Total Log Size is 0. When this reaches the end of the log section, it will wrap to 0 if a new log
retrieval page is received and will continue to increase after every retrieval request is served.
• Total Log Size: The total log size in the Fatal Error Event Log section. If there is no fatal error log the value
should be 0.
When the SEP receives the Fatal Error Event Log retrieval command, it will prepare for event log retrieval. First, it
will check whether the log is available. If it’s available SEP will retrieve the log starting from the current Start Offset
maintained in firmware. The current Start Offset will be increased the length of the log retrieved in the page, the
original Start Offset and the total Log size will be returned to host in the same page. The Log Start Offset will be 0
(zero) when the expander is reset, power cycled or recovers from a fatal error. This value will be increased when the
log is retrieved until it reaches the end of the Fatal Error Event Log section. If any log page is missed, the host may
specify the Start Offset through the Fatal Error Event Log Control Page and then retrieve the missed section.
The host may request multiple SES pages to retrieve the entire Fatal Error Event Log from the expander and the host
can check whether the following equation is true to judge whether it reaches the end of the log section:
Total Log Size is equal to (Log Start Offset + Length of the error log data returned through this page).

Protocol Stack Library

14.2.4 SES Error Handling Summary

The following is a summary of error conditions that can be returned from SES. Every error will return a CHECK
CONDITION with a sense key of ILLEGAL REQUEST. ASC and ASCQ are set as outlined in the following table.
Table 14-98. SES Error Handling Summary

SES Page Affected Error ASC / ASCQ

All Unsupported SES page requested. “Invalid Field in Parameter List”

Enclosure/Threshold Generation code non-zero. “Invalid Field in Parameter List”

Control.

Control Page. Page length/buffer length mismatch. “Invalid Field in Parameter List”,
“Invalid Field in CDB”

Control Page. Invalid value on page (e. g. threshold out of “Invalid Field in Parameter List”
range).

String Out Firmware Download Failed/Error on FW “Invalid Field in Parameter List”

download page.

Status Page. Database data was not initialized. “Internal Target Failure”

14.2.5 Adding New SES Pages to the Code Base

The following section outlines how newly created SES pages can be added to the SES module. It assumes that the
database will need to be used to store SES page data. If this is not the case, the database creation steps can be
skipped.
Determine if your page is a standard or a custom, a control or status page. Decide which SES page code is
appropriate for your page (for example, 0x80-0xFF is for custom pages). For custom pages decide on the format of
the page.
Determine if you need to use the DBS database to store the information for your SES page. In cases where data for
an SES page cannot be retrieved when a request for an SES page comes in (like in the case when peripherals need
to be read through TWI), it needs to be gathered and stored somewhere. The DBS database is a convenient place for
this purpose. The database can also be used when data from an SES page is to be shared between different parts of
the firmware.
In the following it is assumed, that a control/status custom page needs to be created, which needs to store data in the
database, as this is the case that is most involved. Note that the yyy_ prefix in the file names needs to be replaced
with the prefix relevant to your project (e. g.sxp).
The SES and DBS modules are divided into two parts each; the first one, a project independent part, typically
stored under /ses/src/ses and ses/src/dbs contains reusable code that will in many cases not depend on the specific
configuration supported in the enclosure, and will in most cases not need to get modified. The second, a project
dependent part, is typically under yyy/src/ses or yyy/src/ses_yyy and is meant to be modified.
DBS database entry creation
All database page identifiers need to be uniquely defined and are stored in two files; dbs_id. h and dbs_yyy_id. h.
The latter file is to be used for additions to the database, where the former is to be used as is. When creating new
database entries it is important to make sure that database codes are unique.
A struct needs to be created that would describe the elements in the new database page. This is done for
convenience to simplify the accesses to individual fields in the database page (using the offsetoff() macro). This
struct will be defined in ses_yyy. h. In there a definition for the size of the database page that was created is added,
similar to e. g. SES_PAGE_SIZE_EMM_SYS_LOG_PG. This new define is then added to the yyy_ses_page_sizes
array in ses_yyy. c. This array is used by the database to allocate the proper amount of memory at firmware start-up.
The database entry is now created (assuming that the initialization code for DBS has been in place already) and can
be accessed using the page identifier; however, it does not contain any data.

Protocol Stack Library

14.2.5.1 Database Entry Initialization

This is done in ses_init() in the ses_yyy. c file. You need to create some init data and add the code to ses_init() to
write that init data to the database.

14.2.5.2 Adding SES Support to Access the Data

So far a database page was created and initialized with some meaningful data. Now the functionality to read and
write this data through SES needs to be added.
File ses_process. c contains the functions that would receive the SES request, decode the SES page code and
branch out to the processing functions. The decoding logic to ses_process. c for received and send diagnostic pages
(for this example) needs to be added here. Alternatively, the ses_hooks. c file can be utilized where additional page
decoding can be added.
A new file that contains the two processing functions for your SES page would need to be created (and typically be
stored under yyy/src/ses) and included in the build file for the SES library libses. gpj in yyy/build.

14.3 SCSI Target Emulator (STE)

The SCSI Target Emulator (STE) implements the subset of the SCSI protocols required for the target side of an
enclosure services application. The implementation supports multi-host applications with up to16 I_T nexuses and 32
queue depths
STE implements portions of the SCSI Architecture Model –3 (SAM-5) and the SCSI Primary Commands –4 (SPC-4)
required to support SCSI Enclosure Services – 2 (SES-3).

14.3.1 STE Structure

This section briefly describes the structure of the STE firmware.
The files comprising the STE firmware are summarized in the following table. In general, the first five files need to be
referenced.
Table 14-99. STE Files

File Name Visibility Description

ste. H scsi\inc Top level system interface

ste_parms. h scsi\inc Top level parameter definitions

ste_log. H scsi\inc STE logging definitions

ste_ses_msgs. h scsi\inc SES interface definitions (to EMA)

ste_sense. h scsi\inc Sense data definitions used in SES interface

ste_scsi_msgs. h scsi\inc SCSI transport interface definitions

ste_sense_index. h scsi\inc Sense index used in SCSI transport interface

ste_conn_mp. h scsi\inc Disconnect – Reconnect mode page definitions

ste_cmd. c scsi\src\ste SCSI command processor

ste_main. c scsi\src\ste Top level interface module

ste_resp. c scsi\src\ste SCSI command response module

ste_tm. c scsi\src\ste SCSI task management

ste_utils. c scsi\src\ste Utility functions

ste_cmd. h scsi\src\ste Interface to SCSI command processor module

Protocol Stack Library

...........continued
File Name Visibility Description

ste_cmds. h scsi\src\ste SCSC command definitions

ste_loc. h scsi\src\ste Common include for all STE modules

ste_resp. h scsi\src\ste Interface to SCSI command response module

ste_tm. h scsi\src\ste Interface to SCSI task management module

ste_utils. h scsi\src\ste Interface to Utility functions module

The top-level interface provided by the STE consists of three functions; ste_parms_get, ste_create, and ste_init. This
follows the Microchip convention for threaded firmware.
The ste_parms_struct, defined in ste_parms. h, contains all parameters used to configure the STE firmware.
The function ste_parms_get allocates an instance of ste_parms_struct and initializes with default values. The same
instance of ste_parms_struct must be used in subsequent calls to ste_create and ste_init.
The ste_parms_struct has an embedded structure, ste_config_struct. The parameters in ste_config_struct must be
set by the user before calling ste_create, and must not be modified after the call.
Remaining parameters in ste_parms_struct (not ste_config_struct) must be set before the call to ste_init, and
must not be modified after the call. Note that some of these parameters must be copied from other components
xx_parms_struct.
Documentation of all parameters, including default values, is included in the documentation of the associated
structures.
The following table summarizes the preprocessor definitions that are used to control STE firmware compilation.
Table 14-100. STE Compilation Options

Compile Switch Usage

PMC_CSW_BIT_FIELD_ALLOC_L_TO_R STE firmware should assume left to right bit field allocation by the
compiler.
Must be defined, because there is no
PMC_CSW_BIT_FIELD_ALLOC_R_TO_L.

PMC_STE_CSW_FC_TRANSPORT SCSI transport is FC.

Only one of PMC_STE_CSW_FC_TRANSPORT or
PMC_STE_CSW_SAS_TRANSPORT must be defined.

PMC_STE_CSW_SAS_TRANSPORT SCSI transport is SAS.

Only one of PMC_STE_CSW_SAS_TRANSPORT or
PMC_STE_CSW_FC_TRANSPORT must be defined.

STE_CHECK_PARMS STE should fully validate passed parameters (ste_init). Assert on

error.
Recommend using during development and testing, but not
production.

STE_LOG Compile in STE logging code.

14.3.2 SCSI Command Support

SCSI commands conforming to the SCSI Primary Commands (SPC) are sourced by your host controller or test
system and are terminated by the STE portion of the SMC Firmware. This section describes the commands

Protocol Stack Library

supported by the STE, and the parameter values supported for each command. This section should be used
alongside the SPC reference.
The PM73206_04 Firmware implements the following features of the protocol:
• Target Mode
• Single Logical Unit Number (LUN) support (zero)
• Full Task Management Model, SIMPLE task support
• Sense data reporting through auto-sense mechanism
• Configurable number of tracked initiators (tracking requires additional RAM for each initiator)
• Configurable number of tasks (each supported task has RAM requirements)
The following table summarizes the SCSI commands supported by the STE. For each command there is a summary
of the modes of the command that are supported, and an indication of whether the command is fully processed by
the STE, or if part of the processing must be performed by the EMA. The commands requiring processing by the
EMA are the “SES commands”.
Table 14-101. SCSI Command Summary

Command Name Description Processed By

INQUIRY Standard Inquiry Data STE

Device Identification
Extended Inquiry Data
Supported VPD Pages

MODE SELECT(10) No changeable values STE

MODE SENSE(10) Control mode page STE

Disconnect–Reconnect mode page
Protocol Specific Logical Unit mode page
Protocol Specific Port mode page

READ BUFFER Data mode STE

RECEIVE DIAGNOSTIC Page mode STE, EMA

RESULTS

REPORT LUNS STE

REQUEST SENSE STE

SEND DIAGNOSTIC Default Self–Test STE, EMA

Page mode STE, EMA

TEST UNIT READY STE

WRITE BUFFER Vendor Specific mode STE

Download Microcode and Save mode (not supported by STE, EMA
SRC)
STE, EMA
Download Microcode with Offsets mode

The STE terminates the SCSI command in all cases, even for the SES commands. The STE communicates with the
EMA using 14.3.5 SES Interface.

Protocol Stack Library

The STE firmware supports only a single data transfer for each Data In or Data Out command, except for the
Download Microcode and save mode of the WRITE BUFFER command (see the following section). The maximum
size of a single transfer is determined by the STE Maximum Data Size field defined in Init String.
For the Download Microcode and Save mode of the WRITE BUFFER command, the STE Maximum Data Size
parameter specifies the maximum size of each packet requested from the initiator.
For the Vendor Specific mode of the READ BUFFER and the WRITE BUFFER command, the Buffer ID field is
considered part of Buffer Offset field to make Buffer Offset field 4 bytes to provide access to entire MIPS address
space. Customer code may add the additional address validation per board memory condition, otherwise MIPS may
hits general exception and firmware crashes.
Customers must set the STE Maximum Data Size parameter to allow for the maximum SES page size transferred
to or from the host. Specifics of the support provided for each SCSI command are discussed under the sections that
follow.

14.3.2.1 INQUIRY
The following data pages are supported for the INQUIRY command:
• Standard Inquiry Data
• Device Identification VPD
• Extended Inquiry Data VPD
• Supported VPD Pages
The data used in all pages, except for Supported VPD Pages, are included in the ste_parms_struct, so the STE user
may modify. The STE user must follow the instructions in the ste_parms_struct documentation when modifying the
data.

14.3.2.2 MODE SELECT (10)

The following mode pages are supported for the MODE SELECT command:
• Control
• Protocol Specific Port

14.3.2.3 SAS Control Mode Page

The Control Mode page is initialized by the indicated array and the STE copies this array pointer to the
ste_parms_struct. MODE SELECT command can change the Control Mode parameter. Currently, the SDK only
supports that Qerr, TAS and TST are 0. If one of them is set to non-zero, the SDK returns CHECK CONDITION
status with additional INVALID PARAMETERS LIST. The SDK also checks the SPF(0), PS(0), PAGE CODE(0x0A)
and PAGE LENGTH(0x0A). If one of them has the wrong value, the SDK returns CHECK CONDITION status with
additional INVALID PARAMETERS LIST. The other bits’ setting value are not implemented.
Table 14-102. SAS Control Mode Page

Byte \ Bit 7 6 5 4 3 2 1 0

0x00 PS (0x0) SPF (0x0) Page Code (0x0A)

0x01 Page Length (0x0A)

D_SEN
0x02 TST TMF_ONLY DPICZ GLTSD RLEC
SE

0x03 QUEUE ALGORITHM MODIFIER NUAR QErr obsolete

0x04 VS RAC UA_INTLCK_CTRL SWP Obsolete

0x05 ATO TAS ATMPE RWWP reserve AUTOLOAD MODE

0x06
Obsolete
0x07

Protocol Stack Library

...........continued
Byte \ Bit 7 6 5 4 3 2 1 0

0x08
BUSY TIMEOUT PERIOD
0x09

0x08
EXTENDED SELF-TEST COMPLETION TIME
0x09

TST: This bit set to one specifies the logical unit maintains separate task sets for each I_T nexus. This bit cleared to
zero specifies that the logical unit maintains one task set for all I_T nexuses. This bit supports value 0. See the Table
407, [14].
QErr: The field specifies how the device server must handle other commands when one command is terminated with
a CHECK CONDITION status. See the Table 409, [14]. The field only supports zero.
TAS: The bit set to zero specifies that aborted commands must be terminated by the device server without any
response to the application client. The bit set to one specifies that commands aborted by the actions of an I_T nexus
other than the I_T nexus on which the command was received must be completed with TASK ABORTED status. The
bit only supports zero.
These bits and fields are not implemented.
• D_SENSE
• GLTSD
• RLEC
• QUEUE ALGORITHM MODIFIER
• NUAR
• RAC
• UA_INTLCK_CTRL
• SWAP
• ATO
• ATMPE
• TMF_ONLY
• DPICZ
• RWWP
• AUTOLOAD MODE
• BUSY TIMEOUT PERIOD
• EXTENDED SELF-TEST COMLETION TIME
Table 14-103. SAS Control Mode Parameter Defaults

Parameters Default

TST (Task Set Type) 0b00 (one task set for all initiators)

D_SENSE (Descriptor Format Sense Data) 0b0 (fixed format only)

GLTSD (Global Logging Target Save Disable) 0b0(not applicable)

DPICZ 0b0(not applicable)

TMF_ONLY 0b0(not applicable)

RLEC (Report Log Exception Condition) 0b0(not applicable)

NUAR 0b0(not applicable)

Protocol Stack Library

...........continued
Parameters Default

QUEUE ALGORITHM MODIFIER 0b0 (restricted reordering)

QERR (Queue Error Management) 0b00 (process other tasks)

TAS (Task Aborted Status) 0b0 (return UAC)

RAC (Report a Check) 0b0 (no detection of long busy conditions)

UA_INTLCK_CTRL (Unit Attention Interlocks Control) 0b00 (clear if reported)

SWP (Software Write Protected) 0b0(not applicable)

ATO (Application Tag Owner) 0b0 (not applicable)

AUTOLOAD MODE 0b000 (not applicable)

BUSY TIMEOUT PERIOD 0x0000 (undefined)

EXTENDED SELF-TEST COMPLETION TIME 0x0000 (non-zero SELF-TEST CODE not

supported)

14.3.2.4 SAS Port Mode Page – Short Format

Port mode page is initialized by the indicated array, and the STE copies this array pointer to the ste_parms_struct.
Then, MODE SELECT command can change this pointer and update the new port value to the system. The updated
value can influence the BROADCAST ASYNCHRONOUS EVENT action. Currently, port mode page just changes the
BC async event field, but other fields remain reserved with the MODE SELECT command.
The SDK checks the SPF (0), PS(0), PAGE CODE(0x19) and PAGE LENGTH(0x0E). If one of them has the wrong
value, the SDK returns a CHECK CONDITION status with additional INVALID PARAMETERS LIST.
Table 14-104. SAS Port Mode Page – Short Format

Byte \ Bit 7 6 5 4 3 2 1 0

0x00 PS (0x0) SPF (0x0) Page Code (0x19)

0x01 Page Length (0x0E)

Broadcast
Continue Ready LED
Asynchronous
0x02 Reserved AWT Meaning Protocol Identifier (0x6)
Event
(0x1) (0x0)
(0x0)

0x03 Reserved

0x04
I_T Nexus Loss Time
0x05

0x06
Initiator Response Timeout
0x07

0x08
Reject to open limit
0x09

0x0a~0x0f Reserved

Protocol Stack Library

Broadcast Asynchronous Event: This bit set to one specifies that the device server must enable the origination
of Broadcast (Asynchronous Event). This bit set to zero specifies that the device server must disable origination of
Broadcast (Asynchronous Event). It is set to default 0 in SDK. See the Table 208, [7].
Ready LED Meaning, Continue AWT, I_T Nexus Loss Time, Initiator Response Timeout, Reject to open limit:
These fields are not implemented.
Table 14-105. SAS Port Mode Parameter Defaults

Parameter Default

Continue AWT 0b1

Broadcast Asynchronous Event 0b0

I_T Nexus Loss Time 0x0(timer must set it after SDK running)

Initiator Response Timeout 0xfa0

Reject to open limit 0x0(timer must set it after SDK running)

Ready LED Meaning 0b0

14.3.2.5 MODE SENSE(10)

The following mode pages are supported for the MODE SENSE command:
• Control
• Disconnect – Reconnect
• Protocol Specific Logical Unit
• Protocol Specific Port

14.3.2.6 SAS Control Mode Page – Short Format

The STE gets the Control mode parameter defaults as Table 14-102.

14.3.2.7 SAS Port Mode Page – Short Format

The STE gets the Port mode parameter defaults as Table 14-104.

14.3.2.8 SAS Logical Unit Mode Page – Short Format

The following are the field definitions for this mode page, along with their default values:
Table 14-106. SAS Logical Unit Mode Page – Short Format

Byte \ Bit 7 6 5 4 3 2 1 0

0x00 PS (0x0) SPF (0x0) Page Code (0x18)

0x01 Page Length (0x06)

Transport
0x02 Reserved Layer Retries Protocol Identifier (0x6)
(0x0)

0x03 Reserved

0x04

0x05
Reserved
0x06

0x07

Protocol Stack Library

Transport Layer Retries: This bit set to one specifies that, for commands received in COMMAND frames with the
TLR CONTROL field, the target port must support transport layer retries for XFER_RDY and DATA frames for the
logical unit. The bit is not implemented. Refer the Table 207 in [7].

14.3.2.9 Disconnect-Reconnect Mode Page

The following are the field definitions for this mode page, along with their default values:
Table 14-107. Disconnect-Reconnect Mode Page

Byte \ Bit 7 6 5 4 3 2 1 0

0x00 PS (0x0) SPF (0x0) Page Code (0x02)

0x01 Page Length (0x0E)

0x02 Reserved

0x03 Reserved

0x04
Bus Inactivity Time Limit
0x05

0x06
Reserved
0x07

0x08
Maximum Connect Time Limit
0x09

0x0a
Maximum Burst Size (0x0009)
0x0b

0x0c Reserved

0x0d Reserved

0x0e
First Burst Size (0x0000)
0x0f

Bus Inactivity Time Limit: The field specifies the maximum time that the target port is permitted to maintain an
interconnect tenancy without data or information transfer. It is not supported in the SDK.
Maximum Connect Time Limit: The field specifies the maximum duration of a single interconnect tenancy. If the
connect time limit is exceeded, then the target port must conclude the interconnect tenancy. The virtual SSP Port in
the SDK supports the MCT timer.
Maximum Burst Size: The field indicates the maximum amount of data that the target port can transfer during a
single data transfer operation. It is not supported in the SDK.

14.3.2.10 LOG SELECT

The following log subpages are supported for the LOG SELECT command:
• Supported pages and subpages
• Main firmware log retrieves last n entries
• Main firmware log filter control
• EMIP firmware log retrieve last n entries
• EMIP firmware log filter control

Protocol Stack Library

Table 14-108. LOG SELECT CDB Format

Byte \ Bit 7 6 5 4 3 2 1 0

0 OPERATION CODE (4Ch)

1 Reserved PCR SP

2 PC PAGE CODE

3 SUBPAGE CODE

4 (MSB)
Reserved
6 (LSB)

7 (MSB)
PARAMETER LIST LENGTH
8 (LSB)

9 CONTROL

Table 14-109. LOG SELECT CDB Fields

Byte
Field Name Description
[Bit(s)]

0 OPERATION CODE 4C

1[0] SP Save parameter (see below)

1[1] PCR Parameter code reset (see below)

1[2:7] Reserved

2[0:5] PAGE CODE LOG RETRIEVE and Filter (0x30)

2[6:7] PC Page Control(see below)

MAIN Firmware LOG RETRIEVE subpage(0x01)

MAIN Firmware LOG FILTER subpage (0x02)
3 SUBPAGE CODE
EMIP Firmware LOG RETRIEVE subpage(0x03)
EMIP Firmware LOG FILTER subpage (0x04)

4:6 Reserved

PARAMETER LIST
7:8 Vendor Specific
LENGTH

9 CONTROL 00

LOG SELECT can configure the CDB to indicate special action with the parameter length.
The table lists the all applications for the bits: PCR, SP and DS and the parameter.
PC bit is omitted since the format_and_linking field is binary format in the log parameters.
DS (disable save) bit is in the log parameters such as log retrieval subpage or log filter subpage. It can affect the
CDB bit action.

Protocol Stack Library

Table 14-110. LOG SELECT CDB Field Configuration Sets

Parameter Length PCR SP DS Description

0 0 Ignore No changes to any log parameter value

0 1 Ignore Save current parameters to non-volatile media

0 Set parameters to the default values but not save

1 0 Ignore
to non-volatile media

Set parameters to the default values and save to

1 1 Ignore
non-volatile media

0 0 x Set the specific values

Save current specific values to non-volatile

0 1 0
media
>0
0 1 1 Set the specific values

Check condition with sense key ILLEGAL

1 x x
REQUEST and ASC is INVALID FIELD IN CDB

14.3.2.11 Supported Pages and Subpages

STE firmware reports all kinds of the supported pages and subpages. Use LOG SENSE and set the page to 0x00
and subpage to 0xff, then supported pages and subpages will be listed in the format of SPC4-r32 7.3.19 table 374.
Table 14-111. Page and Subpage Supported by LOG SELECT

Page Subpage Description

0x01 Main firmware log retrieve

0x02 Main firmware log filter

0x30
0x03 EMIP firmware log retrieve

0x04 EMIP firmware log filter

0x00 0xff All current pages and subpages supported

Refer to Table 14-113 and Table 14-117 for page format.

14.3.2.12 Log Retrieve Last n entries

Log Retrieve is used to get the data entries that firmware supplied. It is useful to get the data to analyze current
system status or to debug the system. LOG SELECT sets the last n entries to tell the SXP the number of entries
reported and the LOG SENSE coordinate with LOG SELECT to report the real entry numbers to the host.
The parameter length in CDB must be less than the value of STE Maximum Data Size (default value is 4608). If
larger, LOG SELECT will be terminated and the host will report a check condition status. The sense key is ILLEGAL
REQUEST with additional sense code INVALID FIELD IN CDB.
The last n entries may be set to a large value (etc. 65536) but LOG SENSE may not get much data since buffer
granularity exists. Buffer granularity means that only size of data defined by STE Maximum Data Size parameter in
Init String should be read in one LOG SENSE command.

Protocol Stack Library

Table 14-112. Relationship Layout for Last n Entries, Max Entries and STE Maximum Data Size

Requested Max Entries in Log STE Maximum Data Size Description

Entries Buffer

Last n entries Last n entries is Max entries is larger than max See case 1
larger than max data size
entries
Max entries is less than max data See case 2
size

Last n entries is less The Last n entries is larger than See case 3
than max entries max data size

The Last n entries is less than See case 4

max data size

Case 1: If last n entries is larger than max entries, last n entries will be modified to max entries. At this phase, if the
max entries data size is larger than one granularity, LOG SENSE reads the entries additional times until the firmware
reports an error with finishing to read all entries, the response buffer will be filled with the remaining entries and the
actual acquired entries following entries data in each buffer granularity.
Case 2: If last n entries is larger than max entries, last n entries will be modified to max entries. At this phase, if the
max entries data size is less than one granularity, LOG SENSE reads the entries one time, the response buffer will be
filled with the remaining entries and actual acquired entries following entries data.
Case 3: If last n entries is less than max entries, and if last n entries data size is larger than one granularity, LOG
SENSE reads the entries additional times until the firmware reports an error with finishing to read all entries. The
response buffer will be filled with the remaining entries and actual acquired entries following entries data in each
buffer granularity.
Case 4: If last n entries is less than max entries, and if last n entries data size is less than one granularity, LOG
SENSE reads the entries one time, the response buffer will be filled with the remaining entries and actual acquired
entries following entries data.
Table 14-113. Log Retrieval Format

Bit/Byte 7 6 5 4 3 2 1 0

0 DS SPF(1b) PAGE CODE (30h)

1 SUBPAGE CODE (01h or 03h)

2 (MSB)
PAGE LENGTH (n–3)
3 (LSB)

…. Log Retrieve Parameter

Note: Table 14-113 is same for main firmware log retrieval and EMIP firmware log retrieval.
Table 14-114. Log Retrieve Parameter Format

Bit/Byte 7 6 5 4 3 2 1 0

0 (MSB)
PARAMETER CODE
1 (LSB)

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...........continued
Bit/Byte 7 6 5 4 3 2 1 0

2 DU Obsolete TSD ETC TMC FORMAT AND LINKING

3 PARAMETER LENGTH(n-3)

… EMM EVENT LOG

FORMAT AND LINKING: Only binary format are used and PC bit in LOG SELECT CDB will be omitted.
TMC, ETC, TSD, DU: These bits are not implemented and just fill zero.
Note: Table 14-114 is same for main firmware log retrieval and EMIP firmware log retrieval.
Table 14-115. EMM Event Log Format for Main Firmware Log Retrieve

Bit/Byte 7 6 5 4 3 2 1 0

0
LAST N LOG ENTRIES
1

2
Reserved
3

LAST N LOG ENTRIES: The field reflects how many log entries are requested. If last n entries is larger than max
entries or 0, last n entries will be modified to max entries.
Table 14-116. EMM Event Log Format for EMIP Firmware Log Retrieve

Bit/Byte 7 6 5 4 3 2 1 0

0
LAST N LOG ENTRIES
1

2 Logical PHY ID

3 Reserved

LAST N LOG ENTRIES: The field reflects how many log entries are requested. If last n entries is larger than max
entries or 0, last n entries will be modified to max entries.
Logical PHY ID: The field specifies the logical PHY ID to retrieve the EMIP firmware log on this PHY. The valid range
of logical PHY ID is zero to (logical PHY count-1). Each EMIP log select command can only retrieve the EMIP log for
a single PHY at a time.

14.3.2.13 Log Filter Control

STE Log Filter is used to set the filter rules for the log. It can change the filter level and update pattern to indicate
what specific log can go to the entries.
Table 14-117. Log Filter Format

Bite/ 7 6 5 4 3 2 1 0
Byte

0 DS SPF(1b) PAGE CODE(30h)

Protocol Stack Library

...........continued
Bite/ 7 6 5 4 3 2 1 0
Byte

1 SUBPAGE CODE(02h or 04h)

2 (MSB)
PAGE LENGTH(n-3)
3 (LSB)

0 Logical PHY ID

1 FILTER COUNT n (MAX 16)

Protocol Stack Library

...........continued
Bit/Byte 7 6 5 4 3 2 1 0

2
LOG FILTER DESCRIPTOR LIST (first)
14

2+(n-1)*13
LOG FILTER DESCRIPTOR LIST (last)
14+(n-1)*13

Logical PHY ID: The field specifies the logical PHY ID to filter the EMIP firmware log on this PHY. The valid range
of logical PHY ID is zero to (logical PHY count-1). Each EMIP log select command can only filter the EMIP log for a
single PHY at a time
Table 14-121. Log Filter Descriptor Format for Main Firmware Log Filter

Bit/Byte 7 6 5 4 3 2 1 0

0 APPLICATION FILTER INDEX

1
MASK
4

5
PATTERN
8

9
FILTER TYPE
12

Table 14-122. Log Filter Descriptor Format for EMIP Firmware Log Filter

Bit/Byte 7 6 5 4 3 2 1 0

0 APPLICATION FILTER INDEX

1
MASK
4

5
MODE
8

9
Reserved
12

APPLICATION FILTER INDEX: This field is the index of the filter descriptor in this log select command and starts
from 0.
MASK: This field specifies the 32 bits EMIP event log mask to indicate which event EMIP firmware will do event
logging.
MODE: This field specifies the EMIP event mode. The EMIP event mode is defined as follows:
0x000000: EMIP IDLE mode;
0x000001: EMIP BCT mode;
0x000002: EMIP SAS buffering mode;

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0x000003: EMIP SATA buffering mode;

For the filter control field description, refer chapter 17.2.2 Event Logging Filter Format.
The max filter count can be indicated and set, if the count is less than the max filter count. LOG SENSE just reports
the indicated filter count to the host. If the count is larger than the max filter count, it will report check condition status
and sense key is ILLEGAL REQUEST with additional sense code INVALID FIELD IN CDB.

14.3.2.14 LOG SENSE

STE Firmware Coordinates LOG SENSE with LOG SELECT to report the retrieval log or current filter control rule or
supported pages.
• Supported pages and subpages
• Main firmware log retrieve last n entries
• Main firmware log filter control
• EMIP firmware log retrieve last n entries
• EMIP firmware log filter control
Table 14-123. LOG SENSE CDB Format

Bit/Byte 7 6 5 4 3 2 1 0

0 OPERATION CODE (4Dh)

1 Reserved Obsolete SP

2 PC PAGE CODE

3 SUBPAGE CODE

4 Reserved

5 (MSB)
PARAMETER POINTER
6 (LSB)

7 (MSB)
ALLOCATION LENGTH
8 (LSB)

9 CONTROL

SP bit: LOG SENSE disables this bit, if SP is TRUE, the command will be terminated.
PC bit: Page control is omitted since the log parameters define the binary format.
PAGE CODE: Define 30h to support log retrieval and log filter subpages.
SUBPAGE CODE: Define 0x01 to log retrieval and 0x02 to log filter control.
PARAMETER POINTER: Only implement the value 0x0000; if not 0x0000, the command will be terminated.
ALLOCATION LENGTH: Specific defines.

14.3.2.15 Supported Pages and Subpages

Protocol Stack Library

Table 14-124. Page and Subpage Supported by LOG SENSE

Page Subpage Description

0x01 Main Firmware Log retrieve

0x02 Main Firmware Log filter

0x30
0x03 EMIP Firmware log retrieve

0x04 EMIP Firmware Log filter

0x00 0xff All current pages and subpages supported

14.3.2.16 Log Retrieve

LOG SENSE command must be executed after LOG SELECT set the last n entries, if using the LOG SENSE but
not indicating the last n entries by LOG SELECT, the host will get the ILLEGAL REQUEST and LOG SENSE will be
terminated.
The detail rule of LOG SENSE with LOG SELECT is explained in the LOG SELECT for log retrieve.
The alloc length must be less than STE Maximum Data Size. If larger, LOG SENSE will be terminated, firmware will
report check condition status and sense key will be ILLEGAL REQUEST with additional sense code INVALID FIELD
IN CDB. Recommend STE Maximum Data Size to be used as alloc length.
LOG SENSE response buffer structure is shown in the following table:
Table 14-125. LOG SENSE Response Buffer Format

Byte Field Description

[0:1] Remaining It reflects how many entries should be read again after one
LOG SENSE command, 0 means that all of the entries data are
Entries Num
finished to acquire.

[2:3] Really Acquired Entries It reflects how many entries have been read after one LOG
Num SENSE command.

[4:x] Entries Data Fill the real entries data, the data sequence is little endian.

14.3.2.17 Log Filter Rule

LOG SENSE reports the current filter rule, if not using LOG SELECT to indicate the filter rule and count, LOG SENSE
will report all of the filters and their configuration. If using LOG SELECT to indicate the filter rule and count, LOG
SENSE will report the filter data with the indicated filter count.
Note: LOG SELECT and LOG SENSE cannot support the multi-initiator access mode.

14.3.2.18 REPORT LUNS

The STE firmware supports all report types for the REPORT LUNS command.
The well-known logical unit’s report (0x01) will return an empty LUN list.
The single LUN (zero) supported by the STE firmware is reported for the other types.

14.3.2.19 TEST UNIT READY

TEST UNIT READY always returns a GOOD completion if the STE is active.

14.3.2.20 REQUEST SENSE

The REQUEST SENSE will return any unit attention condition that is outstanding for the initiator.
The STE firmware expects to return the sense data associated with command completion using the auto-sense
mechanism. The sense data is cleared as soon as it is returned, so the REQUEST SENSE command will never
return sense data associated with a command.
Only fixed format sense data is supported by the STE.

Protocol Stack Library

14.3.2.21 SEND DIAGNOSTIC

The STE validates the CDB and forwards the request to the EMA if it is a valid command.
The STE firmware supports two modes of the SEND DIAGNOSTIC command; default self-test and SES page
download.
If the SELFTEST bit is set, then STE will assume that a default self-test is being specified and validate the CDB
parameters according to the following table.
Table 14-126. SEND DIAGNOSTIC AND SELFTEST

Command Valid Setting

SELFTEST 1

PF X (Don’t Care)

SELF-TEST CODE 0b000

PARAMETER LIST LENGTH 0

If the SELFTEST bit is not set, then STE will assume that an SES page download is being specified and validate the
CDB parameters according to the following table.
Table 14-127. SEND DIAGNOSTIC AND NOT SELFTEST

CDB Parameter Valid Setting

SELFTEST 0

PF 1

SELF-TEST CODE 000b

PARAMETER LIST LENGTH Length of SES page

A valid request is translated into a request to the EMA for the corresponding function. If the PF is also set to zero
in this table configuration, firmware should ignore it and report error since the command has no significance, the
Firmware need the PF bit is set to 1.

14.3.2.22 RECEIVE DIAGNOSTIC RESULTS

The STE validates the CDB and forwards the request to the EMA if it is a valid command.
Only the Page Code mode of the RECEIVE DIAGNOSTIC RESULTS command is supported and the PCV bit must
be set (one).
The EMA is responsible for validating the contents of the Page Code field.

14.3.2.23 READ BUFFER

The READ BUFFER command can be used to read the SEP device’s memory.
The STE firmware implements a Vendor Specific mode of the READ BUFFER command, but the format of the CDB
is identical to the SPC-4 READ BUFFER command Data mode except that the Buffer ID field, byte 2, is used to
extend the Buffer Offset, bytes 3 to 5, to make a 4 byte offset field. This allows the initiator to specify any address in
the virtual memory space.
The STE does not validate the address before attempting the read, so an invalid address may result in a memory
fault.
The READ BUFFER command is intended for debugging during development, and careful consideration should be
given to using it to provide product functionality.

14.3.2.24 WRITE BUFFER

The STE supports three modes of this command:

Protocol Stack Library

• Vendor Specific mode.

• Download Microcode and Save mode. (not available for SRC)
• Download Microcode with Offsets and Save mode.
The Vendor Specific mode is analogous to the Vendor Specific mode of the READ BUFFER command, described
above. The Vendor Specific mode is really Data Mode, and the Buffer ID field is used to extend the Buffer Offset field
to 4 bytes.
Warnings regarding use of the Vendor Specific mode of the READ BUFFER command apply equally, at least, to the
WRITE BUFFER command.
Unlike Vendor Specific mode, the Download Microcode modes of the WRITE BUFFER command are fully intended
for use in a product.
The Download Microcode modes of the WRITE BUFFER command are treated as SES commands, and a valid
request will be forwarded to the EMA for processing. The request is passed through the EMA so that the EMA can
ultimately control the download process.
The important difference between the two Download Microcode modes is whether the application client breaks the
firmware into multiple packets for download, or the STE is responsible for downloading in burst size packets.

14.3.3 Task Management Function

The Task Management Function implemented in the STE module is updated to the latest SAM5.
Table 14-128. Supported Task Management Functions

Task Management Function

ABORT TASK

ABORT TASK SET

CLEAR TASK SET

LOGICAL UNIT RESET

I_T NEXUS RESET

QUERY TASK

QUERY TASK SET

QUERY ASYNCHRONOUS EVENT

ABORT TASK
The task manager must abort the specified command, if a task exists. Previously established conditions, including
mode parameters, reservations, and ACA must not be changed by the ABORT TASK function.
A response of FUNCTION COMPLETE indicates that the command was aborted or was not in the task set. In either
case, the SCSI target device must guarantee that no further requests or responses are sent from the command.
ABORT TASK SET
The task manager must abort all commands in the task set that were received on the specified I_T nexus.
Commands received on other I_T nexuses or in other task sets must not be aborted. This task management function
performed is equivalent to a series of ABORT TASK requests.
All pending status and sense data for the commands that were aborted must be cleared. Other previously established
conditions, including mode parameters, reservations, and ACA must not be changed by the ABORT TASK SET
function.
CLEAR TASK SET
This function must be supported by all logical units. The task manager must abort all commands in the task set. If
the TST field (SDK only set the 0b000) is set to 001b (that is, per I_T nexus) in the Control mode page, there is

Protocol Stack Library

one task set per I_T nexus. As a result, no other I_T nexuses are affected and CLEAR TASK SET is equivalent to
ABORT TASK SET. All pending status and sense data for the task set must be cleared. Other previously established
conditions, including mode parameters, reservations, and ACA must not be changed by the CLEAR TASK SET
function. All SCSI transport protocol standards must support the CLEAR TASK SET task management function.
LOGICAL UNIT RESET
This function must be supported by all logical units. Before returning a FUNCTION COMPLETE response, the logical
unit must perform the logical unit reset functions.
I_T NEXUS RESET
SCSI transport protocols support I_T NEXUS RESET and require logical units accessible through SCSI target ports
using such transport protocols to support I_T NEXUS RESET.
Each logical unit accessible through the SCSI target port must perform the I_T nexus loss functions for the I_T nexus
on which the function request was received, the SCSI target device must return a FUNCTION COMPLETE response
and must perform any additional functions specified by the SCSI transport protocol.
QUERY TASK
SCSI transport protocols support QUERY TASK and require logical units accessible through SCSI target ports using
such transport protocols to support QUERY TASK. The task manager in the specified logical unit must return a
service response set to FUNCTION SUCCEEDED if the specified command is present in the task set, or return
FUNCTION COMLETE if the specified command is not present in the task set.
QUERY TASK SET
SCSI transport protocols support QUERY TASK SET and require logical units accessible through SCSI target ports
using such transport protocols to support QUERY TASK SET.
The task manager in the specified logical unit must return a service response set to FUNCTION SUCCEEDED if any
command present in the task, or set to FUNCTION COMPLETE if no command present in the task set.
QUERY ASYNCHRONOUS EVENT
SCSI transport protocols support QUERY ASYNCHRONOUS EVENT. A SCSI transportprotocols supporting QUERY
ASYNCHRONOUS EVENT require logical units accessible through SCSI target ports using that transport protocol
to support QUERY ASYNCHRONOUS EVENT. The task manager in the specified logical unit must return a service
response set to FUNCTION SUCCEEDED if there is a unit attention condition for the specified I_T nexus, or set to
FUNCTION COMPLETE if there is no unit attention condition g for the specified I_T nexus.

14.3.4 SCSI Sense Data

This section describes the sense data returned by the STE firmware to report SCSI command failures or unit
attention conditions. Note that the EMA may return sense data in 14.3.5 SES Interface messages (see section
14.3.5 SES Interface), and that sense data is not covered here.
The following tables summarize the sense data returned by the STE firmware.
Table 14-129. SCSI Sense Keys

Key Description

0x00 NO SENSE

0x05 ILLEGAL REQUEST

0x06 UNIT ATTENTION

0x0B ABORTED COMMAND

Table 14-130. SCSI Sense Data

Key ASC ASCQ Description Usage

0x06 0x29 0x03 BUS DEVICE RESET OCCURRED Task Management Logical Unit Reset

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...........continued
Key ASC ASCQ Description Usage

0x06 0x2F 0x00 COMMAND CLEARED BY ANOTHER Task Management request from
INITIATOR another initiator caused task(s) to be
aborted

0x0B 0x44 0x00 INTERNAL TARGET FAILURE SEP firmware error

0x05 0x20 0x00 INVALID COMMAND OPERATION CODE Unsupported operation (command)
code

0x05 0x24 0x00 INVALID FIELD IN CDB All CDB field errors

0x05 0x26 0x00 INVALID FIELD IN PARAMETER LIST All errors in command data

0x05 0x49 0x00 INVALID MESSAGE ERROR Unsupported Task Attribute

0x05 0x25 0x00 LOGICAL UNIT NOT SUPPORTED Unsupported logical unit number (non-
zero)

0x06 0x29 0x00 POWER ON, RESET, OR BUS DEVICE First time STE hears from initiator
RESET OCCURRED

0x05 0x35 0x01 UNSUPPORTED ENCLOSURE FUNCTION The enclosure services process has
been asked to invoke an enclosure
services function that does not exist.

0x05 0x39 0x00 SAVING PARAMETERS NOT SUPPORTED MODE SENSE Page Control field
specifies saved values

0x0B 0x0E 0x01 INFORMATION UNIT TOO SHORT Set by transport, if applicable

0x0B 0x4B 0x02 TOO MUCH WRITE DATA Set by transport, if applicable

0x0B 0x4B 0x03 ACK/’NAK TIMEOUT Set by transport, if applicable

0x0B 0x4B 0x04 NAK RECEIVED Set by transport, if applicable

0x0B 0x4B 0x05 DATA OFFSET ERROR Set by transport, if applicable

0x0B 0x4B 0x06 INITIATOR RESPONSE TIMEOUT Set by transport, if applicable

For sense data that is specified as “Set by transport, if applicable”, the user should consult the device-specific
firmware user manual to see if the sense data applies for that device.

14.3.5 SES Interface

This section describes the interface used by the STE to forward SES requests to the EMA for processing. The
interface is defined in ste_ses_msgs. h
The following table summarizes the SES interface messages that correspond to SCSI commands. The STE
translates a validated SCSI command into an SES message of the indicated type to the EMA.
Table 14-131. SES Interface Messages

Message Structure SCSI Command

ste_ses_send_diag_msg_struct SEND DIAGNOSTIC, Page Code mode

ste_ses_rcv_diag_msg_struct RECEIVE DIAGNOSTIC RESULTS, Page Code mode

ste_ses_self_test_msg_struct SEND DIAGNOSTIC, default self-test mode

Protocol Stack Library

...........continued
Message Structure SCSI Command

ste_ses_write_microcode_msg_struct WRITE BUFFER Download Microcode modes

The ste_ses_msg_struct defines the common (first) fields of all SES messages. This includes an OSF message
header, a message identifier, and a sense data field. The sense data field must be set by the EMA to indicate the
result of the request. The message identifier uniquely identifies each command message sent to the EMA across the
SES interface.
In addition to the command messages, the SES interface includes an abort message (ste_ses_abort_msg_struct)
that may be used to cancel any of the command messages. The command message to be canceled is indicated by
the message identifier. Further instructions for use of the abort message are provided in the documentation of the
structure.
The STE sends only one message to the EMA at a time. The primary purpose of this single threading is to simplify
the processing for the EMA.
The STE is responsible for allocating and deallocating all buffers associated with SES messages.

14.4 Serial SCSI Protocol (SSP) Target Transport Layer

As shown in Figure 14-2, the SAS Port thread interfaces with the SCSI Target Emulator thread. It implements the full
SCSI Transport Protocol messaging interface that allows SCSI command sequences to be supported
The SAS Port thread converts SCSI Response/Request messages received from a SCSI application into SSP frames
for transmission by the Port Layer. In the other direction, SSP frames received on connections by the Port Layer build
SCSI Indication and Confirmation messages that are sent back to the SCSI application.
The following sub-sections describe the events that take place in each stage of the command sequence.

14.4.1 SCSI Command Received

1. The SAS Port receives a “frame received” event from the PACK_LT driver.
2. The SAS Port thread determines that the frame is a SSP Command frame, allocates a message buffer, and
formats the buffer with a SCSI command message using the CDB IU field from SSP Command frame.
3. The SAS Port thread sends the SCSI command message to the STE thread message queue.

14.4.2 SCSI Data Out

1. The SAS Port thread receives a “SCSI Data Out request” message from the STE thread, telling it to retrieve
data from a SCSI Initiator port. The message contains a pointer to a data buffer (allocated by the STE thread)
that holds the data received from the initiator.
2. The SAS Port thread coordinates the data retrieval by sending SSP XFER_RDY frames to the initiator and
receiving SSP DATA frames in response.
3. The data from each SSP DATA frame is copied into the correct location in the STE thread data buffer.
4. Once the data transfer is completed, the “SCSI Data Out Request” message is sent back to the STE thread.
A Data Out transfer is limited to the Maximum Burst Size supported by the STE thread. If this size is greater than the
maximum DATA payload in a single SSP frame, multiple DATA frames are requested.

14.4.3 SCSI Data In

1. The SAS Port thread receives a “SCSI Data In request” message from the STE thread, telling it to send data to
a SCSI Initiator port. The message contains a pointer to a buffer containing the data to transfer.
2. The SAS Port thread coordinates the transfer by sending SSP DATA frames to the initiator and monitoring the
ACK primitives received in response.
3. Once the data transfer is completed, the SCSI Data In message is sent back to the STE thread.
A Data In transfer is limited to the Maximum Burst Size supported by the STE thread. If this size is greater than the
maximum DATA payload in a single SSP frame, multiple DATA frames are sent.

Protocol Stack Library

14.4.4 SCSI Response

1. When the STE thread is ready to respond to a SCSI command, it sends the original SCSI command message
back to the SAS Port thread, with the additional response and sense fields filled out.
2. The SAS Port thread receives the message and builds a SSP RESPONSE frame.
3. The SSP RESPONSE frame is sent to the specific SAS address.
4. Upon completion, the SAS Port thread frees the SCSI Command message buffer.

14.5 Serial SCSI Protocol (SSP) Initiator Transport layer

The SSP initiator transport layer interfaces with the firmware SCSI Initiator Application (SIA) for the purpose of
sending SCSI commands. To achieve this functionality, the SSP initiator transport layer handles many events, the
simplified ones of which are described next.

14.5.1 SCSI Command Received (from SIA)

When a SCSI command or task management function is received, the transport mechanism builds an SSP
COMMAND or TASK frame and then forwards the frame to the port layer for transmission. Depending on the SCSI
command received, the transport layer enters the SCSI data (in or out) phase or terminates the command sequence
if no data phase is expected.

14.5.2 SCSI Data Out

Once XFER_RDY primitives are received, the firmware starts sending SCSI data frames out to the target until
completion or an error is encountered. The appropriate status is returned to the application level code.

14.5.3 SCSI Data In

For SCSI commands that expect incoming data from the target, the firmware waits until the data is received or an
error is encountered. The appropriate response is generated and the data (if successful) returned to the application
level code.

14.6 SCSI Tunneling Protocol (STP) Initiator Transport Layer

The STP initiator transport, managed through a nexus control structure, interfaces with the Serial ATA Host
Application (SAHA) for the purpose of initiating ATA commands to end devices. The following subsections describe
the major states through which the nexus transitions to achieve the desired functionality.

14.6.1 Transmit Frame

When an ATA command is received from the SAHA, the STP nexus creates an internal frame transmit request
structure consisting of the ATA FIS. It passes the structure to the port layer to initiate the transmission of the ATA
command. The appropriate response is returned to the application layer depending on the completion status.

14.6.2 Receive Frame

On receiving a device-to-host data FIS, a data buffer is allocated and the subsequent data frames are buffered. Once
complete, the data is returned to the application layer for processing.
If a host-to-device data FIS is received, the nexus transmits any remaining data of the ATA command until completion
or an error is encountered. In any case, the appropriate status is returned to the application level code.

14.7 Serial Management Protocol (SMP) Application Layer

The Serial Management Protocol (SMP) is an in-band protocol that monitors and controls the SAS expander. It
manages the SAS expanders and to communicates management information between SAS devices within a SAS
domain.
The SMP Application Component processes and responds to incoming SMP requests, generating outgoing SMP
requests, and processing the corresponding SMP responses. The SMP Application also manages SMP access to the
logical expander route table.

Protocol Stack Library

The SMP subsystem component contains two main processing objects:

• SMP Initiator Application object: Encapsulates outgoing SMP requests: parses and processes the corresponding
response frames.
• SMP Target Application object: Parses and processes incoming SMP requests; generates the appropriate
responses.
The following sections provide an overview of these processing objects.

14.7.1 SMP Initiator

The SMP Initiator Application provides a means for the Topology Discovery Application to generate and send SMP
Request frames. It also processes and parses the corresponding SMP Response frames.
The SMP Initiator Application supports the SMP function types listed in the following table.
Table 14-132. Supported SMP Function Types

SMP Function Type SMP Function

Code

0x00 Report General

0x01 Report Manufacturer Information

0x10 Discover

0x13 Report Route Information

0x20 Discover List

0x22 Report Expander Route Table List

0x85 Zoned Broadcast

0x90 Configure Route Information

0x91 PHY Control

14.7.2 SMP Target

The SMP Target Application provides standard SMP services to an external SMP initiator. It parses incoming SMP
Request frames from the SMP Transport Layer, performs the requested operation, and generates the appropriate
SMP Response message. It then returns the completed SMP Response frame to the SMP Transport component for
transmission.
The SMP Target Application supports the SMP function types listed in the following table.
Table 14-133. Supported SMP Function Types

SMP Function Type SMP Function

Codes

0x00 Report General

0x01 Report Manufacturer Information

0x02 Read GPIO Register

0x03 Report Self-Configuration Status

0x04 Report Zone Permission Table

0x05 Report Zone Manager Password

Protocol Stack Library

...........continued
SMP Function Type SMP Function
Codes

0x06 Report Broadcast

0x10 Discover

0x11 Report PHY Error Log

0x12 Report PHY SATA

0x13 Report Route Information

0x14 Report PHY Event

0x20 Discover List

0x21 Report PHY Event List

0x22 Report Expander Route Table List

0x79 Microchip Report Status

0x7A Microchip Read

0x7B Reserved

0x80 Configure General

0x81 Enable Disable Zoning

0x82 Write GPIO Register

0x85 Zoned Broadcast

0x86 Zone Lock

0x87 Zone Activate

0x88 Zone Unlock

0x89 Configure Zone Manager Password

0x8A Configure Zone PHY Information

0x8B Configure Zone Permission Table

0x90 Configure Route Information

0x91 PHY Control

0x92 PHY Test

0x93 Configure PHY Event

0xFA Microchip Write

0xFB Reserved

Detailed descriptions of the standard SMP functions are available in [4] and Section 14.7.3 Standard SMP
Functions . The proprietary Microchip functions are described in Section 14.7.4 SMP Functions Specific to Microchip.
Zoning-related SMP functions are documented in [4] 10.4.3.

Protocol Stack Library

14.7.3 Standard SMP Functions

The standard SMP subsystem component contains some functions that are defined in SPL-2.
Firmware supports SAS-2.x and previous SAS1.x SMP functions.
SAS-2.x may have different length response frames compared with SAS1.x. For compatibility with previous versions
of this standard, SMP target firmware parses incoming SMP request frames from the SMP Transport Layer and
returns SMP response frames based on the ALLOCATED RESPONSE LENGTH field and SMP function.
• If this SMP function is introduced by SAS-2.x, the SMP target firmware truncates the additional response bytes
to the number of Dwords specified by the ALLOCATED RESPONSE LENGTH field.
• SAS1.1 compatible functions: If the ALLOCATED RESPONSE LENGTH field is:
• Not zero: The SMP target firmware truncates the additional response bytes to the number of Dwords specified
by the ALLOCATED RESPONSE LENGTH field.
• Zero: The SMP target firmware thinks this SMP function is a SAS1.x SMP function. (When the SAS-2.x function
allocates a response length of zero, it means that it expects a response without additional response data and
returns the SMP response frame length specified by SAS1.1.)

14.7.3.1 Report General

Table 14-134. Report General Response Frame Format

Byte Description Notes

0 SMP Frame Type (0x41)

1 SMP Function (0x00)

2 SMP Function Accepted (0x00)

3 RESPONSE LENGTH (00h or 11h)

4 Expander Change Count (MSB)

5 Expander Change Count (LSB)

6 Expander Route Indexes (MSB)

7 Expander Route Indexes (LSB)

8 Reserved [0:6]

8 Long response [7] set it to one

9 Number of PHY’s ()

10 EXTERNALLY Configurable Route Table [0]

10 Configuring [1]

10 CONFIGURES OTHERS[2]

10 OPEN REJECT RETRY SUPPORTED [3],

10 STP CONTINUE AWT[4]

10 SELF_CONFIGURING[5]

10 ZONE_CONFIGURING[6]

10 TABLE TO TABLE SUPPORTED,[7]

11 Reserved (0x00)

Protocol Stack Library

...........continued
Byte Description Notes

12 -19 ENCLOSURE LOGICAL IDENTIFIER

20 - 27 Reserved (0x00)

The following are sas2.x introduced fields and not including SAS1.1 response frame

28 - 29 Reserved (0x00)

30 - 31 STP BUS INACTIVITY TIME LIMIT

32 - 33 STP MAXIMUM CONNECT TIME LIMIT

34- 35 STP SMP I_T NEXUS LOSS TIME

36 NUMBER OF ZONE GROUPS [6:7]

36 Reserved [5]

36 ZONE LOCKED[4]

36 PHYSICAL PRESENCE SUPPORTED[3]

36 PHYSICAL PRESENCE ASSERTED[2]

36 ZONING SUPPORTED[1]

36 ZONING ENABLED[0]

37 Reserved [5:7]

37 SAVING[4]

37 SAVING ZONE MANAGER PASSWORD

SUPPORTED [3]

37 SAVING ZONE PHY INFORMATION

SUPPORTED [2]

37 SAVING ZONE PERMISSION TABLE

SUPPORTED[1]

37 SAVING ZONING ENABLED[0] SUPPORTED[0]

38–39 MAXIMUM NUMBER OF ROUTED SAS

ADDRESSES

40–47 ACTIVE ZONE MANAGER SAS ADDRESS

48–49 ZONE LOCK INACTIVITY TIME LIMIT

50–51 Reserved (0x00)

52 POWER DONE TIMEOUT

53 FIRST ENCLOSURE CONNECTOR ELEMENT Not supported, zero.

INDEX

54 NUMBER OF ENCLOSURE CONNECTOR Not supported, zero

ELEMENT INDEXES

Protocol Stack Library

...........continued
Byte Description Notes

55 Reserved (0x00)

56 Reserved (0x00)[0:6]

56 REDUCED FUNCTIONALITY[7] .

56 NDSR INDICATION[6] Microchip Feature. Default zero.

57 TIME TO REDUCED FUNCTIONALITY

58 INITIAL TIME TO REDUCED FUNCTIONALITY

59 MAXIMUM REDUCED FUNCTIONALITY TIME

60–61 LAST SELF-CONFIGURATION STATUS

DESCRIPTOR INDEX

62–63 MAXIMUM NUMBER OF STORED SELF-

CONFIGURATION STATUS DESCRIPTORS

64 - 65 LAST PHY EVENT LIST DESCRIPTOR INDEX It equals maximum number of PHY event list
descriptors instead last recording index due to
firmware implementation.

66 - 67 MAXIMUM NUMBER OF STORED PHY EVENT

LIST DESCRIPTORS

68 - 69 STP REJECT TO OPEN LIMIT

70 - 71 Reserved (0x00)

72 CRC (MSB)

73 CRC

74 CRC

75 CRC (LSB)

14.7.3.2 Report Manufacturer Information

Firmware implements this feature in accordance with the SAS-2 standard.

14.7.3.3 Discover
Table 14-135. Discover Response Frame Format

Byte Description Notes

0 SMP Frame Type (0x41)

1 SMP Function (0x10)

2 SMP Function Accepted (0x00)

3 RESPONSE LENGTH (00h or 1Ah)

4-5 EXPANDER CHANGE COUNT

6-8 Reserved (0x00)

Protocol Stack Library

...........continued
Byte Description Notes

9 PHY Identifier

10 Reserved (0x00)

11 Reserved (0x00)

12 ATTACHED REASON [0:3]

12 Attached Device Type [6:4]

12 Reserved [7]

13 Negotiated logical Link Rate [3:0]

13 Reserved [4:7]

14 Attached SATA Host [0]

14 Attached SMP Initiator [1]

14 Attached STP Initiator [2]

14 Attached SSP Initiator [3]

14 Reserved [4:7]

15 Attached SATA Device [0]

15 Attached SMP Target [1]

15 Attached STP Target [2]

15 Attached SSP Target [3]

15 STP BUFFER TOO SMALL[4] Set it to 0

15 Reserved [5:6]

15 Attached SATA Port Selector [7]

16 SAS Address (MSB)

17 SAS Address

18 SAS Address

19 SAS Address

20 SAS Address

21 SAS Address

22 SAS Address

23 SAS Address

24 Attached SAS Address

25 Attached SAS Address

26 Attached SAS Address

Protocol Stack Library

...........continued
Byte Description Notes

27 Attached SAS Address

28 Attached SAS Address

29 Attached SAS Address

30 Attached SAS Address

31 Attached SAS Address

32 Attached PHY Identifier

33 ATTACHED BREAK_REPLY CAPABLE[0]

33 ATTACHED REQUESTED INSIDE ZPSDS [1]

33 - ATTACHED INSIDE ZPSDS PERSISTENT [2]

33 ATTACHED PARTIAL CAPABLE[3]

33 ATTACHED SLUMBER CAPABLE[4]

33 ATTACHED POWER CAPABLE[5:6]

33 Reserved [7]

34-39 Reserved(0x00)

40 Hardware Minimum Physical Link Rate [3:0]

40 Programmed Minimum Physical Link [7:4]

41 Hardware Maximum Physical Link Rate [3:0]

41 Programmed Maximum Physical Link Rate [7:4]

42 PHY Change Count

43 Partial Pathway Timeout Value [3:0]

43 Reserved [4:6]

43 Virtual PHY [7]

44 Routing Attribute [3:0]

44 Reserved [4:7]

45 CONNECTOR TYPE [0:6]

45 Reserved [7]

46 CONNECTOR ELEMENT INDEX

47 CONNECTOR PHYSICAL LINK

48 SATA PARTIAL CAPABLE[0]

48 SATA SLUMBER CAPABLE[1]

48 SAS PARTIAL CAPABLE[2]

Protocol Stack Library

...........continued
Byte Description Notes

48 SAS SLUMBER CAPABLE[3]

48 SAS POWER CAPABLE[4:5]

48 PHY POWER CONDITION[6:7]

49 SATA PARTIAL ENABLE[0]

49 SATA SLUMBER ENABLE[1]

49 SAS PARTIAL ENABLE[2]

49 SAS SLUMBER ENABLE[3]

49 Reserved[4:7]

50 Vendor Specific (0x00)

51 Vendor Specific (0x00)

The following are sas2.x introduced fields and not including SAS1.1 response frame

52 - 59 ATTACHED DEVICE NAME

60 ZONING ENABLED[0]

INSIDE ZPSDS [1]

ZONE GROUP PERSISTENT[2]

Reserved [3]

REQUESTED INSIDE ZPSDS[4]

INSIDE ZPSDS PERSISTENT[5]

REQUESTED INSIDE ZPSDS CHANGED BY

EXPANDER[6]

Reserved [7]

61 -62 Reserved(0x00)

63 ZONE GROUP

64 SELF-CONFIGURATION STATUS Not supported, zero.

65 SELF-CONFIGURATION LEVELS COMPLETED Not supported, zero.

66 - 67 Reserved(0x00)

68 - 75 SELF-CONFIGURATION SAS ADDRESS Not supported, zero.

76 - 79 PROGRAMMED PHY CAPABILITIES

80 - 83 CURRENT PHY CAPABILITIES

84 - 87 ATTACHED PHY CAPABILITIES

88 - 93 Reserved(0x00)

Protocol Stack Library

...........continued
Byte Description Notes

94 NEGOTIATED PHYSICAL LINK RATE[0:3]

94 Reason[4:7]

95 HARDWARE MUXING SUPPORTED[0]

95 NEGOTIATED SSC [1]

95 OPTICAL MODE ENABLED[2]

95 Reserved[3:7]

96 DEFAULT ZONING ENABLED [0]

Reserved [1]

DEFAULT ZONE GROUP PERSISTENT[2]

Reserved [3]

DEFAULT REQUESTED INSIDE ZPSDS[4]

DEFAULT INSIDE ZPSDS PERSISTENT [5]

Reserved [6:7]

97 - 98 Reserved(0x00)

99 DEFAULT ZONE GROUP

100 SAVED ZONING ENABLED [0]

Reserved [1]

SAVED ZONE GROUP PERSISTENT[2]

Reserved [3]

SAVED REQUESTED INSIDE ZPSDS[4]

SAVED INSIDE ZPSDS PERSISTENT [5]

Reserved [6:7]

101 - Reserved(0x00)
102

103 SAVED ZONE GROUP

104 SHADOW ZONING ENABLED[0]

104 Reserved [1]

SHADOW ZONE GROUP PERSISTENT[2]

Reserved [3]

SHADOW REQUESTED INSIDE ZPSDS[4]

SHADOW INSIDE ZPSDS PERSISTENT[5]

Protocol Stack Library

...........continued
Byte Description Notes

Reserved [6:7]

105-106 Reserved(0x00)

107 SHADOW ZONE GROUP

108 DEVICE SLOT NUMBER Indicates the number of the enclosure device slot to
which the phy provides access.

109 DEVICE SLOT GROUP NUMBER Not supported, Default value is 0xFF which indicates
that no enclosure number is available.

110-115 DEVICE SLOT GROUP OUTPUT CONNECTOR Not supported, Default value is 0x202020202020 (six
space characters) indicates that no device slot group
output connector information is available.

116 CRC (MSB)

117 CRC

118 CRC

119 CRC (LSB)

14.7.3.4 Report PHY Error Log

Firmware implements this feature in accordance with the SAS-2 standard.

14.7.3.5 Report PHY SATA

Table 14-136. Report PHY SATA Response Frame Format

Byte Description Notes

0 SMP Frame Type (0x41)

1 SMP Function (0x12)

2 SMP Function Accepted (0x00)

3 RESPONSE LENGTH (00h or 10h)

4 -5 EXPANDER CHANGE COUNT

6 -8 Reserved (0x00)

9 PHY Identifier

10 Reserved (0x00)

11 Affiliation Valid [0]

11 AFFILIATIONS SUPPORTED [1]

11 STP I_T NEXUS LOSS OCCURRED[2]

12 Reserved (0x00)

13 Reserved (0x00)

14 Reserved (0x00)

Protocol Stack Library

...........continued
Byte Description Notes

15 Reserved (0x00)

16 STP SAS Address

17 STP SAS Address

18 STP SAS Address

19 STP SAS Address

20 STP SAS Address

21 STP SAS Address

22 STP SAS Address

23 STP SAS Address

24 Register Device to Host FIS

25 Register Device to Host FIS

26 Register Device to Host FIS

27 Register Device to Host FIS

28 Register Device to Host FIS

29 Register Device to Host FIS

30 Register Device to Host FIS

31 Register Device to Host FIS

32 Register Device to Host FIS

33 Register Device to Host FIS

34 Register Device to Host FIS

35 Register Device to Host FIS

36 Register Device to Host FIS

37 Register Device to Host FIS

38 Register Device to Host FIS

39 Register Device to Host FIS

40 Register Device to Host FIS

41 Register Device to Host FIS

42 Register Device to Host FIS

43 Register Device to Host FIS

44 – 47 Reserved (0x00)

48 Affiliated STP Initiator SAS Address

Protocol Stack Library

...........continued
Byte Description Notes

49 Affiliated STP Initiator SAS Address

50 Affiliated STP Initiator SAS Address

51 Affiliated STP Initiator SAS Address

52 Affiliated STP Initiator SAS Address

53 Affiliated STP Initiator SAS Address

54 Affiliated STP Initiator SAS Address

55 Affiliated STP Initiator SAS Address

56 - 63 STP I_T NEXUS LOSS SAS ADDRESS

64 Reserved (0x00)

65 AFFILIATION CONTEXT PM8005/PM8004 support single affiliation, it is zero.

66 CURRENT AFFILIATION CONTEXTS

67 MAXIMUM AFFILIATION CONTEXTS PM8005/PM8004 supports single affiliation, it is one.

68 CRC (MSB)

69 CRC

70 CRC

71 CRC (LSB)

14.7.3.6 Report Route Information

Firmware implements this feature in accordance with the SAS-2 standard.

14.7.3.7 Configure Route Information

Firmware implements this feature in accordance with the SAS-2 standard.

14.7.3.8 PHY Control

SMP PHY CONTROL LINK RESET to a zoning expander will also trigger Firmware to increase the internal counter
on EXPANDER CHANGE COUNT as the zone PHY information will be updated after link reset sequences.
Additionally, there are also two DSQ specific operations:
Table 14-137. Additional SMP PHY Operation

Code Operation Description

0xAA DSQ_Disable Disable disk qualification

0xAB DSQ_Enable Enable disk qualification

If the PHY IDENTIFIER field specifies the PHY that is in the same wide port with the one being used for the SMP
connection and a PHY operation of HARD RESET is requested, the function result SMP FUNCTION FAILED is
returned in the response frame.
PHY Control adds support for ENABLE SAS SLUMBER, ENABLE SAS PARTIAL, ENABLE SATA SLUMBER,
ENABLE SATA PARTIAL bits.

Protocol Stack Library

14.7.3.9 PHY Test Function

Supports JTPAT/CJTPAT/Scramble_0 PHY Test Pattern.

14.7.3.10 Report Broadcast

Firmware implements this feature in accordance with the SAS-2 standard.

14.7.3.11 Configure General

Table 14-138. Configure General Request Frame Format

Byte Description Notes

0 SMP Frame Type (0x40)

1 SMP Function Type (0x80)

2 ALLOCATED RESPONSE LENGTH

3 REQUEST LENGTH (04h)

4-5 EXPECTED EXPANDER CHANGE COUNT

6-7 Reserved(0x00)

8 UPDATE STP BUS INACTIVITY TIME LIMIT [0]

8 UPDATE STP MAXIMUM CONNECT TIME LIMIT[1]

8 UPDATE STP SMP I_T NEXUS LOSS TIME [2]

8 UPDATE INITIAL TIME TO REDUCED FUNCTIONALITY[3]

8 UPDATE STP REJECT TO OPEN LIMIT [4]

8 Reserved[5-7]

9 Reserved

10 -11 STP BUS INACTIVITY TIME LIMIT

12 - 13 STP MAXIMUM CONNECT TIME LIMIT

14 - 15 STP SMP I_T NEXUS LOSS TIME To SMP connection

0000h/FFFFh:
The port will never recognize an I_T
nexus loss (that is, it will retry the
connection requests forever).
0x0001 to 0xFFFE:
Time in milliseconds.
To STP connection:
0x0000, 0x2000 to 0xFFFF:
The port will never recognize an I_T
nexus loss (that is, it will retry the
connection requests forever).
0x0001 to 0x1999: Time in milliseconds.

16 INITIAL TIME TO REDUCED FUNCTIONALITY

17 POWER DONE TIMEOUT

Protocol Stack Library

...........continued
Byte Description Notes

18 - 19 STP REJECT TO OPEN LIMIT Not supported due to hardware

20 CRC (MSB)

21 CRC

22 CRC

23 CRC (LSB)

14.7.3.12 Report Self Configuration Status

Firmware has implemented the SMP interface for the management application client to query the logs of Self-
Configuration Status. Refer to chapter 17.3 SMP Self Configuration Event Logging.

14.7.3.13 Report PHY Event and Report PHY Event List

1. The firmware support 5+4 kinds of PHY events, four are implicated and four should be explicated configured
by initialization string (Table 8-18).
The firmware supports 5 PHY Event sources:
• Invalid Dword count(0x01)
• Running disparity err count (0x02)
• Loss of Dword sync count(0x03)
• PHY reset problem count(0x04)
• Address frames err count(0x05)
1. The firmware supports four of the following PHY Event sources by configuring it in initialization string (Table
8-18).
– Transmitted abandon class open reject count(0x21)
– Received abandon class open reject count (0x22)
– Transmitted retry class open reject count (0x23)
– Received retry class open reject count (0x24)
– Received AIP waiting on partial count (0x25)
– Received AIP waiting on connection count (0x26)
– Received break count (0x28)
– Break time count (0x29)
– Connection count (0x2a)
– Received SSP frame count (0x41)
– Received SSP frame error count (0x43)
– Received credit blocked count (0x45)
– Received SATA frame count (0x51)
– SATA flow control buffer overflow count (0x52)
– Received SMP frame count (0x61)
– Received SMP frame error count(0x63)
2. PHY Event descriptor index: PHY Event descriptors are sorted by PHY Identifier. Each PHY Identifier is
assigned a maximum of possible PHY event sources (6 here). For example PHY 0 is assigned 1-6, PHY1 is
assigned 7 - 12 and so on.
The SMP target firmware uses a fixed number of PHY Event descriptors. The Last PHY Event List Descriptor index
equals to the maximum number of PHY event descriptors.

14.7.3.14 Discover List

With hardware SMP assistance, SMP function processing performance is improved on multiple levels.
For the SMP Discover List command, firmware:

Protocol Stack Library

• Reads 19 necessary SSPL/SXL/ECMR registers for each PHY descriptor in a critical section. The time to
access all these registers is around 100us
• Adds additional checks for ensuring the PHY information data coherency in SMP DISCOVER Response fields.
• Records the timestamps when the egress request interrupt is received and checks the timestamps when
firmware populates each PHY descriptor. If the time consumed is longer than 1.5ms, firmware stops populating
the descriptors and transmits the filled descriptors in the response.

14.7.3.15 Report Expander Route Table List

SXP 12G device maps the whole ECMR hash table into a block of continuous memory so as to access all ECMR
hash entries without polling delay.

14.7.3.16 Report Zone Permission Table

Firmware implements this feature in accordance with the SAS-2 standard.

14.7.3.17 Report Zone Manager Password

Firmware implements this feature in accordance with the SAS-2 standard.

14.7.3.18 Enable Disable Zoning

Firmware implements this feature in accordance with the SAS-2 standard.

14.7.3.19 Zoned Broadcast

Firmware implements this feature in accordance with the SAS-2 standard.

14.7.3.20 Zone Lock

Firmware implements this feature in accordance with the SAS-2 standard.

14.7.3.21 Zone Activate

As zone activate step sets the zoning expander current values equal to the zoning expander shadow values,
Firmware increases the internal counter to get accumulated on top of the existing global EXPANDER CHANGE
COUNT value for SMP ZONE ACTIVATE though there is no primitive generation.
Firmware implements this feature in accordance with the SAS-2 standard.

14.7.3.22 Zone Unlock

Firmware implements this feature in accordance with the SAS-2 standard.

14.7.3.23 Configure Zone Manager Password

Firmware implements this feature in accordance with the SAS-2 standard.

14.7.3.24 Configure Zone PHY Information

Firmware implements this feature in accordance with the SAS-2 standard.

14.7.3.25 Configure Zone Permission Table

Firmware implements this feature in accordance with the SAS-2 standard.

14.7.4 SMP Functions Specific to Microchip

The SMP subsystem contains some functions that are proprietary to Microchip.

14.7.4.1 Microchip Report Status

The Microchip Report Status function implements a vendor-specific backdoor register access into the Expander
device’s internal status information, which lets you to support and debug specific PHYs. The function performs
backdoor triggers to retrieve the information. The format of the corresponding request frame is listed in the following
table.
Table 14-139. Microchip Report Status Request Frame Format

Byte Description

0 SMP Frame Type (0x40)

Protocol Stack Library

...........continued
Byte Description

1 SMP Function Type (0x79)

2 Reserved

3 Reserved

4 Ignored

5 Ignored

6 Ignored

7 Ignored

8 Reserved

9 PHY Identifier

10 Ignored

11 Reserved

12 CRC (MSB)

13 CRC

14 CRC

15 CRC (LSB)

The format and source of information for the Microchip Report Status response frame are detailed in the following
table.
Table 14-140. Microchip Report Status Response Frame Format

Byte Description

0 SMP Frame Type (0x41)

1 Function Type (0x79)

2 SMP Function Accepted (0x00)

3 Reserved

4 Ignored

5 Ignored

6 Ignored

7 Ignored

8 Reserved

9 PHY Identifier: Specifies the PHY number of the link configuration being requested.

10 Ignored

11 Reserved

Protocol Stack Library

...........continued
Byte Description

12 Reserved

13 Reserved

14 Reserved

15 Reserved

16 ECMR Register 0x00(MSB)

17 ECMR Register 0x00

18 ECMR Register 0x00

19 ECMR Register 0x00(LSB)

… ...

268 ECMR Register 0x3F(MSB)

269 ECMR Register 0x3F

270 ECMR Register 0x3F

271 ECMR Register 0x3F(LSB)

272 SXL Register 0x00(MSB)

273 SXL Register 0x00

274 SXL Register 0x00

275 SXL Register 0x00(LSB)

… ...

524 SXL Register 0x3F(MSB)

525 SXL Register 0x3F

526 SXL Register 0x3F

527 SXL Register 0x3F(LSB)

528 SSPL Register 0x00(MSB)

529 SSPL Register 0x00

530 SSPL Register 0x00

531 SSPL Register 0x00(LSB)

... ...

652 SSPL Register 0x1F(MSB)

653 SSPL Register 0x1F

654 SSPL Register 0x1F

655 SSPL Register 0x1F(LSB)

Protocol Stack Library

...........continued
Byte Description

656 CRC (MSB)

657 CRC

658 CRC

659 CRC (LSB)

14.7.4.2 Microchip Read

The vendor-specific Microchip Read function lets you read from the ECBI registers in the device. The format of the
corresponding request frame is detailed in the following table.
Table 14-141. Microchip Read Request Frame Format

Byte Description

0 SMP Frame Type (0x40)

1 SMP Function Type (0x7A)

2-3 Reserved

4-7 Ignored

8 Memory Address (MSB)

9 Memory Address

10 Memory Address

11 Memory Address (LSB)

12 - 14 Reserved

15 Read Length

16 CRC (MSB)

17 CRC

18 CRC

19 CRC (LSB)

The format and source of information for the Microchip Read response frame are detailed in the following table.
Table 14-142. Microchip Read Response Frame Format

Byte Description Notes

0 SMP Frame Type (0x41)

1 SMP Function (0x7A)

2 SMP Function Accepted (0x00)

3 Reserved (0x00)

4 Ignored

Protocol Stack Library

...........continued
Byte Description Notes

5 Ignored

6 Ignored

7 Ignored

8 Memory Address (MSB) Echo from received SMP Request Frame.

9 Memory Address Echo from received SMP Request Frame.

10 Memory Address Echo from received SMP Request Frame.

11 Memory Address (LSB) Echo from received SMP Request Frame.

12 Reserved

13 Reserved

14 Reserved

15 Read Length Echo from received SMP Request Frame.

16 + Read Data[0](MSB)
Read
Length*4

Read Data[0]

Read Data[0](LSB)

N–3 CRC (MSB)

N–2 CRC

N–1 CRC

N CRC (LSB)

14.7.4.3 Microchip Write

The vendor-specific Microchip Write function lets you write to the ECBI registers in the device. The format of the
corresponding request frame is detailed in the following table.
Table 14-143. Microchip Write Request Frame Format

Byte Description

0 SMP Frame Type (0x40)

1 SMP Function Type (0xFA)

2-3 Reserved

4-7 Ignored

Protocol Stack Library

...........continued
Byte Description

8 Memory Address (MSB)

9 Memory Address

10 Memory Address

11 Memory Address (LSB)

12 Write Operation
Valid values:
0x00 NOP
0x01 Write data.
0x04 Bitwise AND with write data
0x05 Bitwise OR with write data
0x06 Bitwise XOR with write data

13 - 14 Reserved

15 Write Length

16 –

16 + Write Write Data[0](MSB)

Length*4

Write Data[0]

Write Data[0](LSB)

N–3 CRC (MSB)

N–2 CRC

N–1 CRC

N CRC (LSB)

The requisite registers are written accordingly. The format and source of information for the Microchip Write response
frame are detailed in the following table.
Table 14-144. Microchip Write Response Frame Format

Byte Description

0 SMP Frame Type (0x41)

1 SMP Function (0xFA)

2 SMP Function Accepted (0x00)

3 Reserved

Protocol Stack Library

...........continued
Byte Description

4 CRC (MSB)

5 CRC

6 CRC

7 CRC (LSB)

Note that both Microchip-specific SMP Read and Write commands are intended for accessing 8-bit registers aligned
on 32-bit address boundaries, as most of the registers in the expander devices are. As such, there is no guarantee
that these commands properly access 32-bit registers.

14.7.4.4 Microchip Disk Qualification Status

The vendor-specific Microchip Disk Qualification Status function lets users to poll SXP for disk qualification status and
reasons. The format of the corresponding request frame is detailed in the following table.
Table 14-145. Microchip Disk Qualification Status Request Frame Format

Byte Description

0 SMP Frame Type (0x40)

1 SMP Function Type (0x7C)

2-8 Reserved

9 PHY ID

10-11 Reserved

12 CRC (MSB)

13 CRC

14 CRC

15 CRC (LSB)

The format and source of information for the Microchip DSQ Status response frame are detailed in the following
table.
Table 14-146. Microchip Disk Qualification Status Response Frame Format

Byte Description

0 SMP Frame Type (0x41)

1 SMP Function Type (0x7C)

2-8 Reserved

9 PHY ID

10-13 Reserved

14 Pass status (Disk attached to PHY has passed disk qualification or not)

15 Reason code (Reason of PASS or FAIL)

Protocol Stack Library

...........continued
Byte Description

16 CRC (MSB)

17 CRC

18 CRC

19 CRC (LSB)

14.8 Serial Management Protocol (SMP) Transport Layer

The SMP Transport Layer ends SMP messages from the SMP Initiator in the SAS Port thread’s Application Message
Queue. Unlike the SSP Transport layer, the SMP Initiator transport layer needs the SMP Initiator application to
completely format the content of the SMP frames for transmission and parse the content of the received SMP frames.
The SMP Transport layer only provides a context for accessing the port layer.
Note that the SMP Transport Layer is only involved in SMP Initiator transactions. The SMP Target application has no
inputs to the SAS Port other than exporting a functional API that the SAS Port Thread invokes.

14.8.1 SMP Initiator Transport Layer

The SMP Initiator Transport Layer consists of a single state machine that is instantiated on the receipt of a Serial
Management Protocol Request message.
The SMP Initiator Transport layer sends the SMP Request Frame to the Port Layer for transmission and returns the
received SMP Response frame to the SMP Initiator application as a Received SMP Function Complete Message.

14.9 SAS Port Layer

The Port Layer establishes connections on the PHY for both the SSP and SMP protocols. The Port Layer manages
the PHY interface and provides a bridge between the connectionless SSP/SMP Transport Layers and the PACK_LT
device which implements the link layer (SL) in hardware.
The Port Layer consists of a number of state machines that implement the functionality contained within the PL_OC
and PL_PM state machines described in SAS 1.1. The state machines are combined because there is only be one
PHY supported.
The port layer operates as a port control state machine that manages connections on a single SAS PHY.
When connections are opened, one or more protocol specific state machine instances are started to handle the
transmission and reception of SAS frames and any global events that can occur.
The SAS port handles received (egress) frames asynchronously as they arrive on an open connection. Ingress
frames are queued on a per-connection basis with the port layer assuming the responsibility of opening the required
connections to transmit the queued frames. Ingress frames are transmitted to completion for one connection before
moving on to the next connection. Connections are opened in the order that they are received as part of the frame
transmission requests from the transport layer. If a connection is opened by a peer endpoint, any ingress frames
queued for that destination are transmitted even if the ingress frames were queued against a connection further down
the list of connections to open.
As specified in the SAS 1-1 specification, the number of credits is set to zero when a connection is opened. The SAS
Port immediately grants one credit to the destination if there are internal buffers available. The SAS will never grant
more than one credit at a time.

14.10 Dethroughtions from the SAS Standard

Several simplifications were made during the course of the development of the SAS Port component. This section
describes these simplifications and addresses why each was included.

Protocol Stack Library

14.10.1 SAS Transport Layer

The following table identifies specific dethroughtions to the implementation of the transport layer functionality from the
implementation described in SAS 1.1[3].
Table 14-147. Transport Layer Dethroughtions from SAS 1.1

SAS 1.1 Dethroughtion Reasoning

The SSP target transport layer state SSP DATA frames required to send The port layer is already designed to
machine (ST_T) sends each DATA the data requested to be transferred queue frames for transmission.
frame of a Send Data In Operation in a Send Data In command from
Should have no effect on the
to the Port Layer for transmission one the SCSI application are sent to the
initiator’s ability to receive the data
at a time, waiting for a Transmission Port Layer for transmission without
frames.
Status (frame transmitted) before waiting for the transmission status
sending the next frame. (frame transmitted) status point to be Simplifies the transport layer
returned after each one.

14.10.2 Port Layer

The following table identifies specific dethroughtions to the implementation of the port layer functionality from the
implementation described in SAS 1.1[3].
Table 14-148. Port Layer Dethroughtions from SAS 1.1

SAS 1.1 Dethroughtion Reasoning

SMP Transmit Break The SMP Transmit Break command is not There is no transport layer
supported. code fast enough to use this
effectively.

Support for a Wide Port (multiple The Port Layer Port Control State machine Support for multiple PHYs is not
PHYs per port) for virtual SSP port only supports a single PHY (narrow port) for required for virtual SSP port.
virtual SSP port

SSP Data Frames are transmitted The Port Layer SSP Transmit state machine This is required for
as non-interlocked frames only transmits interlocked SSP frames the enclosure management
application.

14.11 Telnet, TCP/IP and Ethernet

The TCP/IP layer supports IPv4 addressing and provides support for baseline operations including frame
management, retransmission, error checking. The TCP/IP stack can also support applications such as PING, DHCP,
TELNET and HTTP.
Note: The Ethernet feature is for the PM805x device only.

14.11.1 IPv4
The TCP/IP stack supports IPv4 service with common network protocol such as UDP, TCP, ICMP, ARP, and so on
The TCP/IP stack is optional for building the firmware image. If the macro option “–DTCPIP_ENABLE” is defined in
the project file(.gpj), the TCP/IP stack will be built into the firmware image. If TCPIP_ENABLE is not defined, the
TCP/IP stack will not be built into the firmware image, and network applications such as the telnet server, HTTP
server and DHCP will not be supported.

14.11.2 DHCP
Firmware includes a DHCP client to retrieve IP network configuration information from the DHCP Server when the
IP stack module initializes. The network configuration information includes the IP address, netmasks and the default
gateway IP address.
DHCP client functionality can be configured through the initialization string field. When disabled, the IP stack module
loads the default IP network configuration information from the initialization string fields during module initialization.

Protocol Stack Library

Users can query the current IP network configuration information of the IP stack module through the UART console
command “ipconfig”. If DHCP is ON, issue the command “ipconfig dhcp 1” to retrieve the IP address from the DHCP
server.

14.11.3 Telnet/CMDSVR
Using the telnet interface, users can log in and then execute all available commands supported by the CMDSVR
such as memory read/write, SES page retrieval and SMP commands. The register GUI accesses the expander
product using the telnet interface in the same manner as the UART interface, which is the only interface for SXP3G
product.
The telnet server is designed to allow only one active telnet connection at any time to prevent command sequences
from different telnet terminals being issued at the same time because some command sequences (such as the. SMP
command) must be executed atomically. For the same reason, although CMDSVR is available in both telnet and
UART modes, it is not recommended that UART CMDSVR and telnet CMDSVR be used simultaneously.

14.11.4 HTTP
The HTTP server facilitates the access and management to an embedded system by providing a standard web
browser interface. Firmware provides an HTTP1.1-based HTTP server along with a basic web page example. Note,
there are no specific services provided to control expander operations through this web page; Optional headers in
HTTP message are also unsupported (e.g., If-Modified-Since). Users have the flexibility to enhance the web interface
to meet their specific needs.
If the macro option “–DTCPIP_ENABLE” and “–DHTTP_ENABLE” are defined in the project file(.gpj), the HTTP
server is built into the firmware image. By default, HTTP server is disabled in firmware.
The HTTP service is embedded with a simple file system in which the web page is stored. Microchip provides a
simple file system image as an example for you to build your own.
The web pages used to create example file system image are located in the “\tr_tcpip\httpdemo\romfs\demopage”
folder. The file system image is trrombld.h and txrom0.c located under “\SXP 12G\src\tcpip” directory.
The ROM FS Builder is provided as a GUI tool named trromfs.exe which can be found under
\trk_tcpip\httpdemo\romfs\. This tool allows you to build a file system image from the files under an “Input Directory”
(including its subdirectories). The generated image is a “.h” file and several “.c” files. The default “.h” file is trrombld.h
and will be output to “Output .h Directory”. Each page/segment of the file system is contained in a separate “.c” file
(txrom0.c, txrom1.c, txrom2.c, txrom3.c and txrom4 and so on) and will be output to “Output .c Directory”.
Notes
• Before using ROMFS Builder, make sure to clear the archive file attribute of “Input Directory” and all its
subfolders. For example, issue command “attrib –R -A c:\tmp” to changes the directory attributes.
• The default filename for home page is “index.htm”. Currently firmware doesn’t provide method to change the
default filename.
By default, the HTTP server only provides a simple web page as a demo. To use a new file system image, follow
these steps:
1. Prepare the file system image used by the HTTP server.
2. Run “\trk_tcpip\httpdemo\romfs\trromfs.exe”.
3. Set “Input Directory” to “\tr_tcpip\httpdemo\romfs\demopage”.
4. Set “Output .h Directory” and “Output .c Directory” to “\SXP 12G\src\tcpip”.
5. Click Build to generate the new image files. See “How to Create file system image for HTTP server” for detail.
6. Add all image “.c” files(txromN.c) into “\SXP 12G\tcpip\ txrom.c” as the following examples:
#include “txrom0.c”
#include “txrom1.c”
#include “txrom2.c”
#include “txrom3.c”
……

Protocol Stack Library

7. Open the top project file “\SXP 12G\build\sxp_pmc_evbd.gpj” or “\SXP 12G\build\sxp_wks_evbd.gpj” to build
firmware image.

14.11.5 Ethernet
The Ethernet driver runs in interrupt-based mode and provides frame management including frame receiving/
transmitting, collision detect and error recovery. The Ethernet driver also provides PHY layer configuration
functionality such as setting (or auto-negotiating) the link speed and Duplex mode.
Before the Ethernet driver starts, it should be assigned a unique 48-bit MAC address. MAC address can be
configured in initialization string

14.11.6 ipconfig Command

The firmware provides the command ipconfig to set IP address/netmask/gateway online. See the following for
ipconfig command help. (Note: ipconfig does not save the configuration into flash memory.)
ipconfig - Show IP configuration
ipconfig help - This command
ipconfig macb [verbose] - Print MACB Statistics
ipconfig dhcp 1 - Config DHCP ON
ipconfig dhcp 0 [option] - Config DHCP OFF
option: ip ip_address
nm net_mask
gw gate_way

PHY and Power Management

15. PHY and Power Management

15.1 Managed SAS Connector Support

15.1.1 Introduction
Firmware manages the SAS 2.1 Mini SAS HD connector through connector management interfaces on the
PM2513/14/15/16/32-KIT SXP 24/36/48/68/36Sx12G Evaluation Kit [28]. The connector management interface is
defined in the following table and in SFF-8644.
Table 15-1. Connector Management Interface

Signal Description Board Support in FPGA Firmware Actions

IntL Active Low The IntL and ModPrs are routed to In the interrupt service routine, firmware
Module Interrupt the FPGA logic in the SXP 12G FVB identifies the Module interrupt reason by
board. The FPGA feeds the connector reading the cable management interface
interrupt to the SXP 12G INITB [0]. memory map through the TWI. Firmware
provides the callback for the action for the
The FPGA logic provides the interrupt
corresponding reason.
cause register for firmware identifying
ModPrs Active Low these connector events: If it is a connector connected event,
L Module Present - Module interrupt firmware reads the connector profile and
makes the PHY configuration change on
- Connector connected the corresponding PHY.
- Connector disconnected If it is a connector disconnected event,
firmware does cleanup on the previous PHY
settings.

SCL Two-wire Direct TWI bus connection to SXP or Firmware reads the connector profiles from
interface clock to TWI Expander that is connected to the management interface memory map
SXP. registers. See SAS-2.1
SDA Two-wire
interface data

Vact Active cable The FPGA logic provides firmware Firmware turns on Vact when detecting an
power control interface for turning on/off Vact. Active Cable connected.

Vman Management The FPGA logic provides firmware Firmware may turn off when entering low
interface power control interface for turning on/off power mode.
Vman.

Table 15-2. Managed Connectors Supported in SDK

SAS-2.1 Managed Connector Managed in SDK Static configuration thru

categories initialization string

Mini SAS HD external connector Supported Supports static configuration

QSFP+ connector Supported Supports static configuration

15.1.2 FPGA Logic

The SXP SDK cable management implementation relies heavily on characteristics of the board design such as the
cable event interrupt implementation and the TWI port connection. Microchip evaluation boards use the FPGA logic
to implement cable event management and the INTIB[0] interrupt as the interrupt source for all SAS connectors.

PHY and Power Management

PM805x devices can access the FPGA registers directly through Local bus (CS2) and PM804x devices can access
the FPGA registers through TWI port 1 with slave address 0x6A.
The FPGA logic in the SXP 24/36/48/68/36Sx12G Evaluation Kit [28] provides some support for SAS connector
management, including registers and interrupt assertion to MBIC.
The registers supported include interrupt registers, interrupt mask registers and status registers. For detailed register
information, refer to section 7.1 FPGA Memory Map of reference document [31].
FPGA registers can be accessed through the local bus for PM8056/55/54/53 devices and through the TWI bus for
PM8044/43 devices. By default, the SXP 12G uses TWI port 1 to access FPGA registers for the PM8044/43 devices.
If any FPGA interrupt register bit is asserted, FPGA logic sends an active-low signal to MBIC interrupt source
INTIB[0], which causes MBIC to assert an interrupt to MIPS, if this interrupt is enabled.

15.1.3 Firmware Implementation

A firmware connector management thread is created to read cable information from SEEPROM through the TWI bus
and perform corresponding connector and cable management.
The connector management thread is driven by interrupt events. The firmware interrupt service routing for these
interrupt events only sends the event notification to the connector management thread. When a cable is plugged in,
the thread accesses the cable’s memory map and configures the PHY settings according to the cable type, length,
and rate. For example:
• Optical cable: Active power is turned on, SAS-2.1/3.0 optical mode is enabled and PTT is disabled.
• Active cable: Active power is turned on, and PTT is disabled.
• Passive cable: PTT is enabled.
If the cable is not manageable or if firmware is unable to access its SEEPROM, the PHYs in this connector are
not enabled. When a cable is unplugged, a connector management thread clears the cable information and restores
the PHY settings. Firmware can report events to the application, including cable warning/alarming events, through
callback functions.
The SXP 12G expander families support 12 TWI master ports. If you need to manage more than 12 connectors,
use bus switch logic. The Microchip evaluation board for the PM8056/55 uses 2 TWI expanders and 6 TWI ports to
access a total of 17 SAS connectors. The Microchip evaluation board for the PM8054/53/44/43 uses 9 TWI ports to
access a total of 9 SAS connectors.
Refer to the Microchip reference kit for implementation detail. Table 15-3 and Table 15-4 list the map of TWI ports and
SAS ports on Microchip FVB boards.
Table 15-3. Map of TWI and SAS Ports on the SXP 68-Port FVB

SAS Connector Bus Switch Logic DUT TWI

Expander Channel

0 3

1 2 6 7

2 4

3 1 7 2

4 5

5 1 6 2

6 6

7 1 5 2

8 2 0 7

PHY and Power Management

...........continued
SAS Connector Bus Switch Logic DUT TWI

Expander Channel

9 1 4 2

10 2 5 7

11 1 3 2

12 2 4 7

13 1 2 2

14 2 3 7

15 1 0 2

16 2 2 7

Table 15-4. Map of TWI Ports and SAS Ports on the SXP 36-Port FVB

SAS Connector DUT TWI Notes

0 3 3

1 4 4

2 5 5

3 6 6

4 7 7

5 9 Cannot be used due to SGPIO muxing on this TWI port.

6 10 Cannot be used due to SGPIO muxing on this TWI port.

7 2 2

8 11 Cannot be used due to SGPIO muxing on this TWI port.

Managed connectors are configured through the initialization string (Refer to Table 8-17). By default, the SXP 12G
disables the cable management feature by setting the manage type to 0. To enable this feature, set the manage type
to 1.
After enabling the cable management feature, enter “cinfo connector_id” through the command server interface to
get the inserted cable information. The only parameter “connector_id” means the number of connectors the cable is
inserted into. For example, the command “cinfo 0” will output information for the first cable:

This SAS connector can be managed

And manageable cable is present
The cable information is as follows:
Active: No
Ident: 0x0f
Ext Ident: 0x00
Type: 0x21
SAS/SATA Rate: 0x30
Trans Tech: 0x0a
Device Tech: 0x00
Max Temp: 0x46
Length: 0x00000002
vend Name: SC
vend Partial Number: SA-7044-2M

PHY and Power Management

vend Reversion: 00
Log PHY in connector: 0x00 0x01 0x02 0x03

15.2 Optical Cable Support

Firmware supports enabling the SAS-2.1 optical mode in the SXP 12G PHY(s) according to the PHY optical mode
settings in the initialization string. The default 512 Dwords of STP flow control buffer size in the SXL12G block
provides support for an optical cable length of much longer than 100m.

15.3 Coordination of SAS Device Power Consumption

The SPL-2 standard adds four new primitives to facilitate the coordination of multiple devices requiring additional
power. This allows expanders and HBAs to directly manage the PHYs’ power and to limit when the end devices can
spin up. The SXP 12G supports power control as the source power device for processing requests for additional
power consumption.
SXP 12G firmware supports this function in the following two ways:
• Firmware implements link layer source power device state machine (SL_P_S) based on the hardware capability
of transmitting/receiving the four new power control primitives:
– PWR_ACK. PWR_ACK specifies the positive acknowledgement of PWR_DONE, PWR_GRANT, or
PWR_REQ
– PWR_DONE. PWR_DONE is used by an end device to indicate it has completed consumption of the
additional power requested as a result of a PWR_GRANT
– PWR_GRANT. PWR_GRANT is used to specify that an end device may consume additional power
– PWR_REQ. PWR_REQ is used by an end device to request the consumption of additional power
• Firmware uses the SSU algorithm to coordinate the power consumption in multi-drive systems and to control
granting the power permissions. See the section 10.4 Disk Spin-up.

15.4 Wake-on-LAN / Wake-on-SAS

Market forces in today’s “green” environment dictate that enterprise storage devices minimize operating power and
contain very low power sleep modes when they are taken offline for a period of time.
To meet these requirements, the SXP 12G defines two modes and approaches for controlling entering and leaving
low power sleep mode: Wake-On-LAN (WOL) (PM805x devices only) and Wake-On-SAS (WOS).
The SXP 12G expander enters low-power sleep mode when either of the following conditions is met:
• In-band String Out SES page (Sleep on LAN) command in Wake-On-LAN mode or
• All upstream PHYs come OFF state for a WOS SLEEP DELAY TIME period of time.
See Table 15-6 for details on the in-band String Out SES page (Sleep on LAN) command.
The SXP 12G expander in low-power sleep mode clock-gates most of its hardware modules. The DPRAM (75M),
MBIC, memory controller, reset synchronizer, AXI interconnect, register slices, X2H bridge, and MAC modules are
never clock-gated.
Table 15-5. Clock Control of SXP 12G Modules

Modules Control Method WOL WOS

MTSB_REG_RSTB
All MTSBs are in SAS-3 power down
Analog MTSB MTSB_APB_RSTB All MTSBs sleep mode except for upstream MTSBs

CSU CSU0/1/2_ARSTB Reset Not reset

PHY and Power Management

...........continued
Modules Control Method WOL WOS

SSPL
PHY_CORE_PWRDOWN[68:0]
SXL PHY_XCBI_PWRDOWN[68:0] All PHYs Sleep All PHYs sleep except upstream PHYs

ECMR ECMR_CLK_PWRDOWN Sleep Sleep

All EMIPs sleep except upstream

EMIP EMIP_LOWPOWER All EMIPs Sleep EMIPs

FWS FWS_OCR_SHUT_DOWN Sleep Sleep

PACK

SGPIO EXTSS_CORE300_PWRDOWN Sleep Sleep.

TWI

UART

GPIO

Watchdog

Timer

X2P bridge EXTSS_CORE75_PWRDOWN Sleep Sleep

Internal SPRAM SPRAM_SD_ENABLE Sleep Not Sleep

Internal DPRAM DPRAM_SD_ENABLE Sleep Sleep

MIPS Core WAIT instruction Sleep Sleep

The following events wake up the SXP 12G expander from WOL/WOS sleep mode:
• For WOL, the Magic Packet arrives in the Ethernet MAC that generates NMI to the MIPS core, the processor
reloads its PC to the MIPS starting address and restarts the boot procedure.
• For WOS, a COMINIT primitive detected from any of the upstream PHYs that generate interrupts to wake up
the MIPS core and all hardware blocks in sleep mode are recovered to the normal state in the firmware interrupt
process routine. Afterward, firmware continues to run from the point it was before entering WOS.
The current SXP 12G SDK does not support enabling WOL and WOS at the same time. Specifically, if the SXP
12G enters sleep mode through the WOL sleep command, it can be woken up only by receiving a Magic Packet
in the Ethernet MAC port. If the SXP 12G enters WOS sleep mode, it can be woken up only by receiving COMINIT/
COMWAKE interrupts from upstream PHYs.
WOL and WOS have similar state transitions except for the state transition after being woken up. See the following
figure.

PHY and Power Management

Figure 15-1. WOL/WOS State Transition Diagram

15.4.1 WOL Implementation

Note: The WOL feature is for the PM805x device only.

15.4.1.1 Sleep on LAN Condition

If WOL is enabled in the SXP 12G and the device receives an SES string out page (Sleep on LAN) command, the
SXP 12G starts the SLEEP DELAY timer. The purpose of the SLEEP DELAY time is for the host to do cleanup. For
example, it completes the outstanding I/Os to disk and SES target, puts the disk in low-power mode, and shuts down
the fan. When the timer expires, the SXP 12G prepares to enter sleep mode. The timeout delay value is defined in
this SES page or in the initialization string WOL SLEEP DELAY TIME field. (See Table 15-6, Table 15-7, and Table
17-3)
Table 15-6. SES String Out Page - (Sleep on LAN) Command

Component Name Bytes Field Name Value Notes

0 Page Code 0x04 String Out SES page code

1 Sub-Enclosure 0x00

Identifier
Page Header
2-3 (MSB) 0x0006 The length of String Out data is 6
bytes.
Page Length (n-3)
(LSB)

PHY and Power Management

...........continued
Component Name Bytes Field Name Value Notes

4 Command 0x03 General WOL/WOS command

5 Subcommand 0x00 Sleep on LAN command

The delay from firmware receives a

WOL SES page start command to
Vendor Specific ready firmware to enter sleep mode.
If the timeout delay is zero, then the
(LSB) default time delay in the initialization
string (offset 0x14D8 - 0x14DB) is
Parameter 0x00000000
used. The time unit is milliseconds
6-9 (MSB) Or other values (ms).

Note
Due to the maximum timeout value of the current application timer of 57266230us, the valid range for the WOL sleep
delay time is 0x0~0xDFB2

15.4.1.2 Sleep on LAN Sequence

The SES string out page (Sleep on LAN) command causes the SXP 12G to enter deep sleep mode. This clock-gates
most modules except for the MAC, Memory controller, MBIC and Flash module. The sequence to gate the clocks of
these modules is as follows:
1. Disable all interrupt sources from the MBIC controller.
2. Restart the watchdog timer to avoid watchdog timeout during sleep-waking.
3. Send Notify Power Loss (Expected) primitive to all PHYs to end all SAS traffic.
4. Wait for TWI master to end all existing traffic.
5. Disable all TWI slaves to end all existing traffic.
6. Disable all PHYs from the SSPL layer and clean all SSPL/SXL interrupts.
7. Turn off the Vman power of all manageable cables and Vact power of all active cables.
8. Change the output of SGPIO PHYs to OFF and wait for SGPIO status to be updated.
9. Flush all error logs to NVRAM.
10. Set WOL NMI flag bit in the MBIC Scratchpad register for checks later during the waking up phase.
11. Enable the Magic Packet NMI event before the device enters sleep mode.
12. Make all EMIP cores enter low-power mode and shut down FWS module.
13. Clock-gate all PHYs, including Analog, MTSB, SSPL, SXL, CSU modules.
14. Clock-gate ECMR, Core300, Core75, including ECMR, PACK, SGPIO, TWI, UART, GPIO, Watchdog, and
Timer modules.
15. Power down internal DPRAM.
16. Power down internal SPRAM.
17. Clean MIPS instruction lines.
18. Issue a WAIT instruction to stop MIPS activity and enter sleep mode.
Note
Due to MAC functionality, the device can only assert the WOL NMI bit (bit 5) in MBIC - Raw NMI Status VPE0
register for only 64 clocks. Set a firmware flag explicitly in step 10. This firmware flag is reusing bit 0 of the MBIC
Scratchpad 0 register, so you cannot use this bit if WOL is enabled.

15.4.1.3 Wake on LAN Condition

When the SXP 12G enters WOL sleep mode, it is unable to respond to any event or activity except for receiving the
magic data packet from the MAC. If the MAC has received the correct Magic Packet with its MAC address, the MAC
asserts a MAC NMI to the MIPS core, which will be woken up by this event.

PHY and Power Management

The Magic Packet (MP) consists of 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF followed by 16 repetitions of the 48-bit MAC
address. The Magic Packet is scanned only for the signature above – it does not pass through the full protocol stack
thus it does not need CPU assistance to decode the message – it is decoded by MAC hardware. The message is
usually sent by a program executed on another computer on the same local area network. It is also possible to initiate
the message from another network by using Subnet directed broadcasts or a WOL gateway service.

15.4.1.4 Wake on LAN Sequence

Since the device is woken up by the NMI event, the MIPS core reboots from the starting address (0xBF000000).
During the boot procedure, firmware enters the NMI handler nmi_gen_handler() and checks the WOL NMI reason.
The reason is flagged in the MBIC Scratchpad register. If it is asserted, firmware begins the sequence to wake up the
SXP 12G.
1. Clock de-gate ECMR, Core300, and Core75, including the ECMR, PACK, SGPIO, TWI, UART, GPIO,
Watchdog and Timer modules.
2. Power on internal DPRAM and SPRAM.
3. Trigger SPRAM and DPRAM hardware initialization.
4. Save the CPU context and enter the WOL NMI handler.
5. Restart the watchdog timer again to avoid a watchdog timeout during wakeup.
6. Restore the CPU context to continue the boot procedure.
7. The boot procedure is the same as the normal procedure except that WOL NMI boot clears the WOL NMI flag
bit in the MBIC scratchpad register.
Note
The clocks for all Analog MTSBs, EMIP cores, FWS and PHYs are de-gated during firmware initialization. This is the
same as in the normal firmware boot procedure.

15.4.1.5 WOL Configuration

The WOL feature can only be implemented by defining the macro WOL_ENABLE in the SXP 12G build project
sxp_pmc_evbd.gpj.
If the WOL feature is implemented, WOL enabling and the sleep delay time can be configured by the initialization
string and SES pages. (See Table 15-7, and Table 15-6.)
Table 15-7. SES String Out Page - (WOL Enabling) Command

Component Name Bytes Field Name Value Notes

0 Page Code 0x04 String Out SES page code

Sub-Enclosure
1 Identifier 0x00
Page Header
2-3 (MSB) 0x0006 The length of String Out data is 6 bytes.
Page Length (n-3)
(LSB)

4 Command 0x03 General WOL/WOS command

5 Subcommand 0x02 WOL Enable command

Vendor Specific 0x00 or 0x00: Disable WOL function

Enable/Disable
6 WOL function 0x01 0x01: Enable WOL function

7-9 Reserved 0x000000

Only until WOL is implemented and enabled, can it work with the correct WOL state transition.

15.4.2 WOS Implementation

PHY and Power Management

15.4.2.1 Sleep on SAS Conditions

The WOS feature defines the set of upstream PHYs that transfers/routes the I/O request from the host to the end
disks attached to the SXP. If WOS is enabled in the SXP 12G and the upstream PHYs are down for one specified
period of time – WOS SLEEP DELAY TIME, the SXP 12G will prepare to enter sleep mode. The purpose of the WOS
SLEEP DELAY time is to avoid entering WOS sleep mode immediately due to an upstream PHY being down for a
short time. Firmware also completes the pending tasks during this time. When WOS SLEEP DELAY time expires,
firmware puts disks in low power mode, shuts down FAN, and so on. The upstream PHY can only be configured
in the initialization string WOS_UPSTREAM_PHY_MAP field. The time delay can be configured in the initialization
string WOS SLEEP DELAY TIME field or an SES string out page.
Notes
The WOS sleep delay time cannot be less than the time it takes for an SXP PHY to become READY after waking up;
otherwise, the device will enter an endless sleep-wake up-sleep loop since the Sleep on SAS condition will be met
again just after waking up. The suggested value is more than 1 second.

15.4.2.2 Sleep on SAS Sequence

If the WOS sleep condition is met, the SXP 12G prepares for the clock-gating modules. This preparation sends a
Notify Power Loss (Expected) primitive to disable all PHYs, which isolates the SXP 12G from outside connections.
It leaves time for firmware to complete the pending tasks and to set the correct firmware status and necessary
hardware registers. The preparation guarantees consistent firmware status when firmware resumes running from the
sleep point. After sleep preparation, firmware begins to gate the clock of most of the modules:
1. Save the current interrupt source from the MBIC controller and disable the MIBC interrupt source.
2. Reset the watchdog timer to avoid a watchdog timeout during sleep-waking.
3. Wait for the TWI master to end all existing traffic.
4. Disable all TWI slaves to end all existing traffic.
5. Enable SSPL COMINIT and COMWAKE interrupts for the upstream PHYs. Clear all SSPL/SXL interrupts.
6. Turn off the Vman power for all manageable cables and the Vact power for all active cables if this cable
contains no upstream PHYs.
7. Turn off the output of the SGPIO PHYs and wait for the SGPIO status update.
8. Change all downstream SAS-3 analog MTSBs into power down mode.
9. Make all EMIP cores enter low power mode and shut down the FWS module.
10. Clock-gate all downstream PHYS, including the SSPL and SXL modules.
11. Clock-gate ECMR, Core300, Core75, including ECMR, PACK, SGPIO, TWI, UART, GPIO, Watchdog and
Timer modules.
12. Power down internal DPRAM.
13. Enable and register COMMINIT and COMMWAKE interrupt process routines for upstream PHYS in the MBIC
controller.
14. Clean MIPS instruction lines.
15. Issue a WAIT instruction to stop MIPS activity and enter sleep mode.
Notes
As WOS requires that firmware resume running after being woken up, the WOS cannot clock-gate the SPRAM or
data in the SPRAM may be lost.

15.4.2.3 Wake on SAS condition

When the SXP 12G enters WOS sleep mode, only the upstream PHYs can respond to COMINIT and COMWAKE
events received from peer PHYs. If a COMINIT or COMWAKE event is received, an SSPL COMINIT or COMWAKE
interrupt is asserted to the Interrupt Controller. The MIPS core is woken up to handle this interrupt and the PHY’s
interrupt source from the MBIC is disabled.
To wake up the entire SXP 12G, the number of PHYs that have received COMINIT or COMWAKE interrupts should
reach the minimum number defined in the initialization string field WOS WAKEUP BY MIN NUM OF PHY. Otherwise,
MIPS will enter sleep mode again after a time delay defined by the initialization string field WOS WAKEUP WINDOW
TIME.

PHY and Power Management

Note: In general, COMINIT will be periodically sent from the peer PHY. Disable the COMINIT or COMWAKE interrupt
source from the MBIC to avoid MIPS being too busy to handle these events or to wake up MIPS if it enters sleep
mode again.

15.4.2.4 Wake on SAS sequence

If the WOS wake up condition is met, firmware begins to wake up the whole device and resume running from the
sleep point. This sequence is:
1. Clock de-gate ECMR, Core300, Core75, including the ECMR, PACK, SGPIO, TWI, UART, GPIO, Watchdog
and Timer modules.
2. Power on internal DPRAM.
3. Make all EMIP cores exit low-power mode and power on the FWS module.
4. Clock de-gate all downstream PHYs, including the SSPL and SXL modules.
5. Change all downstream SAS-3 analog MTSBs into power up mode.
6. Start the watchdog thread again to avoid a watchdog timeout during sleep-waking.
7. Initialize the ECMR hash table and the logical routing table to clear any remaining routing table information.
8. Turn on the Vman power for all manageable cables and the V act power for all active cables.
9. Send the present cable events to the cable management thread.
10. Enable all TWI slaves which have been enabled before sleep.
11. Disable and unregister the COMMINIT and COMMWAKE interrupt process routine for upstream PHYs in the
MBIC controller.
12. Restore the same MIBC interrupt sources to the MBIC controller.
Note: This sequence is handled in a COMMINIT and COMMWAKE interrupt process routine.

15.4.2.5 WOS Configuration

The WOS feature can only be implemented by defining the macro WOS_ENABLE in the SXP 12G build project
sxp_pmc_evbd.gpj.
If WOS is implemented, the enabling and sleep delay time can be configured by the initialization string and SES
pages.
Table 15-8. SES String Out Page - (WOS Enabling) Command

Component Name Bytes Field Name Value Notes

0 Page Code 0x04 String Out SES page code

Sub-Enclosure
1 Identifier 0x00
Page Header
2-3 (MSB) 0x0006 The length of String Out data is 6 bytes.
Page Length (n-3)
(LSB)

4 Command 0x03 General WOL/WOS command

5 Subcommand 0x01 WOS Enable command

Vendor Specific 0x00 or 0x00: Disable WOS function

Enable/Disable
6 WOS function 0x01 0x01: Enable WOS function

7-9 Reserved 0x000000

Only when WOS is implemented and is enabled, can it work with the correct WOS state transition.
Table 15-9. SES String Out Page - (WOS Sleep Delay Time Set) Command

Component Name Bytes Field Name Value Notes

PHY and Power Management

0 Page Code 0x04 String Out SES page code

Sub-Enclosure
1 Identifier 0x00
Page Header
2-3 (MSB) 0x0006 The length of String Out data is 6 bytes.
Page Length (n-3)
(LSB)

4 Command 0x03 General WOL/WOS command

5 Subcommand 0x03 WOS sleep time delay set command

The delay from the time all WOS

Vendor Specific upstream PHYs are down to when
firmware gets ready to enter sleep
(LSB) mode. If the timeout delay is zero,
the default time delay in initstring(offset
Parameter 0x00000000
0x14CC - 0x14CF) will be used. The
6-9 (MSB) Or other values time unit is milliseconds (ms).

15.4.3 WOL/WOS callback function

You can register a callback function into a WOL/WOS function during WOL/WOS initialization. The callback function
is used to take specific actions before/after a power state change. This function has two phases:
Phase 1 is performed before a power state change and
Phase 2 is performed after power state change.
Use callback function phase 1 to save data, complete traffic, disable peripherals or send notifications before the
device enters sleep mode.
Use callback function phase 2 to restore the data, enable peripherals, or send notifications after the device leaves
sleep mode. If no action is needed, users can use NULL as a null function.

15.5 Early Power Off Warning (EPOW)

The Early Power-Off Warning (EPOW) is a hardware feature within the expander that quickly acts when the expander
is alerted to the probable loss of power is occurring. When detected it can alert attached SAS target devices and
potentially downstream expanders by sending NOTIFY (POWER LOSS EXPECTED) primitives in accordance to the
SAS standard. The number of times that the NOTIFY primitive will be sent out will be in a 3 bit register (0 through7
and default to 3). The choice of PHYs in which to send these primitives is fully configurable by firmware.
Firmware supports enabling or disabling the EPOW function based on the initialization string setting.
To enable EPOW:
1. Ensure the function of the GPIO Pin 43 (see Table 7-1 and Table 8-25) is configured as GPIO.
2. Set the EPOW_EN bit in the initialization string (see Table 8-29) as 1, and set the POLARITY bit for the actual
system being used.
3. Set the 68-bit Q_PHY bitmap and the 68-bit N_PHY bitmap in the initialization string (see Table 8-29) for the
actual system being used.
The EPOW trigger condition is that
• At least one of the PHYs identified by the Q_PHY bitmap is in a PHY ready state and
• AC_GOOD_L is de-asserted.

PHY and Power Management

15.6 Power Disable

SPL3r6 maps a new function onto pin P3 of the SAS drive connector and our firmware supports this feature. To
use this feature, “Power Disable Supported” should be enabled, and addtitional hardware is required to let expander
control each pin P3 of the SAS drive. The following hook API should be implemented based on the hardware
implementation.
Table 15-10. Power Disable Hooks

Hook Name Description

ema_process_power_disable_pin_ Provides a mechanism for a user to add firmware code to operate the power
hook() disable pin.

Inter-Expander Communication

16. Inter-Expander Communication

There has been requirement of an efficient and reliable communication channel between expanders for synchronizing
the Enclosure Management Information and vendor specific data. The typical inter-expander communication channel
includes TWI, In-band SAS, Ethernet and UART.
The SXP 12G SDK provides the APIs over TWI and over in-band SAS respectively for meeting this kind of
application.

16.1 Inter-Expander Communication Over TWI

Microchip has provided the IPCTWI library for inter-SXP communication since the SXP3G SDK.
The IPCTWI library contains simplified code and improved TWI functionality with communication efficiency based on
the hardware based TWI and simultaneous TWI master and slave functions. The IPCTWI library keeps the same API
interfaces.

16.2 Inter-Expander Communication Over SAS

A reliable high-speed path such as a SAS link is more powerful solution than the two-wire interface which is
commonly used to satisfy the requirement. Firmware provides capabilities as an SSP initiator and an SSP Target
from both the SAS protocol lower layer and SCSI application layer. This enables development of application specific
code for achieving inter-expander communication over SAS links.
The inter-expander SAS link can be created:
• If the two SXP 12G expanders are in the two SAS domains, for example two Link Control Cards in one SAS
Disk Enclosure, the two SXP 12G expanders can be inter-connected with the Redundant Virtual SSP link. Refer
to Figure 8-2 for the configuration
• If the two SXP 12G expanders are in the same SAS domain, there is no requirement for the dedicated link for
this purpose.
The capabilities that SXP functions as the SCSI initiator are briefed as follows:
• The SCSI Initiator Application module (SIA) provides the message interfaces for user’s application to issue SCSI
Commands and get responses. These message interfaces include:
– INQUIRY
– TEST UNIT READY
– REPORT LUNS
– SEND DIAGNOSTIC
– RECIEVE DIAGNOSTIC RESULT
– RAW COMMAND, This is a common interface to support various kinds of SCSI commands from user’s
application
Table 16-1. SIA Message Interface

Message Interfaces SCSI Command

sia_inquiry_req_msg_struct INQUIRY
sia_inquiry_rsp_msg_struct

sia_report_luns_req_msg_struct REPORT LUNS

sia_report_luns_rsp_msg_struct

sia_send_diag_req_msg_struct SEND DIAGNOSTIC

sia_send_diag_rsp_msg_struct

Inter-Expander Communication

...........continued
Message Interfaces SCSI Command

sia_rcv_diag_req_msg_struct RECEIVE DIAGNOSTIC

sia_rcv_diag_rsp_msg_struct

sia_test_unit_ready_req_msg_struct TEST UNIT READY

sia_test_unit_ready_rsp_msg_struct

sia_raw_cmd_req_msg_struct INQUIRY, REPORT LUNS, SEND DIAGNOSTIC,

RECEIVE DIAGNOSTIC, TEST UNIT READY,
sia_raw_cmd_rsp_msg_struct
LOG_SENSE, LOG_SELECT, MODE_SENSE,
MODE_SELECT.

• SIA is responsible for handling service delivery or target failure errors with Task Management functions and for
handling automatic retries for the application layer depending on the error code in the response. The number of
retires is a configurable parameter that can be configured through the initialization string.
• SIA is enhanced to support configurable maximum outstanding SCSI related requests from DSQ, Command
Server and user specific threads. By default, the maximum outstanding request is 5 in the initialization string. It
is expected that the total outstanding requests from the application threads never exceeds the configured value,
or else a firmware assert will occur.
• The SAS low layer protocol (SASD module) is enhanced for simultaneous virtual SSP initiator and target
operation support.

16.2.1 Implementing a User Application Thread for Issuing SCSI Commands to the SCSI Target
• To utilize the SIA module to issue a SCSI command to a target, the user’s application needs:
• To have a data structure to maintain target_address, connection_rate, and request_id.
• A malloc data buffer for these types of Data In commands and for passing the data buffer to the SIA module, like
INQUIRY, REPORT LUNS, and so on.
• To fill in various command parameter fields.
• To pass the command request message with the appropriate message type to the SIA module, and to monitor
the response message from the SIA module.
• To handle response message per request_id and free data buffer if it has been malloced in request phase.

16.2.2 Command Line Interface for Issuing SCSI Commands to the SCSI Target
The SXP 12G firmware implements several SSP commands in the cmdsvr interface. These commands demonstrate
how to use the message interfaces in the SIA module to perform the SCSI transaction with the SCSI target into the
peer expander.
In SXP 12G SDK, the maximum outstanding requests number from cmdsvr to SIA has been hardcoded
as CMDSVR_SIA_MAX_SIMUL_SSP_REQ_NUM (default 0x02), and the maximum data buffer size has been
hardcoded as CMDSVR_MAX_DATA_MEM_BUF_SIZE (default 0x100).
• ssp addr_rate <dest_addr> <conn_rate 0x1~0xf>
Use this command to set the address of the peer expander and the connection rate between expanders. The
address and connection rates set by this command will be used for all commands issued until a new “ssp
addr_rate” command is executed. The range of conn_rate is:
– 0x8 = 12G
– 0x4 = 6G
– 0x2 = 3G
– Others = 1.5G
• ssp inquiry <alloc_len 0x0~0x100>
Use this command to send an INQUIRY command to peer expander. The range of alloc_len is from 0x0 to
0x100.
• ssp rep_luns <alloc_len 0x0~0x100>

Inter-Expander Communication

Use this command to send a REPORT LUNS command to peer expander. The range of alloc_len is from 0x0 to
0x100.
• ssp send_diag <raw data Max. 14 bytes>
Use this command to send a SEND DIAGNOSTIC command to peer expander with Max 14 bytes payload data.
The data should use a “0x” to indicate it is HEX.
• ssp rcv_diag <page code> <alloc_len 0x0~0x100>
Use this command to send a RECEIVE DIAGNOSTIC RESULTS command to peer expander. The range of
alloc_len is from 0x0 to 0x100.
• ssp cmd <cdb 6/10/12 bytes>
Use this command to input cdb of a raw ssp command to peer expander. The cdb data is stored in a global
data structure and will not be sent out until an “ssp exec” command is executed. Since the command is
only for demo usage, currently only max 255 bytes is supported for both PARAMETER_LIST_LENGTH and
ALLOCATION_LENGTH field which means only the LSB byte of the two fields is valid and MSB bytes should be
0. Currently the raw command supports TEST UINT READY, INQUIRY, REPORT LUNS, SEND DIAGNOSTIC,
RECEIVE DIAGNOSTIC RESULTS, LOG SELECT, LOG SENSE, MODE SELECT(10) and MODE SENSE(10)
commands.
• ssp dout <raw data Max.255 bytes>
Use this command to input payload data of a raw ssp command to peer expander. User can execute this
command for multiple times to input max 255 bytes raw data. The payload data is stored in a global data
structure and will not be sent out until an “ssp exec” command is executed. The data should use a “0x” to
indicate it is HEX.
• ssp exec
Use this command to send out the raw command with cdb input by “ssp cmd” and payload by “ssp dout”.

Event Logging and Error Handling

17. Event Logging and Error Handling

To help solve problems in the field, the SXP Error Handling in firmware has:
• Enhanced error detection that covers SXP hardware block errors and SXP firmware module errors
• Improved event logging, with configurable event filtering by module and by event severity level
• Multiple interfaces for the management application client to retrieve the SXP error logs through in-band SCSI
Command LOG_SENSE and SMP REPORT SELF-CONFIGURATION STATUS, and out-of-band Command
Server
• Improved error processing for recovering errors from the module layer, the SXP sub-system level and the
system level

17.1 Hardware and Firmware Block Errors

The SXP 12G firmware detects faults caused by hardware blocks and firmware modules in the system with the
following features:
• Power-on Self-Test (POST) example code
• High priority threads are installed in the Watchdog timer services.
• NMI Reset for Watchdog Timeout, ECC/Parity Error or other fatal errors.
• Firmware drivers detect the errors in SXP hardware peripheral interfaces (TWI/UART/Ethernet/SGPIO) and
Expander PHY/ECMR/PACK.
• Firmware modules detect SAS protocol errors in SXP SAS stacks, SAS topology discovery failures, NDSR
failures, DSQ failures, Initialization String failures, Boot failures, firmware upgrade failures and others.
The following section lists the errors that are monitored and recorded by firmware.

17.1.1 Hardware Block Errors

• EXTSS Block (CPU subsystem)
• PACK Block
• SXL Block
• SSPL Block
• MABC Block
• ECMR Block
• EMIP Block
• SSSF Block

17.1.2 Hardware ECC/Parity Errors

The SXP 12G firmware enables hardware ECC/Parity protection in the following scenarios:
• On-chip SPRAM and DPRAM is protected by HW ECC by default.
• As to on-chip DSPRAM and Cache, Firmware enables MIPS34Kc core Parity protection for them.
• EMIPs’ DRAM and IRAM is protected by HW ECC by default.
• If an EMIP controlling a downstream buffered PHY has an uncorrectable ECC error then::
– The EMIP would halt and the downstream PHY will be held in a COM_INIT state.
– The HOST would receive a BROADCAST(CHANGE) and detect IO timeouts for the target connected to
that PHY.
– The HOST should execute Discovery to find the missing target.
– The HOST can check the corresponding PHY’s buffering status with SES SSSF page (See Table 14-93).
– If the page reported there was an uncorrectable ECC error detected, the HOST can reset the EMIP with
the SES page (See Table 14-84, Table 14-85, and Table 14-87). The SXP Firmware will execute the EMIP
BIST. If the BIST passes, the EMIP will restart the corresponding PHY. If the BIST fails, the EMIP will
remain halted and the PHY will remain in the COM_INIT state.
• If an EMIP that controls an unbuffered upstream or downstream PHY has an uncorrectable ECC error:

Event Logging and Error Handling

– The EMIP will halt.

– The PHY would link up to 6G if a link reset happens because the EMIP is halted. (NOTE: The upstream
PHY’s link is not interrupted when the uncorrectable error is detected.)
• SSSF’s buffer RAM is protected by HW ECC by default.
– If a PHY that is in SAS/SATA buffering mode has an SSSF uncorrectable ECC error then:
• The PHY will be held in the COM_INIT state and the SSSF HW will be reset.
• The HOST will receive a BROADCAST(CHANGE) and will detect IO timeouts for that target
connected to that PHY.
• The HOST should run Discovery to see which target is missing.
• The HOST should check the corresponding PHY’s buffering status with SES SSSF page(See Table
14-93)
• If the SSSF status reports an uncorrectable ECC error then:
1. (OPTIONAL) the HOST could use the SES SSSF page (See ). To request the SXP to scan the
SSSF buffer RAM to check for a physical RAM error.
2. If the SSSF buffer RAM has a physical failure, the HOST can disable buffering using the
SES SSSF page (See Table 14-92). The SXP firmware would bring up the PHY with buffering
disabled and the target is accessible.
3. If the SSSF buffer RAM has no physical failure, the HOST can reset the PHY with the SES
page (See Table 14-92). The SXP firmware would bring up the PHY with buffering enabled.
– The SDK provides the following function to scan SSSF buffer RAM:
Table 17-1. SSSF RAM Scan Function

Function Description

emip_sssf_ecc_scan Scan the SSSF buffer RAM

emip_sssf_ecc_scan
The emip_sssf_ecc_scan() is used to scan the SSSF buffer RAM. The SXP firmware writes the specified pattern
into the RAM and reads it back. The uncorrectable ECC error indicator will be checked to see if the read operation
encountered a failure. If the read operation passes, the firmware will compare the read value to the write pattern to
check for consistency. If an uncorrectable ECC error occurs the function will return FALSE.

Prototype BOOL emip_sssf_ecc_scan(

UINT8 log_phy_id,
sssf_ecc_scan_moduel_enum module,
UINT32 pattern)

Inputs log_phy_id The logical PHY id identifies which PHY’s SSSF.

module The module specific the which RAM should be scanned.

pattern The scan pattern.

Outputs None

Returns Success = TRUE

Failure = FALSE

Side Effects The content of RAM

of SSSF is changed.

Event Logging and Error Handling

• For local bus interface (PM805x devices only), ECC is enabled individually for each memory bank (chip select).
– Specifically, for CS0, a hardware bootstrap pin is implemented to enable/disable ECC of parallel boot flash
after power on/reset, which means we support boot from parallel flash with ECC enabled or ECC disabled.
– ECC is disabled by default for other memory banks (CS1, CS2, CS3). ECC for CS1 can be enabled by
setting the corresponding parameter in firmware initialization string. If a memory bank has been used for an
External SRAM, ECC for this memory bank should never be enabled.
– ECC for SPI flash memory is not supported.
A non-correctable ECC error will cause NMI, and a correctable ECC error will only generate a normal
interrupt. A parity error from DSPRAM or Cache will cause a MIPS exception.

17.1.3 Firmware Module Errors

• BOOT – Bootloader
• ISTR – Initialization String Field Validation
• SAS – SAS protocol stack for the virtual port in the SXP
• SCFG_EXP_STAT – Self-Configuring Expander Status, including SMP, topology discovery and logic route table
errors.
• STE – SCSI Target Emulator
• SES – SES Application
• FWDL – Firmware Updating
• NDSR – SXP NDSR Reset
• PORTMGR – Port Manager
• SIA – SCSI Initiator Application
• SAHA – SATA Host Application
• DSQ – Disk Qualification
• TCP/IP – TCP/IP Application and Services
See Table 17-6 for full module list.

17.2 Enhanced Event Logging

The goal for enhancing the event logging is to provide more information for problem solving in the field. The major
ways logging has been enhanced include:
• Introduces the event level to reflect the event severity.
• Configurable to capture events for specific modules.
• Adds logs in more modules for better coverage for SXP events.
• Adds an on-the-fly logging filter configurable by severity level and module ID.
• Uses SES page 0x4 (STRING IN/OUT) page to configure the log filters.
• Stores the log and some context information to flash memory while detecting fatal errors.

17.2.1 Event Logging Filter Level

Event level filtering allows the masking of the severity for each SXP event. Adjustment of the event level setting in the
logging filter to capture events helps in debugging and diagnosing problems.
Each log entry has the level field. Log entries are not recorded in the following conditions:
• The log level is higher than its own filter level if the filter type is Filter IN.
• The log level is higher than the global filter level if the module is not in the filter list or if the filter type is Filter
Don’t Use.
• The filter type is set to Filter OUT.
The ability to filter the logs by level is also available. See the event level definition in the following table.

Event Logging and Error Handling

Table 17-2. Log Severity Level Definitions

Severity Level Description Logging Examples

0x0 Disabled

Critical Error Fatal error, such as memory Logged to RAM. HW: Memory Corruption, WDG
corruption. This results in the Timeout
(0x1, Highest) When fatal error
firmware halting. Need storage
happens, flushes all the FW: Failed to allocate resource
system level operations to recover
logs in RAM to flash
this kind of error. Asserted in corner case.
memory.

Error Non-Fatal error for the HW/FW Logged to RAM FW: SAS/SCSI Stack based
module. After this error occurs on PACK
(0x2, High)
some HW/FW modules may not
FW: SMP Initiator and TOPD
function well, but the SXP core
Failure
functions still work. The recovery
operation is in the SXP sub- FW: DSQ/IPC
system level.
HW: MABC/SSPL/SXL/ECMR/
PACK ERROR
HW: TWI/MAC

Warning These relatively rare events Logged to RAM FW: Driver

encountered in regular operation,
(0x3, Medium)
e.g. TWI read timeout. retry
operation can recover this
temporary failure.

INFO Log for information Logged to RAM FW/HW: BPPFW: TOPD Start/
Stop Event
(0x4, Low)

Debugging This is a special level meant to Logged to RAM

debug consistently reproducible
(0x5, Lowest)
issues by adding more logs while
debugging. This level is currently
for internal use.

Reserved (0x6~0xF)

17.2.2 Event Logging Filter Format

The logging filter table is used to store up to 16 filter entries for the SXP functional modules. These are stored to the
NVRAM (SEEPROM by default) and can be updated on-the-fly through in-band SES Commands with Page 0x4.
Each Logging Filter Entry stores the rules for filtering the events by module, by event level, and by filter operation
type. See the following table for the definition of the logging filter entry in string out Page Log Control command
(0x40).
Table 17-3. SES String Out LOG Control Command Format

Byte\Bit 7 6 5 4 3 2 1

0 GLOBAL FILTER LEVEL

1 FILTER COUNT n (MAX 16)

2
FILTER DESCRIPTOR LIST (first)
14

Event Logging and Error Handling

...........continued
Byte\Bit 7 6 5 4 3 2 1

2+(n-1)*13
FILTER DESCRIPTOR LIST (last)
15+(n-1)*13

Table 17-4. Filter Descriptor Format

Byte\Bit 7 6 5 4 3 2 1

0 APPLICATION FILTER INDEX

1
MASK
4

5
PATTERN
8

9
Reserved
10

11 FILTER SEVERITY LEVEL

12 FILTER TYPE

Table 17-5. Filter Descriptor Field Definitions

Name Description/Value

Global filter level controls whether to record the log when the filter is
GLOBAL FILTER LEVEL not in the list or with the type “don’t use”. See Table 17-2.

FILTER COUNT The filter count that needs to be configured. Maximum is 16.

Each descriptor contains the same information as log control in string

FILTER DESCRIPTOR LIST out diagnostic page.

For convenience, all the logs divided into 16 types. Currently the
assigned application filter indexes are listed here by default. 0:
ISTR (Module ID: 0x001F) 1: SAS (Module ID: 0x001A)2: SPS_CFG
APPLICATION FILTER INDEX (Module ID: 0x0038) 3: SCFG_EXP_STAT (Module ID: 0x0063)

MASK Mask applied to data before pattern matching LOG_MSK 0x00FF0000

Pattern to match against ISTR_PATTERN (PMCFW_MID_ISTR

<< 16) SASD_PATTERN (PMCFW_MID_SAS << 16)
SPSCFG_PATTERN (PMCFW_MID_SPS_CFG << 16 )
SCFG_EXP_STAT_PATTERN (PMCFW_MID_SCFG_EXP <<16)
PORTMGR_PATTERN (PMCFW_MID_PORTMGR << 16)
PATTERN For all the Module Pattern, see Table 17-6.

Filter severity level for each filter controls whether to record the log if
FILTER Severity LEVEL the filter type is set to Filter IN. See Table 17-2.

Event Logging and Error Handling

...........continued
Name Description/Value

0: Do not use this filter 1: Filter IN 2: Filter OUT

When the filter is set to Filter IN, its own filter severity level controls
whether to record the event log.
When the filter is set to Filter OUT, the event log in this module is not
recorded.
When the filter is set to ‘Do not use this filter’, the global severity level
FILTER TYPE controls whether to record the event log.

For each module there is a filter pattern. The value is defined in the following table.
Table 17-6. Module Pattern ID and Name Mapping

Default in Initialization
Module ID Module Name String

0x10 OSF

0x15 STE

0x17 logic route table

0x1A SAS, including PACK Yes

0x1D SPIN UP

SXP, including SXL, ECMR, SSPL, MTSB, EMIP, TOP level HW

0x1E block

0x1F Initialization String Yes

0x22 Power Management

0x28 Command Server

0x2A Serial ATA Host Application (SAHA)

0x2B SCSI Initiator Application (SIA)

0x2C Disk Qualification (DSQ)

0x31 SES

0x35 Port manager

0x36 SMP

0x38 SPS config download Yes

0x4F Topology Discovery

0x5B M34KHAL

0x63 Self-configuration expander device status log Yes

0x65 TCPIP, including MAC

0x66 Zone Server Module for configuring zone

Event Logging and Error Handling

...........continued
Default in Initialization
Module ID Module Name String

SOCIO, including NMI, TWI, UART, SPI, Firmware Download,

0x69 FLM, Timer, GPIO and SGPIO

17.2.3 Event Logging Format and APIs

Event logging APIs provide the API interface to perform these operations:
• Logging filter array loading and initialization
• Modifying logging filter entries, which can be modified on-the-fly through SES String Out LOG Control Command
(0x40)
• Logging a new application event.
The Application log is recorded as the format of application Log described in Table 6-8 and logging API can refer
to section 6.6.1 External Interface

17.2.4 External Log Retrieval Interfaces

The SXP 12G SDK supports multiple interfaces for the host to retrieve the event logs as provided in the following list:
• In-band interfaces available when the SXP firmware is in normal operation or in the minimal function mode.
• SCSI LOG SELECT/SENSE
• SMP REPORT SELF-CONFIGURATION STATUS
• Microchip-specific SES Page – System Log Retrieval Status diagnostic page
• Out-of-band interfaces
• CMDSVR over UART/Telnet
– Available when the SXP firmware is in the normal operation.

17.3 SMP Self Configuration Event Logging

The SMP self-configuration log is created by the SMP self-configuration process if the expander is set to SCE
(Self-configuration Expander). Other than ECE (external configuration expander), it saves the current status or error
event in the different protocol layers. The REPORT SELF CONFIGURATION command can retrieve the detail from
the log buffer.

17.3.1 Event Logging Status

The Self-Configuration Status types supported in the firmware are listed in the following table.
Table 17-7. Supported Self-Configuration Status Type

Code Description FW Logged

00h Reserved NO

01h Error not related to a specific layer NO

The expander device currently has a connection or is currently attempting to establish

02h YES
a connection with the SMP target port with the indicated SAS address.

Expander route table is full. The expander device was not able to add the indicated
03h YES
SAS address to the expander route table.

Expander device is out of resources (e.g., it discovered too many SAS addresses
04h while performing the discovery process through a subtractive port). This does not NO
affect the expander route table.

05h to 1Fh Reserved for status not related to specific layers NO

Event Logging and Error Handling

...........continued
Code Description FW Logged

Status reported by the PHY layer

20h Error reported by the PHY layer NO

All PHYs in the expander port containing the indicated PHY lost DWord
21h NO
synchronization

22h to 3Fh Reserved for status reported by the PHY layer NO

Status reported by the link layer

40h Error reported by the link layer NO

41h Connection request failed: Open Timeout timer expired YES

Connection request failed: Received an abandon-class OPEN_REJECT (e.g.,

42h BAD DESTINATION, PROTOCOL NOT SUPPORTED, ZONE VIOLATION, STP YES
RESOURCES BUSY, WRONG DESTINATION)

Connection request failed: Received a vendor-specific number of retry-class

43h YES
OPEN_REJECTs (e.g. RETRY, PATHWAY BLOCKED)

Connection request failed: I_T nexus loss occurred (e.g., OPEN_REJECT (NO
44h DESTINATION) for longer than the time specified by the STP SMP I_T NEXUS LOSS YES
TIME field in the CONFIGURE GENERAL function

45h Connection request failed: Received BREAK YES

46h Connection established: SMP response frame had a CRC error YES

47h to 5Fh Reserved for status reported by the link layer NO

Status reported by the port layer

60h Error reported by the port layer NO

During an SMP connection, there was no SMP response frame within the maximum
61h YES
SMP connection time

62h to 7Fh Reserved for status reported by the port layer NO

Status reported by the SMP transport layer

80h Error reported by the SMP transport layer NO

81h to 9Fh Reserved for status reported by the SMP transport layer NO

Status reported by the management application layer

A0h Error reported by the management application layer NO

A1h SMP response frame is too short NO

A2h SMP response frame contains field(s) with unsupported values YES

SMP response frame contains results inconsistent with other SMP response frames
A3h (for example, the DISCOVER response ATTACHED SAS ADDRESS field does not NO
contain the SAS address the expander device expected)

Event Logging and Error Handling

...........continued
Code Description FW Logged

The SAS ADDRESS field contains the SAS address of a self-configuring expander
device that returned a REPORT GENERAL response with the CONFIGURING bit set
to one, the SELF CONFIGURING bit set to zero, and the ZONE CONFIGURING bit
A4h YES
set to zero (e.g., compliant with a previous version of this standard). Accesses to SAS
addresses two or more levels beyond this expander device may not succeed until the
indicated expander device completes configuration. This is not necessarily an error.

The SAS ADDRESS field contains the SAS address of a self-configuring expander
device that returned a REPORT GENERAL response with the SELF CONFIGURING
A5h bit set to one. Accesses to SAS addresses two or more levels beyond this expander YES
device may not succeed until the indicated expander device completes configuration.
This is not necessarily an error.

The SAS ADDRESS field contains the SAS address of a self-configuring expander
device that returned a REPORT GENERAL response with the ZONE CONFIGURING
A6h bit set to one. Accesses to SAS addresses two or more levels beyond this expander YES
device may not succeed until the indicated expander device completes configuration.
This is not necessarily an error.

A7h to BFh Reserved for status reported by the management application layer NO

Other status

C0h to DFh Reserved NO

E0h to FFh Vendor-specific NO

17.3.2 Self-Configuration Log Ring Buffer

The SDK sets up a separate ring buffer for the SMP self-configuration log. This log does not overlap the OSF log
buffer and does not check the filter rules. Therefore, all of the log types are inserted into the ring buffer.
The ring buffer uses the same read/write index mechanism as the OSF log and maintains the self-configuration index
in one global variable. It improves the search performance for the indicated log and the related log index.

17.3.3 Self-Configuration Log Format

The Self Configuration log does not depend on the OSF entry log format. It only contains 16 bytes of information
about the log index, status type, final bit, PHY_ID and SAS address information. Only the REPORT SMP SELF
CONFIGURATION command can get the ring buffer data content and the log sequence.
Table 17-8. Format of Scfg Log Entry

Word\bit 31:24 23:16 15:8 7:0

0 PHY ID Reserved Final Status Type

1 Reserved

2
SAS ADDRESS
3

17.4 Error Codes

Error Codes are of type PMCFW_ERROR, which is a 32-bit integer (INT32), and are unique across the system.
Each Error Code consists of a Module ID portion and an Error ID portion. The Module ID is defined in the file
PMCFW_MID.H. Each module includes PMCFW_MID.H if it needs to define an error code.

Event Logging and Error Handling

The Error Codes are defined in each module’s include file, and are created by ORing a 12 bit Error ID with the
Module ID. The Error ID portion is usually unique within the module, but is not necessarily unique across the system.
This scheme effectively assigns 4096 Error Codes to each of 512K modules. The Error Codes in each module start at
PMCFW_ERR_BASE_xxx, where ‘xxx’ is the module name.
The following example shows how error codes are defined.
#define STE_ERR_FAIL (PMCFW_ERR_BASE_STE | 0x01)
#define UART_STAT_ERR_PARITY (PMCFW_ERR_BASE_UART | 0x02)
A special Error Code, PMC_SUCCESS, is defined as 0x0000 in PMCFW_ERR. H. PMC_SUCCESS may be used by
any module to indicate that no problems have been encountered.

17.5 Log Parsing Instructions

This section contains instructions for adding the log and parsing the log entry.
1. Before adding the log to the firmware code, define the error code and add the log data to the header file
corresponding to each module.
For example:
In the SASD module, to add the new log code to the sas_log.h file enter:
SAS_LOG_DATA(SAS_LOG_SMPINIT_INIT, "LINK SMPINIT: init"),
And add the log entry to the c file:
SAS_LOG(osf_log_sev_medium, SAS_LOG_SMPINIT_INIT, 0, 0, 0, 0);
1. Use the SES string out LOG CONTROL command (0x40), LOG SELECT, INIT STRING, or CMDSVR to set
the log filter level and also set the log mask and pattern for each application filter index. See LOG SELECT
Command in 14.3.2 SCSI Command Support, SES LOG CONTROL Command in 17.2.2 Event Logging Filter
Format and the static configuration in Table 8-21.
2. To retrieve the log entry from the SXP the firmware, see the instructions in 17.2.4 External Log Retrieval
Interfaces .
3. Before parsing the retrieved log, use gen_log_def_sxp.sh to generate the osf_log_def.data under
\fwcs\scsi_host\etc folder in Windows CLI, and use the following instructions. Make sure to use ‘/’ instead
of ‘\’ in the path.
cd fwcs\scsi_host\bin
sh.exe ../etc/gen_log_def_sxp.sh <absolute path of fwcs folder>
3.1. Use a tool to convert the data file retrieved from firmware to the binary file that the log parser can
recognize if necessary. For example, if a log data file is retrieved from command server in a ASCII
string format, need to have a tool like ‘xxd’ to convert it to a pure binary file with big endian format.
3.2. Use pmc_log.exe under \fwcs\scsi_host\bin folder to parse the log as follows:
Example:
pmc_log.exe –D –I log.bin –o log.txt
-D: Decode a log data file in raw binary format
-i: Specify the raw log data file to be decoded
-o: Specify the output file
For the detailed usage of this tool, refer to section 19.2 Microchip Log Parser Utility.

17.6 Fatal Error Handling

The SXP 12G firmware implements a fatal error handling mechanism for hardware and firmware errors. These fatal
errors include:
• NMI caused by hardware errors. By default, the SXP 12G firmware implements callback which adds a log entry,
flushes logs, dumps stack, activates thread information in flash memory, and then enters Customer Fatal Error

Event Logging and Error Handling

Handler. Under some conditions, error handling for NMI may be unreliable since the hardware to run the code
itself maybe in an error state, e.g., SPRAM Uncorrectable ECC, Memory Controller Uncorrectable ECC and
MBIC Error.
• General Exception/TLB Exception/DSPRAM Error. By default, the SXP 12G firmware implements callback which
adds a log entry, flushes logs and dumps GPR registers and stack and activates thread information in flash
memory, and then enters Customer Fatal Error Handler finally.
• PMCFW_ASSERT. The SXP 12G firmware adds a log entry, flushes logs, dumps stack, activates thread
information into flash, and then enters a minimal firmware debugging mode.
• Watchdog Timeout. The SXP 12G firmware adds a log entry, flushes logs, dumps stack, activates thread
information into flash, and then enters the Customer Fatal Error Handler.
Figure 17-1. Fatal Error Dump Flow

The format of information dumped into flash is defined by the data structure sxp_dump_info_hdr_struct, which is
located in sxp12g/inc/sxp_fatal_err.h.
Table 17-9. SXP Dump Header Definition

Member Description

Magic_string A magic string, filled in as “DUMPINFO”

Event Logging and Error Handling

...........continued
Member Description

Dump_reason Indicate why dump happened.

typedef enum
{
osf_dump_fatal_err_nmi = 1, /* NMI Error */
osf_dump_fatal_err_fw_assert, /* Firmware Assert */
osf_dump_fatal_err_wdg_timeout, /* Watchdog timeout */
osf_dump_fatal_err_gen_exc, /* General exception */
osf_dump_fatal_err_tlb_exc, /* TLB exception */
osf_dump_fatal_err_cache_dspram_err, /* Cache/DSPRAM error */
osf_dump_wol /* Wake on LAN */
}osf_dump_reason_enum;

Section_cnt The block number followed from log_offset to the last block. In this version it’s 6.

Firmware_rev The firmware version with which the fatal error event log is dumped to the flash.

Log_offset Offset address of the log dump block in partition. This field is 0 if Log dumping failed.

Log_len Length of the log block. This field is 0 if Log dumping failed.

Reg_offset Offset address of the Register dump block in partition. GPR is dumped only for General
Exception, TLB Exception and DSPRAM error. This field is 0 if register dumping failed.

Reg_len Length of the Register dump block. This field is 0 if Log dumping failed.

Stack_offset Offset address of the System Stack dump block in partition. This field is 0 if System Stack
dumping failed.

Stack_len Length of the System Stack dump block. This field is 0 if System Stack dumping failed.

Act_thr_ctl_blk_offset Offset address of the Active Thread Control Struct dump block in partition. This field is 0 if
currently no Active Thread, or the Active Thread Control Struct dumping failed.

Act_thr_ctl_blk_len Length of the Active Thread Control Struct dump block. This field is 0 if currently no Active
Thread or the Active Thread Control Struct dumping failed.

Act_thr_stack_offset Offset address of the Active Thread Stack dump block. This field is 0 if currently no Active
Thread, or the Active Thread Stack dumping failed.

Act_thr_stack_len Length of the Active Thread Stack dump block. This field is 0 if currently no Active Thread
or the Active Thread Stack dumping failed.

Thread_offset Offset address of the All Thread Information block. This field is 0 if currently All Thread
Information is empty or the All Thread Information dumping failed.

Thread_len Length of the All Thread Information block. This field is 0 if currently All Thread
Information is empty or the All Thread Information dumping failed.

Timestamp The timestamp of the fatal error log is dumped. This is for user to check whether there is
a new fatal error log or old fatal error log that was not erased.

hdr_crc The dump header CRC32 checksum. Firmware uses this value to check whether the fatal
error log is valid.

Event Logging and Error Handling

The following table illustrates the layout of the dump information in the flash NV_Log partition.
Table 17-10. SXP Dump Info Layout

Address 00 01 02 03 04 05 06 07 Note

NV_Log
Magic String (DUMPINFO)
Base

Dump Section
0x08 Reserved firmware_rev
Reason Count

0x10 log offset log_len

0x18 reg_offset reg_len

0x20 stack_offset stack_len

0x28 act_thr_ctl_blk_offset act_thr_ctl_blk_len Dump Header

• rd_log
• emip
• wr_32 (no response for this command)
• reset (no response for this command)
The command and response formats are defined as follows:
Table 17-11. TWI Interface rd_log Command

Byte \ Bit 7 6 5 4 3 2 1 0

0x00 OpCode (0x03)

Table 17-12. TWI Interface rd_log Response

Byte \ Bit 7 6 5 4 3 2 1 0

0x00 Address (LSB)

0x01 …

0x02 …

0x03 Address (MSB)

0x04 Num of log entry (LSB)

0x05 …

0x06 …

0x07 Num of log entry (MSB)

Table 17-13. TWI Interface rd_32 Command

Byte \ Bit 7 6 5 4 3 2 1 0

0x00 OpCode (0x04)

0x01 Address (LSB)

0x02-0x03 …

0x04 Address (MSB)

0x05 Num of DWORD (LSB)

0x06-0x07 …

0x08 Num of DWORD (MSB)

Table 17-14. TWI Interface rd_32 Response

Byte \ Bit 7 6 5 4 3 2 1 0

0x00 Data0

… …

Event Logging and Error Handling

...........continued
Byte \ Bit 7 6 5 4 3 2 1 0

Data 4N-1
4N-1
(N is the num of 32 bit words)

Table 17-15. TWI Interface emip log Command

Byte \ Bit 7 6 5 4 3 2 1 0

0x00 OpCode (0x05)

0x01 Emip id

Table 17-16. TWI Interface emip log Response

Byte \ Bit 7 6 5 4 3 2 1 0

0x00 Data0 in emip log buffer

… …

Last data in emip log buffer

8N-1
(N is the num of the emip log entry)

Table 17-17. TWI Interface wr_32 Command

Byte \ Bit 7 6 5 4 3 2 1 0

0x00 OpCode (0x06)

0x01 Address (LSB)

0x02-0x03 …

0x04 Address (MSB)

0x05 Data of DWORD (LSB)

0x06-0x07 …

0x08 Data of DWORD (MSB)

Table 17-18. TWI Interface reset Command

Byte \ Bit 7 6 5 4 3 2 1 0

0x00 OpCode (0x07)

Firmware defines boundary of these RAMs in sxp_common_base.ld and defines size of RAM for system stack, heap,
free_memory (OSF resource) in sxp_evbd_ram.ld and sxp_evbd_rom.ld. You need to increase the size of those
sections based on real situations, e.g., to support more outstanding requests for SAS, to support more payload data
for STE, and so on.

18.2.5 Build Switches

The firmware provides several build switches to customize the firmware image during compile time. See the following
table for more detail.
Table 18-1. Build Switch

Build Switch Default Usage Description

(Typically for
PM805x)

WDG_ENABLE On Build watch dog into firmware image

TCPIP_ENABLE On Build TCP/IP stack into the firmware image, including

TCP/IP application (DHCP client and Telnet server)

HTTP_ENABLE Off Build HTTP server and demo web page into firmware
image. HTTP_ENABLE is valid only when TCPIP_ENABLE
is defined

WOS_ENABLE On Build WOS feature into firmware image

WOL_ENABLE On Build WOL feature into firmware image

PMC On Enable PMCFW_ASSERT in firmware

FW_ASSERT_ENABLE When enabled, the PMCFW_ASSERT() macro tests an
input condition, generates an unrecoverable FW assertion
error if the condition is false
When disabled, the PMCFW_ASSERT() macro usages in
the SDK is replaced with an empty function

PMC_SXP12G_EVBD On Build PMC EVBD board-specific feature into firmware

image. Currently only for the ‘Managed SAS Connector
Support’ feature.

18.2.6 ThreadX Thread Stack Size

The firmware has set a default stack size for each ThreadX thread. If any specific function is introduced in any one
of these threads, it is necessary that you increase the stack size of the thread to avoid the potential risk of a thread
stack buffer overflow.
Use the MULTI debug tool to monitor the thread current and peak stack usage.
Recommendations:
• Do not use the -Olink and -delete link options while linking an image. To prevent a watchdog timeout while
checking the stack usage, disable the watchdog.
• Use the MULTI tool to load the image to target the board.
• Add a breakpoint in a thread (for example, at the beginning of portmgr_state_poll_bpp_proc in portmgr.c).
• Once the firmware hits the breakpoint and tops, click the "TX" icon and check the "stack Check list" box.
The following table describes the ThreadX threads, their size and how to modify them.

Application Code Examples

Table 18-2. ThreadX Stack Details

Thread Name Default Stack Stack Size Location

Size (Bytes)

System Timer Thread 1024 Unmodified

Cmdsrv 2048 cmdsvr_parms_ptr->cfg.thread_stack_size =

SXP_THREADS_STACK_SIZE_LRG;(sxp.c)

EMA 1532 ema_parms_ptr->config.thread_stack_size =

SXP_THREADS_STACK_SIZE_MED;(sxp.c)

Portmgr Thread 2048 portmgr_parms_ptr->config.stack_size =

SXP_THREADS_STACK_SIZE_LRG;(sxp.c)

Port Connector Thread 1532 portmgr_conn_parms_ptr->config.stack_size =

SXP_THREADS_STACK_SIZE_MED;(sxp.c)

SAS 2048 sas_parms_ptr->config.stack_size =

SXP_THREADS_STACK_SIZE_LRG;(sxp.c)

STE thread 1532 ste_parms_ptr->config.stack_size =

SXP_THREADS_STACK_SIZE_MED;(sxp.c)

SGPIO 1532 sgpio_parms_ptr->config.stack_size =

SXP_THREADS_STACK_SIZE_MED;(sxp.c)

SMP Init 1532 smpinit_parms_ptr->config.stack_size =

SXP_THREADS_STACK_SIZE_MED;(sxp.c)

DSQ Thread 1024 dsq_parms_ptr->config.stack_size =

SXP_THREADS_STACK_SIZE_SML;(sxp.c)

SAHA Thread 1024 saha_parms_ptr->config.stack_size =

SXP_THREADS_STACK_SIZE_SML;(sxp.c)

SIA Thread 1024 sia_parms_ptr->config.stack_size =

SXP_THREADS_STACK_SIZE_SML;(sxp.c)

TCPIP Telnet Server 2048 tcpip_parms_ptr->apps_task.stack_size =

TCPIP_APPS_THREAD_STACK_SIZE_DEFAULT;(tcpip.c)

TCPIP Timer 2048 tcpip_parms_ptr->timer_task.stack_size =

TCPIP_TIMER_THREAD_STACK_SIZE_DEFAULT;(tcpip.c)

TCPIP Ethernet 2048 tcpip_parms_ptr->eth_task.stack_size =

TCPIP_ETH_THREAD_STACK_SIZE_DEFAULT; (tcpip.c)

WDG Thread 1024 wdg_parms_ptr->cfg.thread_stack_size = WDG_STACK_SIZE;

(wdg.c)

Note: Adjust the stack size properly for customized application threads, for example. EMA thread, TCPIP thread,
TCPIP Timer thread, Command Server thread, and so on.

18.2.7 Structure Redefinition

In a number of the custom structures defined in the SDK, reserved fields have been added in order to maintain 32-bit
alignment. Maintaining this alignment is necessary to avoid memory alignment exceptions during runtime. Similar
fields are also used to ensure that protocol-specific data structures observe any reserved fields defined in the
standard. It’s important that both of these restrictions are taken into consideration when extending existing structures
to implement custom functionality.

Host Utilities

19. Host Utilities

The Host utilities provide tools for firmware download, diagnostic and so on.
The Host Software executes on a PC configured with:
• Win2000/XP/Win2003/Win2008/Win7 PC
• WinPE 5.1 – only pmc_scsi_x64.exe can be used
• Host Bus Adapter (HBA)
• HBA Driver
To rebuild the host controller software the following additional software is required:
• Microsoft Device Driver Kit (DDK)
• Microsoft Visual C/C++ v6. 0
• Microsoft Visual C/C++ v6. 0 Service Pack 5
To rebuild the native 64bits host controller software the following additional software is required:
• Microsoft Windows WDK 8.1
• Microsoft Visual Studio Express 2013 for Web with Update 4
Note: pmc_scsi_x64.exe is PMC_SCSI host utility native 64bits version, it can run on Microsoft WinPE 5.1.

19.1 Microchip SCSI Utility

The Host Software consists of a prebuilt example pmc_scsi.exe and pmc_scsi_x64.exe (A native 64bits version of
Microchip SCSI utility). This utility provides the following operations:
• Scanning the SCSI adapters and displaying available devices
• Sending SCSI commands
• Sending SES commands
• Processing a *. mem MIPS program into a downloadable *. bin image
• Downloading an image through SES to the SXP 12G device
The pmc_scsi program utilizes the underlying services of the Microsoft SCSI Pass Through Interface (SPTI) to send
commands to the SXP 12G device. When the SPTI interface is called, the respective HBA driver is used to perform
the operation. The abstraction of SPTI allows pmc_scsi to function in both FC and SAS environments. The pmc_scsi
API is provided as a programming interface example that may be used along with the host compiler tools and DDK to
extend operations.
The SCSI command interface handles initialization, and the SES operations are tunneled through the SCSI SEND
DIAGNOSTIC and RECEIVE DIAGNOSTIC RESULTS commands which can be coded using the correct SCSI
operations through the interface.
The host application calling the interface must ensure that commands are properly sequenced. For example, after
placing a port into an initialization test mode (using a transport diagnostic SES command sent through SEND
DIAGNOSTIC), the next command should be the SES command through RECEIVE DIAGNOSTIC RESULTS to
provide coherent operations in the system.

19.1.1 Host API

The following prototype and parameters are currently used.

Host Utilities

19.1.2 pmc_scsi_exec_scsi_cmd

Execute a SCSI PUBLIC PMCFW_ERROR pmc_scsi_exec_scsi_cmd (pmc_scsi_module_struct

command *module_handle_ptr, UINT8 *cdb_ptr, UINT32 cdb_length, CHAR *adapter_name, UINT32
including send path_id, UINT32 target_id, UINT32 lun, UINT8 *data_ptr, UINT32 data_length, BOOL data_rx,
receive of data UINT8 *sense_ptr)
associated with
the command.
This interface is
utilized by
pmc_scsi.
Prototype

Inputs module_handle_ ptr pointer to the handle returned from the module open which contains
data necessary to perform the command

cdb_ptr pointer to up to PMC_ASPI_CDB_LENGTH bytes of data containing the

SCSI command to send

cdb_length length of cdb pointed to by cdb_ptr.

adapter_name String name of the adapter to issue the command. e. g. “\\. \Scsi0:”

path_id path name (or bus number) on the adapter over which to send the
command

target_id ordinal number of the target to issue the command

lun ordinal number of the logical unit number within the target to issue the
command

data_ptr pointer to location where data is being sent from for a command that
sends data to target

data_length length of data to transmit or maximum length to receive

data_rx TRUE: data is to be received by command (e. g. INQUIRY)

FALSE: data is to be sent with command (e. g. WRITE BUFFER)

Outputs data_ptr pointer to location where data is being sent from/received to during a
command that receives data from target

sense_ptr pointer where up to PMC_SCSI_SENSE_LENGTH data is received

when an error occurs.

Returns PMC_SUCCESS SCSI Command sent and reply received from target. Note that
sense_ptr must be checked to determine if command was successful
or unsuccessful.

PMCFW_ERR_ FAIL Target not accessible or incorrect parameters (lengths, and so on).

Side Effects None

19.1.3 pmc_scsi usage

The pmc_scsi. exe executable is contained in the directory fwcs/scsi_host/bin.
• It is recommended that the PATH be updated to include fwcs/scsi_host/bin to allow pmc_scsi to be invoked from
any directory.

Host Utilities

• There should be no need to re-build the executable but the source code and the pmc_scsi. dsw workspace file is
contained in fwcs/scsi_host/src/pmc_scsi.
• The pmc_scsi executable is invoked from a command prompt. Open a command prompt window, set the PATH
accordingly, navigate to the desired directory, and execute the program.
• To run pmc_scsi on Windows2008/Win7, make sure it is executed with administrator permissions.
The following are details for using the PMC_SCSI_GUI to perform a number of tasks:
• Displaying pmc_scsi command line options.
• Creating firmware binary files for download.
• Scanning for adapters and devices.
• Downloading firmware binary files.
• Issuing SCSI commands.
• Supported SES Diagnostic Pages.

19.1.3.1 Displaying pmc_scsi Command Line Options

There are a number of command-line options that direct the operation of pmc_scsi. An extensive list of these options,
allowable settings, and some examples of their use is generated by issuing the command:
pmc_scsi

19.1.3.2 Creating Firmware Binary Files for Download

The MULTI toolset can generate Memory Image files with the extension . mem. These files can be converted to . bin
files suitable for downloading through SCSI.
To create an executable application . bin file from a . mem file issue the command:
pmc_scsi -dwnld -c inputfile. mem outputfile. bin -part 6 -vendor "PMC" -prod_id 0x1 -hw_rev 0xB -fw_rev
"0x04060033"
The italicized strings – input and output filenames, -vendor vendor ID, -prod_id product ID, -hw_rev target hardware
revision, and –fw_rev firmware revision – are configurable. The flash memory partition specified with –part, is not
configurable. When creating a file for download, it is recommended that the partition be set to 6. This partition
specifies the secondary application partition in flash. A reference batch file, program_to_bin. bat, for creating
application . bin files has been included in the release under fwcs\scsi_host\bin.
To create a data image . bin file from a . mem file issue the command:
pmc_scsi -dwnld -c inputfile. mem outputfile. bin -part 2 -vendor "PMC_BOOT" -prod_id 0x1 -hw_rev 0xB -fw_rev
"0x04060033"
Again, the italicized strings are configurable, but the flash memory partition is not. When creating a data image for
download, it is recommended that the partition be set to 2. This partition specifies the secondary data image partition
in flash. A reference batch file, data_to_bin. bat, for creating data image. bin files has been included in the release
under fwcs\scsi_host\bin.
To create a bootloader . bin file from a . mem file issue the command:
pmc_scsi -dwnld -c inputfile. mem outputfile. bin -part 0xff -vendor "PMC_BOOT" -prod_id 0x1 -hw_rev 0xB -fw_rev
"0x0405001d"
Again, the italicized strings are configurable, but the flash memory partition must be 0xff and the last four characters
of the vendor ID must be “BOOT”. A reference batch file, bootloader_to_bin. bat, for creating bootloader .bin files are
included in the release under fwcs\scsi_host\bin.

19.1.3.3 Scanning for Adapters and Devices

19.3.2.2 Receiving Diagnostics SES Page

pmc_scsi –ses –diagrecv
The firmware receives a diagnostic reports SES page from the expander device and stores it in a temporary binary
file. Included is the binary SES page data, with each byte formatted as an ASCII character.

19.3.2.3 Parsing Reports SES Page

pmc_scsi -diagformat
When using this API, pmc_scsi calls the diagnostics host user application internally to parse the reports SES page
stored in the temporary file and stores the formatted reports in an ASCII file. The prepared ASCII file is then
displayed on the screen.

19.3.3 Input Command File Format

User commands are specified in files to help you maintain and organize the diagnostic operations. A command file
can have any number of commands, each listed on a single line. Comments are supported to help documenting the
file.

19.3.3.1 Comments
A comment begins with ‘#’ character. Characters between ‘#’ and an end of line character are treated as comment. A
comment can begin anywhere on a line.

19.3.3.2 Command
A command is specified on a separate line. The format of a command is as follows:
• Command Type – Type of command, specified by a keyword
• Command Descriptor – Details of the command, specified by a keyword
• Logical PHY ID – Logical PHY ID of the PHY on which the Diagnostics operation is performed, specified as a
hex number
• User arguments – Depending on the command specified with the command type and command descriptor, there
might be 0-2 user arguments specified as hex numbers.
• Spaces or tabs can be used to separate the various user command parts.

19.3.3.3 Command Type and Command Descriptor

A command is identified by the combination of Command Type and Command Descriptor. However, not all
combinations are valid. The following table describes the valid combinations.

Host Utilities

Table 19-1. Command Type and Descriptor

Command Command Details

Type Descriptor

start setupctrl Start setup control before or after diagnostic test with patterns inserted

start prbs Start inserting PRBS patterns

start invprbs Start inverted PRBS patterns

start cjtpat Start inserting CJTPAT patterns

start usrpat Start inserting user-defined patterns

start ssmon Start SPS Monitoring

start/once spscjtpat Insert one CJTPAT errors on SPS port

start spssetcjtpat Start inserting CJTPAT pattern on SPS port

start HDD Start HDD Access test

once codeviol Insert Code Violation once

once disperr Insert Disparity Error once

once errprbs Insert PRBS Error once (using a mask) (PRBS insertion continues)

once errcjtpat Insert erroneous CJTPAT pattern once (CJTPAT insertion continues)

once errusrpat Insert erroneous user-defined pattern once (using a mask) (user-defined pattern
insertion continues)

conf lsal Configure Line Side Analog Loop back

conf lsdl Configure Line Side Digital Loop back

conf ssal Configure System Side Analog Loop back

conf slsml Configure SPS Line Side metallic Loop back

conf ssdgnl Configure SPS System Side diagnostic Loop back

conf bppsuppress Configure bpp suppress

stop prbs Stop continuous insertion of PRBS patterns

stop cjtpat Stop continuous insertion of CJTPAT patterns

stop usrpat Stop continuous insertion of User-defined patterns

stop ssmon Stop SPS Monitoring

stop spssetcjtpat Stop inserting CJTPAT pattern on SPS port

deconf lsal De-configure Line Side Analog Loop back

deconf lsdl De-configure Line Side Digital Loop back

deconf ssal De-configure System Side Analog Loop back

deconf bppsuppress De-configure bpp suppress

Host Utilities

...........continued
Command Command Details
Type Descriptor

start setupctrl Start setup control before or after diagnostic test with patterns inserted

deconf/stop slsml De-configure SPS Line Side metallic Loop back

deconf/stop ssdgnl De-configure SPS System Side diagnostic Loop back

rxen prbs Enable receiving and processing of PRBS patterns

rxen cjtpat Enable receiving and processing of CJTPAT patterns

rxen usrpat Enable receiving and processing of user-defined patterns

thresh codeviol Specify Code Violation Error Interval Threshold

thresh disperr Specify Disparity Error Interval Threshold

report prbserrcnt Get PRBS Error Count Report

report cjtpaterrcnt Get CJTPAT Error Count Report

report usrpaterrcnt Get User-defined pattern Error Count Report

report cverrcnt Get Code Violation Error Count Report

report disperrcnt Get Disparity Error Count Report

report crcerrcnt Get CRC Error Count Report

report iccrcerrcnt Get In-Connection CRC Error Count Report

report lostdwsyncnt Get Lost DWORD Sync Count Report

report invaliddwcnt Get Invalid DWORD Count Report

report cverr$ Get Code Violation Error Interval Threshold Reached? Report

report disperr$ Get Disparity Error Interval Threshold Reached? Report

report cverrcnt$ Get Code Violation Error Count and Threshold Reached? Report

report disperrcnt$ Get Disparity Error Count and Threshold Reached? Report

report all Get Error Counts and Threshold Reached? Reports

report/ spscjtpat$ Get SPS CJTPAT error count

report$

report/ HDD$ Get HDD Access test report

report$

Host Utilities

...........continued
Command Command Details
Type Descriptor

start setupctrl Start setup control before or after diagnostic test with patterns inserted

reset prbserrcnt

reset cverrcnt

reset disperrcnt Any one of these commands resets the SSPL and SXL error counts including
PRBS Error Count, Code Violation Error Count, Disparity Error Count, CRC
reset crcerrcnt
Error Count, In-Connection CRC Error Count, Lost DWORD Sync Count, Invalid
reset iccrcerrcnt DWORD Count,

reset lostdwsyncnt

reset invaliddwcnt

reset cverr$ Reset Code Violation Error Interval Threshold Reached? Info

reset disperr$ Reset Disparity Error Interval Threshold Reached? Info

reset cverrcnt$ Reset Code Violation Error Count and Threshold Reached? Info

reset disperrcnt$ Reset Disparity Error Count and Threshold Reached? Info

reset all Reset Error Counts and Threshold Reached? Info registers

reset$ spscjtpat$ Reset SPS CJTPAT error count

19.3.3.4 User Arguments for Commands

The following table describes the commands that require user arguments. Commands not listed in this table require
no arguments.
Table 19-2. Command User Arguments

Type Descriptor Argument Type

start setupctrl Setup control word 24-bit Hex

start/rxen usrpat User pattern 1 40-bit Hex

User pattern 2 40-bit Hex

once codeviol Code violation Pattern 10-bit Hex

once errprbs PRBS/User pattern Error Mask 40-bit Hex

thresh codeviol Threshold 8-bit Hex

PMON Period 24-bit Hex

thresh disperr Threshold 8-bit Hex

PMON Period 24-bit Hex

Host Utilities

Table 19-3. SPS Diagnostics Command User Arguments

Type Descriptor Argument Type

start ssmon SPS Port number 8 bit Hex

start / once spscjtpat SPS Port number 8 bit Hex

start spssetcjtpat SPS Port number 8 bit Hex

conf ssdl SPS Port number 8 bit Hex

conf slsml SPS Port number 8 bit Hex

conf ssdgnl SPS Port number 8 bit Hex

stop ssmon SPS Port number 8 bit Hex

stop spssetcjtpat SPS Port number 8 bit Hex

deconf / stop ssdl SPS Port number 8 bit Hex

deconf / stop slsml SPS Port number 8 bit Hex

deconf / stop ssdgnl SPS Port number 8 bit Hex

report$ spscjtpat$ SPS Port number 8 bit Hex

19.3.3.5 Last User Command

The keyword ‘END’ should be the last parameter at the end of the last command. Any command after such a line is
ignored.

19.3.3.6 Ordering of Commands

The order that commands are entered in a file is maintained while creating the SES page.
Note the endianness of the parameters. Parameters after logical PHY ID are 16 bits.
For example, for
Start usrpat 0x12 0x0201 0x4030 0x5566 0x0
the logical PHY ID is 0x12,
the
1st parameter is 0x01,
2nd parameter is 0x02,
3rd parameter is 0x30, and so on.

19.3.3.7 Example Input User Command of File

Diag_example.txt
start setupctrl 0x08 0x0001 0x00
start prbs 0x08
conf lsal 0x08
rxen prbs 0x08
reset prbserrcnt 0x08
once errprbs 0x08 0x5555 0x5555 0x5555
report prbserrcnt 0x08
stop lsal 0x08
stop prbs 0x08
start setupctrl 0x08 0x0000 0x0000 END

19.3.4 Output Report File Format

The report file presents reports in a tabular format using four columns – (Report) Type, PHY, Status, and Report:

Host Utilities

• The Type column shows ASCII title of a report type e.g. PRBS Error Count.
• PHY column shows Logical PHY ID as a hex number.
• The Status column shows ‘good’ or ‘bad’ depending on the command processing status of the corresponding
user command.
• The Report column is either a number, specifying an error count, or a string – ‘yes’ or ‘no’ specifying if a
threshold was reached.
As an example, the following report file was obtained after running the Input User Command sequence specified in
Section 19.3.3 Input Command File Format.
Diagnostics Reports -------------------------------------------------- Type PHY Status Report
PRBS Err Count 0x8 good 0xc
Code Viol Err Count 0x8 good 0x1a3c0456
Code Viol Err Thhd 0x8 good no
Disparity Err Count 0x8 good 0x1c3c5f99
Disparity Err Thhd 0x8 good no
CRC Err Count 0x8 good 0x0
In-Conn CRC Err Count 0x8 good 0x0
Lost DW Sync Count 0x8 good 0x1
Invalid DW Count 0x8 good 0x1c3c8627

19.3.5 Examples
The location fwcs\scsi_host\src\pmc_scsi\sxp\etc contains sample user command files.
Table 19-4. SXP 12G Initialization String Table—PHY Configuration Global Setting

Byte 7 6 5 4 3 2 1 0 Default Value Range

0x0200 Reserved 0x00 Bit Field

0x0201 Reserved 0x00

0x0202 Reserved 0x00

STP
OPEN
0x0203 Reserved REJECT 0x01
AWT
Clear

0x0204 TX BCT C1 MAX 0x00

0x0205 TX BCT C1 MIN 0xF6

0x0206 TX BCT C3 MAX 0x00

0x0207 TX BCT C3 MIN 0xED

0x0208 TX BCT VPP MAX 0x40

0x0209 TX BCT VMA MIN 0x06

Host Utilities

...........continued
Byte 7 6 5 4 3 2 1 0 Default Value Range

DP FFE M
PRELOAD
0x020A SAS3 12G Reserved DP FFE M PRELOAD SAS3 12G 0x1F
Global
Disable

Test
0x020B–
Threshold Reserved 0x00
0x020F
Enable

0x0210 TMF Tag0 (MSB) 0xFF

0x0211 TMF Tag0 (LSB) 0xFE

0x0212 TMF Tag1 (MSB) 0xFF

0x0213 TMF Tag1 (LSB) 0xFF

0x0214 SAS Buffering Initiator Retry Timeout (MSB) 0x3A

0x0215 SAS Buffering Initiator Retry Timeout (LSB) 0x98

Xopen
Multi-
0x0216 Reserved Detect 0x00
LUN En
En

0x0217–
Reserved 0x00
0x0219

0x021A Reserved 0x00

SATA
Buffering
STP
Link
open
0x021B Reserved Reset 0x00
control
Error
disable
PHY
Enable

0x021C–
Reserved 0x00
0x022F

Revision History

20. Revision History

Revision Date Description

A 05/2021 Document converted to the Microchip format. Document number changed from PMC-2120216 to
DS00004013.

19 10/2019 Updated Table 8-9 to add description of ‘PHY reset handling Enable and PHY reset in progress
timeout’

Updated Table 51 to add description ‘PHY reset handling Enable and PHY reset in progress timeout’

Updated ‘Take effect immediately’ field that indicates whether SSSF PHY configurations in the SES
page will take effect immediately on a PHY

18 07/2019 Added new section 3.1.21 SATA Interlace Feature SATA Interlace Feature

Updated 9.2.1 Terminal Interface Terminal Interface

Updated TMF Tag 0 to TMF Tag 1 in section ‘SGPIO Drive Slot Bus ID’

Updated Table 14-93 Updated Table 14-91

17 07/2017 Added the new init string field ‘Disable expander phy’ at Table 8-22

Added the new init string field ‘SMP Initiator Nexus Timeout’ at Table 8-34.

Updated the number of ‘LOG Entry Count’ at Table 8-30.

16 01/2017 Added ‘Reserved’ and ‘Page length’ fields to ‘SES Delay test page’ in Table 14-73.

15 07/2016 Section 8.3.1 Flash Memory Initialization String Format

Add new field ‘First Virtual Connector Element Index’ in Table 8-17

Add detail description about how to set phy connector element index.

Section 14.2.3 Supported SES Pages and Limitations

Add new field “EIIOE” in Table 14-51.

14 04/2016 Section 14.2.3 Supported SES Pages and Limitations

Updated Table 226 PHY Analog Setting Page Format with correct bit number for Analog Setting
descriptor

13 03/2016 Section 4.2.1 Firmware Download Mechanism: Updated firmware image header with new fields

Section 4.5 Firmware Image Authentication: Added this section to describe firmware image
authentication

Section 15.2.3: Modified Page size from 32 to 33 in L (LINK RESET) to reset the PHY.

Table 14-75

Table 14-91, added “Multi-Host A/A XOPEN STS CLR PHYx”, “Xopen Detect En” and “Multi- LUN En”
fields.

Table 14-94, added “Multi-Host A/A Xopen Deadlock Detect”, “Multi-Host A/A Xopen Detect” and
“Multi-Host A/A Xopen deadlock hit count” fields.

Section 8.3.1 Flash Memory Initialization String Format

Table 8-9, added “Xopen Detect En” and “Multi- LUN En” fields.

Revision History

...........continued
Revision Date Description

12 11/2015 Section 3

2.2.3 Memory Controller, add a table to describe memory space.

Section 8

Table 8-5, change 0x39-0x3A from reserved to Zone configuration EEPROM setup

Table 8-9, added note of SSSF TMF Tag0 and TMF Tag1 field

Table 8-9, added “STP open control disable” field

change the Zone Configuration table size description from 2175 to 8383

Table 8-9, added “DP FFE M PRELOAD SAS3 12G Global Disable” field and “Test Threshold Enable”
field;

Table 8-9, added “Power Disable Supported” field, “DP FFE M PRELOAD SAS3 12G” field, “Test
Threshold” field;

Table 8-17, changed “NUMBER OF ENCLOUSRE CONNECTOR” to “TOTAL NUMBER OF

ENCLOUSRE CONNECTOR”; Changed “Connector Physical Link” description

Table 8-40, updated “No SATA Spin-up Hold Broadcast” field description

Table 8-37, added 0xF4 page; Changed the default value and value range of the change field

Section 14. Protocol Stack Library

Added Fatal Error Event Log Control/Retrieval Page(0xF4)

14.2.3 Supported SES Pages and Limitations, 14.2.3.45 SSSF PHY Configuration Page (0xF3),
update description of the field “Uncorrectable ECC control”;

Table 14-4, added Fatal Error Event Log Control/Retrieval Page(0xF4)

Table 14-44, changed the “Connector Physical Link” definition

Table 14-92, changed field “EMIP Uncorrectable ECC error” to reserved; Added new fields “SSSF ram
uncorrectable ecc”, “SXL uncorrectable ecc error”, “EMIP uncorrectable ecc error”, “sssf split mode”

Table 14-135, changed the DEVICE SLOT NUMBER field definition

Section 17. Event Logging and Error Handling

Table 17-9, changed SXP Dump Header Definition to add more fields

Table 17-10, changed SXP Dump Info Layout for the newly added fields

Section 19. Host Utilities

Added pmc_scsi 64bits version description

Added pmc_scsi 64bits version

Revision History

...........continued
Revision Date Description

11 12/2014 Section 8

7.2.1 External Interface, added twi_mst_stretch_time_set() for TWI driver functions.

Section 8

8.3.1, Change the description of SCSI Supported Initiator Count field.

8.3.1 Flash Memory Initialization String Format, Change the note of STE Maximum Data Size Field.

Added Table 8-24

Table 8-9, added DP FFE M PRELOAD SAS3 12G field

and Table 14-76, added SAS12G PGA BOOST EN field;

Table 8-17, Remove “legacy optical without OOB” option in Unmanaged Connector Type field.

Table 8-19, added IBPI enable flag field and Blink rate C field;

Table 8-19, added Bus Used By Rx GP field

Table 8-20, description of “TWI Master Speed Mode” field, change unit “K” to “kbit/s”.

Table 8-32, CS0 Timing Register0 and Timing Register1 field. Add note for special flash that is not
applicable to default value.

Table 8-34, updated description of the STP Bus Inactivity Time field

Table 8-37, added SES-3 supported pages field

Table 90, deleted NZGF Disable field.

Section 9

Figure 9-3, Command Server Console Trace, added update_see and err_cnts commands.

Section 15

Added Table 14-17 voltage control element, Table 14-36 voltage status element andTable 14-37.
Added voltage field in Table 14-9 and Table 14-24.

Revision History

...........continued
Revision Date Description

10 05/2014 Section 8

7.2.1 External Interface, added twi_slv_offset_width_set() for TWI driver functions and modified the
prototype of twi_nonthreadx_slv_init() and twi_slv_init().

Figure 7-1, added note for starting address to keep 24-byte alignment.

Section 9

Table 8-7, added Phy Reset If Zone Phy Info Change.

Table 8-8, updated PHY and SGPIO Maps description.

Table 8-9, added 6G/3G connection management enable, TX Cx BCT START POINT and No
Equalization for Tx Coefficient Settings, changed 12G connection management field description and
added note of the TX 3 ID frame field and the SAS align mode field.

Table 8-18, added note of the additional PHY event fields.

Table 8-34, added new field used to limit the retry open time. Added mask map field for reject to open.

Table 8-36, changed max disk drive count from 0x30 to 0x44.

Table 8-50, extended zone group to 8 bits.

Changed default SEEPROM table size from 0x0000 to 0x0100 in

, changed bit 5 from reserved to Ethernet Info.

Added Table 8-64.

Added Table 8-65 and updated .

Table 8-66, updated the length of the Number of Zone Groups and Increment CRC Protection Scope
fields.

Section 10

9.2.1 Terminal Interface, added rx_para_get and tx_para_get in command server to capture SAS
Rx/Tx parameters.

Section 11

Added Figure 10-11 SSU State Machine, Table 10-7, and Table 10-8 to describe the SSU Events.

Added Table 10-12 to describe programming hook functions.

Section 15

14.2.3 Supported SES Pages and Limitations, added PHY Analog Setting Status Page (0x83).

14.2.3 Supported SES Pages and Limitations, added Element Status page (0x7), Supported
Diagnostics page (0x0D), Subenclosure Nickname Page (0xF).

14.2.3 Supported SES Pages and Limitations, changed ES Electronics count from 2 to 1 and updated
offset in Table 14-9 and Table 14-24.

Table 14-74, added BCT version.

Table 14-76, added TX Cx BCT START POINT.

Table 14-92, added new field used to control the SXP handling the 2-bit ECC error and added 6G/3G
connection management enable.

Table 14-94, added maximum frame count.

Section 18

17.1.2 Hardware ECC/Parity Errors, added new description for SSSF and EMIP uncorrectable ECC
error, and added SSSF Read/Write (Test Pattern) API description and added Table 17-1.

Revision History

...........continued
Revision Date Description

9 10/2013 Overall Minor formatting and grammar fixes.

Section 7 Device Drivers

Modified SPI API parameter Data_length type from UINT8/UINT16 to UINT32

Table 7-5, added spi_hw_assisted_write_read and spi_hw_assisted_write_write.

Added spi_mem_mapped_write_write

Added spi_mem_mapped_write_read

Section 8

Table 8-1, updated field 0x1350 - 0x135F description.

Table 8-9, removed phy low power related fields.

Table 8-9, added 12G connection management related fields.

Added Table 8-26 Pin Drive Strength Control.

Added Table 8-27 Drive Strength Modes.

Table 69 modified the value of MAC_ADDR and Net Mask 2.

Table 8-50, Reserved bit 7.

Table 8-51, Updated Group 10 to Group 252 Permission Entry.

, Updated 0x0002 and 0x000F names.

Section 13

Table 12-1, updated Init String Fields Classification.

Section 14

13.10 Zoning Configuration On The Fly, updated the zone unlock description for NDSR with the lock
inactivity timer

Section 15

Table 14-92, added 12G connection management related fields.

Section 15

Removed the PHY Low Power Condition Support section.

Section 18

Added Table 17-10 layout of the dump information.

Revision History

...........continued
Revision Date Description

8 08/2013 Overall

The QoS feature which provides the ability to dynamically adjust AWT values based on event counters
will not be supported and has been removed from the FUM Revision issue 7.

Minor format fix

Fixed some wording

Section 4

3.1.19 Cable Management, updated cable management description

Section 5

Table 10, updated firmware download status

Section 6

5.3 System Recovery in Bootloader, added system recovery in bootloader

Section 7

Table 6-2, updated osf function usage

6.2.2 Data Structures, updated osf_sys_cfg_struct

Section 8

Table 7-4, updated Flash Driver Functions

7.1.4 SPI Flash Driver, updated SPI Flash Sector erasing procedure

7.2.2 TWI Slave Usage, added TWI slave usage

Table 7-11, update HAL functions

Section 9

Table 8-5, modified value range of SAS_BASE_ADDR

Table 8-6, updated the description of SAS address MAP

Table 8-32, updated the description of watchdog block timeout field

Table 8-34, updated the description of STP reject to open limit timer field

Section 10

9.1.2 Data Structures, updated wdg_cfg_struct

Figure 9-3, updated command server trace

Figure 9-4, updated command list

9.5 SXP Diagnostics, removed PRBS error threshold

Table 9-4, updated diagnostic Counters description

Section 14

13.2 Zone PHY Information, added notes about detecting SATA device

Section 15

15.2 Optical Cable Support, updated STP Flow Control Buffer size statement

Section 18

17.5 Log Parsing Instructions, update log parsing instructions description

Section 19

18.2.7 Structure Redefinition, added structure redefinition

Revision History

...........continued
Revision Date Description

7 05/2013 Overall

Minor format fix

Section 8

7.1 Flash, added expanded description of flash timing parameter used in firmware.

Section 9

8.3 Initialization String Format, added a recommendation that initialization string table should only be
accessed per byte.

Table 8-5, Modified definition of SAS_BASE_ADDR, SMP_SAS_ADDR_LSB and

SSP_SAS_ADDR_LSB.

Table 8-5, added a new field SAS_BASE_ADDR_LSB_MASK.

Table 8-8, modified value range of the PHY_COUNT field.

Table 8-8, modified default value for TX BCT C1 MIN and TX BCT C3 MIN.

Table 8-9, added fields T PISO PRE2 SEL SAS 1G5/SAS 3G/SAS2 6G/SATA 1G5/SATA 3G/SATA
6G.

Table 8-9, added fields T PISO EDGE DELAY SEL SAS 1G5/SAS 3G/SAS2 6G/SATA 1G5/SATA
3G/SATA 6G.

, modified definition for SAS_BASE_ADDR, SMP_SAS_ADDR_LSB and SSP_SAS_ADDR_LSB.

, added a new field SAS_BASE_ADDR_LSB_MASK

Section 15

14.2.3 Supported SES Pages and Limitations, added Help Text diagnostic page and SES Delay Test
page

14.2.3 Supported SES Pages and Limitations, updated description for SXP-Specific Diagnostics Page
for SAS (0x3F)

14.2.3 Supported SES Pages and Limitations, added corresponding new fields in table 206 as in
table 45 for PHY Analog Setting Control Page(0x83).

14.3.4 SCSI Sense Data, fixed sense data of COMMAND CLEARED BY ANOTHER INITIATOR

Section 19

18.2.5 Build Switches, removed build switches that are not supposed to be used by customer

6 01/2013 Section 7

6.10 Interrupt Control Framework, updated SSSF related interrupts

Section 9

Table 8-9, added buffering related fields

Section 13

12.2.2 NDSR Process, updated Firmware Load Process for two EMIP images

Section 15

14.2.3 Supported SES Pages and Limitations, added “SSSF PHY Configuration Page” and “SSSF
PHY Status Page”

Revision History

...........continued
Revision Date Description

5 12/2012 Overall

added more markers for the PM805x device only feature

Section 8

Table 7-1, updated the table for 2nd SPI

7.2 TWI, updated ThreadX TWI APIs for 256 bytes payload support, and Non-ThreadX TWI APIs for
parameter type change

Section 16

15.1 Managed SAS Connector Support, added EVBD related description for the ‘Managed SAS
Connector Support’ feature

15.4 Wake-on-LAN / Wake-on-SAS, updated description for WOL/WOS

Section 19

18.2.5 Build Switches, added PMC_SXP12G_EVBD build switch

Revision History

...........continued
Revision Date Description

4 11/2012 Overall

Fixed some wording

Section 6

5.4 Reset Event and NMI Handling, changed description of NMI callback.

5.5 Bootloader User-Defined Hooks, added ‘reset_type’ parameter for boot_hook_hw_init

Section 7

6.10 Interrupt Control Framework, updated new interrupts for EMIP and FWS

Section 8

7.2 TWI, added twi_nonthreadx_slv_init and changed description of Threadx TWI APIs for 128-byte
payload support

7.3 UART, added description of non-Threadx UART driver

Section 9

Table 8-5, removed “PM8043_REVA” and “PM8044_REVA” fields, and changed SMP_PHY_ID and
SSP_PHY_ID as 7bits.

Table 8-7, removed ‘BPP Forward Inhibit’, ‘Wide port SMP Ping Instances’ and ‘Downstream
Expander Maximum PHY Count’ fields

Table 8-9, added ‘GLOBAL QOS EN’ field

Table 8-9, added ‘SAS Slumber En’, ‘SAS Partial En’ and ‘TRS TXCLK SEL SATA 1G5/3G/6G SSC’
fields, and removed ‘SATA G1/G2/G3 SSC EN’, ‘TRS TXCLK SEL SATA SSC’ and ‘TX EMI CAL
ENABLE’ fields

Table 8-11, updated PHY RATE description

Table 8-11, updated SNW3 PHY capability description.

Table 8-21, added ‘Nonthreadx CMDSVR Interface’, ‘Nonthreadx CMDSVR TWI PORT ID’ and
‘Nonthreadx CMDSVR TWI Slave Address’ fields

Table 8-25, redefined the whole format for GPIO Configuration

Table 8-29, added description for ‘POLARITY’ and ‘EPOW_EN’ fields

Table 8-30, changed default setting of ‘LOG Global Filter Level’ to 2

Table 8-34, added ‘SSP Initiator Response Timeout’, ‘STP Max Connect Limit time’ and ‘STP REJECT
TO OPEN LIMIT’ fields

Table 8-36, changed default setting of ‘Disk Drive Count’ to 0x0C

Table 8-40, added ‘Power Control Enable’ file

Table 90, changed default setting of ‘NZGF Disable’ to 1

added new table for PHY QOS Configuration

, changed SMP_PHY_ID and SSP_PHY_ID as 7 bits

Table 8-60, removed ‘BPP Forward Inhibit’, ‘Wide port SMP Ping Instances’ and ‘Downstream
Expander Maximum PHY Count’ fields

Section 10

9.5.4 Diagnostics Commands, changed Inverted CJTPATs to Erroneous CJTPATs

9.5.5 Diagnostics SES Pages, added support for Loopback mode

Revision History

...........continued
Revision Date Description

Section 15

14.2.3 Supported SES Pages and Limitations, changed page code of ‘PHY Analog Setting Control
Page’ from 0x13 to 0x83

14.2.3 Supported SES Pages and Limitations, added ‘PHY QOS Setting Set/Get Page’

14.2.3 Supported SES Pages and Limitations, added ‘Port Mirroring Control/Status Page’

14.3.2 SCSI Command Support, added support for EMIP firmware log

14.7.4 SMP Functions Specific to Microchip, added ‘PMC Report PHY QOS’ and ‘PMC Configure
PHY QOS’

Section 16

15.5 Early Power Off Warning (EPOW), changed description of EPOW

Section 18

17.6.1 Customer Fatal Error Handler, added more detail for ‘customer fatal error handler’

Revision History

...........continued
Revision Date Description

3 09/2012 Overall

Add description for two new variants 8043, 4044

Section 5

4.2 Firmware Download , added firmware download steps

4.4 Flash Partition Map , added 8M partition map and rules to customize a vendor specific partition
map

Section 6

5.4 Reset Event and NMI Handling, updated the Figure – NMI Handling Flow, minor change

Section 7

6.6.1 External Interface, added two APIs for log global severity level set/get

6.10.2 SXP 12G Enabled Interrupt, added a table for SXP 12G enabled interrupts

Section 8

7.1 Flash, changed description of flash erasing operation

7.1.4 SPI Flash Driver, added a bus_id parameter for SPI driver API

7.5 GPIO, changed parameters for gpio_port_cfg, gpio_port_write and gpio_port_read

Section 9

Table 8-3, added a PMC Table version field

Table 8-5, added a field for PM8044 and PM8043 Device ID

Table 8-7, changed description for the ‘Wide-Port Policing Enable’ Field and added a ‘Report Partial
RT’ field

Table 8-9, removed the ‘PHY Delay Interval’ field, added a ‘STP OPEN REJECT AWT Clear’ field and
redefined those fields for analog parameters

PHY Configuration Per PHY, removed the ‘STP OPENREJECT AWT Clear’ field; removed
the ‘IMPEDANCE SAS 1G5/SAS3G/SAS2 6G/SATA1G5/SATA3G/SATA6G’ fields; removed the ‘T
PISO PRE2 SEL SAS 1G5/SAS3G/SAS2 6G/SATA1G5/SATA3G/SATA6G’ fields; removed the ‘T
PISO EDGE DELAY SEL 1G5/SAS3G/SAS2 6G/SATA 1G5/SATA3G/SATA6G’ fields; removed the
‘ANALOG PEAKING EN’ field; changed description for Tx coefficient setting and added a notes for
relationship between Legacy-AMP, PRE, POST value and SAS3- C1, C2, C3

Table 8-30, redefined the whole table format

Table 8-32, filled in parameters for CS0 and CS1 timing configuration

Table 8-34, removed the field ‘SMP Supported Initiator Count’

Table 8-31, added ‘SIA Thread Maximum Simultaneous Requests from DSQ’ field and ‘SAHA Thread
Maximum Simultaneous Requests from DSQ’; redefined the ‘SIA Thread Maximum Simultaneous
Application Requests’ field

Table 8-46 – RF and NDSR Configuration Block, added the field ‘Flash Erase Poll Period’

Revision History

...........continued
Revision Date Description

Table 90, added the ‘NZGF Disable’ field and added a table of ‘SMP REPORT ZONE PERMISSION
TABLE REQUEST Reserved Bits’, added a ‘PMC Table version’ field

Section 11

10.2.2 Routing Loop Detection and Resolution, changed description for SAS1.1 Routing loop
detection and resolution

10.3.1 Enhanced Distributed Discovery Algorithm, changed description for ‘Enhanced Distributed
Discovery Algorithm’

10.3.5 Loop Topology Detection and Resolution, added ‘Loop Topology Detection and Resolution’

10.4 Disk Spin-up, added SAS3 Power Control related description

10.5 Programmable Staggered Spin-Up Algorithm, changed the ‘Power Budget Equation’

Section 12. Reduced Functionality and Non-I/O Disruptive Soft Reset

RF and NDSR Process change

Section 15

14.2.3 Supported SES Pages and Limitations, added Vhist Capture Control Page and Vhist Capture
Status Page

14.3.2 SCSI Command Support, re-wrote contents of MODE SELECT (10) and MODE SENSE (10)

14.3.3 Task Management Function, added description for ‘Task Management Function’

Section 17

16.2 Inter-Expander Communication Over SAS, added description of ‘SIA support outstanding
request’ and add rules for SIA module usage.

Section 18

17.2 Enhanced Event Logging, changed description for ‘Event Logging Filter Level’ usage

17.3 SMP Self Configuration Event Logging, added description for SMP Self Configuration Event
Logging

17.6 Fatal Error Handling, added description for ‘Fatal Error Handling’ mechanism

17.7 Assert Functionality, changed description for Assert Functionality

Revision History

...........continued
Revision Date Description

2 05/2012 Overall

Fixed some wording and document format issues

Section 4

Updated Figure 4 – PM73206_04 Firmware Modules

4.1, added or modified module description for SSP Initiator/SIA, STP Initiator/SAHA, Power
Management, SAS Zoning, NDSR, Cable management, Inter-expander Communication, Command
Server, TCP/IP Stack and Network-based Application, Event Logging and Error Handling, SAS/SATA
Store& Forward and BCT Microcode, SXP SAS HW Block Drivers and SXP Peripheral Driver Module

4.2, updated Figure 5 – Thread Decomposition, to add the SAS Connector Manager thread

4.3, updated , to add a PHY_MAP_R_SHIFT function interface

Section 5

Added description for Partition Valid Flags in boot config.

5.1, updated firmware management and launching mechanism with new Partition Valid Flags

5.1, updated Figure 6 – Boot up Sequence

5.2, updated firmware download mechanism with new Partition Valid Flags

Section 6

6.3, updated Figure 9 – NMI Handling Flow, to incorporate WOL NMI specific operation

Section 8

8.1.4, added instructions of implementing support for new SPI flash chip

8.1.4, removed SPI ‘direct access mode’ related words

8.1.4, updated Table 7-5, to remove SPI direct access mode API and others private SPI driver API

8.8 updated Table 7-10, to introduce new Application Timer Driver API.

Section 9

9.3.1, updated tables for most of ISTR blocks, to use absolute offset address and HEX notation for all
initialization string fields

Table 8-5, changed name of the field “EEPROM Athroughl” to “address valid”, and fixed typo for
description of the TWI Serial EEPROM ADDR field

Table 8-7, updated usage of the Route Table Cleanup field.

Table 8-7, removed Zone Broadcast Enable field

Table 8-9, removed TX SSC Down Spread Type for all PHYs field, and added one field in

to make it configurable per PHY, removed TX_CX_PRST field, and added TX BCT Cx MAX, TX BCT
Cx MIN, TX BCT VPP MAX and TX BCT VMA MIN fields.

Revision History

...........continued
Revision Date Description

Table 8-9, added the TX SSC Down – Spread Type field

Table 8-9, added the ANALOG PEAKING EN field

Table 8-9, added the TX RR PERIOD FETX SAS3 12G field

Table 8-30, changed width of the LOG Entry Count field from 16bits to 20bits

Table 8-30, updated description of LOG Filter related fields

Table 8-31, added various fields and description

Table 8-32, added the SAS Connector Manager Thread Priority field

Table 8-34, changed SAS Supported Initiator Count from 0x02 to 0x10, SAS Tasks Per Initiator from
0x01 to 0x02, and SCSI Supported Initiator Count from 0x02 to 0x10

Table 8-34, updated description of the STP Bus Inactivity Time field

Table 8-36, changed default value of the Disk Drive Count and Disk Drive Slot 0~47 fields

Table 8-48, updated default zone group ID of PHY 8 to PHY 67

Table 8-50, changed width of the Virtual SSP/SMP PHY’s Group ID from 7bits to 8bits

Table 8-54, changed offset address of this block from 0x3400 to 0x3800

– Device Address Configuration, added Table Size Byte 1 and 0 fields

Section 10

10.5.1, added Figure 32 – SXP 12G Normal Datapath and Diagnostic Datapath

10.5.1, Table 9-4 – Diagnostic Counters, added new CJTPAT Error Count and User Pattern Error
Count, and removed PRBS Error Threshold

10.5.1, added Table 9-5 – Registers for Configuring Performance Counter for CJTPAT Errors

10.5.4, updated description for Diagnostics commands, added Error Insertion, Enabling Receive –
For PRBS, and so on.

Section 15

15.2.3, for Configuration Diagnostic Page, explained method to increase count of drive and connector
elements

Table 14-12 – Common Control Byte for All Element Types, updated usage of the PrdFail and Disable
fields

Table 150~157, updated description to remove words of ‘Rst Swap bit support’.

Table 14-26 – Common Status Byte for All Element Types, updated description of the Swap field, and
removed words of ‘Swap bit support’ for various elements.

15.2.3, added PHY Analog Setting Control Page

15.2.3, modified format of SXP Firmware Status page

Table 14-104 – SAS Port Mode Page – Short Format, added Reject to Open Limit field

Table 14-106 – SAS Logical Unit Mode Page – Short Format and Table 14-107 – Disconnect –
Reconnect Mode Page, added description for various fields

15.3.2, added paragraphs for LOG SENSE and LOG SELECT command

15.11, added ‘ipconfig macb’ command for MACB statistics

Section 16

16.1.2, added paragraph of FPGA Logic to explain what FPGA does for SAS Connector Management
feature

16.1.3, added more detail of FW implementation for SAS Connector Management feature

Revision History

...........continued
Revision Date Description

16.5, added more detail of FW implementation for WOL/WOS

Section 17

17.2, added description of ssp command which is a demo of implementing inter-expander

communication through SIA

Section 18

18.1, added description for ECC/Parity protection strategy in SXP 12G

18.2.2, added a Module Pattern ID table for event logging

18.4, added a paragraph to introduce log parsing mechanism

Section 19

19.2.2, added explanation for EMA thread polling peripherals mechanism when ISTR field of EMA
polling time is set to 0

19.2.3, added priority of new thread for SXP 12G firmware

19.2.6, added new build switch for SXP 12G firmware

19.2.7, updated stack size of various threads for SXP 12G firmware

19.2.4, updated state of RAM/Flash usage for current main firmware image

Section 20

20.1.2, updated description of how to create bin file from mem file by pmc_scsi with new version
scheme

20.2, added a paragraph to introduce PMC Log Parser utility

20.3, updated usage description of Host diagnostic tool, including command introduction and example
of command input/output

1 03/2012 Initial draft for SXP 12G

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