8237

DMA Controller
Group XV - SY EC
 Team Members

01 02 03 04 05

Atharva Atharva Ishayu Shashin Vedant

Ukey Sakpal Potey Vathode Dasgupta
 01
Need for DMA
Interfacing
What Is Interfacing
Interfacing refers to the process of connecting two or more electronic devices
together so that they can communicate and work together effectively.

Need For Interfacing

● Offloading CPU Burden : In our traditional systems, the CPU is responsible for
managing data transfers between peripherals and memory. This can consume
significant CPU resources and reduce overall system performance.

● High-Speed Data Transfer: DMA enables high-speed data transfer between

peripherals and memory without CPU intervention. This is crucial for
applications such as real-time data acquisition, networking, and
high-performance computing where fast and efficient data transfer is essential.
● Reduced Power Consumption: DMA helps us to lower overall system power
consumption. This is particularly beneficial in battery-powered devices, where
power efficiency is crucial for prolonged operations.

● Support for Peripherals: Peripheral devices require fast and efficient data
transfer capabilities, such as ADCs, DACs, and storage devices.

● Improved Multi-tasking: DMA interfacing supports multi-tasking environments

by allowing data transfer operations to proceed independently of CPU
execution.
 02
DMA Interfacing
with 8085
Single and Multiple DMAs
 2.1
8237 Pins related to
Data Transfer
 DREQ
● DREQ (DMA Request) is a signal used by peripheral devices to request access
to the system bus for DMA operations.
● When a peripheral device needs to transfer data to or from memory and wants
to utilize DMA, it asserts the DREQ signal.
● This indicates to the DMA controller that a data transfer request is pending.
The DMA controller then evaluates the priority of the request and, if
appropriate, initiates the data transfer between the peripheral device and
memory.
● DREQ plays a crucial role in enabling efficient and autonomous data transfers
in DMA systems, reducing CPU intervention and improving system
performance.
 Hold/HRQ
● Hold/HRQ (Hold Request) is a signal used by peripheral devices to request
temporary suspension of the CPU's activities.
● When asserted, it indicates to the CPU that the requesting device needs to
gain control of the system bus for a brief period.
● This allows the peripheral device to perform critical operations or access
system resources without interruption.
● The CPU responds to the Hold/HRQ signal by relinquishing control of the bus
and entering a hold state, during which it temporarily suspends execution of
instructions until the requesting device releases the bus.
● Once the hold condition is resolved, the CPU resumes normal operation.
● The Hold/HRQ signal is commonly used in systems employing DMA controllers
or other devices requiring direct access to memory or I/O devices.
 HLDA
● HLDA (Hold Acknowledge) is a signal generated by the CPU in response to a
Hold/HRQ (Hold Request) signal from a peripheral device.
● When the CPU receives a Hold/HRQ signal, it suspends its activities and
asserts the HLDA signal to acknowledge the hold request.
● This informs the requesting device that the CPU has entered a hold state and
has relinquished control of the system bus. While HLDA is asserted, the CPU
remains inactive until the peripheral device releases the hold request.
● Once the hold condition is resolved, the peripheral device releases the
Hold/HRQ signal, and the CPU deasserts the HLDA signal, allowing the CPU to
resume normal operation.
● The HLDA signal facilitates proper coordination between the CPU and
peripheral devices in systems where devices need temporary control of the
system bus.
 DACK
● DACK (DMA Acknowledge) is a signal used in DMA (Direct Memory Access)
systems to acknowledge the completion of a DMA transfer.
● When a DMA controller finishes transferring data between a peripheral
device and memory, it asserts the DACK signal.
● This indicates to the peripheral device that the data transfer has been
successfully completed.
● Upon receiving the DACK signal, the peripheral device can perform any
necessary post-transfer actions, such as updating status flags or releasing
resources.
● DACK is an essential part of the handshaking protocol between the DMA
controller and peripheral devices, ensuring proper coordination and
synchronization of data transfer operations.
 2.2

Modes of Transfer
 Interfacing DUMP 1
1. DREQ - I/O to DMAC
Modes:
2. HOLD/HRQ - DMAC to 8085
1. Single Transfer
3. HLDA - 8085 to DMAC 2. Cascade
3. Block Transfer
4. DACK - DMAC to I/O 4. Demand

DMA READ - 8085 to I/O data

DREQ0 - DREQ3: 0 has highest transfer
priority and 3 has lowest. DREQ
should be active till DACK is DMA WRITE - I/O to 8085 data
activated transfer

DACK0 - DACK3: Priority is

programmable. When RESET, they
equal active LOW
 Interfacing DUMP 2
ACTIVE CYCLE TRANSFER MODES

- SINGLE TRANSFER MODE

- CASCADE MODE

- BLOCK TRANSFER MODE

- DEMAND TRANSFER MODE

 Single Transfer Mode
- Once the DMAC becomes the bus master, it will transfer only ONE BYTE and
return the bus back to the microprocessor. As soon as the microprocessor
performs one bus cycle, DMAC will once again take the bus back from the
microprocessor.

- Both DMAC and microprocessor are constantly stealing bus cycles from each
other. It is the most popular method of DMA, because it keeps the
microprocessor active in the background.

- After a byte is transferred, the CAR and CWCR are adjusted accordingly. The
system bus is returned to the µP. For further bytes to be transferred, the DREQ
line must go active again, and then the entire operation is repeated.
 Cascade Mode
- This mode is used to cascade more than one 8237A together for simple
system expansion.

- The HRQ and HLDA signals from the additional 8237A are connected to the
DREQ and DACK signals of a channel of the initial 8237A.

- This allows the DMA requests of the additional device to propagate through
the priority network circuitry of the preceding device. The priority chain is
preserved and the new device must wait for its turn to acknowledge
requests.

- The Slave gives HRQ to the Master on the DREQ of the Master, and the Master
gives HRQ to the µP on the HOLD of the µP.
 Block Transfer Mode

- In this mode, the DMAC is programmed to transfer all the bytes in one
complete DMA operation. After a byte is transferred, the CAR and CWCR are
adjusted accordingly.

- The system bus is returned to the µP, only after all the bytes are transferred.
i.e. TC is reached or EOP signal is issued. It is the fastest form of DMA but
keeps the microprocessor inactive for a long time.

- The DREQ signal needs to be active only in the beginning for requesting the
DMA service initially. Thereafter DREQ can become low during the transfer.
 Demand Transfer Mode

- It is very similar to Block Transfer, except that the DREQ must active
throughout the DMA operation.

- If during the operation DREQ goes low, the DMA operation is stopped and the
busses are returned to the µP

- In the meantime, the µP can continue with its own operations. Once DREQ
goes high again, the DMA operation continues from where it had stopped.
 03
DMA
Programming
 Programming the 8237
To implement the DMA transfer, the 8237 should be initialized by writing into
various control registers discussed earlier in the DMA channels and interfacing
section. To initialize the 8237, the following steps are necessary :

1. Write a control word in the Mode register that selects the channel and specifies
the type of transfer (Read, Write, or Verify) and the DMA mode (block, single-byte,
etc.).

2. Write a control word in the Command register that specifies parameters such as
priority among four channels, DREQ and DACK active levels, and timing, and
enables the 8237.

3. Write the starting address of the data block to be transferred in the channel
Memory Address Register (MAR).

4. Write the count (the number of the bytes in the data block) in the channel Count
register.
Write initialization instructions for the DMA
controller in Figure to meet the following specs:

- Disable the DMA controller and begin

writing initialization instructions.

- Initialize Channel #3 (CH3) to transfer 1K of

bytes from the system memory to the
floppy disk assigned to CH3.

- The starting address of the data block is

4075H and subsequent data bytes have
memory addresses in increasing order.

- The Command parameters should be:

normal timing, fixed priority, late write.
DREQ and DACK are both active low.

- Set up the demand mode whereby the

DMA can complete the data transfer
without any interruption.
 The initialization to set up the DMA controller are as follows:

MVI A, 00000100 B //Command: disables the DMA

OUT 08H // Send to command register

MVI A, 00000111 B // Mode

OUT 0BH // Send to mode register

MVI A, 75H // Low order byte of starting address

OUT 06H // Output to CH3 Memory address reg (MAG)
MVI A, 40H // High order byte of starting address
OUT 06H // Output to CH3 Memory address reg (MAG)

MVI A, FFH // Low order byte of count 03FF H

OUT 07H // Output to CH3 count register
MVI A, FFH // Low order byte of count 03FF H
OUT 07H // Output to CH3 count register

MVI A, 10000000B //Command

OUT 08H // Send to command register

 04
DMA
Execution
What is DMA Execution
The process of data transfer from the peripheral to the system
memory under the DMA controller can be classified under two
modes:
1. slave mode
2. master mode

Slave Mode
In slave Mode , DMA controller is treated as peripheral using the following steps :-

1. The MPU selects the DMA controller through Chip Select.

2. The MPU writes the control words as illustrated in Example 15.8 in channel
registers and command/status registers by using control signals IOW and IOR.
In this mode, the output signals of the 8237, such as A7-A4, MEMW, and MEMR, are
in tri-state.
5.Next, the DMA as- serts ADSTB (Address Strobe) high that is connected to Latch
Enable (LE) of 373 Latch #1 and places the contents of the data bus, which is a
high-order byte of the starting address, on A15-Ag. At the same time, the DMA also
outputs the low order address A7-A on the low-order address bus.

6. When the entire address As-A, is available on the address bus, the DMA sends
DACK to the peripheral.

7. The DMA controller continues the data transfer by asserting the necessary
control signals (IOR, IOW, MEMR, or MEMW ) until DACK remains high.

8. At the end of the data transfer, the DMA asserts EOP (End of Process) signal low
that can be used to inform the peripheral that the data transfer is complete. The
DMA data transfer can also be terminated by sending a low signal to EOP from
outside.
 Master Mode
Master Mode After the initialization, the 8237 in master mode keeps checking for a
DMA request,
The steps in data transfer can be listed as follows:

1. When the peripheral is ready for data transfer, it sends a high signal to DRQ. 2.
When the DRQ has been received and the channel enabled, the control logic sets
HRQ (Hold Request) high. (HRQ is connected to the HOLD signal of the 8085.)

3. In the next cycle, the MPU relinquishes the buses and sends the HLDA (Hold
Acknowledge) signal to the 8237.

4. After receiving the HLDA signal, the DMA asserts AEN (Address Enable) signal high.
The high AEN signal disables 373 Latch #2, thus disconnecting the demultiplexed
bus A7-Ao of the MPU and enables 373 Latch #1 through an inverter.
Thank You !!