VERILOG SIMULATION ASSIGNMENT

Lohith Allu - EE23BTECH11004

May 7, 2024

Question-1: You have 2 input vectors, x and h, each of which is 8 elements

long, and each element is 4 bits long. Implement a code to convolve the two
signals, giving output y where y is 16 elements long, with each element being 4
bits long, just like the input. Ignore overflow.

y=x*h
Solution:
1. Module code

module conv (
input [3:0] x [7:0] ,
input [3:0] y [7:0] ,
output reg [7:0] z [15:0]
);
integer i ;
integer j ;
always @ (*) begin
// initialising all the z values to be xero
for ( i =0; i <16; i +=1)
x [ i ] = 0;
// doing convolution operation at the
starting phase ( z :0 to 7 terms )
for ( i =0; i <8; i +=1) begin
for ( j =0; j < i +1; j = j +1) begin
z [ i ]= z [ i ]+( x [ j ]* y [7+ j - i ]) ;
end
end
// doing convolution operation at the
ebding phase ( z : 8 to 15 terms )
for ( i =0; i <8; i = i +1) begin
for ( j =0; j < i +1; j = j +1)
z [15 - i ]= z [15 - i ]+( y [ j ]* x [7+ j - i ]) ;
end
end
endmodule

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2. Test bench code

module convtb ;
// Decalarations for two testcases
reg [3:0] x1 [7:0];
reg [3:0] y1 [7:0];
reg [3:0] x2 [7:0];
reg [3:0] y2 [7:0];
wire [7:0] z1 [15:0];
wire [7:0] z2 [15:0];
conv tc1 (
. x ( x1 ) ,
. y ( x2 ) ,
. z ( x3 )
);
conv tc2 (
. x ( x1 ) ,
. y ( x2 ) ,
. z ( x3 )
);
initial begin
integer i ;
integer j ;
$dumpfile ( " wavconv . vcd " ) ;
$dumpvars (0 , convtb ) ;

// testcase one :
for ( i =0; i <8; i = i +1) begin
x1 [ i ]= i ;
y1 [ i ]= i ;
end
// testcase two :
for ( j =0; j <8; j = j +1) begin
x2 [ j ]=5;
y2 [ j ]=8 - j ;
end
// Running simulation
#10;

// testcase one output

$display ( " First ␣ testcase " ) ;

for ( i =0; i <8; i = i +1)
$display ( " x1 [%0 d ]=%0 d , y1 [%0 d ]=%0 d " ,i , x1 [ i ] ,i ,
y1 [ i ]) ;
$display ( " output ␣ z1 " ) ;
for ( i =0; i <16; i = i +1)
$display ( " z1 [%0 d ]=%0 d " ,i , z1 [ i ]) ;

2
 #10;
// testcase 2 output
$display ( " Sec ␣ testcase : " ) ;
for ( i =0; i <8; i = i +1)
$display ( " x2 [%0 d ]=%0 d , y2 [%0 d ]=%0 d " ,i , x2 [ i ] ,i ,
y2 [ i ]) ;
$display ( " Output ␣ z2 " ) ;
for ( i =0; i <16; i +=1)
$display ( " z2 [%0 d ]=%0 d " ,i , z2 [ i ]) ;

$finish ;
end
endmodule

3. Approach:
- I declared two vectors of size 8 each with element having size of 4
bits.
- Before doing convolution operation I initialised all the values of z (i.e,
Convolution product) to be zero.
- Then I did convolution element wise (one by one element from each
vector) and divided them into two section. (For simplicity).
- Those two segments are divided as for the first and last 8 elements
of the product.
- In testbench code I made two testcases with testbench module name
as ”module convtb”.
4. Results
Question-3: Implement a Wallace Tree Multiplier of 8 bits. Take two
4-bit inputs and an 8-bit output to implement the multiplier.
Solution:
1. Module code

// full adder module

module fuad (
input a ,
input b ,
input c ,
output sum ,
output cout
);
assign sum = a ^ b ^ c ;
assign cout =( a & b ) |( a & c ) |( b & c ) ;

3
endmodule

// multiplier module
module mult (
input [3:0] a ,
input [3:0] b ,
output reg [7:0] product
);
reg p [0:3][0:3]; // declaring a initial
product variables as a 4*4 matrix
// From the given picture in latex you can
see that we used 11 sum and 11 carry
variables
wire [11:0] s ;
wire [11:0] c ;
// let ’ s use indexes x [ i ][ j ]
integer i ;
integer j ;
// calculating initial product values
always @ ( a or b ) begin
for ( i =0; i <3; i = i +1) begin
for ( j =0; j <3; j = j +1) begin
p [ i ][ j ] <= a [ j ]& b [ i ];
end
end
end
// adding upthe product values as a sets of
three ( stage -1)
fuad f1 ( p [0][1] , p [1][0] ,1 ’ b0 , s [0] , c [0]) ;
fuad f2 ( p [0][2] , p [1][1] , p [2][0] , s [1] , c [1]) ;
fuad f3 ( p [0][3] , p [1][2] , p [2][1] , s [2] , c [2]) ;
fuad f4 (1 ’ b0 , p [1][3] , p [2][2] , s [3] , c [3]) ;
fuad f5 ( s [1] , c [0] ,1 ’ b0 , s [4] , c [4]) ;
fuad f6 ( s [2] , c [1] , p [3][0] , s [5] , c [5]) ;
fuad f7 ( s [3] , c [2] , p [3][1] , s [6] , c [6]) ;
fuad f8 ( p [2][3] , c [3] , p [3][2] , s [7] , c [7]) ;
fuad f9 ( s [5] , c [4] ,1 ’ b0 , s [8] , c [8]) ;
fuad f10 ( s [6] , c [5] , c [8] , s [9] , c [9]) ;
fuad f11 ( c [9] , s [7] , c [6] , s [10] , c [10]) ;
fuad f12 ( c [10] , p [3][3] , c [7] , s [11] , c [11]) ;
// assign statements for the final
[7:0] product
assign product [0]= p [0][0];
assign product [1]= s [0];
assign product [2]= s [4];
assign product [3]= s [8];
assign product [4]= s [9];
assign product [5]= s [10];

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 assign product [6]= s [11];
assign product [7]= c [11];
endmodule

2. Test Bench

module multitb ;
reg [3:0] a , b ;
wire [7:0] product ;

// Instantiate the original module

mult m (
.a(a),
.b(b),
. product ( product )
);

// Three test cases

initial begin
// Creating a simulation file
$dumpfile ( " wave . vcd " ) ;
$dumpvars (0 , multitb ) ;
a = 4 ’ d13 ; b = 4 ’ d4 ; // 13 * 4 = 52
#10;
$display ( " Product ␣ is : ␣ % b " , product ) ;
a = 4 ’ d9 ; b = 4 ’ d12 ; // 9 * 12 = 108
#10;
$display ( " Product ␣ is : ␣ % b " , product ) ;
a = 4 ’ d7 ; b = 4 ’ d8 ; // 7 * 8 = 56
#10;
$display ( " Product ␣ is : ␣ % b " , product ) ;
$finish ;
end
endmodule

3. Explaination
- The Wallace tree multiplier I designed have only Full adders (or
we can keep both half adders accordingly).
- The first product is computed by performing AND operation
between the two binary number bit wise and then assigning to a
matrix.
- The final out put is assigned to the vector array product[7:0].
- The module code runs mainly in four stages, The first product
will have 4 rows.

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 - The first three tows sum is computed using full adders and results
in two rows results (Sum and carry), Now again the 4th row from
the first and above two rows (Sum and carry) again gets into full
adder to result in another two rows: Sum and carry
- This is the last step for computing, again doing a half adder
operation (or use a full adder by keeping the extra bit to be 0),
we get the final product result.
- At last assigning the resulting values to the main output is done
by using assign statement.
- Due to some error (I am not able to understand the exact error
where it is going to wrong to simulate.)
4. Reference image

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 7

Figure 1: Test case one(question-1)

 8

Figure 2: Test case two(question-1)

Figure 3: Calculation of variables(as a reference)