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Ee278 Assignment 1

The document discusses different numeric formats including single and half precision floating point and fixed point formats. It provides examples of decimal values represented in their binary formats in these different numeric systems. It also provides Verilog code for a 4-bit fixed point sequential multiplier and signed 4-bit fixed point sequential multiplier with test benches. Finally, it asks for the logic diagram of a signed 4-bit array multiplier and provides code for a 15-bit ripple carry adder with pipelining.

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31 views8 pages

Ee278 Assignment 1

The document discusses different numeric formats including single and half precision floating point and fixed point formats. It provides examples of decimal values represented in their binary formats in these different numeric systems. It also provides Verilog code for a 4-bit fixed point sequential multiplier and signed 4-bit fixed point sequential multiplier with test benches. Finally, it asks for the logic diagram of a signed 4-bit array multiplier and provides code for a 15-bit ripple carry adder with pipelining.

Uploaded by

pratikvyas1998
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EE278 Homework #1

1)
(1) single-precision IEEE floating-point (32 bits)

No Decimal Binary Mantissa Exponen Biase Representation


. t d Exp
1 0.25 0.01 00000000000000000000000 -2 125 0_01111101_00000000000000000000000
2 1.125 1.001 00100000000000000000000 0 127 0_01111111_00100000000000000000000
3 -2.5 10.1 01000000000000000000000 1 128 1_10000000_01000000000000000000000
4 7.25 111.01 11010000000000000000000 2 129 0_10000001_11010000000000000000000
5 0.00000001 0.0000000000000000000000000 01010111100110001110111 -27 100 0_01100100_01010111100110001110111
0101010111100110001110111
6 8075 1111110001011.0 11111000101100000000000 12 139 0_10001011_11111000101100000000000

(2) half-precision IEEE floating-point, (16 bits)

No Decimal Binary Mantissa Exponent Biased Exp Representation


.
1 0.25 0.01 0000000000 -2 13 0_01101_0000000000
2 1.125 1.001 0010000000 0 15 0_01111_0010000000
3 -2.5 10.1 0100000000 1 16 1_10000_0100000000
4 7.25 111.01 1101000000 2 17 0_10001_1101000000
5 0.00000001 0.0000000000000000000000000 0000000000 -27 -12 0_00000_0000000000
0101010111100110001110111
6 8075 1111110001011.0 1111100011 12 27 0_11011_1111100011

(3) 8-bit fixed-point

No. Decimal Binary 8-bit Fixed Point Signed


1 0.25 0.01 00000.010
2 1.125 1.001 00001.001
3 -2.5 10.1 11110.100
4 7.25 111.01 00111.010
5 0.00000001 0.0000000000000000000000000 Large number
0101010111100110001110111
6 8075 1111110001011.0 Large number

(4) 5-bit fixed-point

No. Decimal Binary 5-bit Fixed Point Signed


1 0.25 0.01 000.01
2 1.125 1.001 01.001
3 -2.5 10.1 110.10
4 7.25 111.01 0111.1
5 0.00000001 0.0000000000000000000000000 Large number
0101010111100110001110111
6 8075 1111110001011.0 Large number
Q2.

Corrected Verilog code for unsigned 4-bit fixed sequential multiplier.

Endmodule

Simulatio
Test Bench:
Q3.
Code for signed 4-bit fixed point sequential multiplier. for. -1 x -1 = 1;

Simulation Wavef
Test Bench:

timescale 1ns / 1ps


module tb();
reg clk;
reg St;
reg [3:0] Mplier;
reg [3:0] Mcand;
wire [8:0] Prod; //added
wire done;

mult4x4 m1(clk,St,Mplier,Mcand,Prod,done);

always #5 clk = ~clk;


initial begin
clk = 1;
#2
Mplier = 4'b1111;
Mcand = 4'b1111;
#1St = 1;
#5 St = 0;
#100;
#10 $finish;

end

initial begin
$monitor ("Result = %b",Prod);
$dumpfile("waves.vcd");
$dumpvars();
end
endmodule
Q4.
Logic Diagram for signed 4-bit fixed point Array Multiplier [eg. 1111 (-1) x 1111 (-1) = 0000_0001 (1) ]
Q5.

CODE:

module Adder(x, y, sum, clk);


parameter WIDTH = 15,
WIDTH1 = 7, //LSB
WIDTH2 = 8; //MSB
input [WIDTH-1:0] x, y;
input clk;
output [WIDTH-1:0] sum;
reg [WIDTH-1:0] sum;
reg [WIDTH1-1:0] I1, I2, r1, q1;
reg cr1, cq1;
reg [WIDTH2-1:0] I3, I4, q3, q4, U2;
//Pipeline stage 1
always @(*) begin
I1 = x[WIDTH1-1:0];
I2 = y[WIDTH1-1:0];
I3 = x[WIDTH-1:WIDTH1];
I4 = y[WIDTH-1:WIDTH1];
{cr1,r1} = I1 + I2;

end
//Pipeline registers
always @(posedge clk) begin
q1 <= r1;
cq1 <= cr1;
q3 <= I3;

q4 <= I4; end

//Pipeline stage 2
always @(*) begin
U2 = q3 + q4 + cq1;
sum = {U2,q1};
end
endmodule

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