Aeronautics Institute of Technology – ITA
Electronic Engineering Division – IEE
EA-268 Digital Signal Processors
Prof. Dr. Osamu Saotome
Teaching assistant: Canisio Barth
Laboratory 02P1
Last document update: March 22, 2024
1 Objectives
1.1 General Objectives
• Practice applying theoretical concepts covered in the Digital Signal Processors course (EA-268).
1.2 Specific Objectives
• This lab aims to introduce AMD/Xilinx Vivado tool by guiding through a basic hardware task:
blinking an LED, often considered the hardware equivalent of "Hello World!". The lab is based on
a tutorials by Digilent for Zedboard, accessible at Guides for Xilinx Tools.
2 Prerequisites
• Personal computer with a minimum of 8GB RAM (16GB recommended);
• VirtualBox software. Download and documentation available at the following link: VirtualBox;
• Ubuntu virtual machine (VM) on VirtualBox with Xilinx tools installed (version 2019.2 or later).
A clone of the VM will be provided. Use the following credentials:
– user: osboxes
– password: osboxes.org
• ZedBoard Development kit including required hardware accessories (power supply, JTAG cable).
Additional resources for the ZedBoard (files, documentation, schematics, tutorials, example projects)
can be found in the following link ZedBoard. Similar boards can also be used.
• Basic hardware description language (HDL) understanding. For a comprehensive set of tutorials
for beginners on HDL and FPGA, visit the site FPGA Tutorial. Examples in this lab will be in
Verilog, but they can easily be adapted to VHDL
Note: For an independent installation (without VirtualBox), one can follow the instructions pro-
vided at: Installing Vivado, Vitis, and Digilent Board Files.
3 Lab Development
3.1 Launch Vivado
1. Open the terminal application: Click on the "Terminator" icon on the Ubuntu sidebar. Al-
ternatively, you can use the regular terminal, but consider using Terminator as it offers additional
features that will be beneficial for future labs.
2. Change directory (cd) to the workspace folder:
1 cd / home / osboxes / Workspace /
Note: If you’re currently on the user’s home screen, simply type "cd Workspace". Use TAB key to
auto complete.
3. Create a folder for the lab and cd to it:
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1 mkdir Lab02P1
2 cd Lab02P1
4. Source the settings for the AMD/Xilinx tools:
1 source < install_path >/ Vivado / < version >/ settings64 . sh
Tip: The installation path for the VM is /tools/Xilinx/. Additionally, an alias command has
been set up for this lab as a shortcut. Simply type "xilinx" on the terminal and the shortcut will
handle all the necessary tasks.
5. Launch Vivado with the following command:
1 vivado
The Vivado initial screen should now appear.
3.2 Create Vivado Project
On the Vivado welcome screen, you’ll see:
• Create Project: Starts a wizard to create a Vivado project from scratch.
• Open Project: Allows opening a pre-existing Vivado project (XPR file).
• Open Hardware Manager: Programs an FPGA board without opening a project.
Note: There are other options available, but they’re not discussed in this lab.
1. To continue, click on Create Project. The first page of the New Project wizard summarizes the
steps involved in creating a project. Click Next. The page for selecting project name and location
should appear.
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2. Specify a name for the project. Vivado will utilize this name to structure its folders.
Note: Avoid spaces in the project name or location path as this may lead to issues with Vivado.
Instead, utilize an underscore, a dash, or CamelCase.
3. Keep the project location unchanged and select the "Create project subdirectory" option, this will
add another level to the folder structure, useful for the exercises section. Proceed by clicking Next.
4. At the "Project Type" screen, choose RTL Project and check the "Do not specify sources at this
time" box. Click Next to continue.
Next, youl’ll need to choose a part or board for the project to target in the next screen. The
implemented project will only function with the selected device, although you can modify this
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choice later through the project’s settings. Opting for a board rather than a part is advisable
because board files offer additional configuration details for various peripherals and components
within a design.
5. Click on the Boards tab and locate the ZedBoard Zynq Evaluation and Development Kit
from the provided list. Click Next to proceed to the last step.
Note: If the desired board doesn’t appear in the list, it’s likely that Digilent’s board files haven’t
been installed. Refer to the instructions for Installing Vivado, Vitis, and Digilent Board Files for
guidance on installing these necessary files.
6. The final screen of the "New Project" wizard provides a summary of your selections made in the
previous steps. Click Finish to open your project.
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3.3 The Flow Navigator
The Flow Navigator is the most important pane of
the main Vivado window to know. It is how a user
navigates between different tools within Vivado. The
Navigator is broken into seven sections:
• Project Manager: Access project settings,
add new source files, view snippets of useful
RTL code, and add components of a hardware
design (IP) included within the tool to your
own design.
• IP Integrator: Create a hardware design
through the use of a Block Design by connect-
ing IP blocks together.
• Simulation: Debug and verify a hardware de-
sign fully within software, without deploying it
to hardware.
• RTL Analysis: See how the tools are inter-
preting a design by viewing the circuit that the
design describes.
• Synthesis: Modify Synthesis settings and
view post-synthesis reports - determine
whether the design meets timing, and how
much of the chip resources it will use.
• Implementation: Modify Implementation
settings and view post-implementation reports
- determine whether the design meets timing,
and how much of the chip resources it will use.
• Program and Debug: Access to settings for
bitstream generation and the Hardware Man-
ager. Used to build a design and deploy it to a
board.
3.4 The Project Manager
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This tool serves as the primary environment for development and is the first one you’ll encounter upon
creating a new project. The Project Manager comprises four main panes: Sources, Properties, Results,
and Workspace.
• Sources Pane: The primary organizer for the project hierarchy, facilitating file opening. It main-
tains a structured folder system:
– HDL files reside in the Design Sources folder.
– Constraints are housed within the Constraints folder.
– Simulation files are found in the Simulation Sources folder. Files are opened by double-clicking
entries, and new sources can be added by right-clicking folders or using the Add Sources button.
• Properties Pane: Displays and enables editing of file properties. This pane becomes visible when
a file is selected in the Sources pane.
• Bottom Pane (Unnamed): Hosts several useful tools for project debugging:
– Messages Tool: Parses Tcl console for errors, warnings, and important information.
– Tabs: Allow access to different tools:
∗ Tcl Console: Enables direct command execution.
∗ Reports Tool: Facilitates navigation through Vivado-generated reports, including power,
timing, and utilization reports.
∗ Log: Displays outputs from Synthesis, Implementation, and Simulation runs.
∗ Design Runs: Allows editing of run settings and creation of new runs, particularly useful
for targeting multiple devices with the same design.
• Workspace Pane: The central workspace for editing and viewing:
– Opens reports and HDL/constraints files.
– Initially displays the Project Summary, offering basic information from reports.
3.5 Adding Constraint File
Constraint files specify the design requirements imposed by the components surrounding an FPGA, such
as peripherals, external clocks, and more. To map the ports in an RTL top module (discussed later) to
the physical pins of the FPGA, a constraint file must be added or created. Digilent offers Xilinx Design
Constraint (XDC) files for each board. The XDC file for the ZedBoard can be found within the VM’s
Workspace directory. Alternatively, you can download it from: ZedBoard Master XDC.
1. In the Project Manager section of the Flow Navigator, click the button or use Alt+A shortcut.
In the wizard that pops up, select "Add or create constraints" then click Next.
2. At this point, Vivado shows a list of all the constraint files that will be added or made when we
finish. Right now, the list is empty, but it will fill up once we add or create files. We won’t be
making a constraint file from scratch in this guide, so click on Add Files instead.
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3. Locate the file "Zedboard-Master.xdc" in the workspace using the file navigator. Once clicked, the
name of the file will be added to the "File Name" field. Click the OK button to proceed.
4. Make sure that the selected XDC file has been added to the list of sources, and that the "Copy
constraint files into project" is checked, then click Finish.
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5. Locate the XDC constraints file in the "Sources" section of the project, then double-click to view
its contents. This file maps your design signal names to FPGA pins. For the system clock, we’ll
use GCLK, and for the indicator LED[0], we’ll use LD0. In this example, lines 82, 83, and 176 are
of interest. These lines correspond to the clock and LED[0] for the ZedBoard. Remove the leading
# character to uncomment these lines, ensuring that the get_ports names are [get_ports GCLK]
for the clock and [get_ports LD0] for LED[0].
6. If line 83 is missing add it to the XDC file as shown in the image. The create_clock constraint
informs Vivado about the port and frequency (or period) of a clock signal entering the FPGA.
3.6 Create Verilog Source File
Verilog is one of several hardware description languages (HDLs) that can be used within Vivado to
describe a circuit to be implemented within an FPGA. This section describes how to create a Verilog file
within Vivado, and create a simple circuit that will work on any Digilent FPGA development board.
1. In the "Project Manager" section of the "Flow Navigator", click the button again. Select "Add
or create design sources" then click Next.
2. Click on the button to add files, then select "Create File...". You’ll be asked to choose
the "File type," "File name," and "File location." Ensure you select Verilog for the type and
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"<Local to project>" for the location. Name your file with an extension ".v" and avoid using
spaces. Instead, use underscores, dashes, or CamelCase. Click OK to proceed.
3. Make sure that the new Verilog source file has been added to the list of sources, then click Finish
4. At this stage, a "Define Module" dialog will appear.
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5. You need to define the clock (GCLK) and LED (LD0) ports for the Verilog module. Clicking the
"Add" button will create an empty slot for a port in the "I/O Port Definitions" list.
There are five fields to define for each of the module’s I/O ports:
• Port Name: This field defines the name of the port and needs to match one of the names
you used in your XDC file.
• Direction: This drop-down menu can be set to input, output, or inout, defining the direction
that signals propagate through this port, with respect to your module. Outputs are the signals
that your module will be controlling.
• Bus: This can be checked or not, when checked, this port consists of multiple single-bit signals,
grouped into a single bus.
• MSB: The index of the most significant bit of the port, if it is a bus. This option is grayed
out for single-bit ports.
• LSB: The index of the least significant bit of the port, if it is a bus. This option is grayed out
for single-bit ports.
6. Add a single-bit input port with the same name as the clock port uncommented in your XDC file.
Similarly, include a single-bit output port with the same name as the LED port uncommented in
your XDC file. Click OK to continue.
Once added, the new source file will appear in the "Design Sources" folder within the "Sources"
pane. Double-click on it to open. Next, write Verilog code to define the design behavior.
7. Between the ");" that comes after the module’s port list and the "endmodule" statement, add the
following lines of code:
1 parameter NUM_3Hz = 16666667; // (100 MHz /3)*0.5
2 reg [31:0] count_3Hz = 0; // used to count clock cycles
3 reg t_3Hz = 0; // aux signal to toggle
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5 always @ ( posedge GCLK )
6 begin
7 count_3Hz <= count_3Hz + 1;
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8 if ( count_3Hz == NUM_3Hz )
9 begin
10 t_3Hz <= ~ t_3Hz ;
11 count_3Hz <= 0;
12 end
13 end // end always
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15 assign LD0 = t_3Hz ; // continuous assignment
This code snippet implements a counter that increments by 1 every clock cycle and tests the counter
against the parameter for the desired blinking frequency. When the counter reaches the specified
parameter, the signal driving the LED output toggles and the counter is reset. With the 100MHz
clock of the ZedBoard, the LED blinks (completes one cycle of low-to-high-to-low transitions)
approximately three times per second.
3.7 Generate a Bitstream
To program the target board, each stage of the compilation pipeline must be executed.
1. Synthesis: To run Synthesis, click in the Run Synthesis button the Flow Navigator. The
"Launch Runs" dialog will appear. Keep the default settings unchanged and click OK to proceed.
Synthesis generates logic gate descriptions and establishes connections between them based on the
functionality outlined in the HDL files and the constraints specified in XDC files. The output of
Synthesis is then passed to Implementation.
Note: The status of the task is displayed in the top-right corner of the Vivado environment.
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Once finished, the "Synthesis Completed" dialog will appear. Since the process has been successfully
completed, implementation can be initiated directly. For the purpose of this lab, we will click on
Cancel and proceed to run implementation from the "Flow Navigator.
2. Implementation: Implementation comprises several steps, including Opt Design (optimizing the
design to fit on the target FPGA), Place Design (laying out the design in the target FPGA fab-
ric), and Route Design (routing signals through the fabric). To initiate Implementation, click
Run Implementation in the Flow Navigator. The output from Implementation is then for-
warded to the Bitstream Generator. After completion, close the "Implementation Completed"
dialog and return to the project’s main area.
3. Bitstream Generation: The Bitstream Generator produces the final output file required for
programming the FPGA. To initiate Bitstream Generation, click on Generate Bitstream in
the Flow Navigator. By default, the generator will create a ".bit" file without any settings changed.
Note: Building the project can take 5 to 60 minutes, depending on design complexity, board, and
computer processing power. After completion, a pop-up dialog appears, offering options. Click
Cancel as they’re not explored this lab. Look for the write_bitstream complete status message
in the top-right corner, indicating readiness for board deployment.
3.8 Programming an FPGA Board through Vivado’s Hardware Manager
The project’s bitstream is transferred to the board through Vivado’s Hardware Manager using the
ZedBoard’s JTAG interface. Follow these steps to program your design:
1. Ensure that the ZedBoard is powered on, and connect the micro USB end of the cable to the
"PROG" connector, located adjacent to the power adapter barrel connector. Be cautious not to
confuse it with the UART or USB OTG connectors. Additionally, ensure that the USB end of the
cable is securely plugged into the computer. For VM users, verify that the "Digilent USB Device"
is selected from the "Devices > USB" dropdown menu in VirtualBox.
2. Click Open Hardware Manager at the bottom of the Flow Navigator pane on the left side of
the Vivado window.
3. Click on the Open target link located in the green banner near the top of the window or at the
bottom of the "Flow Navigator". Select the Auto Connect option from the popup menu.
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4. Make sure that the "Hardware" tab of the manager indicates the Digilent target as "Open" on the
"Status" column. Note that the ZedBoard JTAG tree contains both the FPGA (PL) device and the
Arm processor (PS) and that the FPGA is "Not programmed".
5. Click on the Program device link located in the green banner near the top of the window or at the
bottom of the "Flow Navigator". The "Program Device" dialog should appear with the "Bitstream
file" field already populated (if not, use the dots icon to finde the bit file. The default location for
the bit file is: <Project Directory>/<Project Name>.runs/impl_1/
Note: Leave the "Debug probe" field blank. This feature is not covered in this lab.
6. Finally, click Program to program the board.
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7. Verify that the device was successfully programmed by checking the "DONE" blue LED below
the ZedBoard logo on the board silkscreen. Additionally, the "LD0," located above the rightmost
dipswitch, should begin blinking immediately.
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4 Exercises
1. Change the Verilog code and constraints file to include two additional LEDs: one blinking at
approximately 2 Hz and the other at 1 Hz.
Note: You can use the "save as" option on Vivado to create a new project from the current one.
2. Modify the previous design to include two dip switches as inputs. Implement the following logic for
the dip switch combinations:
• 00: All LEDs turned off.
• 01: Only LED[0] blinking at 1 Hz.
• 10: Only LED[1] blinking at 2 Hz.
• 11: Only LED[2] blinking at 3 Hz.
3. Modify your design such that there’s only one LED. The LED blinking frequency should be driven
according to the dip switch combination:
• 00: LED[0] turned off.
• 01: LED[0] blinking at 1 Hz.
• 10: LED[0] blinking at 2 Hz.
• 11: LED[0] blinking at 3 Hz.
4. Explain your source code and demonstrate the working design during the next laboratory section.
Note: Feel free to create new designs exploring what you’ve just learned using Vivado and ZedBoard
resources.
5 Grading
The lab grading will be based on the report containing the results of the lab development and responses
to the exercises section.
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