My Interviews experience

1. Texas Instruments
It came to our college for 3 profiles
1. Digital
2. Analog
3. ATD (Software and Automation engineer) - Requires both coding + VLSI basics
Written exam is 2hrs and extra 40min for ATD profile.
Most of the Digital questions were asked from Gate basics and some from Digi_QS.pdf directly.
Analog questions were purely from gate syllabus. Network analysis, OPAMP, BJT and MOS basic
numerical questions were asked.
For ATD profile the written exam was full of C, C++ and python codes (MCQs only).
I cleared Analog and ATD exams
Analog interview: This was my 1st core interview. I know TI interviews are tough and yes, he
screwed my basics. No self-introduction at all.
Gave integrator circuit using OPAMP and asked to draw the output for step input.
Then he gave some input current to it and asked at steady state what happens to that current?
By using only that circuit, he asked multiple questions like node voltages, peak voltage, steady
state voltage and currents and finally he trapped me into KCL violation because of virtual short.
I was clean bowled and interview was over in 20min.
OBVIOUSLY REJECTED☹
ATD interview:
Choose your comfortable programming language. I said C.
1. Open any C compiler and write Fibonacci series code.
2. What is Recursion?
3. Write this same Fibonacci series code using recursion. I got some errors. Another face
palm moment. He said its ok; let’s go to some questions related to VLSI.
4. Implement logic gates using 2*1 MUX. He doesn’t want any 0 or 1 as one of the inputs.
5. Shown a stick diagram and asked to write Boolean expression
6. CMOS inverter DC characteristics, regions or operations of both Transistors, Voltages at
all the 5 regions.
REJECTED☹
But got to know 2nd round was full of coding for 1hr.
At least, some of my best friends got placed in it. So, felt it’s not impossible for me for next
companies Be optimistic
Tips to crack this: -
RC circuits without using Laplace, Basics of CMOS in depth, should be able to correlate both
PMOS and NMOS short channel effects, Delay and Power topics in CMOS, Analog from gate
basics to Analog IC current mirror circuits. They don’t want mathematics behind any question.
They only want the intuitive explanation using physics. They try to give you some hints and
observe your approach to the problem. Make use of it. No puzzles and coding were asked for
Analog and Digital profiles. Coding was asked only for ATD profile.
2. Qualcomm
Came for two profiles
1. Hardware
2. Software
I applied only for Hardware. C, Data Structures, Network analysis, Digital questions was a bit
lengthy to solve in the stipulated time. I was unable to clear the written test
As per my seniors’ experience, Qualcomm gives preference to CGPA and expects to know basics
in almost all subjects including Computer Architecture, Data Structures, Operating Systems. In
general people leave the above-mentioned topics. But questions from these topics will come in
written test if not in interview.
Anyways, none of my close friends got selected. So again, no much worries Again optimistic.
REJECTED ☹
3. Micron
I applied for the role of Memory Circuit Design Verification Engineer.
Written test has Aptitude, C, Python, and Digital. This exam was comparatively easier than
Qualcomm exam. But I am unable to clear this
Anyways, one of my best friends got selected. So again, I felt it’s not impossible for me for next
companies . But deep inside the mind, already 3 companies came and left
REJECTED☹
Since it’s a memory-based company, be good with memory designs from basic latch to recent
NAND Flash.
4. Synopsys
It came for 3 roles.
1. ASIC Digital Design
2. Memory Circuit Design
3. I/O Circuit and Layout Design
Written test was comparatively easy of all. Synopsys considers every academic performance of
candidate right from 10th, Inter, Engineering, and M. Tech. It gives weightage to written test
also along with interview. I was interviewed by two people separately, each for 1hr.
Interview 1:
• He gave a brief introduction about what his team is doing, what he is expecting and an
talked briefly about the company.
• Asked to introduce myself.
 1. Digital or Analog? You are good in…? Why not analog?
2. Draw a digital circuit to detect number of 1’s and 0’s in a given sequence
3. Draw an Integrator circuit using digital electronics using gates, flip flops and etc but not
using R, C, Opamp.
4. Draw high pass and low pass filters using digital electronics.
5. What are the types of FSMs and their differences?
6. One hot encoding and uses.
7. Latch up problem and how to minimize.
8. Given a negative number and write its 2’s complement, 1’s complement and signed
binary. Explain the differences.
9. Glitches and how to minimize.
10. Types of Power dissipation in MOSFET and how to minimize.
Except 3, 4 questions, I told all the questions.
Interview 2:
1. Self intro
2. 25 horses’ geeks for geeks puzzle
3. What is an LFSR?
4. EXOR using NAND
5. 3000 bananas and 1 camel geeks for geeks puzzle
6. What happens to final profit or loss percentage after +10% profit and -20% loss
consecutive selling?
7. Multiplier circuit using shift register
8. Hazards and how to eliminate?
9. Projects related questions
10. Difference between synchronous and asynchronous reset?
I answered all the questions. Better than 1st interview. When asked about feedback, he said to
improve my shift register concepts.
REJECTED☹
Anyways many of my friends got placed. Competition got reduced so much . But deep inside,
already 4 companies gone Slowly transforming from optimistic to pessimistic
Tips to crack this:
Be perfect with Digi_QS.pdf, your resume and at least 100 geeks for geeks puzzles. Since it’s a
tool-based company, be good with the tools you have used in lab like Cadance and etc.
CGPA also matters a lot. But only if you clear the written test (For any company).
5. Samsung:
1. Software profile
2. Hardware profile
I applied for HW profile. Written test has C, Aptitude, Digital and other gate basics. Most of the
questions were repeated from old gate questions and old Samsung papers. I was unable to
clear it. Most of us wrote well. Maybe it was gone with very less margin.
REJECTED 😊
Anyways, it took very very few.
6. Western Digital:
1. System Design Engineer.
Written test has C, Aptitude, Digital and other gate basics. No proctoring for this exam which
was an irony. Most of the questions were repeated from old gate questions and old WD papers.
I was unable to clear it. Most of us wrote well. Maybe it was gone with very less margin.
REJECTED 😊
Anyways, it took very very few.
Tips to crack this:
Be perfect with Digi_QS.pdf, your resume and at least 100 geeks for geeks puzzles.
They asked mostly Analog IC (Till current mirror in Razavi book) related questions to one of my
friends who got selected. Cadence Virtuso knowledge is an added advantage.
Since it’s a memory-based company, be good with memory designs from basic latch to recent
NAND Flash.
Inner me: If a company is taking more students, okay competition decreased. If a company is
taking less students, common they have no requirement…. Arre bhai…what are the companies
left ??? ☹ ☹☹ Pessimism at peaks
7. NXP semiconductors:
A minimum CGPA criterion for applying is 8.5. Mine was 8.45 by that time. Karma is a
So straight away REJECTION☹
Practice more and more previous year written question papers(for all companies). Most of the
questions/models will repeat. Don’t take written test for granted. If it’s online semester then
some students will score full in written test. So, make your plan accordingly. Out of 10 written
tests, I cleared only 4 and 1 not even qualified to write due to 0.05 CGPA difference.
By this time, I clearly understood that handling pressure is a part of interview preparation
and failures(temporary) are common even though you are in top colleges.
8. MEDIATEK:
Came for 2 profiles
1. Digital Communication Engineer
2. Physical Design Engineer
As a VLSI student, I applied for PD role. The company came with only 2 vacancies in PD. Written
test was separate for VLSI and Communication profiles. Aptitude was a bit difficult compared to
all the company exams. Digital, C were good. Some gate basics were asked. All are MCQs.
I topped the written exam. But my interview was scheduled next day. On the 1st day, 2 students
got selected. As they said they came for only 2 vacancies, I thought my interview won’t be there
and again same dialogues started running in my mind
Anyways many of my friends got placed. Competition got reduced so much ☺. But deep inside,
already 4 companies gone  Anyways, it took very very few 
But, it’s not this time . Next day, my interview went more than 90mins.
He asked, what do you know about MediaTek? And started a ppt about the company for 5min.
1. Using 3 liters and 5 liters cups make 4 liters. You have unlimited source of water.
2. 3 lights and 3 switches puzzle from geeks for geeks
3. Ant crawling a wall, +3 m and -2 m for every 1hr. 30 meters can be covered in….?
4. D latch using 2*1 mux
5. Simplify (A+B) (A+C) without using pen and paper. Similarly, (A+B) (A+C) (A+D)
6. D ff using JK
7. What is a buffer and why it’s used?
8. CMOS vs TTL
9. 1, 2, 3, 4---------> to a digital circuit----------> 1, 4, 9, 16. Find the circuit?
10. Poisonous gas detection digital circuit or logic
11. My family backgrounds
12. Blocking vs non-blocking
13. Power dissipation in VLSI circuits and it’s types
14. Glitch?
15. Project related questions from BTech projects to mini projects in MTech
16. Latch vs FF
17. Setup and hold time definitions
18. Scooter having 3 tires & 1 extra tire. Each tire max dis is 20m. Max distance using all 4?
19. Inverter and Buffer using XOR.
Finally, he said any questions from my side?
I asked, in general a company announces shortlists before they are leaving the college. But you
announced yesterday itself. So, I was little de-motivated. Today also you will be taking if we did
well?
He laughed and said it’s the college T&P policy to give the shortlists by EOD. Don’t worry about
that. I asked about my feedback since I answered all the questions. He said my core is good but
improve communication skills a little.
☺SELECTED ☺
Tips to crack this: Geeks for Geeks puzzles, projects in resume, Digi_qs.pdf and gate basics.
 **** Sources that can be followed ****
1. Puzzles: - Go through at least first 100 geeks for geeks puzzles (1st 40 compulsory). Better
to write in notes. But there are lot more puzzles (nearly 300) in this website. So, you may
get bored at some point of time. Hence, better to follow YouTube channels which have
some of the puzzles from geeks for geeks. One more important thing is new puzzles get
added to the website. So be updated yourselves.
https://www.youtube.com/c/SimplyLogical
https://www.youtube.com/channel/UCTRxnMudmOGNw0g4gZf5D8g
Complete all the puzzles in these channels.
Tip: The interviewer only tests your approach. He doesn’t require the exact complete
solution. In Texas Instruments interview, they usually won’t ask puzzles. Remaining all
companies ask puzzles. I personally studied all the puzzles from above links thinking if at all I
am not able compete other students in core skills, at least in analytical skills I should give
them competition and it helped me too in the interview because I answered all the puzzles.
I personally kept separate short notes for puzzles and wrote question + answer with
different colors, just to get interest while revising.

2. Digital Electronics :-
DIGIQS is must. Be clear with all the concepts in it.
https://drive.google.com/file/d/1C2q7A4Je3vg0pFOHwDRhi6qyA4XK4iGm/view?usp=sharing
Apart from that follow the given references for better understanding
Follow your gate notes
FSMs: https://www.youtube.com/watch?v=k8xxGSkJUhY&feature=youtu.be
https://www.youtube.com/watch?v=p8RkjU-zPGY
Moore and Mealy: Gate Smashers and Neso Academy
Fequency Dividers by Durga ganesh: https://www.youtube.com/watch?v=NG9NVYSp9wo
Carry look ahead adder: https://www.youtube.com/watch?v=EmJA-eEy-b0
Carry skip adder, Carry save adder, Carry select adder
https://www.youtube.com/channel/UC4Oie3QV4OSodf4-W4kEeRA
Synchronizers and Metastability concepts:
https://www.youtube.com/watch?v=Fy9wOF2M-oE and
https://www.youtube.com/watch?v=TRH89_Hw988
https://www.edn.com/synchronizer-techniques-for-multi-clock-domain-socs-fpgas/
Static Timing Analysis – VLSI Expert must and Udemy STA course if interested. Below is
the basic setup and hold explanation by intel.
https://www.edn.com/understanding-the-basics-of-setup-and-hold-time/
Be clear with Setup, hold for transistor level and between flip-flops. Time borrowing and
Time stealing concepts from vlsiuniverse and physicaldesign4u websites.
https://vlsiuniverse.blogspot.com/2013/06/setup-and-hold-basics-of-timing-analysis.html
 https://www.youtube.com/watch?v=0oP9D5xSZJc&list=PLkeXCxa9wnKkrAWJOWmvSmGMjeNYuNH
RQ
https://www.youtube.com/watch?v=mrY0MzCBgAo&feature=youtu.be
Multiple Cycle paths:https://www.edn.com/design/integrated-circuit-design/4433229/Basics-of-
multi-cycle---false-paths
Time Borrowing:http://www.vlsi-expert.com/2011/03/static-timing-analysis-sta-basic-part2.html
Clock Domain Crossing: I)https://www.youtube.com/watch?v=oIpgjiZHOvQ&t=1071s
II)https://www.youtube.com/watch?v=a_RL56y8Fpo
Maximum clock Frequency:http://www.vlsi-expert.com/2012/09/maximum-clock-frequency-
static-timing.html
EDGE DETECTING Circuits (Imp): https://www.cypress.com/file/133046/download
Clock gating:https://vlsiuniverse.blogspot.com/2016/10/integrated-clock-gating-cell.html
Follow TeamVLSI, Back2basics, Technical Bytes, KarthikVippala, YashJain. These
channels are gifted sources for VLSI concepts.
FIFO:
https://drive.google.com/file/d/16pDlzDJMrW7AZYZ-9snzrOiYHfsuYpCn/view?usp=sharing
https://www.youtube.com/watch?v=mMB2K40eF60&feature=youtu.be
Memories, PLA, PAL, SRAM, DRAM:
https://www.youtube.com/watch?v=r787m_IaR1I&feature=youtu.be
https://www.youtube.com/watch?v=U6i8Xmi0Y20
ADC & DAC convertors: from GATE materials
Definitely you will have confusion when you follow many sources. So discuss with your
friends. MTech requires group study. Developing various intuitions is possible only by
group study.

3. Verilog :- Beginners, 1st give your 100% efforts in Verilog

lab(https://www.youtube.com/playlist?list=PL3Soy1ohxlP1TLpcbYXYcVWItRy_XrUk8). Be clear
with those lab programs. Read Samir Palnitkar text book (Enough for understanding
concepts). It is very easily understandable. Do examples from Ciletti text book. Reading
concepts from Ciletti text book takes more time. So, plan accordingly. FSMs, FIFO, Shift
Registers Verilog codes.
For practicing https://hdlbits.01xz.net/wiki/Main_Page
MIT explanation of Mealy and Moore using Verilog
https://drive.google.com/file/d/1q1wrWovJnGR6LLWBdxxYertKHEVnNiOP/view?usp=sharing
Check YouTube videos also for FSM using Verilog. Try to write code yourselves and execute
for practice.
Verilog FAQs pdf
https://drive.google.com/file/d/1bdFMg2WleGqkVL5YrJp4_nQ0uUQkHwfO/view?usp=sharing
http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf
4. Aptitude :- Don’t start from scratch. It eats time. It’s comparatively easy for people who
wrote competitive exams like IES, RRB, SSC, Banks etc. Remaining guys, 1st start with
Indiabix questions & note down your difficult topics. Complete those difficult topics from
Dinesh Miglani & Arun Sharma quantitative aptitude for CAT is directly available in net.
(Level 1 & 2 enough. Don’t keep more time on level 2 also).
Rakesh Yadav playlists also help. But follow them only on topics you are facing difficulty.

5. Analog and RC circuits: - Gate level analog is absolutely fine. Majority of placements are
for digital profiles only. But if you are really interested in analog domain, then go through
the following links. https://www.youtube.com/c/ALLABOUTELECTRONICS
https://www.youtube.com/playlist?list=PL3Soy1ohxlP1PtC70B4qL0KcHYg3oYiCJ -analog basics
https://www.youtube.com/channel/UCbASDVRKAJByMa5rz6Uv_lw for RC circuits
1st order RC circuits (from video number:114) by Nagendra
Krishnapura:https://www.youtube.com/playlist?list=PLa4KQhDlGd7QCTX3gTz0LyoL93jVjtaMe
RC circuits question is must for any Analog profile job roles.
I suggest completing digital first, and then starting these is safe side because the probability
of getting placed in analog domain is less.
Small signal analysis –Input output resistances & gain calculation, clippers clampers, Diodes,
current mirrors, oscillators, Diff amplifier,555 timers are most important focus more on
MOSFET rather than BJT topics and you can get the best basics of all these from Razavi
videos which can make us feel analog is not that difficult:
RAZAVI MOSFET Videos:
https://www.youtube.com/playlist?list=PLshFxj_Xbz5O_eBue_vJR1NbITiTluKAx
13 videos try to make a note for all the contents in these videos.
https://www.youtube.com/watch?v=2i2PMtRDvE8&list=PLuv3GM6-
gsE0ix0s_d6JNIQXePzXr3_GZ&index=1 ---Purely based on your interest and if you have time

6. C, OOPS, DS: - Programming skills are tested in majority of the interviews. Invest good
amount of time but give preference and time to core subjects only. Geeks for Geeks mcqs
are must. Some questions will come directly from it. C in Depth by Deepali Srivatsav is one
of the best books for C language as a beginner. Ignore every remaining book. Learn OOPS
concepts and how to write an example program using them. Data Structures includes
searching and sorting techniques, Linked lists and tree structures. Have idea on why they
are used and their syntax. In written test, answering these questions gives edge because
very few people will learn these. Be ready with the coding part of linear and binary search,
bubble, selection, insertion sort techniques. If you feel coding is difficult for Quick sort,
merge sort and heap sort, then be perfect to explain the algorithm in normal manner.
https://www.youtube.com/watch?v=1Q4I63-hKcY
 https://www.youtube.com/user/mycodeschool
https://www.youtube.com/playlist?list=PLqM7alHXFySHrGIxeBOo4-mKO4H8j2knW
https://www.youtube.com/c/SundeepSaradhi for oops

7. CMOS VLSI: - Weste textbook 1,2,4,5,6,9,10 Chapters are very important and invest
maximum amount of time. Initially it takes time to understand concepts. So parallelly start
watching IIT Madras Janakiraman videos.
https://www.youtube.com/playlist?list=PL3pGy4HtqwD1X9CXdgXMTVGjb7rYd-qr6
Every student from all branches, who want placement in VLSI domain will complete this
playlist. So, try to gain as much as you can from this.
Below are few more basic add ons.
https://www.youtube.com/watch?v=fqiYu6IOtmU
https://www.youtube.com/watch?v=_aF_HpUnGJM&feature=youtu.be
After completing these, there is an openly available pdf in internet from Prof Ajit Pal IIT KGP
which has VLSI Q/A.
https://drive.google.com/file/d/1UW1xRhnHW8jw-M5fnYT5OeX38IThfH--/view?usp=sharing
Most of the students go through this. Some advanced concepts are covered by him
including Low Power VLSI concepts.
To understand some questions his playlist helps you.
https://www.youtube.com/playlist?list=PLTEh-62_zAfHmJE-pcjgREKiKyPSgjkxj
But watch this only if time permits or if you keep Low Power VLSI in your areas of interest.
He covers some of the topics which were and weren’t covered by Janakiraman.
2nd order effects in MOSFET: https://www.youtube.com/playlist?list=PLB38923D3B3EA8EFE
GIDL,DIBL, Short channel effect, Narrow width effect, Punch through voltage, Hot carrier
induced effect, Velocity saturation, Stack Effect, Tristate Buffer, CMOS delay concept
(elmore model), Logic realization using CMOS transmission gates (ex: design full adder using
CMOS transmission gate), Transistor sizing, Static and Dynamic power dissipation, Voltage
Domain concept and level convertors, High and low Vth cells their advantages and
disadvantages, PVT CONCEPT http://www.signoffsemi.com/pvt-rc-variation-ocv/
Latch up Condition and how to avoid or reduce it
https://vlsiuniverse.blogspot.com/2013/03/latchup-condition-in-cmos-devices.html
https://www.youtube.com/watch?v=pkQRd7DqJfA&t=77s
If time permits, enroll in Janakiraman Digital CMOS NPTEL course or else at least try to solve
those assignment questions (Not compulsory but it helps in gaining in depth knowledge)
Jan M. Rabaey lectures needs more time and patience. But follow them along with his
textbook. These are best of its kind and foundation to all the above sources. Very few
follows these because of time constraint and high level of approach.
https://www.youtube.com/playlist?list=PLOTpKcFOwiQSP6tqPjR7xXylPXTpiIOGD
 https://booksonweb.files.wordpress.com/2011/11/digital-integrated-circuits-a-design-perspective-
by-jan-m-rabaey.pdf

8. Analog IC :- Razavi electronics-1 lectures from 29 to 45

https://www.youtube.com/playlist?list=PLiDoPUX9nLkJ8dnPgKoVEOiAb8BfulKRR
Razavi electronics-2
https://www.youtube.com/playlist?list=PLO4mxQzfcml_56XSGcA8ULOv7qEtZd0Hy till whatever u
can understand and have time.
https://www.youtube.com/watch?v=WezDgErVQWU&list=PLC19EACF93A23928B&index=1
Purely based on your interest and if you have time.

9. VLSI system testing: -

For hazards you can follow this http://www.doe.carleton.ca/~shams/ELEC3500/hazards.pdf
For SA1 and SA0 faults, Observability and controllability, Glitches class notes of
Thilagavathy madam (NIT Trichy VLSI) is fine. Or else you can easily get from net.
For DFT, JTAG and BIST
https://youtube.com/playlist?list=PLbMVogVj5nJTClnafWQ9FK2nt3cGG8kCF –DFT and BIST are
explained very clearly from 38 to 44 videos
https://youtu.be/MgCFUO2BrkQ - 4 videos from this till BIST2

10.Physical design: - Entuple physical design videos gives you deep insights. Do this course if
time permits. Generally, companies coming for physical design profile didn’t ask or expect
deep in it (in my case only 2-3 basic questions from PD as mentioned above in my interview
exp). Watch the videos if you get them. We can get clear idea on ASIC flow so that we can
explain in interview confidently if asked. Indranil Sen Gupta lectures are also there
https://www.youtube.com/playlist?list=PLU8VFS-HdvKtKswbcvvA8yVhzleTV7OE8
But Entuple videos were superset of above link.
11.Projects: - Be crystal clear with your projects/mini projects/certifications. Otherwise
remove them from your resume. If you have work experience and worked on other
concepts like SQL, Java, Python etc., then be prepared with those basic questions also and
don’t neglect them. When you know multiple languages, then make a table for difference
between them. Example: - difference between C, C++, Java, Python?

12.COA: - NVIDIA concentrates majorly on this and some companies ask few questions in
written test too. Students who took ESE coaching will have some edge if they studied
already. Otherwise, study these pdfs
https://drive.google.com/file/d/1EOchoV4zJBzZVAx101IZoTnFpotTG0fc/view?usp=sharing
https://drive.google.com/file/d/1GFA_8o5PY72g3xwkaEwJqvAjCaQpHKt4/view?usp=sharing
 Don’t spend too much time on this subject. Have some basic idea on commonly asked
questions. I have no time to read these. So, I only completed this below playlist to have
some basic idea https://www.youtube.com/watch?v=L9X7XXfHYdU

13.ASIC flow: - https://www.linkedin.com/posts/karan-g-019143162_asic-like-share-activity-

6828529759144730624-K6AW some basic idea on what exactly happens at each and every
step should be known. This is a very important question in interviews. Refer FPGA flow also
in net. Some interviewers are asking that too. Difference between FPGA and ASIC is also
common question.

14.For Non ECE background guys: Definitely you guys should start working hard from the
first semester itself. CMOS VLSI, Analog IC, Verilog, DSP were already studied by ECE
students in their BTech. Here they are just reading extensions and add ons. Most of you
guys are less intuitive in these subjects. I am from Electrical background. So, I can feel you.
Even the sources I mentioned were from too basic level.

15.Make friends: Every phase of life needs friends. Similarly, for MTech too. Many of you
may be self-learners. Study self but after that at least discuss among your group (preferably
3-4). This not only corrects your mistake but also helps you for short cuts, makes you to
think in different perspective. Believe me or not, my 1st semester was completely online. I
became CR of my class and able to get very good interaction with every guy in the class. Got
a lot of support from friends in understanding concepts. I still believe becoming CR is also
one of the reasons for me to get the job.

16.IMPORTANT NOTE:
A. Students who were not placed in 3rd semester should have some additional
knowledge than others. First and foremost, have clarity on your MTech project.
And in general, people neglect Physical design, Analog and COA while preparing.
Try to prepare any of them (Give last preference to COA since only NVIDIA
concentrates more on it but have some basic idea for scoring in written exams of
all companies). But before reading these, complete important things like Digital,
Aptitude, C, CMOS concepts, Verilog, Gate analog, Puzzles. Since Digital profile
jobs are more, I kept Digital as 1st priority. If you have confidence and more
interest in Analog then be good at both gate and MTech level Analog at 1 st.
B. I have covered maximum number of sources. But still there is no end for gaining
knowledge. PLEASE DON’T STICK TO ONLY THESE SOURCES. Check multiple videos
 till you understand the concept and able to do any sort of question related to that
concept.
C. Don’t get demotivated if placement is taking time. Maintaining mental health is a
part of placement process. The longer it takes the stronger you become. Just prove
that you are strong enough and wait for the Jersey railway station scene moment.
Don’t neglect health. You are what you eat. Eat good food and have adequate
sleep with fitness.

17.Thank you note:

I want to thank my seniors first who gave us hope that we too can crack these technical
interviews
P. Prathyusha (Qualcomm), Sreedhar (MediaTek), Baskar (Western Digital), Naga Vijay
(Qualcomm), Krishna Teja (Texas Instruments).
In the sources I have mentioned earlier, more than half concepts I studied multiple times
but got clarity only after discussing with these most important people in my MTech.
M. Sreekanth, G. Vasudeva Rao, G. Viswanath, K. Prudhviraj, A. SaiTeja, Reeta Vad,
S. Vinay Kumar, G. Arun Kumar, Swathi Payavula…. unable to write all the names due to
obvious reasons
“Finally, I want to thank my parents Always we should try to give them back the
love and support we received, but still, we can’t return their debt completely”.

18.You can tinkle me at:

https://www.linkedin.com/in/bapeshwar-vinnakota-b8a6571a5/?originalSubdomain=in
All the above-mentioned seniors and my classmates were there in my connections. You can
contact them too for any queries.
Don’t ask us anything related to what companies are coming/came? How many got
placed? What’s the package? kind of curious kiddo questions…
Believe in NIT Trichy. Believe in T & P cell’s rules and regulations.
Before these, most importantly BELIEVE IN YOURSELF.
Never settle and never ever make your latest success as your last success.