Chapter 12

ISA BUS
PC Architecture for
Technicians: Level-1
Systems Manufacturing Training
and Employee Development
Copyright © 1996 Intel Corp.

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 OBJECTIVES: At the end of this section,
the student will be able to do the following:
l Describe the background of the Industry Standard ISA
Expansion Bus.
l Describe Typical System Bus Cycles.
l Explain the Functions of the Signals on the I/O
Channel.
l Discuss the ISA BUS Signal Descriptions.
l Describe 8-bit Memory & I/O ISA BUS Cycles.
l Describe Conversion BUS Cycles.
l Describe 16-bit Memory & I/O ISA BUS Cycles.

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 ISA BUS
OVERVIEW

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 ISA BUS OVERVIEW
l This chapter presents an overview of the ISA bus.
l The I/O channel (defined by IBM) is an expansion bus
permitting the installation of a wide variety of adapter
cards.
l The ISA bus is an industry-wide attempt to standardize
the original IBM I/O Channel.
n IBM did not fully document the PC/AT I/O Channel.
n The IEEE approved an AT bus specification in 1987
which defined what is know as the Industry Standard
Architecture bus, or ISA bus for short.
l The function of each ISA bus signal is presented and
timing diagrams illustrate various ISA bus transfers.
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 IBM PC/AT System Board
AT TYPE

REAR PANEL

XT TYPE
} 62
PINS

} 36
PINS

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 CURRENT ISA BUS STANDARD
l The I/O channel (8-bit) in the original PC and PC/XT
consisted of several 62-pin connectors (slots).
l The ISA bus standard (IEEE P996) very closely
matches the timing of the 8 MHz IBM PC/AT.
n SYSCLK is is still 8 MHz but is no longer necessarily
related to the CPU clock.
3 The CPU clock could be running at 25MHz, 33MHz, 50MHz,
60MHz, or 66MHz
3 SYSCLK is sometimes 8.33 MHz obtained from 25/3, etc.

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 TYPICAL
SYSTEM BUS
CYCLES
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 TYPICAL SYSTEM BUSES
ADDRESS

CPU/
CHIPSET MEMORY
DATA

CONTROL

MEMR#
MEMW#
IOR#
IOW#

I/O

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 TYPICAL SYSTEM BUSES
l Recall that the typical microprocessor reads and
writes to memory and I/O devices using the
following three buses:
l ADDRESS BUS
n The address bus supplies an address to the memory or
I/O device.
l DATA BUS
n The data bus provides a bi-directional pathway for data
flow. The data flow can be:
3 From the CPU to memory or I/O devices (WRITE).
3 From the memory or I/O devices to the CPU (READ).

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 TYPICAL SYSTEM BUSES
l CONTROL BUS
n The control bus provides the control signals (commands)
that tell the memory and I/O devices what type of cycle the
CPU is running. Typical commands follow:
n MEMR#
3 CPU READ FROM MEMORY
n MEMW#
3 CPU WRITE TO MEMORY
n IOR#
3 CPU READ FROM I/O DEVICE
n IOW#
3 CPU WRITE TO I/O DEVICE
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 Typical System Bus Cycle
The figure shows both a read and a write cycle. The
timing of the bus signals in a typical bus cycle follows
the steps on the next pages.
BUS CYCLE
1 3
BALE 2
VALID
ADDRESS 4
IOR#,MEMR#
6
5
DATA READ VALID
4
IOW#,MEMW# 6
5
VALID
DATA WRITE

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 TYPICAL SYSTEM BUS CYCLE
CPU READ FROM MEMORY OR I/O DEVICE

1. BALE goes high, indicating the beginning of a bus cycle.

2. The ADDRESS bus becomes valid.
3. The ADDRESS bus is latched as BALE goes low.
4. The appropriate Command (MEMR#, IOR#) becomes active
low.
5. The addressed memory or I/O device places the data on
the DATA bus.
6. The cycle ends when the CPU samples the DATA bus as
COMMAND goes inactive high.

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 TYPICAL SYSTEM BUS CYCLE
CPU WRITE TO MEMORY OR I/O DEVICE

1. BALE goes high, indicating the beginning of a bus cycle.

2. The ADDRESS bus becomes valid.
3. The ADDRESS bus is latched as BALE goes low.
4. The appropriate Command (MEMW#, IOW#) becomes
active low.
5. The CPU places the data on the DATA bus.
6. The cycle ends when the CPU samples the DATA bus as
COMMAND goes inactive high.

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 ISA BUS
BACKGROUND

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 ISA BUS BACKGROUND
l The original PC 62-pin slot was not adequate for the
PC/AT (80286 CPU) because of the need for the
following:
n more address lines--24 instead of 20
n more data lines--16 instead of 8
n more interrupts--5 interrupts added
n more DMA--4 new DMA channels
n various lines supporting 16-bit access

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 ISA BUS BACKGROUND
COMPATIBILITY WITH THE PC: To permit the PC/AT
to accommodate the PC type of adapter cards, the 62-
pin slot was left almost unchanged.
l A 36-pin extension was added to the original 62 pins
to provide for the extra needs listed above.
n The 36-pin extension is in line with the 62 pins,
3 Giving the PC/AT adapter card a 98-pin connection.
n Most PC/ATs provide a mix of the old and new slots.
l The original IBM PC/AT had the following:
n 6 of the 98-pin slots (62+36)
n 2 of the 62-pin slots

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 IBM PC/AT System Board
AT TYPE

REAR PANEL

XT TYPE
} 62
PINS

} 36
PINS

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 ISA 8-bit
Connector
Signals
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 ISA Bus 8-bit Connector
GND B01 A01 IOCHCK#
RSTDEV B02 A02 SD7
+5V B03 A03 SD6
IRQ9/(IRQ2) B04 A04 SD5
-5V B05 A05 SD4
DRQ2 B06 A06 SD3
-12V B07 A07 SD2
SRDY# (NOWS#) B08 A08 SD1
+12V B09 A09 SD0
0V B10 A10 IOCHRDY
SMEMW# B11 A11 AEN
SMEMR# B12 A12 SA1
IOR# B13 A13 9
SA1
IOW# B14 A14 8SA1
DACK3# B15 A15 7
SA1
DRQ3 B16 A16 6
SA1
DACK1# B17 A17 5
SA1
DRQ1 B18 A18 4
SA1
REFRESH# B19 A19 3
SA1
SYSCLK B20 A20 2
SA1
IRQ7 B21 A21 1
SA1
IRQ6 B22 A22 0
SA
IRQ5 B23 A23 9
SA
IRQ4 B24 A24 8
SA
IRQ3 B25 A25 7
SA
DACK2# B26 A26 6
SA
TC B27 A27 5
SA
BALE B28 A28 4
SA
+5V B29 A29 3
SA2
OSC B30 A30 SA
GND B31 A31 1
SA
0
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 ISA 8-bit Connector Signals
The 62-Pin Portion of the ISA Bus Connector can be
grouped into logical functions:
l ADDRESS BUS (A19:0)
n These are OUTPUT ONLY signals used to address
system-bus Memory & I/O
n With 20 address lines (like the PC/XT), the system can
address up to 1 MByte of Memory.
n A19 is most significant bit , A0 is the least significant
l DATA BUS (D7:0)
n These are Bi-directional data lines.
n There are eight data lines (like the PC/XT).
n D7 is most significant bit , D0 is the least significant.
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 ISA 8-bit Connector Signals (Cont.)
ISA Conn. 62-Pin Portion: Logical Functions (cont.)
l CONTROL--The control bus consist of:
n Four command signals
3 SMEMR#, SMEMW#, IOR#, IOW#
n & IOCHRDY (low to add wait states)
l The fundamental purpose of the control bus is to
identify the type of transaction and provide
synchronization between the fast processor & the
external devices it is reading from or writing to.

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 ISA 8-bit Connector Signals (Cont.)
ISA Conn. 62-Pin Portion: Logical Functions (cont.)
l CONTROL (cont.)
n SMEMR#, SMEMW#: System Memory Read/ Write Command
3 Indicates address bus contains a valid Memory Address.
3 Asserted for Memory Accesses below 1MB
n IOR#, IOW#: Input/Output Read/Write (IORC#, IOWC#)
3 Indicates address bus contains a valid I/O Port Address.
n IOCHRDY: I/O Channel Ready (Active High)
3 When IOCHRDY=1, the I/O Channel is READY.
3 Input only signal used to extend the ISA bus cycles for
devices not fast enough to respond to normal cycles.
3 Pull Low to insert Wait States (I/O Channel NOT READY).
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 ISA 8-bit Connector Signals (Cont.)
ISA Conn. 62-Pin Portion: Logical Functions (cont.)
l INTERRUPTS--There are 6 interrupt request lines.
n Input only lines used to generate Interrupt Requests to
the system board 8259A PIC #1.
n Note that IRQ9 was labelled IRQ2 on the PC/XT. The
IRQ9 vector, type 71H, is redirected to the IRQ2 type
0AH to provide compatibility with XT type boards.
n The interrupts are rising edge triggered.

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 ISA 8-bit Connector Signals (Cont.)
ISA Conn. 62-Pin Portion: Logical Functions (cont.)
l DMA--There are three DMA channels.
n Direct Memory Access Request/Acknowledge
n DRQ1-3--active high requests (8 bit)
n DACK1# - DACK3#--active low acknowledge
n TC--high pulse. NOTE: There is only one TC signal:
3 The DMA system supports a terminal count (TC) signal
which indicates that one of the DMA channels is done.
n Each DMA channel is capable of making a maximum of
64K, 8-bit transfers between memory and I/O devices

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 ISA 8-bit Connector Signals (Cont.)
ISA Conn. 62-Pin Portion: Logical Functions (cont.)
l POWER:
n +5V DC
3 Used to power the logic on adapter cards.
n -5V DC- (Good signal to find pin B5 on ISA connector)
3 Very little used. Originally supplied power to 16K-bit DRAM
chips on older PCs.
n +12V DC-
3 Used primarily for disk power, also for RS232.
n -12V DC
3 Used for RS232.
n 0V DC--GND (ground).
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 ISA 8-bit Connector Signals (Cont.)
ISA Conn. 62-Pin Portion: Logical Functions (cont.)
l CLOCKS
n SYSCLK--System Clock (CLK, BCLK)
3 This is typically 8 MHz.
3 It was originally the CPU clock on the PC/AT, first running at
6 MHz, then 8 MHz.
3 In modern PC’s CLK will be about 8 MHz, not necessarily
related to the CPU clock.
n 84OSC--Oscillator Output (OSC) - 14.31818 MHz
3 It is still used for clocking the 8254 Timer in the PC/AT.
» 14.3MHz/12 = 1.19 MHz
3 Source of the CPU clock in the original PC (4.77 MHz).

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 ISA 8-bit Connector Signals (Cont.)
ISA Conn. 62-Pin Portion: Logical Functions (cont.)
l ODDS AND ENDS
n IOCHCK# -- I/O Channel Check (IOCHK#, CHCHK#)
3 This active low signal is to provide adapter cards with a
method of indicating memory failure.
3 It actually connects through gates to NMI and so is really
non-maskable interrupt, type 2.(Active low).
n RSTDEV -- Reset Device (RESET, RSTDRV)
3 This signal is active high during power-on to allow a reset
of devices on adapter cards.

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 ISA 8-bit Connector Signals (Cont.)
ISA Conn. 62-Pin Portion: Logical Functions (cont.)
l ODDS AND ENDS
n BALE -- Bus Address Latch Enable (BUSALE, ALE)
3 Active high during the beginning of a bus cycle. Addresses
are latched on the falling edge.
3 BUSALE is held high during DMA transfers.
n AEN -- Address enable.
3 A high indicates that the DMA system is in control of the bus
3 Used on the System Board to indicate that this is a NON
CPU driven cycle.
» Disables address decoders on System Board.

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 ISA 8-bit Connector Signals (Cont.)
ISA Conn. 62-Pin Portion: Logical Functions (cont.)
l ODDS AND ENDS
n SRDY# -- Synchronous Ready (OWS, NOWS)
3 This signal, Zero-Wait-State, allows adapter cards to
eliminate wait states on 16-bit memory cycles
3 Minimize wait states to two on 8-bit memory cycles.
3 This signal is active low and should be driven by the
adapter card with an open-collector output device.
3 This is not available for I/O cycles.

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 ISA 8-bit Connector Signals (Cont.)
ISA Conn. 62-Pin Portion: Logical Functions (cont.)
l ODDS AND ENDS
n REFRESH# -- (MEMREF#)
3 An active low signal indicating that a memory refresh cycle
is in progress by the System Board.
3 Note, this signal becomes an input signal when another
master is in charge of the bus. The other master can force
the system board to run a refresh cycle. Must be done
every 15.6 microseconds.

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 ISA 16-bit
Connector
Signals
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 ISA 16-bit Connector Signals
The 36-Pin Portion of the ISA Bus Connector
l When the PC grew into the PC/AT, the need for
more bus signals grew.
l The original PC 62-pin slot was not adequate for the
PC/AT (80286 CPU) because of the need for the
following:
n More address lines -- 24 instead of 20
n More data lines -- 16 instead of 8
n More interrupts -- 5 interrupts added
n More DMA -- 4 new DMA channels
n Various lines supporting 16-bit accesses

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 ISA Bus 16-bit Connector
MCS16# D01 C01 SBHE#
IOCS16# D02 C02 LA23
IRQ10 D03 C03 LA22
IRQ11 D04 C04 LA21
IRQ12 D05 C05 LA20
IRQ15 D06 C06 LA19
IRQ14 D07 C07 LA18
DACK0# D08 C08 LA17
DRQ0 D09 C09 MEMR#
DACK5# D10 C10 MEMW#
DRQ5 D11 C11 SD8
DACK6# D12 C12 SD9
DRQ6 D13 C13 SD10
DACK7# D14 C14 SD11
DRQ7 D15 C15 SD12
+5V D16 C16 SD13
MASTER16# D17 C17 SD14
GND D18 C18 SD15

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 ISA 16-bit Connector Signals (Cont.)
The 36-Pin Portion of the ISA Bus Connector can be
grouped into logical functions:
l ADDRESS BUS (LA17-LA23)
n These Large Addresses, unlike the A0-A19 signals on
the 62-pin connector, are valid slightly earlier (as much
as 70ns) and are NOT LATCHED.
n They are typically used for address decoding.
3 Used to generate the MCS16# signal.
l DATA BUS (SD8-SD15): System Data (D15:8)
n These are the extra eight data lines needed for 16-bit
transfers.

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 ISA 16-bit Connector Signals (Cont.)
ISA Conn. 36-Pin Portion: Logical Functions (cont.)
l CONTROL BUS: MEMR#, MEMW# (MRDC#, MWTC#)
n Memory Read/Write Command
n Active for Memory Accesses from 0-16MB.
n Unlike SMEMR# and SMEMW# on the 62-pin adapter
which were active for addresses below 1MB, these
signals are active for all memory addresses.
n 8-bit agents only receive SMEMR# and SMEMW# due
to connector limitations.

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 ISA 16-bit Connector Signals (Cont.)
ISA Conn. 36-Pin Portion: Logical Functions (cont.)
l INTERRUPTS
n Five new interrupt requests are added.
n The slave 8259 has eight inputs, but three are used on
the system board.
3 IRQ 8 -- Real-time clock chip (Alarm Output)
3 IRQ 9 -- Redirect to type 0AH (old IRQ 2)
3 IRQ 13 -- Coprocessor error
3 The remaining five appear on the 36-pin connector.

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 ISA 16-bit Connector Signals (Cont.)
ISA Conn. 36-Pin Portion: Logical Functions (cont.)
l DMA (Direct Memory Access)
n The added DMA controller (DMA #2) has only three
channels available, since the fourth channel is used in
cascade mode to handle requests from DMA1.
3 DRQ0, DACK0#--Channel 0 from DMA #1, 8 bit
» The DRQ4, DACK#4 lines used for cascade to the original
DMA controller (DMA #1).
n New channels, 16 bit
3 DRQ5-7 -- Direct Memory Access Request
3 DACK5#-DACK7# -- Direct Memory Access Acknowledge.

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 ISA 16-bit Connector Signals (Cont.)
ISA Conn. 36-Pin Portion: Logical Functions (cont.)
l ODDS AND ENDS
n POWER
3 +5V DC.
3 0V DC--GND.
n SBHE# - (System Byte High Enable)
3 Asserted to indicate a transfer of data on the D15:8 Data
lines (High Byte of D15:0 Word).
3 Used with A0 to decode the type of bus cycle.
» SBHE# = 0, A0 = 0 -> 16 BIT TRANSFER
» SBHE# = 0, A0 = 1 -> Upper Byte Transfer (D15:8) - Odd Addr
» SBHE# = 1, A0 = 0 -> Lower Byte Transfer (D7:0)

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 ISA 16-bit Connector Signals (Cont.)
ISA Conn. 36-Pin Portion: Logical Functions (cont.)
l ODDS AND ENDS - TRANSFER SIZE
n MCS16# -- Memory Cycle Select 16-bit (M16#)
n IOCS16# -- I/O Cycle Select 16-bit (IO16#)
3 Indicates the adapter card can support 1 wait state 16 bit
transfers on the present cycle.
3 These two signals permit a 16-bit memory or I/O device
to request that the system board run a 16-bit bus cycle
on the I/O channel.
3 NOTE: The ISA BUS defaults to running 8-bit cycles, even if
the CPU is transferring 16 bits. The default assumes the
transfer is to an XT type adapter.

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 ISA 16-bit Connector Signals (Cont.)
ISA Conn. 36-Pin Portion: Logical Functions (cont.)
l ODDS AND ENDS
n MASTER# (MASTER16#)
n An adapter card can become a limited bus master in the
PC/AT.
n An adapter card wishing to be a bus master takes these
steps:
3 1. Make a DMA request on one of the available
DMA channels.
3 2. After receiving the corresponding DACK#, the adapter
now activates the MASTER# signal (active low).
Cont. next page

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 ISA 16-bit Connector Signals (Cont.)
ISA Conn. 36-Pin Portion: Logical Functions (cont.)
l ODDS AND ENDS
n MASTER# (cont.)
3 3. The adapter can now drive the address, data, and
control signals.
» MASTER# causes the System Board to turn around bus
buffers so the ISA card can drive addresses & bus cycle
definitions.
3 4. To permit memory refresh, the adapter must either drive
the REFRESH# signal every 15.6 us or release the
MASTER# and the DRQ signals.
» The system board actually does the refresh cycle in either
case.

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 ISA BUS
CYCLES
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 ISA BUS CYCLES
l This section discusses the following topics on ISA bus
cycles.
n 8-bit memory cycles
n 8-bit I/O cycles
n Conversion cycles
n 16-bit memory cycles
n 16-bit I/O cycles
l The system board contains logic integrated into chip
sets that execute bus cycles on the ISA bus.
l These bus cycles look very much like the typical
system bus cycles we have seen already.

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 HISTORY OF ISA BUS CYCLE TIMING
l The ISA bus cycle timing was originally dictated
by the 8088 CPU running at 4.77 MHZ.
l The PC/AT I/O channel bus cycle timing included wait-
states to lengthen the inherent 286 bus cycles.
n The original PC/ATs had a CPU clock of 6 MHZ, later
increased to 8 MHZ.
l The PC/AT's 8-bit cycles matched closely those of the
PC/XT for compatibility. The 8-bit cycles included 4
wait-states.
l The PC/AT's 16-bit cycles included a default wait-state
to allow adapters to use slower memory.
l Timing Diagram reference Intel Doc# 458057-001.
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 Standard 8-bit Memory Cycle (Write)
1 byte
1/8MHz= 0.125 us 1 2 3 4 5 6 6 clocks
1.33 MB/Sec
SYSCLK

IOCHRDY

MEMW*

SD<07..00> valid

SA<19..00> valid
SBHE*
BUSALE

LA<23..17> valid

MEMCS16*

Default is Read Cycle Similar

4 Wait States

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 (Add 1 Wait State) 8-bit Memory Cycle (Read)
1 byte
1/8MHz= 0.125 us 1 2 3 4 5 6 7 7 clocks
1.14 MB/Sec
SYSCLK

IOCHRDY

MEMR*

SD<07..00> valid

SA<19..00> valid
SBHE*
BUSALE

LA<23..17> valid

MEMCS16*

Default is Write Cycle Similar

4 Wait States

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 Standard 8-bit I/0 Cycle (Write)
1 byte
1/8MHz= 0.125 us 1 2 3 4 5 6 6 clocks
1.33 MB/Sec
SYSCLK

IOCHRDY

IOWC*

SD<07..00> valid

SA<15..00> valid
SBHE*
BUSALE

LA<23..17> valid

IOCS16*

Default is Read Cycle Similar

4 Wait States

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 (Add 1 Wait State) 8-bit I/O Cycle (Read)
1 byte
1/8MHz= 0.125 us 1 2 3 4 5 6 7 7 clocks
1.14 MB/Sec
SYSCLK

IOCHRDY

IORC*

SD<07..00> valid

SA<15..00> valid
SBHE*
BUSALE

LA<23..17> valid

IOCS16*

Default is Write Cycle Similar

4 Wait States

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 CONVERSION LOGIC
l To make the PC/AT backward compatible with PC/XT
memory and I/O boards, the PC/AT system board
contains logic to convert 16-bit bus cycles to two 8-
bit bus cycles.
l NOTE: The Conversion Cycle is the Default.
n The conversion cycle can be overridden by the use of
#MCS16 or IOCS16#.

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 CONVERSION LOGIC
l Example:
n An instruction causes the CPU to run a 16 bit Memory
Write bus cycle.
n Suppose however, that target of the write is on an 8-bit
memory card, connected only to DO-D7.
l The conversion logic will capture the 16 bits coming from
the CPU and run two 8-bit bus cycles on the ISA BUS.
n During the first bus cycle, the low byte is put directly on
D0-D7.
n During the second bus cycle, the high byte is swapped
from the upper 8 data lines on the system board to D0-
D7 on the ISA bus.

PC Architecture For Technicians Level-1

Rev. 1.0 Sys MFG T/ED 4/25/2003 Technical Excellence Development Series
Ch 12 - Page 50
 16-bit Memory Cycle (STD, Add 1 WS, OWS)
2 bytes 2 bytes
Default is 3 clocks 0.25 us
1 Wait State
5.33 MB/Sec 8.0 MB/Sec

1/8MHz= 0.125 us Standard IOCHRDY (1 wait state) No Wait State

1 2 3 1 2 3 4 1 2 1
SYSCLK

SRDY* (OWS*)

IOCHRDY
SA<19..00>
SBHE*
BUSALE
LA<23..17>

MCS16*
MEMR*/MEMW*
D<15..00> Read valid valid valid

D<15..00> Write valid valid valid

PC Architecture For Technicians Level-1

Rev. 1.0 Sys MFG T/ED 4/25/2003 Technical Excellence Development Series
Ch 12 - Page 51
 16-bit I/O Cycle (STD, Add 1 WS)
2 bytes 2 bytes
Default is 3 clocks 0. 5 us
1 Wait State
5.33 MB/Sec 4.0 MB/Sec

1/8MHz= 0.125 us Standard IOCHRDY (1 wait state)`

1 2 3 1 2 3 4
SYSCLK

IOCHRDY
SA<15..00>
SBHE*
BUSALE

IOCS16*
IOR*/IOW*
D<15..00> Read valid valid

D<15..00> Write valid valid

PC Architecture For Technicians Level-1

Rev. 1.0 Sys MFG T/ED 4/25/2003 Technical Excellence Development Series
Ch 12 - Page 52
 SUMMARY
WE HAVE DISCUSSED THE FOLLOWING:
l The functions of the Industry Standard ISA Expansion
Bus.
l Typical System Bus Cycles.
l The Functions of the Signals on the I/O Channel.
l The ISA BUS Signal Descriptions.
l 8-bit Memory & I/O ISA BUS Cycles.
l Conversion BUS Cycles.
l 16-bit Memory & I/O ISA BUS Cycles.

PC Architecture For Technicians Level-1

Rev. 1.0 Sys MFG T/ED 4/25/2003 Technical Excellence Development Series
Ch 12 - Page 53