1) Threshold voltage depends on

a) Temperature.
b) Doping concentration.
c) Oxide thickness.
d) All.

2) Temperature inversion is
a) Delay increase in higher technologies and decreases in lower technologies.
b) Delay increase in lower technologies and decrease in higher technologies.
c) Maintain the constant delay in high and low technologies.
d) None.

3) Uncertainty is more in
a) Hold.
b) Setup.
c) Both A&B.

4) If gate area is less than metal area then it leads to

a) Antenna violations.
b) Electromigration.
c) Congestion.
d) None.

5) Delay between shortest path and longest path in the clock is called......
a) Global skew.
b) Useful skew.
c) Local skew.
d) Slack.

6) HVT cell has

a) Slower and more leakage power.
b) Faster and more leakage power.
c) Slower and less leakage power.
d) Faster and less leakage power.

7) FRAM view has

a) Layout information and used at the time of tape-out.
b) Layout information and used in place&route.
c) Abstract view and used in place and route.
d) Abstract view and used at the time of tape-out.

8) Clock gating is used to reduce

a) Static power dissipation.
b) Dynamic power dissipation.
c) Short circuit current.

9) Tap cells are used

a) To avoid the dynamic IR drop.
 b) To connect the gap between cells.
c) To avoid dynamic power dissipation.
d) To avoid latch up problem.

10) HFNS is used

a) To balance the timing.
b) To balance the power.
c) To balance the load.
d) None.

11) To detect manufacturing faults in macros we use

a) JTAG (joint test action group).
b) MBIST (macro built in self test).
c) LVS.
d) All.

12) Cross-talk can be avoided by...

a) Using low metal layers.
b) Using long nets.
c) Decreasing the spacing between the metal layers.
d) Shielding the nets.

13) CRPR stands for...

a) Clock reconvergence past removal.
b) Cell reconvergence pessimism removal.
c) Clock reconvergence pessimism removal.
d) Clock reconvergence present removal.

14) what are the pre routing in the design

a) Signal routing.
b) Power routing.
c) Signal and power routing.
d) None.

15) Which configuration is more preferred during floor planning

a) With channel spacing between rows and no double back.
b) Double back with non flipped rows.
c) With channel spacing between rows and no double back.
d) Double back with flipped rows.

16) Which gate is most preferred in the design

a) NOR.
b) NAND.
c) AND.
d) XOR.

17) Elecromigration can be reduced by

a) Increasing the width.
b) Increasing the spacing between nets.
c) Both A&B.
 d) Blockages.

18) I/O delays are more than cell delay

a) True.
b) False.

19) Major importance of power plan is

a) IR drop.
b) Electromigration.
c) Congestion.
d) Both A&B.

20) End cap cell is used

a) To avoid the dynamic IR drop.
b) To avoid cell damage at the end of row.
c) To avoid dynamic power dissipation.
d) To connect the gap between cells.

21) HFNS is used at the stage of

a)CTS.
b) Placement.
c) Routing.
d) Floor plan.

22) Virtual clock is

a) Logically not connected.
b) Physically doe't exist.
c) Both a&b.
d) None.

23) Which of the following metal layer has max resistance

a) Metal 3.
b) Metal 5.
c) Metal 2.
d) Metal 6.

24) Chip utilization depends on..........

a) Only standard cells.
b) Standard cells and macros.
c) Only macros.
d) Standard cells,macros,I/0 pads.

25) To achieve better timing.......cell are placed in critical path

a) HVT
b) LVT
c) SVT

26) Delay of cell depends on____

a) Input transition and output load.
 b) Output transition and input load.
c) Output transition and output load.
d) Input load and output transition.

27) Clock tree does't contain following cell....

a) Clock buffer.
b) AOI cell.
c) Clock inverter.
d) None.

28) What is the effect of high drive strength buffer when added in long net
a) Delay on net decreases.
b) Capacitance on net increases.
c) Delay on net increases.
d) Distance on the net increases.

29) LVT cell has

a) Faster and more leakage power.
b) Slower and more leakage power.
c) Faster and less leakage power.
d) Slower and less leakage power.

30) Cell view has

a) Layout information and used at the time of tape out.
b) Abstract view and used in place and route.
c) Layout information and used in place&route.
d) Abstract view and used at the time of tape out.

31) Jitter is the

a) Difference between two clock pulses.
b) Ratio of input transition and output load.
c) Deviation of clock edge from its ideal position.
d) Difference between required time-arrival time.

32) Decap cell is used

a) To avoid the dynamic IR drop.
b) To avoid cell damage at the end of row.
c) To avoid dynamic power dissipation.
d) To connect the gap between cells.

33) Hard macro is

a) Circuit is fixed,we know only timing information and don't know the functional
information.
b) Circuit is not fixed,we know the timing and functional information.
c) Circuit is fixed,we don't know the timing and functional information.
d) Circuit is fixed,we know the timing and functional information.

34) Which design is more complicated

a) 500mhz.
b) 54mhz.
 c) 500khz.
d) 650mhz.

35) Clock skew can be minimized by

a) Buffering the clock.
b) Add delay in data path.
c) Clock reversing.
d) A&C.
e) A,B&C.

36) FPGA chip is

a) Simple in design.
b) It can be re programmed.
c) Manufacturing time is less.
d) A&C.
e) A,B&C.

37) Capacitance table can be created by

a) .tf file
b) .lib file
c) lef file
d) .sdc

38) To detect manufacturing faults in I/O we use

a) JTAG (joint test action group).
b) MBIST (macro built in self test).
c) LVS
d) All

39) ASIC chip is

a) Simple in design.
b) Manufacturing time is less.
c) It is faster.
d) Both A&C.

40) Use of placement blockage is

a) Block the cells in specific area.
b) Reduce the congestion.
c) Defines std cell area.
d) A&B.
e) A,B&C.

41) In soft blockage........cells are placed

a) No cells.
b) Only buffers and inverters.
c) Only sequential cells.
d) Any cells.

42) More IR drop due to...

 a) Increase in metal width.
b) Decrease in metal length.
c) Lot of metal layers.
d) Increase in metal length.

43) To avoid cross-talk the shielding net is usually connected to____

a) VDD.
b) clock.
c) VDD and VSS.
d) VSS.

44) Which of the following is preferred while placing macros

a) Macros placed left and right side of die.
b) Macros placed center of the die.
c) Macros placed top and bottom side of die.
d) Macros placed based on the connectivity of the I/O.

45) Pitch of the wire is______

a) Min width.
b) Min width+min spacing.
c) Min spacing.
d) Min width-min spacing.

46) In 9 metal layer design which metal layer you will use for power
a) Metal 5 and metal 6.
b) Metal 6 and metal 7.
c) Metal 8 and metal 9.
d) Metal 4 and metal 5.

47) After the final routing the violations in the design

a) There can be hold violations but not setup violations.
b) There can be both violations.
c) There can be setup violations but not hold violations.
d) There can be no setup and no hold violations.

48) JTAG cell is used

a) To check the io connectivity.
b) To avoid cell damage at the end of row.
c) To avoid dynamic power dissipation.
d) To connect the gap between cells.

49) Soft macro is

a) Circuit is fixed,we know only timing information and don't know the functional
information.
b) Circuit is not fixed,we know the timing and functional information.
c) Circuit is fixed,we don't know the timing and functional information.
d) Circuit is fixed,we know the timing and functional information.

50) Latch-up problem can be reduced by

 a) Increasing the spacing.
b) Increase the doping concentration.
c) Use of guard rings.
d) All

51) Antenna problem can be caused by

a) Increasing the net length.
b) Decreasing the net length.
c) Increasing the load.
d) None.

52) Cross-talk can be reduced by

a) Increasing the spacing between nets.
b) Shielding.
c) Decreasing the spacing between nets.
d) Both A&B.

53) FPGA stands for

a) Field programmable gate array.
b) Fixed programmable gate arrangement.
c) Fixed programmable gate array.
d) None

54) Pre-routing means routing of.....

a) Clock nets.
b) Signal nets.
c) IO nets.
d) PG nets.

55) Hold is fixed....

a) Before CTS.
b) Before placement.
c) After CTS.
d) After placement.

56) Which of the following is best suited for CTS

a) Buffer.
b) Clk buffer.
c) Inverter.
d) Clk inverter.

57) Routing congestion is___

a) Available tracks are less than required tracks.
b) Depends on the routing layers available.
c) Required tracks are less than available tracks.
d) None.

58) Halo allows the placement of

a) Only standard cells.
b) Only macros.
 c) Only buffers and inverters.
d) None.

59) Aspect ratio is

a) Width /height.
b) Height/width.
c) Width+height.
d) Width -height.

60) What is the goal of CTS

a) Minimum EM.
b) Minimum slack.
c) Minimum skew.
d) Minimum IR drop.

61) If arrival time is more than required time______violations will come

a) Setup.
b) Hold.
c) Both.
d) None.

62) Maximum voltage drop will be there at(without macros)......

a) Right and left side.
b) Middle.
c) Top and bottom side.
d) None.

63) The solution of antenna effect is.....

a) Shielding.
b) Buffer insertion.
c) Diode insertion.
d) Double spacing.

64) Which of the following is not present in SDC file

a) Max transition.
b) Max current density.
c) Max capacitance.
d) Max fan out.

65) Which is the following is not present in logical DRC's

a) Max transition.
b) Shorts.
c) Max fan-out.

66) Congestion can be reduced by

a) Adjusting the cell density in congested area.
b) Using proper blockage.
c) Both A&B.
d) None.
 67) The metal area and(or)perimeter of conducting layer/gate to gate
area is called...
a) Aspect ratio.
b) OCV.
c) Antenna ratio.
d) Utilization.

68) search and repair is used for.....

a) Reduce EM violations.
b) Reduce IR drop.
c) Reduce DRC.
d) None.

69) Maximum current density of metal is available in....

a) .lib
b) .tf
c) .lef
d) .sdc

70) Dynamic power consumption can be reduced by

a) Reduce voltage swing in all nodes.
b) Reduce the load capacitance.
c) Both A&B.
d) None.

71) what violations solved in LVS

a) Shorts.
b) Opens.
c) Missing text layers.
d) All.

72) Utilization of chip after placement optimization will be_

a) Decreases.
b) Constant.
c) Increases.
d) None.

73) Routing congestion can be avoided by.......

a) Distributing cells.
b) Placing cells closer.
c) Placing cells at corners.
d) None.

74) No.of tracks in high metal layer will be..... tracks in low metal layer
a) Less than.
b) More than.
c) Equal to.

75. Which is not preferred for clock buffers

 a) SVT.
b) LVT.
c) HVT.
d) None

76. Placement blockage is created at the stage of floor plan

a) True
b) False

77. Abutted design has

a) No gap between blocks.
b) Gap between the blocks.
c) Both A&B.
d) None

78. In power planning stage rings are placed

a) In middle of core.
b) Around the core.
c) At corner.
d) None

79. Scan chain re ordering will reduce congestion

a) True
b) False

80. Static power can be reduced by placing

a) LVT cells
b) SVT cells
c) HVT cells

81. Dynamic power consumption can be reduced by

a) Load capacitance.
b) Cell sizing.
c) Load sharing.
d) All of the above.

82. CTO can be performed by

a) Buffering.
b) Gate sizing.
c) Both A&B.
d) None
Asic blog spot
1) Chip utilization depends on ___.
Only on standard cells
b. Standard cells and macros
c. Only on macros
d. Standard cells macros and IO pads

2) In Soft blockages ____ cells are placed.

Only sequential cells
b. No cells
c. Only Buffers and Inverters
d. Any cells

3) Why we have to remove scan chains before placement?

Because scan chains are group of flip flop
b. It does not have timing critical path
c. It is series of flip flop connected in FIFO
d. None

4) Delay between shortest path and longest path in the clock is called ____.
Useful skew
b. Local skew
c. Global skew
d. Slack

5) Cross talk can be avoided by ___.

Decreasing the spacing between the metal layers
b. Shielding the nets
c. Using lower metal layers
d. Using long nets

6) Prerouting means routing of _____.

Clock nets
b. Signal nets
c. IO nets
d. PG nets
7) Which of the following metal layer has Maximum resistance?
Metal1
b. Metal2
c. Metal3
d. Metal4

8) What is the goal of CTS?

Minimum IR Drop
b. Minimum EM
c. Minimum Skew
d. Minimum Slack

9) Usually Hold is fixed ___.

Before Placement
b. After Placement
c. Before CTS
d. After CTS

10) To achieve better timing ____ cells are placed in the critical path.
HVT
b. LVT
c. RVT
d. SVT

11) Leakage power is inversely proportional to ___.

Frequency
b. Load Capacitance
c. Supply voltage
d. Threshold Voltage

12) Filler cells are added ___.

Before Placement of std cells
b. After Placement of Std Cells
c. Before Floor planning
d. Before Detail Routing
13) Search and Repair is used for ___.
Reducing IR Drop
b. Reducing DRC
c. Reducing EM violations
d. None

14) Maximum current density of a metal is available in ___.

.lib
b. .v
c. .tf
d. .sdc

15) More IR drop is due to ___.

Increase in metal width
b. Increase in metal length
c. Decrease in metal length
d. Lot of metal layers

16) The minimum height and width a cell can occupy in the design is called as
___.
Unit Tile cell
b. Multi heighten cell
c. LVT cell
d. HVT cell

17) CRPR stands for ___.

Cell Convergence Pessimism Removal
b. Cell Convergence Preset Removal
c. Clock Convergence Pessimism Removal
d. Clock Convergence Preset Removal

18) In OCV timing check, for setup time, ___.

Max delay is used for launch path and Min delay for capture path
b. Min delay is used for launch path and Max delay for capture path

c. Both Max delay is used for launch and Capture path

d. Both Min delay is used for both Capture and Launch paths
19) "Total metal area and(or) perimeter of conducting layer / gate to gate
area" is called ___.
Utilization
b. Aspect Ratio
c. OCV
d. Antenna Ratio

20) The Solution for Antenna effect is ___.

Diode insertion
b. Shielding
c. Buffer insertion
d. Double spacing

21) To avoid cross talk, the shielded net is usually connected to ___.
VDD
b. VSS
c. Both VDD and VSS
d. Clock

22) If the data is faster than the clock in Reg to Reg path ___ violation may
come.
Setup
b. Hold
c. Both
d. None

23) Hold violations are preferred to fix ___.

Before placement
b. After placement
c. Before CTS
d. After CTS

24) Which of the following is not present in SDC ___?

Max tran
b. Max cap
c. Max fanout
d. Max current density
25) Timing sanity check means (with respect to PD)___.
Checking timing of routed design with out net delays
b. Checking Timing of placed design with net delays

c. Checking Timing of unplaced design without net delays

d. Checking Timing of routed design with net delays

26) Which of the following is having highest priority at final stage (post
routed) of the design ___?
Setup violation
b. Hold violation
c. Skew
d. None

27) Which of the following is best suited for CTS?

CLKBUF
b. BUF
c. INV
d. CLKINV

28) Max voltage drop will be there at(with out macros) ___.
Left and Right sides
b. Bottom and Top sides
c. Middle
d. None

29) Which of the following is preferred while placing macros ___?

Macros placed center of the die
b. Macros placed left and right side of die
c. Macros placed bottom and top sides of die
d. Macros placed based on connectivity of the I/O
30) Routing congestion can be avoided by ___.
placing cells closer
b. Placing cells at corners
c. Distributing cells
d. None

31) Pitch of the wire is ___.

Min width
b. Min spacing
c. Min width - min spacing
d. Min width + min spacing

32) In Physical Design following step is not there ___.

Floorplaning
b. Placement
c. Design Synthesis
d. CTS

33) In technology file if 7 metals are there then which metals you will use for
power?
Metal1 and metal2
b. Metal3 and metal4
c. Metal5 and metal6
d. Metal6 and metal7

34) If metal6 and metal7 are used for the power in 7 metal layer process
design then which metals you will use for clock ?
Metal1 and metal2
b. Metal3 and metal4
c. Metal4 and metal5
d. Metal6 and metal7

35) In a reg to reg timing path Tclocktoq delay is 0.5ns and TCombo delay is
5ns and Tsetup is 0.5ns then the clock period should be ___.
1ns
b. 3ns
c. 5ns
d. 6ns
36) Difference between Clock buff/inverters and normal buff/inverters is __.
Clock buff/inverters are faster than normal buff/inverters
b. Clock buff/inverters are slower than normal buff/inverters

c. Clock buff/inverters are having equal rise and fall times with high drive
strengths compare to normal buff/inverters
d. Normal buff/inverters are having equal rise and fall times with high drive
strengths compare to Clock buff/inverters.

37) Which configuration is more preferred during floorplaning ?

Double back with flipped rows
b. Double back with non flipped rows
c. With channel spacing between rows and no double back
d. With channel spacing between rows and double back

38) What is the effect of high drive strength buffer when added in long net ?
Delay on the net increases
b. Capacitance on the net increases
c. Delay on the net decreases
d. Resistance on the net increases.

39) Delay of a cell depends on which factors ?

Output transition and input load
b. Input transition and Output load
c. Input transition and Output transition
d. Input load and Output Load.

40) After the final routing the violations in the design ___.
There can be no setup, no hold violations
b. There can be only setup violation but no hold
c. There can be only hold violation not Setup violation
d. There can be both violations.
41) Utilisation of the chip after placement optimisation will be ___.
Constant
b. Decrease
c. Increase
d. None of the above

42) What is routing congestion in the design?

Ratio of required routing tracks to available routing tracks
b. Ratio of available routing tracks to required routing tracks
c. Depends on the routing layers available
d. None of the above

43) What are preroutes in your design?

Power routing
b. Signal routing
c. Power and Signal routing
d. None of the above.

44) Clock tree doesn't contain following cell ___.

Clock buffer
b. Clock Inverter
c. AOI cell
d. None of the above