Kamparaju Kasi Rao
Design Verification Engineer
Mob. no : +91 9014368791
Email :
[email protected] LinkedIn : https://www.linkedin.com/in/kasirao-k
Career Objective
To work as a Design and Verification engineer applying my knowledge in the field of testing, designing and
maintenance to cater to the specific needs of the organization. I wish to work in a team of motivated
individuals who wish to work towards the advancement of the company and its goals.
Professional Training
Advanced VLSI Design And Verification Trainee at Maven Silicon VLSI Training Centre,Bangalore.
- June 2023 - present
Digital Design with Verilog at NPTEL-IIT Guwahati - Jan 2024 - April 2024
Hardware Modeling Using Verilog at NPTEL-IIT Kharagpur - July 2023 - September 2023
Education
Graduation Course : B.Tech (Electronics and Communication Engineering)
College : Aditya Institute of Technology& Management(AITAM),Tekkali(AP)
CGPA : 8.32 - Year of passing : 2023
Diploma Course : Electronics and Communication Engineering
College : ESC Govt Polytechnic College,Nandyal(AP)
Percentage : 82.25 - Year of passing : 2020
Schooling Course : Secondary School Certificate ( 10th class)
School : Z . P . H . School,Prakasam(AP)
CGPA : 8.7 - Year of passing : 2017
Foundation Skills
Design Skills : Digital Electronics: Combinational & Sequential circuits, FSM, Memories, CMOS.
HDL : Verilog.
Operating system : Linux, Windows.
Languages : C,DataStructure,Python,Arduino IDE,OOPs concept.
VLSI Domain Skills
HDL : Verilog .
HVL : System Verilog.
Verification Methodologies : CRCDV,Assertion Based Verification - SVA ,VC SpyGlass.
TB Methodology : UVM.
Protocols : AHB,APB.
EDA Tool : Mentor Graphics - Questasim and Xlinix - ISE, Xilinx - Vivado.
Domain : ASIC/FPGA front-end Design and Verification.
Scripting Languages : Perl Scripting.
Design Skills
Digital Electronics
STA
Verilog
Advanced Verilog
Code Coverage
Verification Skills
System Verilog
System Verilog Assertions
UVM
Projects
1.AHB2APB Bridge IP Core Verification
HVL : System Verilog
TB Methodology: UVM
EDA Tools : Questasim and ISE
Description : The AHB to APB bridge is an AHB slave which works as an interface between the
high speed AHB and low performance APB buses.
2.Router 1x3 – RTL design and Verification
HDL : Verilog HDL
HVL : System Verilog
TB Methodology: UVM
EDA Tools : Questasim and ISE
Description : Router that accepts data packets on a single 8-bit port and routes them to one of the
three output channels with parity checking mechanism.The top module of the route
consists of 4 sub-modules named as FIFO, Synchronizer, FSM, Register.
3.An efficient VLSI Design & Simulation of RISC based MIPS Processor
HDL : Verilog HDL
Tools : Xilinx, Modelsim
Description : The Main objective of this project is to create the design of a RISC CPU architecture
based on MIPS using verilog HDL. It also describes the instruction and timing diagram
of the processor.
Certification
1. Digital Design with Verilog at NPTEL.
2. Hardware Modeling Using Verilog at NPTEL.
Soft Skills
Leadership
Quick learning
Time Management
Hobbies
Playing Cricket
Cooking
Listening Music
Declaration
I hereby declare all the information given above is true and correct to the best of my knowledge.
Date :
Place :Bangalore K.Kasi Rao
