HDL & FPGA
Lecture 7. Finite State Machine
Huỳnh Việt Thắng
Faculty of Electronics & Telecommunication Engineering
Danang University of Science and Technology
[email protected] Jun 2023
Contents
• Introduction
– Moore-style and Mealy-style FSMs
– FSM representation: State diagram & ASM chart
• FSM code development
• Exercise
– Sequence detector 1
– Sequence detector 2
• Design examples
– Rising edge detector
– Debouncing circuit
Mealy & Moore Outputs
FSM representation
• An FSM is usually specified by
– State diagram
– or, Algorithmic State Machine chart (ASM)
• The FSM representation is more compact and
better for simple applications
• The ASM chart representation is somewhat like a
flowchart and is more descriptive for applications
with complex transition conditions and actions
State diagram
• Node of a state diagram
ASM chart
• An ASM block
Example of an FSM
• Block Diagram
• FSM state diagram
– y0: Mealy output
– y1: Moore output
a
b y0
fsm_eg_mult_seg
y1
clk
reset
Example of an
FSM (cont.)
• ASM chart
State diagram vs
ASM chart
FSM code development
Internal signal declaration
• 3 code segments:
– State register
– Next-state logic
– Output logic
Representation of FSM’s states
• During synthesis, software usually can recognize the FSM
structure and may map these symbolic constants to
different binary representations (e.g., one-hot codes), a
process known as state assignment
Listing 5.1: the full code
Code for Listing 5.1
Test bench: an example
Waveform
Listing 5.1 code downloadable
https://dutudn-
my.sharepoint.com/:f:/g/personal/thanghv_dut_udn_vn/Egvn5cz
YkwlPksIGrrKraXYBX7WsIs3rcaBgTfSaeaJfvg?e=Ko5s3y
Listing 5.2: FSM with merged combinational logic
Exercise 1: Sequence Detector 1
• Write Verilog code and test bench for the
following FSM (sequence detector)
Exercise 2: Sequence Detector 2
• Design a sequence detector circuit that operates as
follows:
– The circuit has 1 input signal w, 1 output signal z, 1 clock signal
clk (rising edge), 1 reset signal active high
– output signal z = 1 if input sequence w = “1001” or w = “101”
– otherwise, the output signal z = 0
• Requirements:
– Draw the block diagram of the circuit/FSM
– Draw the state transition diagram of the FSM (Hint: 5 states)
– Write Verilog HDL code for the FSM
– Write test bench to verify the operation of the FSM
More examples
• Rising-edge detector (section 5.3.1 page 125)
• Debouncing circuit (section 5.3.2 page 130)
• Testing circuit (section 5.3.3 page 133)
