Microelectronics Reliability 115 (2020) 113965

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Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel

The role of SiN/GaN cap interface charge and GaN cap layer to achieve
enhancement mode GaN MIS-HEMT operation
K. Ahmeda a, *, B. Ubochi b, M.H. Alqaysi c, A. Al-Khalidi d, E. Wasige d, K. Kalna e
a
Cardiff School of Technologies, Cardiff Metropolitan University, Llandaff Campus, Western Avenue, Cardiff, CF5 2YB, Wales, United Kingdom
b
Department of Electrical and Electronics Engineering, The Federal University of Technology, Akure, Nigeria
c
Middle Technical University, Baghdad, Iraq
d
School of Engineering, University of Glasgow, G12 8LP, Scotland, United Kingdom
e
Nanoelectronic Devices Computational Group, College of Engineering, Swansea University, Bay Campus, Fabian Way, Swansea SA1 8EN, Wales, United Kingdom

A R T I C L E I N F O A B S T R A C T

Keywords: The thickness increase of gallium nitride (GaN) cap layer from 2 nm to 35 nm to achieve an enhancement mode
GaN HEMT GaN MIS-HEMT (Metal-Insulator-Semiconductor High-Electron-Mobility Transistor) with a threshold voltage
Enhancement mode (Vth) of +0.5 V is studied using TCAD simulations. The simulations are calibrated to measured I-V characteristics
Interface traps
of the 1 μm gate length GaN MIS-HEMT with the 2 nm thick GaN cap. A good agreement at low and high drain
Parasitic channel
voltages (VDS=1 V and 5 V) between simulations and measurements is achieved by using a quantum-corrected
Cap layer
drift-diffusion transport model. The enhancement mode GaN MIS-HEMT with a GaN cap thickness of 35 nm
achieves Vth = + 0.5 V thanks to positive interface traps occurring between the SiN passivation layer and the GaN
cap as reported experimentally. The simulations indicate that a parasitic channel is created at the interface
between the SiN layer and the 35 nm GaN cap. Our study also shows an increase in the breakdown voltage from
100 V to 870 V when a thickness of the GaN cap layer increases from 15 nm to 35 nm.

1. Introduction research is underway to achieve an enhancement mode GaN HEMT (a

normally-off device operation) to improve the reliability of the transistor
The ongoing research activities on III-Nitrides are driven by the in switching circuits and thus to meet the stringent requirements in
development of advanced types of GaN based devices for decisive op­ power circuit operations, for example, for automotive applications [6].
tical, sensor, power, and RF applications with an excellent performance The enhancement mode of GaN HEMT operation can be achieved by
and a good energy consumption. One of the most perspective GaN based various changes in the device architecture or in the manufacturing
devices is a High Electron Mobility Transistor (HEMT) [1,2] for power process like i) reducing the AlGaN barrier down to 3 nm [7], ii) making a
amplifiers, radar monitoring, and wireless communications. GaN has recessed gate [8], iii) using a dual-gate [9], iv) using a p-type doping of
exclusive material properties such as an energy bandgap of 3.4 eV, a the GaN gate [10], v) making an N-polar GaN [11], vi) using the carbon
great breakdown electric field of 3.3 MV/cm, a large value of electron tetrafluoride (CF4) plasma treatment technique [12], or vii) introducing
mobility in a two-dimensional electron gas (2DEG) of 2000 cm2/Vs, a an InGaN cap layer of about 5 nm to achieve the polarization induced
high saturation velocity of 2.5×107 cm/s, a low relative permittivity of electrostatic potential rising the conduction band [13]. However, many
8.9, and a large thermal conductivity (κ) of 130 Wm− 1K− 1 [3,4]. of these solutions result in decrease in a drive current and negatively
Furthermore, a 2DEG at the interface of an AlxGa1− xN barrier and a GaN affect device reliability [14]. For example, the introduction of GaN cap
substrate might have a sheet density exceeding 1013 cm− 2 which occurs layer, in order to protect a surface of GaN HEMT against surface trap
without doping of the AlxGa1− xN barrier due to a combination of the generation, will substantially decrease the drain current [15].
spontaneous and the piezoelectric polarization. This polarization creates In this paper, we investigate the impact of increasing cap layer
the 2DEG making an AlxGa1− xN/GaN HEMT to operate in the depletion thickness aiming to achieve the enhancement mode transistor operation.
mode (a normally-on device operation) which then requires first to We reported that the increase in a cap layer thickness can lead to drop in
apply a negative bias in switching circuits [5]. Therefore, intensive the drain current [15]. Modifying the cap layer thickness together with

* Corresponding author.
E-mail address: [email protected] (K. Ahmeda).

https://doi.org/10.1016/j.microrel.2020.113965
Received 10 March 2020; Received in revised form 22 August 2020; Accepted 22 September 2020
Available online 23 October 2020
0026-2714/© 2020 Elsevier Ltd. All rights reserved.
K. Ahmeda et al. Microelectronics Reliability 115 (2020) 113965

2 m 3 m
Gate 600
Source Drain Measurement VD=5V
SiN 10 nm

Drain Current ID(mA/mm)

500 Simulation VD=4V
GaN cap 2 nm 400 VD=3V
AlGa N Barrier
0.25 0.75
300
VD=2V
20 nm 200
AlN 1 nm VD=1V
100
GaN Substrate 0
3 m -6 -5 -4 -3 -2 -1 0
Gate Voltage VGS(V)
Fig. 1. Cross-section of the simulated i-GaN capped MIS-HEMT.
Fig. 2. The calibration of IDS-VGS characteristics obtained from drift-diffusion
simulations against experimental data at VDS from 1 V to 5 V with a step of
the gated recess etching led to an increase in a contact resistance from 1 V.
1.0 Ω.mm to 4.0 Ω.mm [16] and an increase in a drain current [17]. The
reason is that the capped layer changes the spread of electric field cm− 2 [34] than a pure SiN or SiO2 density of 1×1011 cm− 2 [35] owing to
increasing the electric field in the AlGaN layer while reducing the the increase of Si dangling bonds at the interface which act as ionized
electric field in the GaN cap [18]. Thus, the thin GaN cap layer mini­ donors [33]. These ionized donors incompletely neutralize the negative
mizes the surface related current collapse when applying a high electric polarization charge at a barrier surface [27]. This positive interface
field stress [19]. However, further increase of the GaN cap layer limits charge between a passivation layer and III-nitride materials also helps to
the electron density in the 2DEG channel [20]. minimise the current collapse [30].
As the GaN cap thickness is only 2 nm and the interface donor traps
2. Simulation method exist at the interface between the SiN passivation layer and the GaN cap
layer, we have used a volume representation model to represent the
Fig. 1 presents device architecture of the 1 μm gate length GaN MIS- donor interface traps. The assumed donor trap concentration in the 2 nm
HEMT. This device is passivated with a 10 nm SiN, has a 2 nm thick n- GaN cap is 4.5×1019 cm− 3 at an energy level of ET = EC − 0.5 eV [36],
type uniformly doped GaN cap, a 20 nm Al0.25Ga0.75N barrier layer which is equivalent to a sheet concentration of 9×1012 cm− 2 at the
thickness, a 1 nm AlN spacer layer to improve channel quantum interface. Fig. 2 shows a calibration of the simulated IDS-VGS charac­
confinement, and a 3 μm GaN substrate. The distance between the drain teristics at VDS=1 V, 2 V, 3 V, 4 V, and 5 V against the actual measured
and the gate is 3 μm and the distance between the source and the gate is data. These transfer characteristics exhibit a very good agreement be­
2 μm. Ohmic contacts made of a composite metal consisting of Ti/Al/Ni/ tween the measurement and the calibration obtained from simulations
Au 30/180/40/100 nm are deposited directly on the SiNx passivation using Atlas, a commercial tool by Silvaco [37].
layer [21,22] followed by the Rapid Thermal Annealing (RTA) at an In the calibration of the device IDS-VGS characteristics to experi­
optimized temperature of 800oC for a duration of 30 s. The 1 μm gate mental data, we employed a drift-diffusion transport model. In these
length GaN MIS-HEMT has a background n-type doping concentration of drift-diffusion simulations, we use a combination of the parallel field
1× 1016 cm− 3. We assume that iron (Fe) traps at an energy level of ET = mobility model and the Albrecht mobility model [38]. The parallel field
EC − 0.36 eV and with a density of 5×1017 cm− 3 are present in the GaN mobility model is calibrated using a low-field effective electron mobility
substrate [23]. of 925 cm2/V.s which embeds also the impact of source/drain resis­
The SiNx passivation layer contains shallow donor-like traps with tance, and an electron saturation velocity of 1.15×107 cm/s. The
energy levels in the range of EC − ET ⩽ 0.30 eV [24] (referred to also as Albrecht mobility mode reproduces Monte Carlo simulations of electron
the border traps) in SiN-passivated AlGaN/GaN HEMTs. These interface transport for a wurtzite GaN [38]. The Albrecht mobility model reads:
traps can be unoccupied or occupied [25] and thus behave at the
( ) ( )− 32 ( )
interface either as a positive charge when the donor traps are unoccu­ 1 N1 ( ) T T c
(1)
2 3
=a ln 1 β b ( )
pied or be neutral when the traps are occupied. Unoccupied shallow + + 2 +
CW
μ 1017 cm− 3 300K 300K exp ΘT − 1
donor-like traps will induce a positive charge at the interface of the SiN
layer and the AlGaN barrier which compensates a large negative po­
larization present normally at the surface of the AlGaN barrier in a Ga- where:
face AlGaN/GaN heterostructure. The compensation of this large nega­ ℏωLO
Θ= = 1065 K
tive polarization at the interface of the AlGaN barrier leads to a 2DEG κB
formation in the channel as opposed to free surface states at the AlGaN ( )2 ( )− 2
barrier in heterostructures with a Schottky gate metal [26]. The exper­ β2CW = 3
T NI 3

imental evidence for this interface donor-like traps in a SiN layer is 300K 1017 cm− 3
based on the fact that comparable 2DEG density values from 0.8×1013
The quantities in Eq. (1) are defined as follows:
cm− 2 to 1.2×1013 cm− 2 [27] in the SiN passivated AlGaN/GaN HEMTs
can be achieved by the Si deposition on the surface of AlGaN. The SiN
NI=(1 + κc)ND, a=2.61×10− 4 V.s.cm− 2, b=2.90×10− 4 V.s.cm− 2, and
interface is therefore believed to have a high positive interface charge
c=1.70×10− 2 V.s.cm− 2, ND is the ionized donor concentration, T is
density of 2×1013 cm− 2 [28].
the ambient temperature, and κc = NNAD is the compensation ratio. In
This positive interface charge between a dielectric layer (Al2O3,
SiON, SiNx) and an III-nitride material has been widely reported in the addition, our simulations employ Shockley-Read-Hall (SRH) model
literature [29–33]. Different dielectric layer materials used as a passiv­ for carrier generation and recombination together with Fermi-Dirac
ation layer induce various positive interface charge densities [32,33]. statistics, and quantum corrections using Schrödinger equation so­
For example, the SiON has a higher fixed charge density of 1.3×1013 lutions across the channel.

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K. Ahmeda et al. Microelectronics Reliability 115 (2020) 113965

passivation dielectric layer and the III-nitride layer, Vth(MIS − HEMT)

stands for the threshold voltage of a metal-insulator-semiconductor
high-electron mobility transistor and Cdielectric is the capacitance of a
dielectric layer.
The cross-section of a proposed enhancement mode device is shown
in Fig. 3. The device architecture is optimized to obtain a normally-off
(the enhancement mode operation) transistor by increasing the GaN
cap thickness from 2 nm to 15 nm, 20 nm, 25 nm, 30 nm and 35 nm in
the 1 μm gate length GaN/Al0.25Ga0.75N/GaN/Al0.075Ga0.925N/
Al0.1Ga0.9N MIS-HEMT but the SiN passivation layer is reduced to 5 nm
[40]. However, a two-dimensional hole gas (2DHG) exists between the
GaN cap layer and the AlGaN barrier alongside the 2DEG when the cap
layer increases more than 10 nm [41]. As the GaN cap thickness is
increased, the AlGaN barrier is kept at the same thickness of 20 nm. The
GaN channel thickness is reduced to 20 nm and two layers of AlGaN
back-barriers are added with different compositions to increase the
quantum confinement of the 2DEG. The GaN channel thickness reduc­
tion to 20 nm and the two layers of low aluminium content back-barriers
help to achieve the normally-off operation [42,43]. The GaN channel is
assumed to have an unintentional background doping concentration of
1×1016 cm− 3.
An iron (Fe) doped GaN channel will inevitably have Fe induced
acceptor energy levels of traps (ET) which can vary from 0.28 eV to 1.0
eV [23,44,45] and have been reported to reduce the substrate-related
Fig. 3. The architecture of a new proposed enhancement mode GaN current collapse when compared to a carbon (C) doped GaN channel
MIS-HEMT. [46,47]. In our study, the Fe induced acceptor traps are located in the
GaN channel at an energy level of ET=EC-0.36 eV with a concentration of
3. Proposed enhancement mode GaN MIS-HEMTs 7×1017 cm− 3 [23] and electron and hole capture cross-sections of σn, p =
1×10− 15 cm2 [48]. The hole concentration in the AlGaN back-barrier is
Enhancement mode MIS-HEMTs are required to avoid the need for a achieved using a polarization doping by ionized Mn acceptors [49,50]. A
negative voltage supply in power switches or in MMICs which leads to Mn concentration of 3×1016 cm− 3 with an energy level at ET=EV + 1.4
unnecessary power loss and impairs circuit safety requirements [39]. eV [51] above the valence band is assumed in the Al0.075Ga0.925N with a
Therefore, in this work, we carried out a research on the effect of the thickness of 20 nm. This layer with a low aluminium concentration is
positive interface charge between the SiN passivation layer and the GaN chosen to avoid any mismatch between the GaN substrate and the AlGaN
cap on the device performance to achieve an enhancement mode oper­ back-barrier layer. Finally, the Al0.1Ga0.9N double back-barrier layer has
ation by increasing the thickness of the GaN cap layer up to 35 nm. The a thickness of 3 μm and is p-type doped with a concentration of
positive interface charge at the interface between dielectric (Al2O3, 1.25×1018 cm− 3.
SiON, SiNx) and III-nitride materials such as GaN, AlxGa1− xN, and AlInN The proposed device structure is simulated at a low drain voltage of
[29–33] leads to the increase of a 2DEG density and improves the VDS = 1 V and a high drain voltage of VDS = 5 V as shown in Fig. 4(a) and
switching performance of GaN MIS-HEMTs. The relationship between (b), respectively. Shockley-Read-Hall (SRH) generation and recombi­
Vth and the positive interface charge is given by [31,33]: nation, Fermi-Dirac statistics, and quantum corrections via solutions of
( ) ( ) Schrödinger equation are consistently used as before. The positive
Vth = Vth MIS − HEMT − Vth HEMT = −
Qf
(2) interface charge with a concentration of 5.25×1012 cm− 2 (or 0.84
Cdielectric μCcm− 2) is placed at the interface between the 5 nm SiN passivation
layer (dielectric layer) and the GaN cap layer for all cap thicknesses. A
where Qf is the positive fixed charge at the interface between the
capacitance of the SiN dielectric layer can be calculated as Cdielectric =

65 270
60 GaN cap 15 nm GaN cap 15 nm
240
GaN cap 20 nm
Drain Current ID(mA/mm)

55
Drain Current ID(mA/mm)

GaN cap 20 nm
50 210
GaN cap 25 nm GaN cap 25 nm
45
GaN cap 30 nm 180 GaN cap 30 nm
40
35 GaN cap 35 nm 150 GaN cap 35 nm
30 120
25
20 90
15 (a) 60 (b)
10 VDS=1 V VDS=5 V
30
5
0 0
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Gate Voltage VGS(V) Gate Voltage VGS(V)

Fig. 4. Simulations of transfer (IDS-VGS) characteristics at low and high drain voltages of VDS=1 V (a) and VDS=5 V (b) for the 1 μm gate length GaN MIS-HEMT with a
varying thickness of the GaN cap layer of 15 nm, 20 nm, 25 nm, 30 nm, and 35 nm assuming a positive interface charge of 5.25×1012 cm2.

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K. Ahmeda et al. Microelectronics Reliability 115 (2020) 113965

3 4
10 10
3
10
(a)
2
10
(b)
2
Drain Current ID(mA/mm) 10

Drain Current ID(mA/mm)

1
10
1
10
0
0
10
10 10
-1

-1 VDS= 1 V 10
-2 VDS= 5 V
10 -3
10
-2 -4
10 10 GaN cap 15 nm
GaN cap 15 nm -5
-3 10
10 GaN cap 20 nm 10
-6 GaN cap 20 nm
-7
10
-4
GaN cap 25 nm 10
-8
GaN cap 25 nm
10
10
-5
GaN cap 30 nm 10
-9 GaN cap 30 nm
10
-6
GaN cap 35 nm 10
-10

-11
GaN cap 35 nm
10
-7 -12
10 10
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
Gate Voltage VGS(V) Gate Voltage VGS(V)

Fig. 5. Transfer characteristics (IDS-VGS) of the 1 μm gate length GaN MIS-HEMT, showing the sub-threshold region, as a function of gate voltage and the different
GaN cap layer thicknesses at a low drain voltage of VDS=1 V (a), and a high drain voltage of VDS=5 V (b).

110 130
GaN cap 15 nm 120 (b)
100 (a)
Transconductance (mS/mm)

Transconductance (mS/mm)
GaN cap 20 nm 110
90 GaN cap 15 nm
GaN cap 25 nm 100
80 GaN cap 30 nm GaN cap 20 nm
90
70 GaN cap 35 nm 80 GaN cap 25 nm
60 70 GaN cap 30 nm
50 60 GaN cap 35 nm
40 50
VDS= 1 V 40
30
30
VDS=5 V
20
20
10 10
0 0
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Gate Voltage VGS(V) Gate Voltage VGS(V)

Fig. 6. Transconductance of the 1 μm gate length GaN MIS-HEMT as a function of gate voltage and different GaN cap layer thicknesses at a low drain voltage of
VDS=1 V (a) and a high drain voltage of VDS=5 V (b), respectively.

εSiN/t. Assuming the SiN permittivity (εSiN) of 7.0 and t=5 nm, transistors at low and high drain voltages of VDS=1 V and VDS=5 V,
Cdielectric=1.24 μFcm− 2. Eq. (2) would thus predict an increase in a respectively. The threshold voltage shifts from − 0.5 V, when using the
threshold voltage shift of − 0.68 V relative to the threshold voltage of a 15 nm GaN cap, up to 0.5 V when using the 35 nm GaN cap layer. We see
Schottky gate HEMT, a desirable improvement that brings the device also an increase in the drain current from 40 mA/mm when using the 15
closer to the enhancement mode operation. The calculated threshold nm GaN cap to 60 mA/mm when using the 35 nm cap. It was reported
voltage shift for a density of positive interface charge of 5.25×1012 cm− 2 that increasing the thickness of GaN cap layer would reduce the electron
is consistent with the results in [33] where shifts in the threshold voltage density in 2DEG channel [41].
of − 4.0 V and − 10.0 V were obtained for GaN transistors having a To test this approach, we place a positive interface charge between
density of positive interface charge of 1.54× 1013 cm− 2 and 2.71× 1013 the SiN and the GaN cap layer by varying of the cap thicknesses in
cm− 2, respectively. simulations. As the result, the drain current increases by 62% and 60%
The positive interface charge, due to Si donors at the interface of the at low and high drain biases which corresponds to the increase from 150
SiN passivation and the GaN cap, was reported experimentally with the mA/mm at the 15 nm GaN cap up to 240 mA/mm at the 35 nm GaN at
value ranging from 8×1012 cm− 2 to 2×1013 cm− 2 [28]. Our simulations VDS = 5 V as shown in Fig. 4(b).
assume that the positive interface charge is 5.25×1012cm− 2, the value Fig. 5 shows a sub-threshold leakage current for the 1 μm gate GaN
close to that reported in Refs. [28, 33]. MIS-HEMT as a function of gate voltage for a different GaN cap layer
thicknesses at a low drain voltage of VDS = 1 V in Fig. 5(a) and at a high
4. The impact of GaN cap drain voltage of VDS = 5 V in Fig. 5(b). Fig. 6 presents transconductance
simulations for the 1 μm gate length GaN MIS-HEMT for several GaN cap
The threshold voltage Vth of the original experimental GaN MIS- layer thicknesses. Fig. 6(a) shows the simulations of transconductance at
HEMT is about − 4.5 V as shown in Fig. 2. Fig. 4(a) and (b) show a low drain voltage of VDS = 1 V giving its highest values at 95 mS/mm
transfer (IDS-VGS) characteristics of the proposed enhancement mode for the 35 nm thick GaN cap. Fig. 6(b) shows the simulations of

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K. Ahmeda et al. Microelectronics Reliability 115 (2020) 113965

3 10
19

C.B (a) (b)

Electron concentration (cm )

18

-3
parasitic channel 10
2 17
10
16 15 nm
1 10 20 nm
15
10 25 nm
Energy (eV)

0 14
30 nm
10
15nm 13 35 nm
-1 Quasi Fermi Level 10
20nm 12
25nm 10
-2 30nm 10
11

35nm 10
10
-3 9
10
8
-4 10
V.B 7
10
0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Distance (μm) Distance (μm)
Fig. 7. (a) Conduction (C.B) and valence (V.B) band profiles of the proposed enhancement mode HEMT at equilibrium (VDS=0 V and VGS=0 V), and (b) electron
concentration for increasing thickness of the GaN cap from 15 nm to 35 nm with a step of 5 nm. No 2DEG channel is formed at the GaN cap thickness of 35 nm as
indicated by the black circle. The location of a parasitic electron channel (black arrow) and the quasi Fermi level (blue dash-dot line) is also indicated. (For
interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)

0
3.0 10
2.5
C.B (a) (b)
Hole Concentration (cm )
-3

2.0 parasitic channel -10

10
1.5
Energy (eV)

1.0
-20
0.5 10
0.0
-0.5 -30
15 nm
-1.0 20 nm
10
Quasi Fermi Level
-1.5 25 nm
-2.0 30 nm -40
10 15nm
35 nm
-2.5 20nm
-3.0 25nm
-50
-3.5 10 30nm
-4.0 35nm
-4.5 V.B -60
10
0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Distance (μm) Distance (μm)
Fig. 8. (a) Conduction (full red lines) and valence (full black lines) band profile of the proposed enhancement mode MIS-HEMT at equilibrium (VDS = 0 V and VGS =
0 V), and (b) hole concentration for increasing thickness of the GaN cap from 15 nm to 35 nm with a step of 5 nm. The location of a parasitic electron channel (black
arrow) and the quasi Fermi level (blue dash-dot line) is also indicated. (For interpretation of the references to color in this figure legend, the reader is referred to the
web version of this article.)

transconductance at a high drain voltage of VDS = 5 V giving its highest to the surface and effectively works as a potential barrier between the
value at 120 mS/mm for the 35 nm thick GaN cap. The increase in gate and the channel [41]. However, the 2DHG channel that was re­
transconductance originates from the creation of a parasitic 2DEG ported in the literature does not play a role in the proposed enhancement
channel at the interface of the SiN layer and the GaN cap because a mode device as its concentration is very low. There is a shift up in the
conduction band offset increases as the thickness of the GaN cap in­ conduction band energy profile which is visible at a GaN cap thickness of
creases. This parasitic 2DEG channel also contributes to the increase in 35 nm with no 2DEG channel created at the equilibrium. However, the
the drain current. A low value of positive interface charge improves the occurrence of a positive interface charge at the interface between the
performance of GaN MIS-HEMT [52]. The reduction in the positive SiN passivation layer and the GaN cap creates there an extra parasitic
interface charge can be achieved by oxygen plasma and post metalli­ electron channel.
zation annealing (PMA) treatment which enables to engineer the The shallow donor-like traps responsible for the positive charge at
threshold voltage (Vth) from − 7 V to − 4 V [28]. the interface of the SiN/GaN-cap can get occupied by electrons and
Figs. 7 and 8 show the conduction band profiles for different thick­ become neutral. Therefore, we also simulate the 1 μm gate length GaN
ness of the GaN cap layers at the equilibrium together with electron and MIS-HEMT assuming that only the deep donor interface traps at an en­
hole concentrations at a surface potential of 1.25 eV. A two-dimensional ergy level of ET=EC-0.5 eV [36] are present at the interface of the SiN
hole gas (2DHG) is created at the interface between the GaN cap and the passivation layer and the GaN cap. Fig. 9 shows the simulations of
AlGaN barrier after the thickness of the GaN cap layer increases above transfer (IDS-VGS) characteristics for the 1 μm gate length GaN MIS-
10 nm [41] and further as shown in Fig. 8. The 2DHG remains very close HEMT with varying cap layers with a thickness of 15 nm, 20 nm, 25

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K. Ahmeda et al. Microelectronics Reliability 115 (2020) 113965

5. The effect of parasitic channel

35
15 nm GaN cap
30 20 nm GaN cap The increasing of a thickness from 15 nm to 20 nm, 25 nm, 30 nm,
Drain Current ID(mA/mm)

25 nm GaN cap and 35 nm of the GaN cap with the positive interface charge presents
25 between SiN passivation layer and GaN cap layer creates a parasitic
channel. The formation of the parasitic channel at the interface between
20 these two layers is due to increase of the potential applied on the drain
[53]. Experimental work confirms the presence of a parasitic channel
15 induced by the on-state stress, originating from applied external fields,
VDS= 1V which occurs after ageing the device for many hours [54]. The location
10 of the parasitic channel is assumed to be between the gate and the source
30nm and 35nm GaN cap
5 but not under the gate. However, our simulations reveal that the loca­
tion of the parasitic channel is between the dielectric layer and the GaN
0 cap layer. The existence of the parasitic channel explains the drain
-2.0-1.5-1.0-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 current increment as the GaN cap layer is increased as shown in Figs. 4
Gate Voltage VGS(V) and 5. This can be contributed to electrons moving from the interface
between the SiN passivation layer and the GaN cap into the 2DEG
channel. Our simulations show that electron concentration in the 2DEG
Fig. 9. Simulations of transfer (IDS-VGS) characteristics at a low drain voltage of
VDS=1 V for the 1 μm gate length GaN MIS-HEMT with a varying cap layer with
channel is reduced while the GaN cap thickness is increased. This leads
a thickness of 15 nm, 20 nm, 25 nm, 30 nm, and 35 nm and a deep donor to the increase of electron concentration in the parasitic channel. This
interface trap concentration of 9×1012 cm− 2 located at the interface of the SiN increase of electron concentration has a crucial impact on the increase in
passivation layer and the GaN cap. the drain current and the transconductance.

nm, 30 nm, and 35 nm with the deep donor interface traps at a low drain 6. Breakdown voltage
voltage of VDS=1 V. We assume an interface trap density of 9×1012 cm− 2
because the electron sheet density has to be the same for various GaN One of the most important figures of merit in power devices is the
cap layer thicknesses. The electron sheet density (Ns) is given by Ns = Ni. breakdown voltage (BV) required for a reliable performance at high
d, where Ni is the donor density in the GaN cap layer and d is the temperatures and in high power applications [55]. Several research
thickness of GaN cap layer. studies in the literature have been reported to improve and optimize the
Increasing the cap thickness will cause a lowering of 2DEG density in breakdown voltage (BV) such as a floating gate [56], an increase in the
the channel and a formation of the higher 2DHG density [41], and thickness of the epitaxial-layer [57], a source extended field plate,
leading to a drop in the drain current and a slight shift of the threshold several field plates [58], and Schottky contact in the drain [59].
voltage to more positive values as shown in Fig. 9. Fig. 9 also demon­ A simulation of the device breakdown voltage requires to establish
strates that these donor interface traps have a detrimental impact on the impact ionization coefficients needed for an impact ionization model.
drain current because the maximum drain current (at VDS=1 V) de­ Impact ionization coefficients for electrons (αn) and holes (αp), we have
creases by 50%, 84%, and, finally, practically by 99% and 99.9%, with used, are given by [60–62]:
respect to the drain current in the 15 nm thick GaN cap transistor, when ( ) (
B
)
the cap layers thickness increases from 15 nm to 20 nm, 25 nm, 30 nm, αn E = An exp − n (3)
E
and 35 nm, respectively.

15 nm GaN cap 30 nm GaN cap

20 nm GaN cap 35 nm GaN cap
25 nm GaN cap

Fig. 10. (a) Simulations of a breakdown voltage for the 1 μm gate length GaN MIS-HEMT with the 15 nm, 20 nm and 25 nm, and (b) with the 30 nm and 35 nm GaN
cap layer thicknesses assuming a positive interface charge of 5.25×1012 e/cm− 2.

6
K. Ahmeda et al. Microelectronics Reliability 115 (2020) 113965

( ) ( )
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