Fds 9953 A
Fds 9953 A
May 2001
FDS9953A
Dual 30V P-Channel PowerTrench MOSFET
DD1 5 4
DD1
DD2 6 Q1
3
D2
D
7 2
SO-8 G1 Q2
S1 G 8 1
G2 S
S2 S
Pin 1 SO-8 S
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
RθJ C Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
Off Characteristics
BV DSS
Drain–Source Breakdown V GS = 0 V, ID = –250 µA –30 V
Voltage
∆BV DSS Breakdown Voltage Temperature ID = –250 µA, Referenced to 25°C –23 mV/°C
∆TJ Coefficient
IDSS Zero Gate Voltage Drain Current V DS = –24 V, V GS = 0 V –2 µA
IGSSF Gate–Body Leakage, Forward V GS = –25 V, V DS = 0 V –100 nA
IGSSR Gate–Body Leakage, Reverse V GS = 25 V, V DS = 0 V 100 nA
On Characteristics (Note 2)
Dynamic Characteristics
Ciss Input Capacitance 185 pF
V DS = –15 V, V GS = 0 V,
Coss Output Capacitance 56 pF
f = 1.0 MHz
Crss Reverse Transfer Capacitance 26 pF
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
10 3.5
V GS = -10V
-6.0V
DRAIN-SOURCE ON-RESISTANCE
3
8 V GS = -3.5V
-4.5V
-I D, DRAIN CURRENT (A)
RDS(ON), NORMALIZED
2.5
6 -4.0V
-4.0V
2
-4.5V
4 -5.0V
-3.5V 1.5
-6.0V
2 -10V
1
-3.0V
0.5
0
0 2 4 6 8 10
0 1 2 3 4 5
-ID , DRAIN CURRENT (A)
-V DS , DRAIN-SOURCE VOLTAGE (V)
1.6 0.5
ID = -1A
VGS = -10V ID = -0.5 A
DRAIN-SOURCE ON-RESISTANCE
1.4 0.4
RDS(ON), NORMALIZED
1.2 0.3
T A = 125o C
1
0.2
T A = 25o C
0.8
0.1
0.6
-50 -25 0 25 50 75 100 125 150 0
2 4 6 8 10
T J, JUNCTION TEMPERATURE ( oC) -V GS, GATE TO SOURCE VOLTAGE (V)
10
6
VGS = 0V
V DS = -5V T A = -55oC
-I S, REVERSE DRAIN CURRENT (A)
25o C
5 1
125o C T A = 125o C
-I D, DRAIN CURRENT (A)
4
0.1
25o C
3
0.01
2 -55o C
0.001
1
0.0001
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4
1.5 2 2.5 3 3.5 4 4.5
-V SD, BODY DIODE FORWARD VOLTAGE (V)
-V GS, GATE TO SOURCE VOLTAGE (V)
10 300
ID =-1.0 A V DS = -5V
-10V
f = 1MHz
-V GS, GATE-SOURCE VOLTAGE (V)
250 VGS = 0 V
8
CISS
CAPACITANCE (pF)
-15V 200
6
150
4
100
COSS
2
50
CRSS
0 0
0 1 2 3 4 5 0 5 10 15 20 25 30
Qg, GATE CHARGE (nC) -V DS, DRAIN TO SOURCE VOLTAGE (V)
100 50
SINGLE PULSE
P(pk), PEAK TRANSIENT POWER (W)
RθJA = 135°C/W
100µs 40 TA = 25°C
10 RDS(ON) LIMIT
-ID, DRAIN CURRENT (A)
1ms
10ms 30
100ms
1 1s
10s
20
DC
V GS = -10V
0.1 SINGLE PULSE
RθJA = 135o C/W 10
T A = 25o C
0.01 0
0.1 1 10 100 0.001 0.01 0.1 1 10 100
-V DS , DRAIN-SOURCE VOLTAGE (V) t 1, TIME (sec)
Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.
1
D = 0.5
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE
0.2
RθJA(t) = r(t) + RθJA
RθJA = 135 °C/W
0.1 0.1
0.05
P(pk)
0.02
0.01
t1
0.01 t2
TJ - TA = P * RθJA(t)
SINGLE PULSE Duty Cycle, D = t 1 / t2
0.001
0.0001 0.001 0.01 0.1 1 10 100 1000
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.
Definition of Terms
Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Rev. H2