Welcome to
Faculty Orientation Workshop, TE (E&TC)
Under the aegis of Board of Studies
Electronics & Telecommunications, SPPU Pune
On
“Embedded Processors [301495]”
Unit-5: Real World Interfacing with Cortex M4 Based
Microcontroller
Date: February 02, 2022 ,[10.00 am to 12.00 PM]
By
Prof. Harshad N. Lokhande
Department of Electronics and Telecommunication Engineering,
NBN Sinhgad School of Engineering, Ambegaon Bk, Pune -411041
Syllabus
GPIO Programming, Interfacing seven segment LED, LDR and MQ3 sensor with STM32F4xx, STM32F4xx:
Counters and Timers: Timer and Delay Generation, UART Programming, on chip ADC and Onchip DAC for
waveform generation.
Unit Objectives
1. To get Peripheral insights of STM32F407VG microcontroller.
2. To enhance the capabilities of students to interface various I/O devices and communication protocol
3. To interface sensors using ADC
Unit Outcomes Mapping With COs :
1. Configure the desired peripheral registers CO1: Understand basics of Embedded C Programming and usage of Embedded C
2. Selection of proper sensors with an interfacing and study different software tools for programming microcontrollers.
3. Write C Programs for STM32F4xx Microcontroller Board
CO6: Recognize the interfacing of real world sensors and standard buses. Will also
able to design different case studies.
Mapping With POs :
Books :
T3: 3. Shujen Chen, Muhammad Ali Mazidi, Eshragh Ghaemi, “STM32 Arm Programming for Embedded Systems: Using C Language with STM32”, Nucleo, Micro
DigitalEd., Illustrated Edition,2018.
R2: RM0390 Reference manual, STM32F446xx advanced Arm®-based 32-bit MCUs
RM0090:- Reference manual STM32F407/
Prof. Harshad N. Lokhande - NBNSSOE
GPIO
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GPIO main features
• Up to 16 I/Os under control
• Output states: push-pull or open drain + pull-up/down
• Output data from output data register (GPIOx_ODR) or peripheral (alternate function output)
• Speed selection for each I/O
• Input states: floating, pull-up/down
• Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
• Bit set and reset register (GPIOx_BSRR) for bitwise write access to GPIOx_ODR
• Each I/O port bit is freely programmable
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basic structure of a 5 V tolerant I/O port bit
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GPIO
In the STM32 Arm, the GPIO ports are connected to AHB bus via AHB/APB1 and AHP/APB2 bridges
1. I/O port control registers
2. I/O port data registers
3. I/O data bitwise handling
Imp:- Data Register and Direction Register
Address Name Description
0x00 GPIOx_MODER GPIOx Port Mode(Direction) Register
0x04 GPIOx_OTYPER Output Type Register
0x08 GPIOx_OSPEEDR Output Speed Register
0x0C GPIOx_PUDR Pull-Up / Down Register
0x10 GPIOx_IDR Port Input Data Register
0x14 GPIOx_ODR Port Output Data Register
0x18 GPIOx_BSRR Bit Set / Reset Register
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GPIO: GPIOx_MODER
• GPIOx_MODER which stands for GPIO Mode Register.
These bits are written by software to configure the I/O direction mode. For eg:- pins 0 and 1 of PORT A as OUTPUT
00: Input (reset state)
01: General purpose output mode
10: Alternate function mode
11: Analog mode (reset state)
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Selecting an alternate function (AFR) on STM32F405
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GPIO- Port Output Register (GPIOx_ODR)
• The output register in STM Arm is called GPIO port output data register (GPIOx_ODR)
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GPIO port input data register (GPIOx_IDR)
If the pin is high, it returns a ‘1’ and if the pin is low, it returns a ‘0’.
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GPIO port bit set/reset register (GPIOx_BSRR)
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GPIO port output speed register (GPIOx_OSPEEDR)
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GPIO: Clock Enable of the Peripheral Registers (RCC_AHB1ENR)
• To conserve power, Arm microcontrollers have ways of either slowing down the peripheral circuit clock or stopping the
clock altogether.
• By default clock to peripheral is disabled coming out of power-on reset.
• So need to enable it from RCC (Reset and Clock Control) registers. RCC_AHB1ENR (AHB1 Enable Register)
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STM32 DISCOVERY BOARD
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Program:- Toggling an LED in C
Ref: [1]
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Reading an Input from Push Button using STM32 ARM
C Code:
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Interfacing with Seven Segment Display
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Interfacing with Seven Segment Display
C Program to turn on two 7-seg digits alternatively.
Algorithm:-
1) Configure Port D as output port to drive the segments,
2) Configure PortB0-1 as output port to select the digits,
3) Write the pattern of numeral 7 on Port D,
4) Turn on the select pin to HIGH to activate the tens digit,
5) Delay for some time,
6) Write the pattern of numeral 5 on Port D,
7) Turn on the select pin to HIGH to activate the ones digit,
8) Delay for some time,
9) Repeat from step 3 to 8.
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Interfacing with Light Dependent Resistor (LDR)
• A photoresistor or light dependent resistor is an electronic component that is
sensitive to light.
• When light falls upon it, then the resistance changes.
• Photoresistor LDR’s are light-dependent devices whose resistance is decreased when
light falls on them and that is increased in the dark
• So, when light falls on LDR: STM32 will Read Input = low “0”
• when no light falls on LDR: STM32 will Read Input = low “1”
Change in Resistance wrt light
LDR
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Interfacing with MQ3 (Alcohol Gas Sensor )
• Gas Sensor(MQ3) module is useful for gas leakage detection (in home and industry).
• It is suitable for detecting Alcohol, Benzine, CH4, Hexane, LPG, CO.
• It is a low cost semiconductor sensor which can detect the presence of alcohol gases at
concentrations from 0.05 mg/L to 10 mg/L
• Due to its high sensitivity and fast response time, measurements can be taken as soon as possible.
• The sensitivity of the sensor can be adjusted by using the potentiometer
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TIMER & COUNTER
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STM32F4 Timer Peripherals
BasicTimer (Simple timer) • General Purpose Timer
TIM6 andTIM7 • TIM2,TIM3,TIM4,TIM5
Can be generic counter and internally connected to DAC • Input capture, output compare, PWM, one pulse mode
16-bit counter • 16-bit (TIM3/4) or 32-bit (TIM2/5) counter
• General PurposeTimer • Advanced Control Timer
• TIM9 to TIM14
• Input capture, output compare, PWM, one pulse mode
• TIM1 and TIM8
• Input capture, output compare, PWM, one pulse mode
• 16-bit counter • 16-bit counter
• Additional control for driving motor or other devices
The main block of the programmable timer is a 16-bit/32-bit counter with its related auto-reload register
In addition to that an 24 bit system timer(SysTick) – standard in all Cortex M4 Microcontrollers
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STM32F407 Programmable Timers
• There are 14 Timers :- Vary with
counter, width, max size and clock
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General-Purpose TIMx timer features
General-purpose TIMx timer features include:
• 16-bit (TIM3 and TIM4) or 32-bit (TIM2 and TIM5) up, down, up/down auto-reload counter.
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any
factor between 1 and 65536.
• Up to 4 independent channels for:
• – Input capture
• – Output compare
• – PWM generation (Edge- and Center-aligned modes)
• – One-pulse mode output
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Timers in STM32F4xx:- Basic timing function
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STM32F407 Programmable Timers
• RCC_APB1ENR and APB2ENR registers are used to enable or disable the clock to individual TIMx timers.
• Bits 8-0 of RCC_APB1ENR register are used to enable the clock to some of TIMx timers.
• Without the clock enabled, the CPU will not be able to communicate with the timer.
RCC_APB1ENR
RCC_APB2ENR
For example, we can use the following code to enable the clock to TIM2: RCC->APB1ENR |= 1; /* enable TIM2 clock */
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Timers in STM32F4xx:- Basic Registers
• There are 14 Registers
Important Registers available in all 14 Timers
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Timers in STM32F4xx:- CONTROL 1 Register (CR1)
Using the CR1 (Control 1) register, we can control the counter direction, one shot, or disable/enable.
Some of the CR1 register bits
CEN (Counter Enable, D0): enables or disables the counter. When the CEN bit is set, the timer starts to count. It counts up
or down depending on the DIR bit.
DIR (Direction, D4): This bit configures the Timer/Counter as an up or down counter.
• If the DIR bit is 0, the timer counts up.
• If the DIR bit is 1, the counter counts down.
Eg:- Find the value for CR1 register, to enable the TIM2 for up counter.
ANS:- TIM2_CR1 = 0b010001 = 0x0011
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Timers in STM32F4xx:- TIMxSR (Status Register)
UIF (D0): This is like overflow flag in other microcontrollers. When the timer counts down from a starting value and
reaches 0, the UIF is set high.
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STM32F407 Programmable Timers
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Timers in STM32F4xx :- Delay Generation
Example:- Using TIM2, show the code that makes a delay of 20 ms.
Assume SYSCLK =16 MHz.
Given Data:-
SYSCLK =16 MHz
Delay = 20 ms
Need to Find? :- N = TIMx_CNT register (Count need to Load to
generate 20 ms delay)
Solution:-
• delay = N × M / SYSCLK
• N = delay × SYSCLK / M = 0.020 sec × 16 MHz / M = 320,000 / M
Initialization Code:
• If we choose the prescaler (PSC) to divide by 64, RCC->APB1ENR |= 1; /* enable TIM2 clock */
TIM2->PSC = 64 - 1; /*divided by 64 */
• N = 320,000 / 64 = 5,000
TIM2->ARR = 5000 - 1; /* divided by 5000
*/ TIM2->CNT = 0;
TIM2->CR1 = 1; /* enable timer2 */
Prof. Harshad N. Lokhande - NBNSSOE
Timers in STM32F4xx :- Timing Diagram
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Timer:- System Tick Timer
• Every Arm Cortex-M comes with a System tick timer.
• System tick timer allows the system to initiate an action on a periodic basis.
• This action is performed internally at a fixed rate without external signal.
• The SysTick is a 24-bit down counter driven by the processor clock (AHB clock, the clock that feeds the CPU).
• It counts from an initial value down to 0.
• When it reaches 0, in the next clock, it underflows and it raises a flag called COUNT and reloads the initial value
and starts over again.
• We can set the initial value to a value between 0x000000 to 0xFFFFFF
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Working of System Tick Timer
• The down counter is named as STCVR (SysTick Current Value Register)
• The clock source is chosen using the CLKSOURCE bit of STCSR (SysTick Control & Status Register)
• Need to configure bits from STCTRL (SysTick Control and Status)
• EN 0 Bit: When the ENABLE bit is set the counter initializes the STCVR (SysTick Current Value Register)
with the value of the STRVR (SysTick Reload Value Register)
Prof. Harshad N. Lokhande - NBNSSOE
Counters in STM32F4xx :- Basic Operation
• In Counter mode the timer is counting
the number of external input pulses.
• A Prescaler for the external signal is
available to divide the external signal by
1, 2, 4, or 8.
• The counter wraps around when the
value matches the ARR on the up count
and set to the value of ARR when down
count to 0.
• It sets the UIF (Update interrupt flag)
when the count wraps around. It sets
CCxIF (Capture Compare Interrupt
Flag) when the value matches the CCRx
register.
Interfacing Diagram
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UART
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UART in STM32F4xx
The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex
data exchange with external equipment requiring an industry standard
• It supports synchronous one-way communication
• half-duplex single wire communication.
• It also supports the LIN (local interconnection network),
• Smartcard Protocol
• IrDA (infrared data association) SIR ENDEC specifications
• modem operations (CTS/RTS). It allows multiprocessor communication.
Prof. Harshad N. Lokhande - NBNSSOE
UART Block Diagram
Register Name Register Function
USART_SR Status Register
USART_ISR USART interrupt and status
USART_DR Data Register
USART_BRR Baud Rate Register
USART_CR1 Control Register 1
USART_CR2 Control Register 2
USART_CR3 Control Register 3
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UART:- Data Framing
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UART:- RCC_CFGR (Clock Configuration Register)
Bits 1:0 SW: System clock switch Bits 7:4 HPRE: AHB prescaler
00: HSI oscillator selected as system clock 0xxx: system clock not divided
01: HSE oscillator selected as system clock 1000: system clock divided by 2
10: PLL selected as system clock 1001: system clock divided by 4
11: not allowed 1010: system clock divided by 8
1011: system clock divided by 16
1100: system clock divided by 64
1101: system clock divided by 128
1110: system clock divided by 256
1111: system clock divided by 512
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UART: RCC_CR (RCC Control Register)
The HSI clock signal is generated from an internal 16 MHz RC oscillator and can be used directly as a system clock
RCC_CR is used to set the clock for UART
Bit 0:- 0:HSI oscillator OFF
1: HSI oscillator ON
By default Peripheral Clock is disabled:
So, From RCC_APB1ENR register, D17 bit is used to enable the clock to the USART2
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UART: Baud rate register (USART_BRR)
BAUD register (USART_BRR) is a 32-bit register but only the lower 16 bits are used.
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UART: Control register 1 (USART_CR1)
Bit 13 UE: USART enable
Bit 10 PCE: Parity control enable
Bit 7 TXEIE: TXE interrupt enable
Bit 5 RXNEIE: RXNE Receive interrupt enable
Bit 3 TE: Transmitter enable
Bit 2 RE: Receiver enable
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UART: Control register 1 (USART_CR1)
Bit 13 UE: USART enable
Bit 10 PCE: Parity control enable
Bit 7 TXEIE: TXE interrupt enable
Bit 5 RXNEIE: RXNE Receive interrupt enable
Bit 3 TE: Transmitter enable
Bit 2 RE: Receiver enable
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UART: Status register (USART_SR)
Bit 7 TXE: Transmit data register empty
This bit is set by hardware when the content of the TDR register has been transferred into the shift register.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register)
Bit 6 TC: Transmission complete:- 0: Transmission is not complete, 1: Transmission is complete
Bit 5 RXNE: Read data register not empty: 0: Data is not received, 1: Received data is ready to be
read.
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UART: Data register (USART_DR)
• Bits 31:9 Reserved, must be kept at reset value
• Bits 8:0 DR[8:0]: Data value
• Contains the Received or Transmitted data character, depending on whether it is read from or written to.
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UART :- Baud Rate Generation
The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as programmed in
the Mantissa and Fraction values of USARTDIV
Baud Rate =
When OVER8=0, the fractional part is coded on 4 bits
When OVER8=1, the fractional part is coded on 3 bits
Example1 :- For SYSCLK = 16MHZ, And for Baud Rate = 9600 with OVER8 = 0 ?
Soln:-
USARTDIV = Fck / 16 x Baud
16MHz / 16 x 9,600 = 104.166.
Now, 104 = 0x68 for upper 12-bits.
For fraction part, 0.166 x 16 = 2.656 ͌ = 0x03
Example 2:- For SYSCLK = 16MHZ, And for Baud Rate = 19200 with OVER8 = 0 ?
Soln:-
USARTDIV = Fck / 16 x Baud
16MHz / 16 x 19,200 = 52.08.
Now, 52 = 0x034 for upper 12-bits.
For fraction part, 0.08 x 16 = 1.28 and we use 1 for lower 4-bits.
Prof. Harshad N. Lokhande - NBNSSOE
Steps to configure USART2 for transmitting data
• 1) Enable the Clock to GPIOA.
• 2) Enable the Clock to USART2.
• 3) Select the peripheral function AF7 for PA2 (USART2_TxD) pin using the GPIO_MODER and GPIO_AFRL
registers.
• 4) Set the baud rate for USART2 using USART2_BRR register.
• 5) Configure the CR1 (Control 1) register for oversampling rate, character size (8-bit or 9-bit) and enabling transmit
(TE).
• 6) Configure the CR2 (Control 2) register for number of stop bit(s) and so on.
• 7) Configure the CR3 (Control 3) register for no hardware flow control and so on.
• 8) Enable USART2 after configuration complete
• 9) Wait until the TXE (Transmit Empty) bit of the USART_SR register is set.
Prof. Harshad N. Lokhande - NBNSSOE
C Code to configure USART2 for transmitting data
#include "stm32F4xx.h"
void USART2_init(void);
void USART2_write(int c);
int main (void) { /* Write a character to USART2 */
USART2_init(); /* initialize USART2 */ void USART2_write (int ch) {
while(1) { /* Loop forever */ while (!(USART2->SR & 0x0080)) {} // wait until Tx
USART2_write('Y’); //Transmit Character buffer empty
USART2_write('e'); USART2->DR = (ch & 0xFF);
USART2_write('s'); }
}}
void USART2_init (void) {
RCC->AHB1ENR |= 1; /* Enable GPIOA clock */
RCC->APB1ENR |= 0x20000; /* Enable USART2 clock */
/* Configure PA2 for USART2_TX */
GPIOA->AFR[0] &= ~0x0F00;
GPIOA->AFR[0] |= 0x0700; /* alt7 for USART2 */
GPIOA->MODER &= ~0x0030;
GPIOA->MODER |= 0x0020; /* enable alternate function for PA2 */
USART2->BRR = 0x0683; /* 9600 baud @ 16 MHz */
USART2->CR1 = 0x0008; /* enable Tx, 8-bit data */
USART2->CR2 = 0x0000; /* 1 stop bit */
USART2->CR3 = 0x0000; /* no flow control */
USART2->CR1 |= 0x2000;/* enable USART2 */
}
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ADC
Prof. Harshad N. Lokhande - NBNSSOE
STM32f4xx: on chip-Analog-to-digital converter (ADC)
• The 12-bit ADC is a successive approximation analog-to-digital converter.
• It has up to 18 multiplexed channels allowing it to measure signals from 16 external sources, two internal
sources
ADC main features
• 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
• Single and continuous conversion modes
• Interrupt generation at the end of conversion
• The STM32F4xx Arm chip has three on-chip ADC modules: the ADCs are designated as ADC1 (master), ADC2 (slave) and
ADC3 (slave).
Prof. Harshad N. Lokhande - NBNSSOE
Block Diagram of ADC
Register Name Register Function
ADC_SR (Status Register)
ADC_CR1 (Control Register1)
ADC_CR2 (Control Register2)
ADC_SMPR1 ADC sample time register 1
ADC_SMPR2 ADC sample time register 2
ADC_DR (Data Register)
RCC_APB2ENR |= 0x00000100; /* enable clock for ADC1 */
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Conversion Clock for ADC
• SYSCLK clock source by AHB by APB Prescalar , Then given to ADC
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Conversion Time for ADC
time to sample the input
signal
conversion time
time to do the conversion
• A sample and hold circuit is added between the input signal and the converter.
The number of clock cycles for sampling time can be programmed using ADC_SMPRx (Sample Time Register) register.
We have two ADC_SMPRx registers to covers all the 18 ADC channels.
• ADC_SMPR2 is used for channels 0 to 9
• ADC_SMPR1 is used for channels 10 to 18.
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ADC sample time register (ADC_SMPR1) to set sampling time
000: 3 cycles 100: 84 cycles
001: 15 cycles 101: 112 cycles
010: 28 cycles 110: 144 cycles
011: 56 cycles 111: 480 cycles
• In the conversion phase, the analog input is converted to binary numbers.
• In this phase, the number of clocks required depends on ADC resolution namely the number of bits of the binary
output 6, 8, 10, or 12.
• For example, if we use the default of 3 clock cycle for sample time with the 8-bit ADC resolution, the total
number of clocks needed for ADC conversion is 11 clocks.
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Analog input pin assignment (GPIO_MODER Register)
GPIO_MODER
• 00: Input (reset state)
• 01: General purpose output mode
• 10: Alternate function mode
• 11: Analog mode
ADC-H/W Pins
Channel Allocation
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ADC_DR (ADC Data Register)
• Upon the completion of a conversion, the result is placed in the DATA registers.
• Its 32 bit, only the lower 12 bits are used and upper 18 bits are unused.
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Control 1 (ADC_CR1) Register
• RES bits (D25-D24) of ADC_CR1 register to select 6, 8, 10, or 12- bit ADC resolution.
• Bit 5 EOCIE: Interrupt enable for EOC
• Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits
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Control 2 (ADC_CR2) register
Bit 0 ADON: A/D Converter ON / OFF
Bit 1 CONT: Continuous conversion
Bit 10 EOCS: End of conversion selection
Bit 11 ALIGN: Data alignment (0: Right , 1: Left)
• ALIGN bit in CR2 register allows the binary output result of ADC conversion to be moved to the left
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ADC regular sequence register 3 (ADC_SQR3)
ADC1->SQR3 = 1; /* conversion sequence starts at ch 1 regular sequence register*/
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ADC_SR(ADC Status) Register
Bit 5: OVR Overrun This bit is set by hardware when data are lost.
This happens if we do not read the result of the last conversion from the Data Register (ADC_DR).
Bit 1: EOC End of Conversion - 0: Conversion not complete , 1: Conversion complete
• This bit is set by ADC itself at the end of each conversion of a channel.
• It is cleared by software or by reading the ADC_DR (ADC Data) register.
• By polling this flag, we know if the conversion is complete and we can read the value in the DATA
register.
We can use EOCIE (EOC Interrupt enable) bit in ADC_CR1 register to enable the interrupt option
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Algorithm:- Configuring ADC and reading ADC channel
1. Enable ADC clock to ADC in RCC_APB2ENR register.
2. Configure ADC right adjusted result (ALIGN), free running conversion (CONT, continuous conversion) using
ADC_CR2 register.
3. Using ADC_CR1 register, select the resolution and the analog input channel.
4. Use GPIOx_MODER register to configure input pin for analog input channel.
5. Using ADC_CR2 register Enable the ADC (ADON) and START (SWSTART) to start the conversion.
6. Monitor the EOC flag in the ADC_SR register for end-of-conversion.
7. When the EOC flag goes HIGH, read the ADC data result from the ADC_DR register and save it.
8. Repeat steps 6 through 7 for the next conversion.
Prof. Harshad N. Lokhande - NBNSSOE
C Program to Read ADC
#include "stm32f4xx.h"
int main (void) {
int result;
/* set up pin PA5 for LED */
RCC->AHB1ENR |= 1; /* enable GPIOA clock */
GPIOA->MODER &=~0x00000C00; /* clear pin mode */
GPIOA->MODER |= 0x00000400; /* set pin to output mode */
/* set up pin PA1 for analog input */
RCC->AHB1ENR |= 1; /* enable GPIOA clock */
GPIOA->MODER |= 0xC; /*PA1 analog */
while (1) {
/* setup ADC1 */
ADC1->CR2 |= 0x40000000; /* start a conversion */
RCC->APB2ENR |= 0x00000100; /* enable ADC1 clock */ while(!(ADC1->SR & 2)) {} /* wait for conv complete */
ADC1->CR2 = 0; /* SW trigger */ result = ADC1->DR; /* read conversion result */
ADC1->SQR3 = 1; /* conversion sequence starts at ch 1 */ if (result & 0x100)
ADC1->SQR1= 0; /* conversion sequence length 1 */ GPIOA->BSRR = 0x00000020; /* turn on LED */
else
ADC1->CR2 |= 1; /* enable ADC1 */
GPIOA->BSRR = 0x00200000; /* turn off LED */ }
}
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DAC
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Features of DAC
• Two DAC converters: one output channel each as DAC1 and DAC2.
• They are available at the analog out pins “PA4 and PA5” for chan1 and chan2
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channel for independent or simultaneous conversions
• DMA capability for each channel
• DMA underrun error detection
Prof. Harshad N. Lokhande - NBNSSOE
STM32F4xx DAC Block Diagram
The DAC integrates two output buffers that can be used to reduce the output impedance, and to drive external loads
directly without having to add an external operational amplifier.
Vref should be at 1.8 V ≤ VREF+ ≤ VDDA
The output voltage from the DAC can be calculated using the following formula:
Prof. Harshad N. Lokhande - NBNSSOE
DAC_CR (DAC Control Register)
The most important bit in DAC_CR is the enable bit.
Bit 0 EN1: DAC channel1 enable ; where 0: DAC channel1 disabled, 1: DAC channel1 enabled
Bit 1 BOFF1: DAC channel1 output buffer disable
Bits 5:3 TSEL1[2:0]: DAC channel1 trigger selection
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DAC Data Holding Registers (DAC_DHR)
• There are 8 registers according to Data Holding Position
• For eg: - DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)
• DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
• Writing new data into DAC holing register starts a conversion.
• Data stored in the DAC_DHRx register are automatically transferred to the Data Output registers (DAC_DOR) register
after one clock cycle.
• The Digital inputs are converted to output voltages on a linear conversion between 0 and VREF+
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DAC- Data Output registers (DAC_DOR) register
• Data stored in the DAC_DHRx register are automatically transferred to the Data Output registers (DAC_DOR) register
after one clock cycle.
• The Digital inputs are converted to output voltages on a linear conversion between 0 and VREF+
Enabling Clock to DAC
• To save power no clock is fed to DAC upon Reset.
• To use the on-chip, DAC we must enable the clock to DAC using RCC APB1 peripheral clock enable register
(RCC_APB1ENR)
Prof. Harshad N. Lokhande - NBNSSOE
C program to generate a step waveform using DAC
• Solution:- The loop counter i is incremented every iteration and written into the DAC_DHR register to create
the 4 steps.
[2]. DAC Waveform
Prof. Harshad N. Lokhande - NBNSSOE
REFERENCES
• [1] https://ezcontents.org/stm32f4-discovery-blink-led-osx
• [2] https://deepbluembedded.com/
Prof. Harshad N. Lokhande - NBNSSOE
THANK YOU
Prof. Harshad N. Lokhande - NBNSSOE
https://www.youtube.com/c/harshadlokhande_veditekk
STM32 Discovery Board Practical's and other Hardware demonstrations will be
available here
Channel Name:- ionbits
Prof. Harshad N. Lokhande - NBNSSOE
