in/shivramchintala ae Timing Snelysis (Coen = Does the design meet a given timing d requirement?! } = How fast canTrun \_-7 } the design?!!!in/shivramchintala Static Timing Analysis Static timing analysis provides a faster and simpler way of checking and analyzing all the timing paths in a design for any timing violations. Given the complexity of present day ASICs, which may contain 10 to 100 million gates, the static timing analysis has become a necessity to exhaustively verify the timing of a design.in/shivramchintala % Clock definition(specification) © By defining the clocks, all the internal timing paths (all flip-flop to flip- flop paths) are constrained; this implies that all internal paths can be analyzed with just the clock specifications. The clock specification specifies that a flip-flop to flip-flop path must take one cycle.at Scenario- 1: in/shivramchintala create_clock -name SYSCLK -period 20 -waveform {0 5} [get_ports SCLK] ' High 1 (guration ———___} Taw duration SYSCLK 0 5 2% 25 Period i Figure A clock definition. Description: ¥ The name of the clock is SYSCLK and is defined at the port SCLK. Y The period of SYSCLK is specified as 20 units- the default time unit is nanoseconds if none has been specified. Y The first argument in the waveform specifies the time at which rising edge occurs and the second argument specifies the time at which the falling edge occurs.we Scenario- 2: in/shivramchintala P, create_clock -period 5 [get_ports SCAN_CLK] SCAN_CLK ° 25 30 75 Figure _Clock specification example. Description: ¥ — Ifno waveform option is specified, the default is :-waveform {0, period/2} ¥ In this specification, since no -name option is specified, the name of the clock is the same as the name of the port, which is SCAN_CLK.“3 Scenario- 3: in/shivramchintala create_clock -name BDYCLK -period 15 -waveform {5 12} [get_ports GBLCLK] BDYCLK | I 0 R "5 20 7 __________ ' ‘One period 1 Figure Clock specification with arbitrary edges. Description: ¥ The name of the clock is BDYCLK and it is defined at the port GBLCLK. v In practice, it is a good idea to keep the clock name the same as the port name.at Scenario-4: in/shivramchintala create_clock -period 1.0 -waveform {0.5 1.375} [get_ports MAIN_CLK] MAIN.CLK | I 1.000 1.375 1.500 Descriptior Y The first rising edge and the next falling edge is specified. Falling edge at 0.375ns is inferred automatically.Scenario-5: in/shivramchintala create_clock-period 10 -waveform {5 10} [get_ports FCLK] FCLK tp 5 10 13 L I tr Period 1 Description: Y Creates a clock with the rising edge at Sns and the falling edge at 10ns.Ne Scenario- 6: in/shivramchintala create_clock-period 125 -waveform {100 150} [get_ports ARMCLK] ARMCLE Description: ¥ Since the first edge has to be rising edge, the edge at 100ns is specified first and then the falling edge at 150ns is specified. The falling edge at 25ns is automatically inferred.“3 Scenario- 7: in/shivramchintala create_clock -period 1.2 -waveform {0.3 0.4 0.8 1.0} [get_ports JTAG_CLK] JTAG_CLK b Period ‘ Description: ¥ Indicates a rising edge at 300ps, a falling edge at 400ps, a rising edge at 800ps and a falling edge at Ins, and this pattern is repeated every 1.2ns.i _. in/shivramchintala “ye set_clock_transition ¥ In some cases, such as the output of some PLL models or an input port, the tool cannot compute the transition time(or slew) automatically. In such cases, it is useful to explicitly specify the transition time at the source of the clock. ¥ This is specified using the set_clock_transition specification. set_clock_transition -rise 0.1 (get_clocks CLK_CONFIG] set_clock_transition -fall 0.12 [get_clocks CLK_CONFIG] ¥ This specification applies only for ideal clocks and is disregarded once the clock trees are built, at which point, actual transition times at the clock pins are used. ¥ Ifa clock is defined on an input port, use the set_input_transition specification to specify the slew on the clock,for more updates , please follow FN /shivramchintala