Micro Controller

Mobile Phone
Memory, Game
E-mail, E-tag, Music
Data Communicate
Camera, Digital-TV
Windows (Software)

PC Mobile

LSI
Life Car

Pace Maker（Health) Hybrid Car

Robot Navigation
Sensor, Monitor Anti-crash Control
Environmental Gas Control

Page 4
Graph of Semiconductor Products Diode,
Transistor,
Discrete device LED,
Consists of just one etc.
Semiconduct circuit element
or device Analog,
Integrated circuit Mixed signal,
Hardware Consists of many Digital.
products circuit elements

Emulator, Evaluation board,

System Hardware platform, etc.
solution
Development
Middleware kit
Software
Device driver
products
Compiler, Operating system, etc.

Page 5
Classification of IC
Integration level
Integration Scale SOC (System-on-a-chip)
low high SiP (System in Package)
SSI MSI LSI VLSI ULSI
Medium Very Functional characteristic
Large Ultra Memory device
Small Scale Integration
Logic device

Classification of IC from the view point of user

General purpose
Standard product
off-the-shelf
DRAM, SRAM, FPGA, etc. components
ASSP (Application Specific Standard Product)
DSP, Embedded type micro processors, etc.
ASCP (Application Specific Custom Product)
ASIC (Application Specific Integrated Circuit)
Specific application

Page 6
LSI Development Flow

device
process design
requirements

device design Platform

LSI development (flow)

development Total
circuit design (flow) LSI design
(flow)
LSI
specifications LSI design LSI design (flow)

fabrication
*characterization
wafer level test
*qualification Production (flow)
packaging
*quality assurance
chip level test
LSI products

Page 8
Total LSI Design Flow

LSI Design Flow

Platform Development Flow System spec

Technology rule
Device spec Device parameters System design
(process spec) Device design Layout design rule
Layout verif. rule
Logic design
Circuit spec Circuit design
Cell library Test design
Logic model
Library spec Library design Timing model Layout design
Circuit model
Layout model

Mask making

Page 9
LSI Development and Business Models

Process/Device Lib. House

System spec

System design Fabless GPSP

ASSP
Logic design ASCP
Design
Test design House

IDM
Layout design

Mask making
Foundry
Fabrication IDM: Integrated
& QA Device Manufacturer
only QA

Page 10
LSI Design Flow

LSI Design Flow

Platform Development Flow System spec

Technology rule
Device spec Device parameters System design
(process spec) Device design Layout design rule
Layout verif. rule
Logic design
Circuit spec Circuit design
Cell library Test design
Logic model
Library spec Library design Timing model Layout design
Circuit model
Layout model

Mask making

Page 12
 System spec

System design Verification and feedback

Logic design Verification and feedback

Minimize Test design Verification and feedback

retrogression
Layout design Verification and feedback

Mask making
No spin!
prototyping

Page 13
Hardware Design Functional specification Manual Handbook

Architecture design
Front-end
Design work design
RTL design

Logic verification

P&R, Timing verification Back-end

design
Mask production

Manufacturing Front-end of
Fabrication/test
process
Back-end of
Packaging/test process
Interaction with
software development Shipping
P&R: Place and Route

Page 14
 specification/manual

input ?? output
Functional specification
seed, power, etc. structure
control/data path

Architecture design

RTL programming
RTL design
logic simulation
test scenario
Logic verification

Place and route Bug report

STA
P&R, Timing verification

timing report
STA: Static timing analysis

Page 15
 GDS file
Photo mask

OPC
Mask production

Lithography Etching

Mask Photoresist
Fabrication/test
Ion implant

Silicon wafer
Deposition
Wire bonding
Packaging/test
Quality assurance/inspection
Molding

LSI tester

Quality assurance/inspection OPC: Optical Proximity Correction

Page 16
Software Design
Functional specification Manual Handbook

Architecture design
Design work
Logic design

Programming

Simulation
Logic verification
Test on actual device

Manufacturing
Packaging/test

Interaction with hardware Shipping

development

Page 17
History of LSI Design Methodologies

Everything has to be designed from scratch.

Full custom design
Closed
system Array of primitive logic
Tools specific to fabrication line
gates are fabricated on
(Manufacturer dependent) silicon beforehand.
1980
1980 UMC User specific logic
Standard Cell IC design gate array can be created by
Logic synthesis tool metal layer mask.
1986 Synopsys 1983 Altera
1987 TSMC ( foundry ) mid 1980s
late 1980s 1984 Xilinx
1988 Cadence
Field Programmable
Cell-based IC Gate Array (FPGA )
User specific logic can
(CBIC) be created by selecting,
placing and connecting
“standard cells”

UMC: United Microelectronics Corp.

Main stream of current LSI design TSMC: Taiwan Semiconductor Manufacturing Company

Page 18
 Old vs. Current Design
Old LSI design Current LSI design
Manufacture dependent Cell base design
General
( Closed system ) ( Open system )
Design Manufacture specific tools. C language, Verilog, VHDL, etc.
functions

Create gate Manual mapping into transistor Automatically mapped into

level logic logic gates and hand standard cells and optimized
optimization needed because by powerful synthesis tools.
of poor synthesis tools.
Created gate diagrams have Created gate diagrams have
poor portability among LSI portability among LSI
production lines. production lines.
Create MASK Manual work needed Automatic optimization by
pattern because of poor layout tools. powerful layout tools.

LSI Possible only on the specific Possible on the compatible

fabrication fabrication lines. No compatible fabrication lines among vendors.
lines among vendors.

Page 19
Classification of IC from the view point of design

Semiconductor vendor Customer

ASSP Basic design

RTL
<= RTL
ASCP Synthesis

Verification
<= net list
ASIC Layout
<= mask pattern
COT WS GDSⅡ
Production
WS: Work Sign Off
Testing
COT: Customer Own Tool
GDSⅡ: Graphic Data System II

Page 20
In the actual implementation, we use a serial interface to reduce
the number of pins, that is, we use a serializer for 64 bits parallel
interface of snake lamps.
The additional specifications needed to design the chip are as
follows.

Snake moving speed: 2 lamps per second ( 2Hz )

Clock : 2Hz*128*32 = 8KHz
Use 32KHz clock and gate it to slow down
the speed.
Maxmum lamps: 128 lamps
( Implementation 64 lamps )
Package: 14 pin so ,
internal connection: 5 PADs x 2 lows

pin: (1)VDDQ (6)U_n (10)LED_CLK

(2)VDDI (7)D_n (11)LED_DATA
(3)VSS (8)L_n (12)ERROR
(4)CLK (9)R_n
(5)RST_n

Page 27
Block structure of the chip
Write this part in Verilog and synthesize it.
VDDQ

VDDI protecter

VSS

Clock LED_CLK
CLK
Input Serializer
RST_n
buffer Output LED_DAT
Noise canceller buffer
ERROR
U_n Synchronization

D_n Input Main logic

buffer
L_n Flip-Flops for
the snake body
R_n

Page 28
always@(posedge CLK or negedge SB) begin
if(!SB) begin
Q <= 1'b1;
end Verilog MOS circuit
else begin
Q <= DATA;
end
end The Flip-Flop of
the snake body

Gate diagram Layout

Page 33