Birla Institute of Technology & Science, Pilani
Work Integrated Learning Programmes Division
First Semester 2023-2024
Mid-Semester Test
(EC-2 Regular)
Course No. : ES/MEL/AEL ZG 554
Course Title : Reconfigurable Computing
Nature of Exam : Closed Book
Pattern of Exam : Typed Only
Weightage : 30% No. of Pages = 5
Duration : 2 Hours No. of Questions = 5
Date of Exam : 23/09/2023
Note to Students:
1. Please follow all the Instructions to Candidates given on the cover page of the answer book.
2. All parts of a question should be answered consecutively. Each answer should start from a fresh page.
3. Assumptions made if any, should be stated clearly at the beginning of your answer.
Q.1 Set. (A) Explain in brief, how each of the following drawbacks of Von Neumann computing
paradigm are addressed in modern day computing systems.
(i) Speed efficiency issue.
(ii) Resource efficiency issue
(iii) Memory access issue [6]
Q.1 Set. (B) Explain in brief, how each of the following drawbacks of DSP computing paradigm
are addressed in modern day computing systems.
(i) Speed efficiency issue.
(ii) Resource efficiency issue
(iii) Memory access issue [6]
Q.1 Set. (C) Explain in brief, how each of the following drawbacks of ASIP computing
paradigm are addressed in modern day computing systems.
(i) Speed efficiency issue.
(ii) Resource efficiency issue
(iii) Memory access issue [6]
Q.2 Set. (A) Temporal and spatial computation styles are unique features of computing
paradigms. Mention three differences between them. Which of the two is dominant in
RC devices? Show how the following digital filter equation be implemented using the
two computational styles:
H(s) = K / (s2 + bs + a) [6]
Q.2 Set. (B) Temporal and spatial computation styles are unique features of computing
paradigms. Mention three differences between them. Which of the two is dominant in
RC devices? Show how the following digital filter equation be implemented using the
two computational styles:
H(s) = K*s / (s2 + bs + a) [6]
Q.2 Set. (C) Temporal and spatial computation styles are unique features of computing
paradigms. Mention three differences between them. Which of the two is dominant in
RC devices? Show how the following digital filter equation be implemented using the
two computational styles:
H(s) = K*s2 / (s2 + bs + a) [6]
Q.3 Set. (A) Using PLA of minimum size, implement the following three functions:
F1 = ABC ; F2 = A + B + C ; F3 = (ABC)’
How many switches are needed to program the three functions? You can use
annotated boxes to indicate logic gates. [6]
Q.3 Set. (B) Using PLA of minimum size, implement the following three functions:
F1 = A ^ B ^ C ; F2 = A + B + C ; F3 = (A + B + C)’ (^ = xor)
How many switches are needed to program the three functions? You can use
annotated boxes to indicate logic gates. [6]
Q.3 Set. (C) Using PLA of minimum size, implement the following three functions:
F1 = (A ^ B ^ C)’ ; F2 = A + B + C ; F3 = (ABC)’ (^ = xor)
How many switches are needed to program the three functions? You can use
annotated boxes to indicate logic gates. [6]
Q.4 Set. (A) Implement the two functions using ONLY three 4-input lookup tables. Show what
logic function will be implemented in each of the three lookup tables by giving the
logic expression as a function of its labeled inputs. Use the simplest logic
expressions possible for each lookup table, using AND, OR, and NOT operators.
Show how the lookup tables are connected together.
F = x1.x2.x3.x4.x5.x6
G = x1’x2’x3’x4’x5’x6’ [6]
Q.4 Set. (B) Implement the two functions using ONLY 4-input lookup tables. Show what
logic function will be implemented in each of the three lookup tables by giving the
logic expression as a function of its labeled inputs. Use the simplest logic
expressions possible for each lookup table, using AND, OR, and NOT operators.
Show how the lookup tables are connected together.
F = x1.x2.x3.x4.x5.x6
G = x1’x2’x3’x4’x5’x6’ [6]
Q.4 Set. (C) Implement the two functions using ONLY 3-input lookup tables. Show what
logic function will be implemented in each of the three lookup tables by giving the
logic expression as a function of its labeled inputs. Use the simplest logic
expressions possible for each lookup table, using AND, OR, and NOT operators.
Show how the lookup tables are connected together.
F = x1.x2.x3.x4.x5.x6
G = x1’x2’x3’x4’x5’x6’ [6]
Q.5 Set. (A) The logic blocks of an FPGA consist of one 5-LUT and one FF. Partition the
following circuit of four inputs {x, y, z, w} into the required number of logic blocks
(specify how many) and write the Boolean function of each LUT (don’t simplify the
expression). The FFs are numbered {r1, r2, r3, r4, r5}, and you can use these names to
represent their outputs as r1next, r2next……..etc. [6]
Q.5 Set. (B) The logic blocks of an FPGA consist of one 5-LUT and one FF. Partition the
following circuit of four inputs {x, y, z, w} into the required number of logic blocks
(specify how many) and write the Boolean function of each LUT (don’t simplify the
expression). The FFs are numbered {r1, r2, r3, r4, r5}, and you can use these names to
represent their outputs as r1next, r2next……..etc. [6]
Q.5 Set. (C) The logic blocks of an FPGA consist of one 5-LUT and one FF. Partition the
following circuit of four inputs {x, y, z, w} into the required number of logic blocks
(specify how many) and write the Boolean function of each LUT (don’t simplify the
expression). The FFs are numbered {r1, r2, r3, r4, r5}, and you can use these names to
represent their outputs as r1next, r2next……..etc. [6]
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