EC18601-VLSI Design

- Stick diagrams
- Layout diagrams

CMOS VLSI Design 4th Ed. 1

UNIT I
MOS TRANSISTOR PRINCIPLE 9
NMOS, PMOS -Enhancement and depletion MOSFET; MOS
transistor-Ideal I-V characteristics; Fabrication Process - MOSFET,
CMOS- n-well, p-well, Twin tub, SOI; Scaling principles and
fundamental limits; CMOS inverter characteristics; Stick diagram;
Layout diagrams ; Design rules; Layer Representation

UNIT II
COMBINATIONAL LOGIC CIRCUITS 9
Static CMOS Design: Examples of Combinational Logic Design;
Complementary CMOS concept and properties; Ratioed Logic -
DCVSL logic gate; Pass Transistor Logic - Concept, Complementary
PTL and Differential PTL; CMOS transmission gate; Elmores
constant; Dynamic CMOS design: Dynamic Logic - Basic Principles;
Issues in Dynamic Design; Cascading Dynamic Gates
UNIT III
SEQUENTIAL LOGIC CIRCUITS 9
Timing Metrics for Sequential Circuits; Static Latches and Registers;
Bi-stability Principle; Multiplexer Based Latches; Master-Slave based
Edge Triggered Register; Non-ideal clock signals; Dynamic Latches
and Registers; Transmission-Gate Edge-triggered Registers; C2MOS
Register; Dual-Edge Registers; True Single-Phase Clocked Register
(TSPCR) Timing issues; Pipelines; Clock Strategies; Synchronous
and Asynchronous design- Low power design principles

UNIT IV
DESIGNING ARITHMETIC BUILDING BLOCKS 9
Data path circuits; Architectures for Ripple Carry Adders; Carry Look
Ahead Adders; Carry Select Adder; Carry Bypass Adder; High speed
adders - Brunt Kung adder, Kogge Stone; Multipliers - Wallace Tree
multiplier, Booth Multiplier; Barrel shifters; Speed and Area Trade-
off for all above Arithmetic Building Blocks
UNIT V
IMPLEMENTATION STRATEGIES 9
Full custom and Semi-custom design; Standard cell design and
cell libraries; FPGA building block architecture - FPGA
interconnect routing procedures; Design for Testability: Ad Hoc
Testing, Scan Design, BIST
TEXTBOOKS:
1. Jan M Rabaey, Anantha Chandrakasan, B. Nikolic, “Digital
Integrated Circuits: A Design Perspective”, Second Edition,
Prentice Hall of India, 2003. (Unit-1 to Unit-4)

2. M.J. Smith, “Application Specific Integrated Circuits”, Addisson

Wesley, 1997 (Unit-5)

REFERENCES:
3. N.Weste, K.Eshraghian, “Principles of CMOS VLSI Design”,
Second Edition, Addision Wesley 1993 (Unit-1 to Unit-4)

4. R.Jacob Baker, Harry W.LI., David E.Boyee, “CMOS Circuit

Design, Layout and Simulation”, Prentice Hall of India 2005

5. A.Pucknell, Kamran Eshraghian, “BASIC VLSI Design”, Third

Edition, Prentice Hall of India, 2007.
 UNIT I MOS TRANSISTOR PRINCIPLE
Syllabus
- NMOS, PMOS, Enhancement and depletion
MOSFET
- MOS transistor-Ideal I-V characteristics
- Fabrication Process - MOSFET, CMOS
- n-well, p-well, Twin tub, SOI,
- CMOS inverter characteristics,
- Stick diagram, Layout diagrams,
- Scaling principles and fundamental limits

CMOS VLSI Design 4th Ed. 6

 STICK DIAGRAM
➢ Stick Diagram conveys the layer information
through the use of a colour.
➢ N-MOS and P-MOS are separated by using demarcation
line.
➢ All P-MOS - placed above demarcation line.
➢ All N-MOS - placed below demarcation line.
➢ N-diffusion and P-diffusion joined by metal.
➢ Diffusion path should not cross demarcation line.
➢ Metal and poly can cross the demarcation line.
➢ VDD and VSS lines are known as rails.
CMOS VLSI Design 4th Ed.
STICK DIAGRAM – NMOS encoding

CMOS VLSI Design 4th Ed. 8

STICK DIAGRAM – CMOS encoding

CMOS VLSI Design 4th Ed. 9

 INSTRUCTIONS TO DRAW
THE STICK DIAGRAM

1. Draw the Vdd, Vss rails using blue colour.

2. Draw the demarcation line between Vdd and Vss rail.
3. Draw n-diffusion, p-diffusion lines. (green and yellow)
4. Draw the polysilicon (red) lines across diffusion lines.
5. Draw the metal contact in blue colour.
6. Draw the contact between metal and other layers using
X symbol (black)

CMOS VLSI Design 4th Ed.

 Stick Diagrams
❑ Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
VDD VDD
A 1. Draw the Vdd,
A Vss
B rails
C
metal1
c using blue colour. poly
ndiff
2. Draw the demarcation line
pdiff
Y between Vdd and Vss rail Y contact

3. Draw n-diffusion, p-
GND diffusion
GND
lines. (green and
INV NAND3
yellow)
1: Circuits & Layout CMOS VLSI Design 4th Ed. 12
 Stick Diagrams
❑ Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
VDD
A 4. DrawVDD
the polysilicon
A B lines
C across
metal1
diffusion lines. (red)
c poly
5. Draw the metal contact in blue ndiff
colour. pdiff
Y
Y contact
6. Draw the contact between metal
and other layers using X symbol
GND
(black) GND
INV NAND3

1: Circuits & Layout CMOS VLSI Design 4th Ed. 13

 Stick Diagrams
❑ Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
– NOT Gate ; 3-i/p NAND Gate
VDD VDD
A A B C
metal1
c poly
ndiff
pdiff
Y
Y contact

GND GND
INV NAND3

1: Circuits & Layout CMOS VLSI Design 4th Ed. 14

 The CMOS NOT Gate
Contact Cut
Vp Vp
X n-well
x x X
x x
X

Gnd
X
Gnd

CMOS VLSI Design 4th Ed.

NAND GATE

CMOS VLSI Design 4th Ed.

 Stick Diagrams – NOT, NAND
Contains no dimensions
Represents relative positions of transistors

VDD VDD

Inverter
NAND2

Out Out

In A B
GND GND

17
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 NAND sticks

VDD

out

VSS

CMOS VLSI Design 4th Ed.

 NAND sticks

VDD
a
out
b
VSS
CMOS VLSI Design 4th Ed.
Stick Diagram – NOR Gate
A OUT

B
NOR Gate

CMOS VLSI Design 4th Ed.

Stick Diagram – NOR Gate
A OUT

B
NOR Gate

CMOS VLSI Design 4th Ed.

Stick Diagram – Function
Power

Out
A

Ground

CMOS VLSI Design 4th Ed.

 A C
B
D
E

A
D
B
C E

CMOS VLSI Design 4th Ed. 23

 LAYOUT DESIGN RULES

Rules followed to prepare the photo mask is known as

layout design rules.

The design rules primarily addresses two issues

1. The geometrical reproduction of features that can be
reproduced by the mask making process and
photolithographic process.
2. Interaction between different layers.

CMOS VLSI Design 4th Ed.

 LAYOUT DESIGN RULES
There are several approaches in describing the design rules.
1. MICRON DESIGN RULES:
Minimum feature size and spacing for all the mask required in a
process.(Features- two different substrates, Doped regions of p and
n transistor forming material, Transistor gate electrodes,
Interconnection paths, Interlayer contacts)
2. ALPHA AND BETA RULES:
Alpha is used to define the minimum grid size. Beta is used to
define the basic feature size. Feature size f = distance between
source and drain Set by minimum width of polysilicon
3. LAMDA BASED DESIGN RULES: Single parameter lamda
characterize the resolution of the complete wafer implementation
process.
25
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 The CMOS NOT Gate Layout
Contact Cut
Vdd Vdd
X n-well
x x X
x x
X

Gnd
X
Gnd

CMOS VLSI Design 4th Ed.

NAND stick and layout

CMOS VLSI Design 4th Ed.

NOR stick and layout

CMOS VLSI Design 4th Ed.

NAND, NOR Layout

CMOS VLSI Design 4th Ed. 29

 Standard Cell Layout Methodology –
1980s

Routing
channel
VDD

signals

GND

30
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
 Layout
❑ Chips are specified with set of masks
❑ Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
❑ Feature size f = distance between source and drain
– Set by minimum width of polysilicon
❑ Feature size improves 30% every 3 years or so
❑ Normalize for feature size when describing design
rules
❑ Express rules in terms of l = f/2
– E.g. l = 0.3 mm in 0.6 mm process

0: Introduction CMOS VLSI Design 4th Ed. Slide 31

Simplified Lambda Based Design Rules for layouts
with 2 metal layers

CMOS VLSI Design 4th Ed. 32

Lamda Based Layout Rules

CMOS VLSI Design 4th Ed. 33

Lamda Based Layout Rules

CMOS VLSI Design 4th Ed. 34

Lamda Based Layout Rules

CMOS VLSI Design 4th Ed. 35

Lamda Based Layout Rules

CMOS VLSI Design 4th Ed. 36

Lamda Based Layout Rules for p-well process

CMOS VLSI Design 4th Ed. 37

Lamda Based Layout Rules for p-well process

CMOS VLSI Design 4th Ed. 38

Lamda Based Layout Rules for p-well process

CMOS VLSI Design 4th Ed. 39

Lamda Based Layout Rules for p-well process

CMOS VLSI Design 4th Ed. 40

Lamda Based Layout Rules for p-well process

CMOS VLSI Design 4th Ed. 41

CMOS VLSI Design 4th Ed. 43
Feature Size = distance between
source and drain

CMOS VLSI Design 4th Ed. 44

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Simplified Lambda Based Design Rules for layouts
with 2 metal layers

CMOS VLSI Design 4th Ed. 73

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