Lecture 21:

Packaging,
Power, &
Clock
 Outline
‰ Packaging
‰ Power Distribution
‰ Clock Distribution

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 2
 Packages
‰ Package functions
– Electrical connection of signals and power from
chip to board
– Little delay or distortion
– Mechanical connection of chip to board
– Removes heat produced on chip
– Protects chip from mechanical damage
– Compatible with thermal expansion
– Inexpensive to manufacture and test

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 3
 Package Types
‰ Through-hole vs. surface mount

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 4
Chip-to-Package Bonding
‰ Traditionally, chip is surrounded by pad frame
– Metal pads on 100 – 200 μm pitch
– Gold bond wires attach pads to package
– Lead frame distributes signals in package
– Metal heat spreader helps with cooling

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 5
 Advanced Packages
‰ Bond wires contribute parasitic inductance
‰ Fancy packages have many signal, power layers
– Like tiny printed circuit boards
‰ Flip-chip places connections across surface of die
rather than around periphery
– Top level metal pads covered with solder balls
– Chip flips upside down
– Carefully aligned to package (done blind!)
– Heated to melt balls
– Also called C4 (Controlled Collapse Chip Connection)

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 6
 Package Parasitics
‰ Use many VDD, GND in parallel
– Inductance, IDD
Package

Chip Bond Wire Lead Frame Board

VDD VDD
Signal Pins

Signal Pads

Chip Package
Capacitor
Chip Board
GND GND

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 7
 Heat Dissipation
‰ 60 W light bulb has surface area of 120 cm2
‰ Itanium 2 die dissipates 130 W over 4 cm2
– Chips have enormous power densities
– Cooling is a serious challenge
‰ Package spreads heat to larger surface area
– Heat sinks may increase surface area further
– Fans increase airflow rate over surface area
– Liquid cooling used in extreme cases ($$$)

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 8
 Thermal Resistance
‰ ΔT = θjaP
– ΔT: temperature rise on chip
– θja: thermal resistance of chip junction to ambient
– P: power dissipation on chip
‰ Thermal resistances combine like resistors
– Series and parallel
‰ θja = θjp + θpa
– Series combination

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 9
 Example
‰ Your chip has a heat sink with a thermal resistance
to the package of 4.0° C/W.
‰ The resistance from chip to package is 1° C/W.
‰ The system box ambient temperature may reach
55° C.
‰ The chip temperature must not exceed 100° C.
‰ What is the maximum chip power dissipation?

‰ (100-55 C) / (4 + 1 C/W) = 9 W

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 10
 Temperature Sensor
‰ Monitor die temperature and throttle performance if it
gets too hot
‰ Use a pair of pnp bipolar transistors
– Vertical pnp available in CMOS
qVBE
kT I c
Ic = I se kT
→ VBE = ln
q Is
kT ⎛ I c1 I c 2 ⎞ kT ⎛ I c1 ⎞ kT
ΔVBE = VBE1 − VBE 2 = ⎜ ln − ln ⎟= ⎜ ln ⎟= ln m
q ⎝ I s I s ⎠ q ⎝ I c2 ⎠ q

‰ Voltage difference is proportional to absolute temp

– Measure with on-chip A/D converter

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 11
 Power Distribution
‰ Power Distribution Network functions
– Carry current from pads to transistors on chip
– Maintain stable voltage with low noise
– Provide average and peak power demands
– Provide current return paths for signals
– Avoid electromigration & self-heating wearout
– Consume little chip area and wire
– Easy to lay out

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 12
 Power Requirements
‰ VDD = VDDnominal – Vdroop
‰ Want Vdroop < +/- 10% of VDD
‰ Sources of Vdroop
– IR drops
– L di/dt noise
‰ IDD changes on many time scales
Power

Max
clock gating

Average

Min

Time

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 13
 IR Drop
‰ A chip draws 24 W from a 1.2 V supply. The power
supply impedance is 5 mΩ. What is the IR drop?
‰ IDD = 24 W / 1.2 V = 20 A
‰ IR drop = (20 A)(5 mΩ) = 100 mV

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 14
 L di/dt Noise
‰ A 1.2 V chip switches from an idle mode consuming
5W to a full-power mode consuming 53 W. The
transition takes 10 clock cycles at 1 GHz. The
supply inductance is 0.1 nH. What is the L di/dt
droop?
‰ ΔI = (53 W – 5 W)/(1.2 V) = 40 A
‰ Δt = 10 cycles * (1 ns / cycle) = 10 ns
‰ L di/dt droop = (0.1 nH) * (40 A / 10 ns) = 0.4 V

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 15
 Bypass Capacitors
‰ Need low supply impedance at all frequencies
‰ Ideal capacitors have impedance decreasing with ω
‰ Real capacitors have parasitic R and L
– Leads to resonant frequency of capacitor
2
10

1
10
0.03 Ω
impedance

1 μF 10
0

0.25 nH
-1
10

-2
10
4 5 6 7 8 9 10
10 10 10 10 10 10 10
frequency (Hz)

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 16
 Power System Model
‰ Power comes from regulator on system board
– Board and package add parasitic R and L
– Bypass capacitors help stabilize supply voltage
– But capacitors also have parasitic R and L
‰ Simulate system for time and frequency responses
Voltage Printed Circuit Package Solder Chip
Regulator Board Planes and Pins Bumps

Bulk Ceramic Package On-Chip On-Chip

VDD
Capacitor Capacitor Capacitor Capacitor Current Demand

Board Package

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 17
 Frequency Response
‰ Multiple capacitors in parallel
– Large capacitor near regulator has low impedance
at low frequencies
– But also has a low self-resonant frequency
– Small capacitors near chip and on chip have low
impedance at high frequencies
‰ Choose caps to get low impedance at all frequencies
impedance

frequency (Hz)

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 18
 Example: Pentium 4
‰ Power supply impedance for Pentium 4
– Spike near 100 MHz caused by package L
‰ Step response to sudden supply current chain
– 1st droop: on-chip bypass caps
– 2nd droop: package capacitance
– 3rd droop: board capacitance

[Xu08] [Wong06]

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 19
 Charge Pumps
‰ Sometimes a different supply voltage is needed but
little current is required
– 20 V for Flash memory programming
– Negative body bias for leakage control during sleep
‰ Generate the voltage on-chip with a charge pump

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 20
 Energy Scavenging
‰ Ultra-low power systems can scavenge their energy
from the environment rather than needing batteries
– Solar calculator (solar cells)
– RFID tags (antenna)
– Tire pressure monitors powered by vibrational
energy of tires (piezoelectric generator)
‰ Thin film microbatteries deposited on the chip can
store energy for times of peak demand

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 21
 Clock Distribution
‰ On a small chip, the clock distribution network is just
a wire
– And possibly an inverter for clkb
‰ On practical chips, the RC delay of the wire
resistance and gate load is very long
– Variations in this delay cause clock to get to
different elements at different times
– This is called clock skew
‰ Most chips use repeaters to buffer the clock and
equalize the delay
– Reduces but doesn’t eliminate skew
21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 22
 Example
‰ Skew comes from differences in gate and wire delay
– With right buffer sizing, clk1 and clk2 could ideally
arrive at the same time.
– But power supply noise changes buffer delays
– clk2 and clk3 will always see RC skew

gclk
3 mm 3.1 mm 0.5 mm
clk1 clk3
clk2
1.3 pF
0.4 pF 0.4 pF

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 23
 Review: Skew Impact
‰ Ideally full cycle is
clk clk

Q1 D2

F1

F2
Combinational Logic

available for work Tc

‰ Skew adds sequencing

clk
tpcq
tskew

Q1 tpdq tsetup

overhead D2

‰ Increases hold time too clk

Q1

F1
CL

t pd ≤ Tc − ( t pcq + tsetup + tskew )

 D2
clk

sequencing overhead

F2
tcd ≥ thold − tccq + tskew tskew

clk
thold

Q1 tccq

D2 tcd

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 24
 Solutions
‰ Reduce clock skew
– Careful clock distribution network design
– Plenty of metal wiring resources
‰ Analyze clock skew
– Only budget actual, not worst case skews
– Local vs. global skew budgets
‰ Tolerate clock skew
– Choose circuit structures insensitive to skew

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 25
 Clock Dist. Networks
‰ Ad hoc
‰ Grids
‰ H-tree
‰ Hybrid

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 26
 Clock Grids
‰ Use grid on two or more levels to carry clock
‰ Make wires wide to reduce RC delay
‰ Ensures low skew between nearby points
‰ But possibly large skew across die

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 27
 Alpha Clock Grids
Alpha 21064 Alpha 21164 Alpha 21264

PLL

gclk grid gclk grid

Alpha 21064 Alpha 21164 Alpha 21264

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 28
 H-Trees
‰ Fractal structure
– Gets clock arbitrarily close to any point
– Matched delay along all paths
‰ Delay variations cause skew
‰ A and B might see big skew A B

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 29
 Itanium 2 H-Tree
‰ Four levels of buffering:
– Primary driver
– Repeater Repeaters

– Second-level
clock buffer
– Gater
‰ Route around Typical SLCB
Locations

obstructions
Primary Buffer

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 30
 Hybrid Networks
‰ Use H-tree to distribute clock to many points
‰ Tie these points together with a grid

‰ Ex: IBM Power4, PowerPC

– H-tree drives 16-64 sector buffers
– Buffers drive total of 1024 points
– All points shorted together with grid

21: Package, Power, and Clock CMOS VLSI Design 4th Ed. 31