Introduction to Computer Chapter 3

Engineering Digital Logic

ECE/CS 252, Fall 2008
Prof. Mikko Lipasti
Structures
Department of Electrical and Computer Engineering
University of Wisconsin – Madison

Slides based on set prepared by

Gregory T. Byrd, North Carolina State University

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Transistor: Building Block of Computers Simple Switch Circuit

Microprocessors contain millions of transistors
• Intel Core 2 Duo: 291 million
Switch open:
• AMD Barcelona: 463 million
• No current through circuit
• IBM Power6: 790 million
• Light is off
• Vout is +2.9V
Logically, each transistor acts as a switch
Combined to implement logic functions Switch closed:
• AND, OR, NOT • Short circuit across switch
Combined to build higher-level structures • Current flows
• Adder, multiplexer, decoder, register, … • Light is on
Combined to build processor • Vout is 0V
• LC-3
Switch-based circuits can easily represent two states:
3-3 on/off, open/closed, voltage/no voltage. 3-4

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N-type MOS Transistor Planar N-type Metal-Oxide Semiconductor Field

Effect Transistor (MOSFET) Source Drain (GND)
MOS = Metal Oxide Semiconductor • Start with silicon substrate on Gate
• two types: N-type and P-type wafer
N-type • “Dope” to create P and N
• when Gate has positive voltage, wells/regions
N+ N+
short circuit between #1 and #2 • Channel conducts only if electric
field is present P-type substrate
(switch closed)
• when Gate has zero voltage, • Overlay SiO2 insulator N Channel

open circuit between #1 and #2 • Deposit metal (or polysilicon)

Gate = 1 gates, contacts
(switch open)
• Use photolithography
• Project geometric shape to etch Light
photoresist
• Apply dopants, metal vapor Mask
Gate = 0
• Repeat for each layer/component
Wafer
Terminal #2 must be
connected to GND (0V).
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P-type MOS Transistor Logic Gates

P-type is complementary to N-type Use switch behavior of MOS transistors
• when Gate has positive voltage, to implement logical functions: AND, OR, NOT.
open circuit between #1 and #2
(switch open) Digital symbols:
• when Gate has zero voltage, • recall that we assign a range of analog voltages to each
short circuit between #1 and #2 digital (logic) symbol
(switch closed)

Gate = 1

• assignment of voltage ranges depends on

electrical properties of transistors being used
Gate = 0
typical values for "1": +5V, +3.3V, +2.9V, +1.1V
Terminal #1 must be for purposes of illustration, we'll use +2.9V
connected to +2.9V.
3-7 3-8

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CMOS Circuit Inverter (NOT Gate)

Complementary MOS
Uses both N-type and P-type MOS transistors
• P-type
Attached to + voltage
Pulls output voltage UP when input is zero
yp
• N-type
Attached to GND
Pulls output voltage DOWN when input is one Truth table

For all inputs, make sure that output is either connected to GND or to +, In Out In Out
but not both!
0 V 2.9 V 0 1
2.9 V 0V 1 0

3-9 3-10

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NOR Gate OR Gate

A B C
0 0 0
0 1 1
1 0 1
1 1 1

A B C
0 0 1
0 1 0 Add inverter to NOR.
1 0 0
1 1 0
Note: Serial structure on top, parallel on bottom. 3-11 3-12

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NAND Gate (AND-NOT) AND Gate

A B C
0 0 0
0 1 0
1 0 0
1 1 1

A B C
0 0 1
0 1 1 Add inverter to NAND.
1 0 1
1 1 0
Note: Parallel structure on top, serial on bottom. 3-13 3-14

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Planar Realization of 2-input NAND Basic Logic Gates

• Gates made up of
planar
components:
• Metal: VDD, Ground,
Output C
• Polysilicon:
P l ili Inputs
I A
and B
• P diffusion: pullup
transistors
• N diffusion: pulldown
transistors

3-15 3-16

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More than 2 Inputs? Practice

AND/OR can take any number of inputs. Implement a 3-input NOR gate with CMOS.
• AND = 1 if all inputs are 1.
• OR = 1 if any input is 1.
• Similar for NAND/NOR.

Can implement with multiple two

two-input
input gates,
or with single CMOS circuit.

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Logical Completeness Practice

Can implement ANY truth table with AND, OR, NOT. Implement the following truth table.
A B C D A B C
0 0 0 0 0 0 0
0 0 1 0 1. AND combinations 0 1 1
that yield a "1" in the
0 1 0 1 1 0 1
truth table.
0 1 1 0 1 1 0
1 0 0 0
1 0 1 1 2. OR the results
1 1 0 0 of the AND gates.

1 1 1 0

3-19 3-20

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DeMorgan's Law Summary

Converting AND to OR (with some help from NOT) MOS transistors are used as switches to implement
Consider the following gate: logic functions.
• N-type: connect to GND, turn on (with 1) to pull down to 0
• P-type: connect to +2.9V, turn on (with 0) to pull up to 1

To convert AND to OR Basic gates: NOT, NOR, NAND

A B A B A B A B (or vice versa)
versa), • Logic
L i functions
f ti are usually
ll expressed
d with
ith AND,
AND OR,
OR and
d NOT
0 0 1 1 1 0 invert inputs and output.
0 1 1 0 0 1 Properties of logic gates
1 0 0 1 0 1 • Completeness
can implement any truth table with AND, OR, NOT
1 1 0 0 0 1
• DeMorgan's Law
convert AND to OR by inverting inputs and output
Same as A+B!

3-21 3-22

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Building Functions from Logic Gates Decoder

We've already seen how to implement truth tables n inputs, 2n outputs
using AND, OR, and NOT -- an example of • exactly one output is 1 for each possible input pattern
combinational logic.

Combinational Logic Circuit

• output depends only on the current inputs
• stateless
Sequential Logic Circuit
• output depends on the sequence of inputs (past and present) 2-bit
• stores information (state) from past inputs
decoder
We'll first look at some useful combinational circuits,
then show how to use sequential circuits to store
information.
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Multiplexer (MUX) Full Adder

n-bit selector and 2n inputs, one output Add two bits and carry-in,
• output equals one of the inputs, depending on selector produce one-bit sum and carry-out. A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

4-to-1 MUX

3-25 3-26

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Four-bit Adder Combinational vs. Sequential

Combinational Circuit
• always gives the same output for a given set of inputs
ex: adder always generates sum and carry,
regardless of previous inputs
Sequential Circuit
• stores information
• output depends on stored information (state) plus input
so a given input might produce different outputs,
depending on the stored information
• example: ticket counter
advances when you push the button
output depends on previous state
• useful for building “memory” elements and “state machines”

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R-S Latch: Simple Storage Element Clearing the R-S latch

R is used to “reset” or “clear” the element – set it to zero. Suppose we start with output = 1, then change R to zero.
S is used to “set” the element – set it to one. 1
0 1
1 1 1
0 1 1 0
1
1 0
0
1 Output changes to zero.
1 0 0 1
0 1
1 1
1 0
1

If both R and S are one, out could be either zero or one. 0 1

0
• “quiescent” state -- holds its previous value 0
• note: if a is 1, b is 0, and vice versa
3-29 Then set R=1 to “store” value in quiescent state. 3-30

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Setting the R-S Latch R-S Latch Summary

Suppose we start with output = 0, then change S to zero. R=S=1
1 • hold current value in latch
1 0 S = 0, R=1
• set value to 1
R = 0, S = 1
0 1
• set value to 0
1 Output changes to one.
0
0
R=S=0
1
• both outputs equal one
• final state determined by electrical properties of gates
1 0 • Don’t do it!
1

Then set S=1 to “store” value in quiescent state. 3-31 3-32

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Gated D-Latch Register

Two inputs: D (data) and WE (write enable) A register stores a multi-bit value.
• when WE = 1, latch is set to value of D • We use a collection of D-latches, all controlled by a common
S = NOT(D), R = D WE.
• when WE = 0, latch holds previous value • When WE=1, n-bit value D is written to register.
S = R = 1

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Representing Multi-bit Values Memory

Number bits from right (0) to left (n-1) Now that we know how to store bits,
• just a convention -- could be left to right, but must be consistent we can build a memory – a logical k × m array of
Use brackets to denote range: stored bits.
D[l:r] denotes bit l to bit r, from left to right
15 0

A = 0101001101010101 Address Space:

Add S
k = 2n
number of locations locations •
(usually a power of 2) •
•
A[14:9] = 101001 A[2:0] = 101

Addressability:
May also see A<14:9>, number of bits per location m bits
especially in hardware block diagrams. (e.g., byte-addressable)

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22 x 3 Memory More Memory Details

word select word WE
address input bits This is a not the way actual memory is implemented.
• fewer transistors, much more dense,
write relies on electrical properties
enable
But the logical structure is very similar.
• address decoder
• word select line
• word write enable
Two basic kinds of RAM (Random Access Memory)
Static RAM (SRAM)
• fast, not very dense (bitcell is a latch)
Dynamic RAM (DRAM)
• slower but denser, bit storage must be periodically refreshed
address
• each bitcell is a capacitor (like a leaky bucket) that decays
decoder
output bits 3-37 Also, non-volatile memories: ROM, PROM, flash, … 3-38

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SRAM Memory Memory Data In

State Machine
Write bitlines m
Another type of sequential circuit
• Combines combinational logic with storage
WE
D D ... D
• “Remembers” state, and changes output (and state)
ad Address Decoder

emory Read Address

based on inputs and current state

Read word line

D D ... D
Write Address Decoder
eAddress

n
...

Write word line State Machine

Rea
Memory Write

Me
...

n
...

Inputs Combinational Outputs

D D ... D Logic Circuit
D Q
Gated
D-latch
Read bitlines
WE Storage
m Elements
Memory Data Out

3-39 3-40

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Combinational vs. Sequential State

Two types of “combination” locks The state of a system is a snapshot of
all the relevant elements of the system
at the moment the snapshot is taken.
30
25 5 Examples:
4 1 8 4 20 10 • The state of a basketball g
game can be represented
p by
y
15
the scoreboard.
Number of points, time remaining, possession, etc.
Combinational Sequential
Success depends only on Success depends on • The state of a tic-tac-toe game can be represented by
the placement of X’s and O’s on the board.
the values, not the order in the sequence of values
which they are set. (e.g, R-13, L-22, R-3).

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State of Sequential Lock State Diagram

Our lock example has four different states, Shows states and
labelled A-D: actions that cause a transition between states.

A: The lock is not open,

and no relevant operations have been performed.
p ,
B: The lock is not open,
and the user has completed the R-13 operation.
C: The lock is not open,
and the user has completed R-13, followed by L-22.
D: The lock is open.

3-43 3-44

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Finite State Machine The Clock

A description of a system with the following components: Frequently, a clock circuit triggers transition from
one state to the next.
1. A finite number of states
“1”
2. A finite number of external inputs
“0”
3. A finite number of external outputs time
One
4
4. A explicit
An li it specification
ifi ti off all
ll state
t t transitions
t iti Cycle
5. An explicit specification of what causes each
external output value. At the beginning of each clock cycle,
state machine makes a transition,
Often described by a state diagram. based on the current state and the external inputs.
• Inputs may cause state transitions. • Not always required. In lock example, the input itself triggers a transition.
• Outputs are associated with each state (or with each transition).

3-45 3-46

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Implementing a Finite State Machine Storage: Master-Slave Flipflop

Combinational logic A pair of gated D-latches,
• Determine outputs and next state. to isolate next state from current state.
Storage elements
• Maintain state representation.

State Machine

Inputs Combinational Outputs

Logic Circuit

Storage During 1st phase (clock=1), During 2nd phase (clock=0),

Clock Elements previously-computed state next state, computed by
becomes current state and is logic circuit, is stored in
sent to the logic circuit. Latch A.
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Storage Complete Example

Each master-slave flipflop stores one state bit. A blinking traffic sign
• No lights on
• 1 & 2 on
The number of storage elements (flipflops) needed 3
• 1, 2, 3, & 4 on 4
is determined by the number of states 1
• 1, 2, 3, 4, & 5 on 5
(and the representation of each state). 2
• (repeat as long as switch
is turned on)
Examples:
• Sequential lock
DANGER
Four states – two bits MOVE
• Basketball scoreboard RIGHT
7 bits for each score, 5 bits for minutes, 6 bits for seconds,
1 bit for possession arrow, 1 bit for half, …

3-49 3-50

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Traffic Sign State Diagram Traffic Sign Truth Tables

Outputs Next State: S1’S0’
(depend only on state: S1S0) (depend on state and input)
Lights 1 and 2 Switch

Lights 3 and 4 In S1 S 0 S 1’ S 0’
Switch on Light 5
0 X X 0 0
Switch off
S1 S0 Z Y X 1 0 0 0 1
0 0 0 0 0 1 0 1 1 0
0 1 1 0 0 1 1 0 1 1
State bit S1
State bit S0 1 0 1 1 0 1 1 1 0 0
Outputs
1 1 1 1 1
Whenever In=0, next state is 00.

Transition on each clock cycle. 3-51 3-52

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Traffic Sign Logic From Logic to Data Path

The data path of a computer is all the logic used to
process information.
• See the data path of the LC-2 on next slide.

Combinational Logic
• Decoders -- convert instructions into control signals
• Multiplexers -- select inputs and outputs
• ALU (Arithmetic and Logic Unit) -- operations on data
Sequential Logic
• State machine -- coordinate control signals and data movement
Master-slave • Registers and latches -- storage elements
flipflop

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LC-2/LC-3 Data Path

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