Triple-Half-Bridge TLE 6208-3 G

1 Overview

1.1 Features
• Three Half-Bridges
• Optimized for DC motor management applications
• Delivers up to 0.6 A continuous, 1.2 A peak current
• RDS ON; typ. 0.8 Ω, @ 25 °C per switch P-DSO-14-9
• Output: short circuit protected and diagnosis Enhanced Power
• Overtemperature-Protection with hysteresis
and diagnosis
• Standard SPI-Interface/Daisy chain capable
• Very low current consumption in stand-by (Inhibit)
mode (typ. 10 µA for power and 2 µA for logic
supply, @ 25 °C)
• Over- and Undervoltage-Lockout
• CMOS/TTL compatible inputs with hysteresis
• No crossover current
• Internal clamp diodes
• Enhanced power P-DSO-Package
• Programming compatibility to the TLE 5208-6 G

Type Ordering Code Package

TLE 6208-3 G Q67006-A9334 P-DSO-14-9

Functional Description
The TLE 6208-3 G is a fully protected Triple-Half-Bridge-Driver designed specifically for
automotive and industrial motion control applications. The part is based on the Siemens
power technology SPT® which allows bipolar and CMOS control circuitry in accordance
with DMOS power devices existing on the same monolithic circuitry.
In motion control up to 2 actuators (DC-Motors) can be connected to the 3 halfbridge-
outputs (cascade configuration). Operation modes forward (cw), reverse (ccw), brake
and high impedance are controlled from a standard SPI-Interface. The possibility to
control the outputs via software from a central logic, allows limiting the power dissipation.
So the standard P-DSO-14-package meets the application requirements and saves
PCB-Board-space and cost. Furthermore the build-in features like Over- and
Undervoltage-Lockout, Over-Temperature-Protection and the very low quiescent current
in stand-by mode opens a wide range of automotive- and industrial-applications.

Data Sheet 1 2001-05-10

 TLE 6208-3 G

1.2 Pin Configuration (top view)

P-DSO-14-9

GND 1 14 GND

OUT 3 2 Leadframe 13 OUT 1

VS 3 12 OUT 2

CSN 4 Chip 11 V CC

DI 5 10 INH

CLK 6 9 DO

GND 7 8 GND

AEP02438

Figure 1

Data Sheet 2 2001-05-10

 TLE 6208-3 G

1.3 Pin Definitions and Functions

Pin No. Symbol Function
1 GND Ground; Reference potential; internal connection to pin 7, 8 and 14;
cooling tab; to reduce thermal resistance place cooling areas on PCB
close to these pins.
2 OUT3 Halfbridge-Output 3;
Internally contected to Highside-Switch 3 and Lowside-Switch 3. The
HS-Switch is a Power-MOS open drain with internal reverse diode;
The LS-Switch is a Power-MOS open source with internal reverse
diode; no internal clamp diode or active zenering;
short circuit protected and open load controlled.
3 VS Power Supply;
needs a blocking capacitor as close as possible to GND Value: 22 µF
electrolytic in parallel to 220 nF ceramic.
5 DI Serial Data Input; receives serial data from the control device; serial
data transmitted to DI is an 16bit control word with the Least
Significant Bit (LSB) being transferred first: the input has an active
pull down and requires CMOS logic level inputs;
DI will accept data on the falling edge of CLK-signal;
see Table Input Data Protocol.
4 CSN Chip-Select-Not Input; CSN is an active low input; serial
communication is enabled by pulling the CSN terminal low; CSN
input should only be transitioned when CLK is low; CSN has an
internal active pull up and requires CMOS logic level inputs.
6 CLK Serial Clock Input; clocks the shiftregister; CLK has an internal
active pull down and requires CMOS logic level inputs.
7, 8, 14 GND Ground; see pin 1.
9 DO Serial-Data-Output; this 3-state output transfers diagnosis data to
the control device; the output will remain 3-stated unless the device
is selected by a low on Chip-Select-Not (CSN);
see Table Diagnosis Data Protocol.
10 INH Inhibit Input; has an internal pull down;
device is switched in standby condition by pulling the INH terminal
low.
11 VCC Logic Supply Voltage;
needs a blocking capacitor as close as possible to GND;
Value: 10 µF electrolytic in parallel to 220 nF ceramic.
12 OUT2 Halfbridge-Output 2; see pin 2.
13 OUT1 Halfbridge-Output 1; see pin 2.

Data Sheet 3 2001-05-10

 TLE 6208-3 G

1.4 Functional Block Diagram

V CC VS
11 DRV1 3
Charge 13
Bias OUT 1
Pump

10 Fault-
INH Inhibit
Detect

4
CSN DRV2
5 16 Bit
DI Logic 12
6 SPI OUT 2
CLK and
9 Latch
DO

UV DRV3
>1 2
OV OUT 3

TSD
1,7,8,14
GND AEB02439

Figure 2 Block Diagram

Data Sheet 4 2001-05-10

 TLE 6208-3 G

1.5 Circuit Description

Figure 2 shows a block schematic diagram of the module. There are 3 halfbridge drivers
on the right-hand side. An HS driver and an LS driver are combined to form a halfbridge
driver in each case. The drivers communicate via the internal data bus with the logic and
the other control and monitoring functions: undervoltage (UV), overvoltage (OV),
overtemperature (TSD), charge pump and fault detect.
Two connection interfaces are provided for supply to the module: All power drivers are
connected to the supply voltage VS. These are monitored by overvoltage and
undervoltage comparators with hysteresis, so that the correct function can be checked
in the application at any time.
The logic is supplied by the VCC voltage, typ. with 5 V. The VCC voltage uses an internally
generated Power-On Reset (POR) to initialize the module at power-on. The advantage
of this system is that information stored in the logic remains intact in the event of short-
term failures in the supply voltage VS. The system can therefore continue to operate
following VS undervoltage, without having to be reprogrammed. The “undervoltage”
information is stored, and can be read out via the interface. The same logically applies
for overvoltage. “Interference spikes” on VS are therefore effectively suppressed.
The situation is different in the case of undervoltage on the VCC connection pin. If this
occurs, then the internally stored data is deleted, and the output levels are switched to
high-impedance status (tristate). The module is initialized by VCC following restart
(Power-On Reset = POR).
The 16-bit wide programming word or control word (see Table Input Data Protocol) is
read in via the DI data input, and this is synchronized with the clock input CLK. The status
word appears synchronously at the DO data output (see Table Diagnosis Data
Protocol). It is also possible to connect two TLE 6208-3 G in a daisy chain configuration.
The DO data output of one device is connected with the DI data input of the second
device. In this configuration these two devices are controlled with a single CSN chip
select and using a 32-bit wide control word.
The transmission cycle begins when the chip is selected with the CSN input (H to L). If
the CSN input changes from L to H then the word which has been read in becomes the
control word. The DO output switches to tristate status at this point, thereby releasing the
DO bus circuit for other uses.
The INH inhibit input can be used to cut off the complete module. This reduces the
current consumption to just a few µA, and results in the loss of any data stored. The
output levels are switched to tristate status. The module is reinitialized with the internally
generated POR (Power-On Reset) at restart.
This feature allows the use of this module in battery-operated applications (vehicle body
control applications).

Data Sheet 5 2001-05-10

 TLE 6208-3 G

Every driver block from DRV 1 to 3 contains a low-side driver and a high-side driver. Both
drivers are connected internally to form a half-bridge at the output. This reduction of
output pins was necessary to meet the small P-DSO-14 package.
When commutating inductive loads, the dissipated power peak can be significantly
reduced by activating the transistor located parallel to the internal freewheeling diode. A
special, integrated “timer” for power ON/OFF times ensures that there is no crossover
current.

Input Data Protocol Diagnosis Data Protocol

BIT BIT
15 OVLO on/off 15 Power supply fail
14 not used 14 Underload
13 Overcurrent SD on/off 13 Overload
12 not used 12 not used
11 not used 11 not used
10 not used 10 not used
9 not used 9 not used
8 not used 8 not used
7 not used 7 not used
6 HS-Switch 3 6 Status HS-Switch 3
5 LS-Switch 3 5 Status LS-Switch 3
4 HS-Switch 2 4 Status HS-Switch 2
3 LS-Switch 2 3 Status LS-Switch 2
2 HS-Switch 1 2 Status HS-Switch 1
1 LS-Switch 1 1 Status LS-Switch 1
0 Status Register Reset 0 Temp. Prewarning
H = ON H = ON
L = OFF L = OFF

Data Sheet 6 2001-05-10

 TLE 6208-3 G

Fault Result Table

Fault Diag.-Bit Result
Overcurrent (load) 13 Only the failed output is switched OFF. Function
can be deactivated by bit No. 13.
Short circuit to GND 13 Only the failed output is switched OFF. Function
(high-side-switch) can be deactivated by bit No. 13.
Short circuit to VS 13 Only the failed output is switched OFF. Function
(low-side-switch) can be deactivated by bit No. 13.
Temperature warning 0 Reaction of control device needed.
Temperature shut – All outputs OFF.
down (SD) Temperature warning is set before.
Underload/Openload 14 Reaction of control device needed.
Undervoltage lockout 15 All outputs OFF.
(UVLO)
Overvoltage lockout 15 All outputs OFF.
(OVLO) Function can be deactivated by bit No. 15.
H = failure;
L = no failure.

Data Sheet 7 2001-05-10

 TLE 6208-3 G

2 Electrical Characteristics

2.1 Absolute Maximum Ratings

Parameter Symbol Limit Values Unit Remarks
min. max.
Supply voltage VS – 0.3 40 V –
Supply voltage VS –1 – V t < 0.5 s; IS > – 2 A
Logic supply voltage VCC – 0.3 5.5 V 0 V < VS < 40 V
Logic input voltages VI – 0.3 5.5 V 0 V < VS < 40 V
(DI, CLK, CSN, INH) 0 V < VCC < 5.5 V
Logic output voltage VDO – 0.3 5.5 V 0 V < VS < 40 V
(DO) 0 V < VCC < 5.5 V
Output voltage VOUT – 0.3 40 V 0 V < VS < 40 V
(OUT 1-3)
Output current (cont.) IOUT1-3 – – A internal limited
Output current (peak) IOUT1-3 – – A internal limited
Note: Current limits are mentioned in the overcurrent section of electrical charateristics
Junction temperature Tj – 40 150 °C –
Storage temperature Tstg – 50 150 °C –
ESD voltage, human body VESD-HBM – – 4kV all pins
model, according to: VESD-HBM- – – 8kV only pins 2, 12 and
• MIL STD 883D, 13 (outputs)
OUT
• ANSI EOS\ESD S5.1
• JEDEC JESD22-A114
ESD voltage, mashine model, VESD-MM – – 300V all pins
according to:
• ANSI EOS\ESD S5.2
• JEDEC JESD22-A115

Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Data Sheet 8 2001-05-10

 TLE 6208-3 G

2.2 Operating Range

Parameter Symbol Limit Values Unit Remarks
min. max.
Supply voltage VS VUV OFF 40 V After VS rising
above VUV ON
Supply voltage slew rate dV S / dt – 10 V/µs –
Logic supply voltage VCC 4.75 5.50 V –
Supply voltage increasing VS – 0.3 VUV ON V Outputs in tristate
Supply voltage decreasing VS – 0.3 VUV OFF V Outputs in tristate
Logic input voltage (DI, CLK, VI – 0.3 VCC V –
CSN, INH)
SPI clock frequency fCLK – 1 MHz –
Junction temperature Tj – 40 150 °C –

Thermal Resistances

Junction pin Rthj-pin – 30 K/W measured to

pin 1, 7, 8, 14
Junction ambient RthjA – 65 K/W –

Note: In the operating range, the functions given in the circuit description are fulfilled.

Data Sheet 9 2001-05-10

 TLE 6208-3 G

2.3 Electrical Characteristics

8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C;
unless otherwise specified
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.

Current Consumption

Quiescent current IS – 8 20 µA INH = Low;

VS = 13.2 V
Tj = 25 °C
Quiescent current IS – – 30 µA INH = Low;
VS = 13.2 V;
Logic-Supply current ICC – 2 10 µA INH = Low
Logic-Supply current ICC – 1 2 mA SPI not active
Supply current IS – 2 5 mA –

Over- and Under-Voltage Lockout

UV-Switch-ON voltage VUV ON – 6.5 7 V VS increasing

UV-Switch-OFF voltage VUV OFF 5.6 6.1 6.6 V VS decreasing
UV-ON/OFF-Hysteresis VUV HY – 0.4 – V VUV ON – VUV OFF
OV-Switch-OFF voltage VOV OFF 34 37 40 V VS increasing
OV-Switch-ON voltage VOV ON 30 33 36 V VS decreasing
OV-ON/OFF-Hysteresis VOV HY – 4 – V VOV OFF – VOV ON

Data Sheet 10 2001-05-10

 TLE 6208-3 G

2.3 Electrical Characteristics (cont’d)

8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C;
unless otherwise specified
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.

Outputs OUT1-3

Static Drain-Source-On Resistance

Source (High-Side) RDS ON H – 0.8 0.95 Ω 8 V < VS < 40 V

IOUT = – 0.5 A Tj = 25 °C
– 1.6 Ω 8 V < VS < 40 V
1 – Ω VS OFF < VS ≤ 8 V
Tj = 25 °C
– 2 Ω VS OFF < VS ≤ 8 V
Sink (Low-Side) RDS ON L – 0.75 0.9 Ω 8 V < VS < 40 V
IOUT = 0.5 A Tj = 25 °C
– 1.5 Ω 8 V < VS < 40 V
1 – Ω VS OFF < VS ≤ 8 V
Tj = 25 °C
– 2 Ω VS OFF < VS ≤ 8 V

Leakage Current

Source-Output-Stage 1 to 3 IQLH –5 –1 – µA VOUT1-3 = 0 V

Sink-Output-Stage 1 to 3 IQLL – 150 300 µA VOUT1-3 = VS

Overcurrent

Source shutdown threshold ISDU –2 – 1.3 – 1 A –

Sink shutdown threshold ISDL 1 1.2 2 A –
Current limit IOCL – 2.4 4 A sink and source
Shutdown delay time tdSD 10 28 40 µs sink and source

Data Sheet 11 2001-05-10

 TLE 6208-3 G

2.3 Electrical Characteristics (cont’d)

8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C;
unless otherwise specified
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.

Open Circuit/Underload Detection

Detection current IOCD 15 30 45 mA –

Delay time tdOC 200 370 600 µs –

Output Delay Times; VS = 13.2 V; RLoad = 25 Ω (device not in stand-by for t > 1 ms)

Source ON td ON H – 8 20 µs –
Source OFF td OFF H – 4 20 µs –
Sink ON td ON L – 7 20 µs –
Sink OFF td OFF L – 3 20 µs –
Dead time tD HL 1 3 – µs td ON L – td OFF H
Dead time tD LH 1 5 – µs td ON H – td OFF L

Output Switching Times; VS = 13.2 V; RLoad = 25 Ω (device not in stand-by for t > 1 ms)

Source ON tON H – 5 20 µs –
Source OFF tOFF H – 2 5 µs –
Sink ON tON L – 2.0 10 µs –
Sink OFF tOFF L – 1.5 5 µs –

Clamp Diodes Forward Voltage

Upper VFU – 0.9 1.3 V IF = 0.5 A

Lower VFL – 0.9 1.3 V IF = 0.5 A

Data Sheet 12 2001-05-10

 TLE 6208-3 G

2.3 Electrical Characteristics (cont’d)

8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C;
unless otherwise specified
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.

Inhibit Input

H-input voltage threshold VIH – 0.52 0.7 VCC –

L-input voltage threshold VIL 0.2 0.48 – VCC –
Hysteresis of input voltage VIHY 50 200 500 mV –
Pull down current II 5 25 100 µA VI = 0.2 × VCC
Input capacitance CI – 10 15 pF 0 V < VCC <
5.25 V
Note: Capacitances are guaranteed by design.

SPI-Interface

Delay Time from Stand-by to Data In/Power on Reset

Setup time tset – – 100 µs –

Logic Inputs DI, CLK and CSN

H-input voltage threshold VIH – 0.52 0.7 VCC –

L-input voltage threshold VIL 0.2 0.48 – VCC –
Hysteresis of input voltage VIHY 50 200 500 mV –
Pull up current at pin CSN IICSN – 50 – 25 – 10 µA VCSN = 0.7 × VCC
Pull down current at pin DI IIDI 10 25 50 µA VDI = 0.2 × VCC
Pull down current at pin CLK IICLK 10 25 50 µA VCLK = 0.2 × VCC
Input capacitance CI – 10 15 pF 0 V < VCC <
at pin CSN, DI or CLK 5.25 V
Note: Capacitances are guaranteed by design.

Data Sheet 13 2001-05-10

 TLE 6208-3 G

2.3 Electrical Characteristics (cont’d)

8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C;
unless otherwise specified
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.

Logic Output DO

H-output voltage level VDOH VCC VCC – V IDOH = 1 mA

– 1.0 – 0.7
L-output voltage level VDOL – 0.2 0.4 V IDOL = – 1.6 mA
Tri-state leakage current IDOLK – 10 0 10 µA VCSN = VCC
0 V < VDO < VCC
Tri-state input capacitance CDO – 10 15 pF VCSN = VCC
0 V < VCC <
5.25 V
Note: Capacitances are guaranteed by design.

Data Input Timing

Clock period tpCLK 1000 – – ns –

Clock high time tCLKH 500 – – ns –
Clock low time tCLKL 500 – – ns –
Clock low before CSN low tbef 500 – – ns –
CSN setup time tlead 500 – – ns –
CLK setup time tlag 500 – – ns –
Clock low after CSN high tbeh 500 – – ns –
DI setup time tDISU 250 – – ns –
DI hold time tDIHO 250 – – ns –
Input signal rise time trIN – – 200 ns –
at pin DI, CLK and CSN
Input signal fall time tfIN – – 200 ns –
at pin DI, CLK and CSN

Data Sheet 14 2001-05-10

 TLE 6208-3 G

2.3 Electrical Characteristics (cont’d)

8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C;
unless otherwise specified
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.

Data Output Timing

DO rise time trDO – 50 100 ns CL = 100 pF

DO fall time tfDO – 50 100 ns CL = 100 pF
DO enable time tENDO – – 250 ns low impedance
DO disable time tDISDO – – 250 ns high impedance
DO valid time tVADO – 100 250 ns VDO < 0.2 VCC;
VDO > 0.7 VCC;
CL = 100 pF

Thermal Prewarning and Shutdown

Thermal prewarning junction TjPW 120 145 170 °C –

temperature
Temperature prewarning ∆T – 30 – K –
hysteresis
Thermal shutdown junction TjSD 150 175 200 °C –
temperature
Thermal switch-on junction TjSO 120 – 170 °C –
temperature
Temperature shutdown ∆T – 30 – K –
hysteresis
Ratio of SD to PW TjSD/TjPW 1.05 1.20 – – –
temperature
Note: Temperatures are guaranteed by design.
The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and
the given supply voltage.

Data Sheet 15 2001-05-10

 TLE 6208-3 G

3 Timing Diagrams

CSN High to Low & rising edge of CLK: DO is enabled. Status information is transferred to Output Shift Register

CSN

time
CSN Low to High: Data from Shift-Register is transferred to Output Power Switches

CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1

time

Actual Data New Data

DI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
+ +
time
DI: Data will be accepted on the falling edge of CLK-Signal
Previous Status Actual Status
DO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
- - - - - - - - - - - - - - - -
time
DO: State will change on the rising edge of CLK-Signal
e.g.
Old Data Actual Data
HS1
time
AET02177

Figure 3 Data Transfer Timing

Data Sheet 16 2001-05-10

 TLE 6208-3 G

CSN High to Low & CLK Stays Low: Status information of Data Bit 0 (temperature prewarning) is transfered to DO

CSN

time
CLK

time

DI

time
DI: Data is not accepted

DO 0-

time
DO: Status information of Data Bit 0 (temperature prewarning) will stay as long as CSN is low
AET02620

Figure 4 Timing for Temperature Prewarning only

0.7 VCC
CSN
0.2 VCC
t CLKH
0.7 VCC
CLK
0.2 VCC

t lead t CLKL t lag

t DISU
t bef t DIHO t beh

0.7 VCC
Don’t
DI Don’t Care Valid Valid Don’t Care
Care
0.2 VCC
AET02178

Figure 5 SPI-Input Timing

Data Sheet 17 2001-05-10

 TLE 6208-3 G

t rIN t fIN

70%
CSN 50%
20%
t dOFF

70%
Case 1
Ι OUT ON State OFF State 50%
20%
t OFF
t dON
t ON

70%
Case 2
Ι OUT OFF State ON State 50%
20%
AET02179

Figure 6 Turn OFF/ON Time

t rIN t fIN <_ 10 ns

0.7 VCC
CLK 50%
0.2 VCC
t rDO

0.7 VCC
DO (low to high)
0.2 VCC
t VADO
t fDO

0.7 VCC
DO
(high to low)
0.2 VCC
AET02180

Figure 7 DO Valid Data Delay Time and Valid Time

Data Sheet 18 2001-05-10

 TLE 6208-3 G

t fIN t rIN <_ 10 ns

0.7 VCC
CSN 50%
0.2 VCC
t ENDO t DISDO

10 k Ω
DO Pullup 50%
to VCC
t ENDO t DISDO

DO 10 k Ω
Pulldown 50%
to GND

AET02181

Figure 8 DO Enable and Disable Time

Data Sheet 19 2001-05-10

 TLE 6208-3 G

Watchdog
Reset Ι
TLE 4278G V S = 12V
Q D01
1N4001

D D02
CQ CD CS
22 µF Z39
47 nF 10 µF

WD R V CC V CC VS
11 DRV1 3
Charge 13 OUT 1
Bias
Pump

INH 10 Fault-
Inhibit
Detect
M

CSN 4
DRV2
DI 5 16 Bit
Logic 12 OUT 2
CLK 6 SPI
µP and
DO 9 Latch

UV DRV3
>1 2 OUT 3
OV

TSD
1,7,8,14
GND GND
AEB02441

Figure 9 Application Circuit

Data Sheet 20 2001-05-10

 TLE 6208-3 G

4 Package Outlines

P-DSO-14-9
(Plastic Dual Small Outline Package)

GPS09222

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device Dimensions in mm

Data Sheet 21 2001-05-10