Freescale Semiconductor Document Number: FXTH870xD

Data Sheet: Advance Information Rev. 1.4, 02/2015

An Energy-Efficient Solution by Freescale

FXTH870xD Tire Pressure Monitor

Sensor FXTH870xD
The FXTH870xD family is comprised of the following functions all within the
same package.
Features
Top and bottom view
• Pressure sensor with one of two calibrated pressure ranges
— 100 - 450 kPa
— 100 - 900 kPa
• Temperature sensor
• Optional XZ- or Z-axis accelerometer with adjustable offset option
• Voltage reference measured by ADC10
• Six-channel, 10-bit analog-to-digital converter (ADC10) with two external
24-Pin, 1-hole lid
I/O inputs
7 x 7 QFN
• 8-bit MCU
— S08 Core with SIM and interrupt
— 512 RAM
Top view
— 8K FLASH (in addition to 8K providing factory firmware and trim
data)
ID Feature

24 PTB0
— 64-byte, low-power, parameter registers

23 N/C

22 N/C

21 N/C

20 N/C

19 N/C
on top lid

• Dedicated state machines to sequence routine measurement and

transmission processes for reduced power consumption PTB1 1 18 PTA3

• Internal 315-/434-MHz RF transmitter PTA2 2 17 LFA

— External crystal oscillator

PTA1 3 16 LFB
— PLL-based output with fractional-n divider
PTA0 4 15 BKGD/PTA4
— OOK and FSK modulation capability
RESET 5 14 X0
— Programmable data rate generator
— Manchester, Bi-Phase or NRZ data encoding VSS 6 13 X1
RFVSS 10

RF 11

VREG 12
9
8
VDD 7

— 256-bit RF data buffer variable length interrupt

VDDA

VSSA

— Direct access to RF transmitter from MCU for unique formats

— Low power consumption (less than 8 mA at 434 MHz, 5 dBM at
3.0 V, 25 °C) Pin connections
• Differential input LF detector/decoder on independent signal pins
• Seven multipurpose GPIO pins
— Four pins can be connected to optional internal pullups/pulldowns and STOP4 wakeup interrupt
— Two of seven pins can be connected to a channel on the ADC10
— Two of seven pins can be connected to a channel on the TPM1
• Real-Time Interrupt driven by LFO with interrupt intervals of
8, 16, 32, 64, 128, 256, 512 or 1024 ms
• Low-power, wakeup timer and periodic reset driven by LFO
• Watchdog timeout with selectable times and clock sources
• Two-channel general purpose timer/PWM module (TPM1)

This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© 2014-2015 Freescale Semiconductor, Inc. All rights reserved.
• Internal oscillators
— MCU bus clock of 0.5, 1, 2 and 4 MHz (1, 2, 4 and 8 MHz HFO)
— Low frequency, low power time clock (LFO) with 1 ms period
— Medium frequency, controller clock (MFO) of 8 sec period
• Low-voltage detection
• Normal temperature restart in hardware (over- or under-temperature detected by software)

ORDERING INFORMATION
Part number Accelerometer axis Package Range Code1
FXTH870502DT1 Z 2264 (7 x 7, 1-hole lid) 100-450 kPa $08
FXTH870511DT1 XZ 2264 (7 x 7, 1-hole lid) 100-450 kPa $0C
FXTH870902DT1 Z 2264 (7 x 7, 1-hole lid) 100-900 kPa $18
FXTH870911DT1 XZ 2264 (7 x 7, 1-hole lid) 100-900 kPa $1C
FXTH870912DT1 XZ Ext. Range 2264 (7 x 7, 1-hole lid) 100-900 kPa $1E

Related Documentation
The FXTH870xD device features and operations are described in a variety of reference manuals, user guides, and application
notes. To find the most-current versions of these documents:
1. Go to the Freescale homepage at:
http://www.freescale.com/

2. In the Keyword search box at the top of the page, enter the device number FXTH870xD.

FXTH870xD
Sensors
Freescale Semiconductor, Inc. 2
Contents
1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Overall Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Multi-Chip Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 System Clock Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Pins and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Recommended Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 RUN Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 WAIT Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 ACTIVE BACKGROUND Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 MCU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Reset and Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 MCU Register Addresses and Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 High Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 MCU Parameter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6 MCU RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7 FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.8 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.9 FLASH Registers and Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5 Reset, Interrupts and System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 MCU Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3 Computer Operating Properly (COP) Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4 SIM Test Register (SIMTST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.6 Low-Voltage Detect (LVD) System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.7 System Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.8 Keyboard Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.9 Real Time Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.10 Temperature Sensor and Restart System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.11 Reset, Interrupt and System Control Registers And Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.12 System STOP Exit Status Register (SIMSES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6 General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1 Unused Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.2 Pin Behavior in STOP Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.3 General Purpose I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.4 Port A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.5 Port B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7 Keyboard Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.4 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.5 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8 Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.3 Programmer’s Model and CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.4 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.5 Special Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.6 HCS08 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

FXTH870xD
Sensors
Freescale Semiconductor, Inc. 1
9 Timer Pulse-Width Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.2 TPM1 Configuration Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.4 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.6 TPM1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10 Other MCU Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.1 Pressure Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.2 Temperature Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.3 Voltage Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.4 Optional Acceleration Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.5 Optional Battery Condition Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.6 Measurement Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.7 Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11 Periodic Wakeup Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.2 Wakeup Divider Register - PWUDIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.3 PWU Control/Status Register 0 - PWUCS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.4 PWU Control/Status Register 1 - PWUCS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.5 PWU Wakeup Status Register - PWUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.6 Functional Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12 LF Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.3 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.4 Input Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.5 LFR Data Mode States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.6 Carrier Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.7 Auto-Zero Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.8 Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.9 Data Clock Recovery and Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.10 Manchester Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.11 Duty-Cycle For Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.12 Input Signal Envelope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.13 Telegram Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.14 Error Detection and Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.15 Continuous ON Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.16 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.17 LFR Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13 RF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
13.1 RF Data Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
13.2 RF Output Buffer Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.3 Transmission Randomization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
13.4 RFM in STOP1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.5 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.6 RF Output Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.7 RF Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.8 Datagram Transmission Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.9 RFM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.10 RFM Control Register 1 - RFCR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.11 RFM Control Register 2 - RFCR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.12 RFM Control Register 3 - RFCR3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
13.13 RFM Control Register 4 - RFCR4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.14 RFM Control Register 5 - RFCR5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.15 RFM Control Register 6 - RFCR6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.16 RFM Control Register 7 - RFCR7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.17 PLL Control Registers A- PLLCR[1:0], RPAGE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.18 PLL Control Registers B- PLLCR[3:2], RPAGE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
13.19 EPR Register - EPR (RPAGE = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
13.20 RF DATA Registers - RFD[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.21 VCO Calibration Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

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2 Freescale Semiconductor, Inc.
14 Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.1 Software Jump Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.2 Function Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.3 Memory Resource Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
15.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
15.2 Background Debug Controller (BDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
15.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
16 Battery Charge Consumption Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
16.1 Standby Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
16.2 Measurement Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
16.3 Transmission Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
16.4 Total Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
17 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
17.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
17.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
17.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
17.4 Power Consumption (MCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
17.5 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
17.6 Voltage Measurement Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
17.7 Temperature Measurement Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
17.8 Pressure Measurement Characteristic (100 to 450 kPa ranges) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
17.9 Pressure Measurement Characteristic (100 to 900 kPa Ranges) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
17.10 Optional Acceleration Sensor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
17.11 LFR Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
17.12 LFR Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
17.13 LFR Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
17.14 RF Output Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
17.15 Power Consumption RF Transmissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
18 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
18.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
18.2 Media Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
18.3 Mounting Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
19 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
20 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

FXTH870xD
Sensors
Freescale Semiconductor, Inc. 3
1 General Information
1.1 Overall Block Diagram
The block diagram of the FXTH870xD is shown in Figure 1. This diagram covers all the main blocks mentioned above and their
main signal interactions. Power management controls and bus control signals are not shown in this block diagram for clarity.

1.2 Multi-Chip Interface

The FXTH870xD contains two to three devices using the best process technology for each.
• Microcontroller with accelerometer and pressure sensor interfaces, and RF transmitter (MCU)
• Optional ranges on pressure transducers
• Optional XZ- or Z-axis acceleration transducer
As shown in Figure 1 the MCU interfaces to the RF transmitter using a standard memory mapped registers. The transducers
connect to the MCU using custom analog interfaces and inter-chip bonding wires.

1.3 System Clock Distribution

The various clock sources and their distribution are shown in Figure 2. All clock sources except the low frequency oscillator, LFO,
can be turned off by software control in order to conserve power.

FXTH870xD

Sensors
4 Freescale Semiconductor, Inc.
 SENSOR MEASUREMENT
TRANSDUCERS SMI MCU
PWU

INTERFACE
PRESS TIMER
P SENSOR

(SMI)
XZ Z LFO LFO
1 ms RTI
ACCEL ACCEL TIMER
(OPTION) (OPTION)
BKGD/
VSENS PTA4
LVD
XZ Z
OSC
TEMP MCU CORE
ADC10 VDD VDD
RESTART S08
10-BIT
TEMP VTP AVDD AVDD
TEMP SENSOR 6-CHAN
HFO 64 Byte
1, 2, 4 or 8 PARAMETER
AVSS
MHz REGISTER
BANDGAP V0
REF
MFO MFO VSS
RAM
8 Sec
MEMORY
V1 512
VREG V2
8K USER
FLASH
AVDD MEMORY RESET

8K
VOLT FIRMWARE
VREG REG MEMORY
RFVDD
DX TPM1
BIT TIMER/PWM
XI XTAL RATE 2-CHAN
OSC GEN
RF LVD
XO

LF LFA
RECVR
(LFR)
256-BIT LFI LFB
RF CONTROLLER

DATA
VCO/PLL BUFFER
FRACTL
DIVIDER
DATA
ENCODE

RF RF PTA0
AMP
RVSS PTA1

KEY
GP PTA2
RFM BOARD
KBI WAKEUP I/O
PTA3

PTB0

PTB1

Figure 1. FXTH870xD Overall Block Diagram

FXTH870xD

Sensors
Freescale Semiconductor, Inc. 5
 SYSTEM MCU
LFO ADC10
OSC RTICLKS CONTROL CLOCK
1 mS LOGIC
PERIOD
PAR
ADC10 REG RAM FLASH
BUSCLKS[1:0] RTI

ADCCLK ADC10
HFO OSC fOSC fBUS 4 kbps
1, 2, 4, 2
and 8 MHz
LF
CLSA, CLKSB
COPCLKS (125 kHz)

CPU
WATCH LFRO
TPM1 LFR
DOG OSCILL

CH0 CH1
BDC fLFO (1 kHz)

PTA3 RANDOM
TCLKDIV (0 - 1 MHz)
PWU DX (500 kHz)
fLFO (1 kHz)
PTA2 RANDOM
8 (0 - 1 MHz)

LFOSEL
fMFO

fMFO
BIT MFO
RATE RF STATE OSC
GEN MACHINE 8 Sec
XTL
OSC
26 MHz fXCO

XI XO DATA
PLL VCO
BUFFER SENSOR MEASUREMENT
INTERFACE

RF
OUT 41.67 kHz 41.67 kHz 41.67 kHz
Sampling Sampling Sampling

PRESSURE X-AXIS Z-AXIS

SENSOR SENSOR SENSOR

TRANSDUCERS

Figure 2. FXTH870xD Clock Distribution

1.4 Reference Documents

The FXTH870xD utilizes the standard product MC9S08 CPU core. The user can obtain further detail on the full capabilities of
this core by referring to the HCS08 Family Reference Manual (HCS08RMV1).

FXTH870xD

Sensors
6 Freescale Semiconductor, Inc.
2 Pins and Connections
This section describes the pin layout and general function of each pin.

2.1 Package Pinout

The pinout for the FXTH870xD device QFN package is shown in Figure 3 for the orientation of the pressure port up. The
orientation of the internal Z-axis accelerometer is shown in Figure 4.

Top View
ID Feature
24 PTB0

23 N/C

22 N/C

21 N/C

20 N/C

19 N/C
on top lid +Y

PTB1 1 18 PTA3
Y-AXIS
ORIENTATION
PTA2 2 17 LFA

PTA1 3 16 LFB
-Y
PTA0 4 15 BKGD/PTA4

RESET 5 14 X0
-X +X
VSS 6 13 X1 X-AXIS
ORIENTATION
RFVSS 10

RF 11

VREG 12
9
8
VDD 7

VDDA

VSSA

N/C = No Connect: Do not connect PCB pads to signal traces, power/ground or multi-layer via.

Figure 3. FXTH870xD QFN Package Pinout

Pressure +Z
Port

Z-AXIS
ORIENTATION
Side View

POSITIVE ACCELERATION MOVES MASS

IN +Z DIRECTION (VALUE INCREASES)
-Z
Figure 4. FXTH870xD QFN Optional Z-axis Accelerometer Orientation

2.2 Recommended Application

Example of a simple OOK/FSK tire pressure monitors using the internal PLL-based RF output stage is shown in Figure 5. Any of
the PTA[3:0] pins can also be used as general purpose I/O pins. Any of the PTA[3:0] pins that are not used in the application
should be handled as described in Section 6.1.

FXTH870xD

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Freescale Semiconductor, Inc. 7
2.3 Signal Properties
The following sections describe the general function of each pin.
g
L1 and matching network
optimized for specific PWB and
antenna layout. Recommend
R2 and R3, <10 k 0603 minimum size for L1 and
recommended for R2 R3
highest EMC resistance other matching network inductors
BKGD/PTA4 for maximum efficiency.
RESET
ANT
AVDD
3.0 V VDD L1
BATTERY RF MATCHING
0.1 µF 0.1 µF NETWORK

VSS
AVSS RVSS
FXTH870xxx
LFA
R1
LF VREG
COIL
C1
LFB XI C4*

PTA0
C1 and R1 optimized XO
XTAL
for coil used, but PTA1 470 nF
recommended
PTA2 C5
RC < 15.3 sec. C2 C3
PTA3 C2, C3, C4
optimized
PTB0
for crystal
PTB1
GENERAL
PURPOSE I/O

The device C4, although drawn here as a capacitor, may be any type of passive component(s) sufficient to block
or reduce unwanted external radiated signals from corrupting the crystal oscillator circuit: PCB traces for the LFA
/ LFB, AVDD / VDD, and VSS / AVSS pins and bypass capacitors should be minimized to reduce unwanted external
radiated signals from corrupting the power input circuits.

Figure 5. FXTH870xD Example Application

2.3.1 VDD and VSS Pins

The digital circuits operate from a single power supply connected to the FXTH870xD through the VDD and VSS pins. VDD is the
positive supply and VSS is the ground. The conductors to the power supply should be connected to the VDD and VSS pins and
locally decoupled as shown in Figure 6.
Care should be taken to reduce measurement signal noise by separating the VDD, VSS, AVDD, AVSS and RVSS pins using a “star”
connection such that each metal trace does not share any load currents with other external devices as shown in Figure 6.

2.3.2 AVDD and AVSS Pins

The analog circuits operate from a single power supply connected to the FXTH870xD through the AVDD and AVSS pins. AVDD is
the positive supply and AVSS is the ground. The conductors to the power supply should be connected to the AVDD and AVSS pins
and locally decoupled as shown in Figure 6.

FXTH870xD

Sensors
8 Freescale Semiconductor, Inc.
Care should be taken to reduce measurement signal noise by separating the VDD, VSS, AVDD, AVSS and RVSS pins using a “star”
connection such that each metal trace does not share any load currents with other external devices as shown in Figure 6.

Bypass capacitors FXTH870xxx and Other Load Currents

closely coupled to star connected to battery terminals
the package pins
FXTH870xxx IDD ILOAD
VDD
0.1 µF Battery to other
loads
VSS

The decoupling devices, although

AVDD drawn here as 0.1 F capacitors,
may be any type of passive component(s)
0.1 µF
sufficient to block or reduce unwanted
AVSS external radiated signals from corrupting
the power input protection circuits;
application tuning may be required.
RVSS

Figure 6. Recommended Power Supply Connections

2.3.3 VREG Pin

The internal regulator for the analog circuits requires an external stabilization capacitor to AVSS.

2.3.4 RVSS Pin

Power in the RF output amplifier is returned to the supply through the RVSS pin. This conductor should be connected to the power
supply as shown in Figure 6 using a “star” connection such that each metal trace does not share any load currents with other
supply pins.

2.3.5 RF Pin
The RF pin is the RF energy data supplied by the FXTH870xD to an external antenna.

2.3.6 XO, XI Pins

The XO and XI pins are for an external crystal to be used by the internal PLL for creating the carrier frequencies and data rates
for the RF pin.

2.3.7 LF[A:B] Pins

The LF[A:B] pins can be used by the LF receiver (LFR) as one differential input channel for sensing low level signals from an
external low frequency (LF) coil. The external LF coil should be connected between the LFA and the LFB pins.
Signaling into the LFR pins can place the FXTH870xD into various diagnostic or operational modes. The LFR is comprised of
the detector and the decoder.
Each LF[A:B] pin will always have an impedance of approximately 500 k to VSS due to the LFR input circuitry. The LFA/LFB
pins are used by the LFR when the LFEN control bit is set and are not functional when the LFEN control bit is clear.

2.3.8 PTA[1:0] Pins

The PTA[1:0] pins are general purpose I/O pins. These two pins can be configured as normal bidirectional I/O pins with
programmable pullup or pulldown devices and/or wakeup interrupt capability; or one or both can be connected to the two input
channels of the A/D converter module. The pulldown devices can only be activated if the wakeup interrupt capability is enabled.
User software must configure the general purpose I/O pins so that they do not result in “floating” inputs as described in
Section 6.1. PTA[1:0] map to Keyboard Interrupt function bits [1:0].

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2.3.9 PTA[3:2] Pins
The PTA[3:2] pins are general purpose I/O pin. These two pins can be configured as normal bidirectional I/O pin with
programmable pullup or pulldown devices and/or wakeup interrupt capability; or one or both can be connected to the two input
channels of the Timer Pulse Width (TPM1) module. The pulldown devices can only be activated if the wakeup interrupt capability
is enabled. User software must configure the general purpose I/O pins so that they do not result in “floating” inputs as described
in Section 6.1. PTA[3:2] map to Keyboard Interrupt function bits [3:2].

2.3.10 BKGD/PTA4 Pin

The BKGD/PTA4 pin is used to place the FXTH870xD in the BACKGROUND DEBUG mode (BDM) to evaluate MCU code and
to also transfer data to/from the internal memories. If the BKGD/PTA4 pin is held low when the FXTH870xD comes out of a power-
on reset the device will go into the ACTIVE BACKGROUND DEBUG mode (BDM).
The BKGD/PTA4 pin has an internal pullup device and can connected to VDD in the application unless there is a need to enter
BDM operation after the device as been soldered into the PWB. If in-circuit BDM is desired the BKGD/PTA4 pin can be left
unconnected, but should be connected to VDD through a low impedance resistor (<10 k) which can be over-driven by an
external signal. This low impedance resistor reduces the possibility of getting into the debug mode in the application due to an
EMC event.

2.3.11 RESET Pin

The RESET pin is used for test and establishing the BDM condition and providing the programming voltage source to the internal
FLASH memory. This pin can also be used to direct to the MCU to the reset vector as described in Section 5.2.
The RESET pin has an internal pullup device and can connected to VDD in the application unless there is a need to enter BDM
operation after the device as been soldered to the PWB. If in-circuit BDM is desired the RESET pin can be left unconnected; but
should be connected to VDD through a low impedance resistor (<10 k) which can be over-driven by an external signal. This low
impedance resistor reduces the possibility of getting into the debug mode in the application due to an EMC event.
Activation of the external reset function occurs when the voltage on the RESET pin goes below 0.3 x VDD for at least 100 nsec
before rising above 0.7 x VDD as shown in Figure 7.

> 100 nsec

0.7 VDD
RESET
Reset
Initiated
0.3 VDD

Figure 7. RESET Pin Timing

2.3.12 PTB[1:0] Pins

The PTB[1:0] pins are general purpose I/O pins. These two pins can be configured as nominal bidirectional I/O pins with
programmable pullup devices. User software must configure the general purpose I/O pins so that they do not result in “floating”
inputs as described in Section 6.1

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3 Modes of Operation
The operating modes of the FXTH870xD are described in this section. Entry into each mode, exit from each mode, and
functionality while in each of the modes are described.

3.1 Features
• ACTIVE BACKGROUND DEBUG mode for code development
• STOP modes:
— System clocks stopped
— STOP1: Power down of most internal circuits, including RAM, for maximum power savings; voltage regulator in
standby
— STOP4: All internal circuits powered and full voltage regulation maintained for fastest recovery

3.2 RUN Mode

This is the normal operating mode for the FXTH870xD. This mode is selected when the BKGD/PTA4 pin is high at the rising edge
of reset. In this mode, the CPU executes code from internal memory following a reset with execution beginning at address
specified by the reset pseudo-vector ($DFFE and $DFFF).

3.3 WAIT Mode

The WAIT mode is also present like other members of the Freescale S08 family members; but is not normally used by the
FXTH870xD firmware or typical TPMS applications.

3.4 ACTIVE BACKGROUND Mode

The ACTIVE BACKGROUND mode functions are managed through the BACKGROUND DEBUG controller (BDC) in the HCS08
core. The BDC provides the means for analyzing MCU operation during software development.
ACTIVE BACKGROUND mode is entered in any of four ways:
• When the BKGD/PTA4 pin is low at the rising edge of a power up reset
• When a BACKGROUND command is received through the BKGD/PTA4 pin
• When a BGND instruction is executed by the CPU
• When encountering a BDC breakpoint
Once in ACTIVE BACKGROUND mode, the CPU is held in a suspended state waiting for serial BACKGROUND commands
rather than executing instructions from the user’s application program. Background commands are of two types:
• Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive
commands can be issued through the BKGD/PTA4 pin while the MCU is in RUN mode; non-intrusive commands can also
be executed when the MCU is in the ACTIVE BACKGROUND mode. Non-intrusive commands include:
— Memory access commands
— Memory-access-with-status commands
— BDC register access commands
— The BACKGROUND command
• ACTIVE BACKGROUND commands, which can only be executed while the MCU is in ACTIVE BACKGROUND mode.
ACTIVE BACKGROUND commands include commands to:
— Read or write CPU registers
— Trace one user program instruction at a time
— Leave ACTIVE BACKGROUND mode to return to the user’s application program (GO)
The ACTIVE BACKGROUND mode is used to program a bootloader or user application program into the FLASH program
memory before the MCU is operated in RUN mode for the first time. When the FXTH870xD is shipped from the Freescale factory,
the FLASH program memory is erased by default (unless specifically requested otherwise) so there is no program that could be
executed in RUN mode until the FLASH memory is initially programmed.
The ACTIVE BACKGROUND mode can also be used to erase and reprogram the FLASH memory after it has been previously
programmed.

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3.5 STOP Modes
One of two stop modes are entered upon execution of a STOP instruction when the STOPE bit in the system option register is
set. In all STOP modes, all internal clocks are halted except for the low frequency 1 kHz oscillator (LFO) which runs continuously
whenever power is applied to the VDD and VSS pins. If the STOPE bit is not set when the CPU executes a STOP instruction, the
MCU will not enter any of the STOP modes and an illegal opcode reset is forced. The STOP modes are selected by setting the
appropriate bits in SPMSC2. Table 1 summarizes the behavior of the MCU in each of the STOP1 and STOP4 modes. The STOP2
mode found in other Freescale S08 family members is not available; but the STOP3 mode is present like other members of the
Freescale S08 family members.

3.5.1 STOP1 Mode

The STOP1 mode provides the lowest possible standby power consumption by causing the internal circuitry of the MCU to be
powered down.
When the MCU is in STOP1 mode, all internal circuits that are powered from the voltage regulator are turned off. The voltage
regulator is in a low-power standby state. STOP1 is exited by asserting either a reset or an interrupt function to the MCU.
Entering STOP1 mode automatically asserts LVD. STOP1 cannot be exited until the VDD is greater than VLVDH or VLV/DL rising
(VDD must rise above the LVI re-arm voltage).
Upon wakeup from STOP1 mode, the MCU will start up as from a power-on reset (POR) by taking the reset vector.

NOTE
If there are any pending interrupts that have yet to be serviced then the device will not go
into the STOP1 mode. Be certain that all interrupt flags have been cleared before entry to
STOP1 mode.

3.5.2 STOP4 LVD Enabled in STOP Mode

The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If
the LVD is enabled by setting the LVDE and the LVDSE bits in SPMSC1 when the CPU executes a STOP instruction, then the
voltage regulator remains active during STOP mode. If the user attempts to enter the STOP1 with the LVD enabled in STOP
(LVDSE = 1), the MCU will enter STOP4 instead.

Table 1. STOP Mode Behavior

Mode STOP1 STOP4

LFO Oscillator, PWU Always On & Clocking
Real-Time Interrupt (RTI)(1) Always On if using LFO as Clock
MFO Oscillator(2) Optionally On Optionally On
HFO Oscillator Off Off
CPU Off Standby
RAM Off Standby
Parameter Registers On On
FLASH Off Standby
TPM1 2-Chan Timer/PWM Off Off
Digital I/O Disabled Standby
Sensor Measurement Interface (SMI) Off Optionally On
Pressure P-cell Off Optionally On
Optional Acceleration g-cell Off Optionally On
Temperature Sensor (in ADC10) Off Optionally On(3)
Normal Temperature Restart Optionally On Optionally On
Voltage Reference (in ADC10) Off Optionally On(3)
LFR Detector(4) Periodically On Periodically On
LFR Decoder Optionally On Optionally On
RF Controller, Data Buffer, Encoder Optionally On Optionally On
RF Transmitter(5) Optionally On Optionally On
ADC10 Off Optionally On(3)

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Table 1. STOP Mode Behavior (continued)

Mode STOP1 STOP4

Regulator Off On
I/O Pins Hi-Z States Held
Wakeup Methods Interrupts, resets Interrupts, resets
1. RTI can be used in STOP1 or STOP4 if the clock selected is the LFO. To use the HFO as the clock the MCU must be in the RUN mode.
2. MFO oscillator started if the LFR detectors are periodically sampled, the LFR detectors detect an input signal; a pressure or acceleration
reading is in progress or the RF state machine is sending data.
3. Requires internal ADC10 clock to be enabled.
4. Period of sampling set by MCU.
5. RF data buffer may be set up to run while the CPU is in the STOP modes.

Specific to the tire pressure monitoring application the parameter registers and the LFO with wakeup timer are powered up at all
times whenever voltage is applied to the supply pins. The LFR detector and MFO may be periodically powered up by the LFR
decoder.

3.5.3 Active BDM Enabled in STOP Mode

Entry into the ACTIVE BACKGROUND DEBUG mode from RUN mode is enabled if the ENBDM bit in BDCSCR is set. The
BDCSCR register is not memory mapped so it can only be accessed through the BDM interface by use of the BDM commands
READ_STATUS and WRITE_CONTROL. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the
BACKGROUND DEBUG logic remain active when the MCU enters STOP mode so BACKGROUND DEBUG communication is
still possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If
the user attempts to enter the STOP1 with ENDBM set, the MCU will instead enter this mode which is STOP4 with system clocks
running.
Most BACKGROUND commands are not available in STOP mode. The memory-access-with-status commands do not allow
memory access, but they report an error indicating that the MCU is in STOP mode. The BACKGROUND command can be used
to wake the MCU from stop and enter ACTIVE BACKGROUND mode if the ENDBM bit is set. Once in BACKGROUND DEBUG
mode, all BACKGROUND commands are available.

3.5.4 MCU On-Chip Peripheral Modules in STOP Modes

When the MCU enters any STOP mode, system clocks to the internal peripheral modules except the wakeup timer and LFR
detectors/decoder are stopped. Even in the exception case (ENDBM = 1), where clocks are kept alive to the BACKGROUND
debug logic, clocks to the peripheral systems are halted to reduce power consumption.
I/O Pins
If the MCU is configured to go into STOP1 mode, the I/O pins are forced to their default reset state (Hi-Z) upon entry into stop.
This means that the I/O input and output buffers are turned off and the pullup is disconnected.
Memory
All module interface registers will be reset upon wakeup from STOP1 and the contents of RAM are not preserved. The MCU must
be initialized as upon reset. The contents of the FLASH memory are non-volatile and are preserved in any of the STOP modes.
Parameter Registers
The 64 bytes of parameter registers are kept active in all modes of operation as long as power is applied to the supply pins. The
contents of the parameter registers behave like RAM and are unaffected by any reset.
LFO
The LFO remains active regardless of any mode of operation.
MFO
The medium frequency oscillator (MFO) will remain powered up when the MCU enters the STOP mode only when the SMI has
been initiated to make a pressure or acceleration measurement; or when the RF transmitter’s state machine is processing data.
HFO
The HFO is halted in all STOP modes.
PWU
The PWU remains active regardless of any mode of operation.

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ADC10
The internal asynchronous ADC10 clock is always used as the conversion clock. The ADC10 can continue operation during
STOP4 mode. Conversions can be initiated while the MCU is the STOP4 mode. All ADC10 module registers contain their reset
values following exit from STOP1 mode.
LFR
When the MCU enters STOP mode the detectors in the LFR will remain powered up depending on the states of the bits selecting
the periodic sampling. Refer to Section 12 for more details.
Bandgap Reference
The bandgap reference is enabled whenever the sensor measurement interface requires sensor or voltage measurements.
TPM1
When the MCU enters STOP mode, the clock to the TPM1 module stops and the module halts operation. If the MCU is configured
to go into STOP1 mode, the TPM1 module will be reset upon wakeup from STOP and must be re-initialized.
Voltage Regulator
The voltage regulator enters a low-power standby state when the MCU enters any of the STOP modes except STOP4 (LVDSE
= 1 or ENBDM =1).
Temperature Sensor
The temperature sensor is powered up on command from the MCU.
Temperature Restart
When the MCU enters a STOP mode the temperature restart will remain powered up if the TRE bit is set. If the temperature restart
level is reached the MCU will restart from the reset vector.

3.5.5 RFM Module in STOP Modes

The RFM’s external crystal oscillator (XCO), bit rate generator, PLL, VCO, RF data buffer, data encoder, and RF output stage will
remain powered up in STOP modes during a transmission, or if the SEND bit has been set and DIRECT mode has been enabled.
RF Output
When the RFM finishes a transmission sequence the external crystal oscillator (XCO), bit rate generator, PLL, VCO, RF data
buffer, data encoder, and RF output stage will remain powered up if the SEND bit is set.

3.5.6 P-cell in STOP Modes

The P-cell is powered up only during a measurement if scheduled by the sensor measurement interface. Otherwise it is powered
down.

3.5.7 Optional g-Cell in STOP Modes

The g-cell is powered up only during a measurement if scheduled by the sensor measurement interface. Otherwise it is powered
down.

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4 Memory
The overall memory map of the FXTH870xD resides on the MCU.

4.1 MCU Memory Map

As shown in Figure 8, MCU on-chip memory in the FXTH870xD consists of parameter registers, RAM, FLASH program memory
for nonvolatile data storage, and I/O and control/status registers. The registers are divided into four groups:
• Direct-page registers ($0000 through $004F)
• Parameter registers ($0050 through $008F)
• RAM ($0090 through $028F)
• High-page registers ($1800 through $182B)

$0000
DIRECT PAGE REGISTERS
$004F
$0050
PARAMETER REGISTERS $008F
$0090
RAM 512 BYTES
$028F
$0290
UNIMPLEMENTED
5488 BYTES
$17FF
$1800
HIGH PAGE REGISTERS
$182B
$182C
41964 BYTES $BFFF
$C000
USER FLASH
8128 BYTES
$DFBF
$DFC0
USER VECTORS
$DFFF
$E000
FIRMWARE JUMP TABLE
$E03F
$E040
FIRMWARE FLASH
8128 BYTES
$FFFF

Figure 8. FXTH870xD MCU Memory Map

The total programmable FLASH memory map is 16K, but the upper 8K is used for firmware and test software. Upon power up
the firmware will initialize the device and redirect all vectors to the user area from $DFC0 through $DFFF. Any calls to the firmware
subroutines are accessed through a jump table starting at location $E000 (see Section 14).

4.2 Reset and Interrupt Vectors

Table 2 shows address assignments for jump table to the reset and interrupt vectors. The vector names shown in this table are
the labels used in the equate file provided by Freescale in the CodeWarrior project file.

Table 2. Vector Summary

User Vector Addr Vector Name Module Source

$DFE0:DFE1 Vkbi KBI
$DFE2:DFE3 Reserved
$DFE4:DFE5 Reserved
$DFE6:DFE7 Vrti Sys Ctrl - RTI
$DFE8:DFE9 Vlfrcvr LFR
$DFEA:DFEB Vadc1 ADC10
$DFEC:DFED Vrf RFM

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Table 2. Vector Summary (continued)

User Vector Addr Vector Name Module Source

$DFEE:DFEF Vsm SMI
$DFF0:DFF1 Vtpm1ovf TPM1
$DFF2:DFF3 Vtpm1ch1 TPM1
$DFF4:DFF5 Vtpm1ch0 TPM1
$DFF6:DFF7 Vwuktmr PWU
$DFF8:DFF9 Vlvd Sys Ctrl - LVD
$DFFA:DFFB Reserved
$DFFC:DFFD Vswi SWI opcode
Sys Ctrl - POR, PRF, COP, LVD
$DFFE:DFFF Vreset
Temp Restart, Illegal opcode or address

4.3 MCU Register Addresses and Bit Assignments

The registers in the FXTH870xD are divided into these four groups:
• Direct-page registers are located in the first 80 locations in the memory map; these are accessible with efficient direct
addressing mode instructions.
• The parameter registers begin at address $0050; these are also accessible with efficient direct addressing mode
instructions.
• High-page registers are used less often, so they are located above $1800 in the memory map. This leaves more room in the
direct page for more frequently used registers and variables.
• The nonvolatile register area consists of a block of 16 locations in FLASH memory at $FFB0:FFBF. Nonvolatile register
locations include:
— Three values that are loaded into working registers at reset
— An 8-byte back door comparison key that optionally allows the user to gain controlled access to secure memory.
Because the nonvolatile register locations are FLASH memory, they must be erased and programmed like other FLASH memory
locations.
Direct page registers are located within the first 256 locations in the memory map, so they are accessible with efficient direct
addressing mode instructions, which requires only the lower byte of the address. Bit manipulation instructions can be used to
access any bit in any direct-page register. Table 3 is a summary of all user-accessible direct-page registers and control bits.
Those related to the TPMS application and modules are described in detail in this specification.
The register names in column two of the following tables are shown in bold to set them apart from the bit names to the right. Cells
that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded
cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s.

Table 3. MCU Direct Page Register Summary

Address Register Name Bit 7 6 5 4 3 2 1 Bit 0

$0000 PTAD PTAD[4:0]
$0001 PTAPE PTAPE[3:0]
$0002 Reserved
$0003 PTADD PTADD[3:0]
$0004 PTBD PTBD[1:0]
$0005 PTBPE PTBPE[1:0]
$0006 Reserved
$0007 PTBDD PTBDD[1:0]
$0008 Reserved
$0009 Reserved
$000A Reserved
$000B Reserved
$000C KBISC 0 0 0 0 KBF KBACK KBIE KBIMOD

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Table 3. MCU Direct Page Register Summary (continued)

Address Register Name Bit 7 6 5 4 3 2 1 Bit 0

$000D KBIPE KBIPE[3:0]
$000E KBIES KBEDG[3:0]
$000F Reserved
$0010 TPM1SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
$0011 TPM1CNTH Bit [15:8]
$0012 TPM1CNTL Bit [7:0]
$0013 TPM1MODH Bit [15:8]
$0014 TPM1MODL Bit [7:0]
$0015 TPM1C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0
$0016 TPM1C0VH Bit [15:8]
$0017 TPM1C0VL Bit [7:0]
$0018 TPM1C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0
$0019 TPM1C1VH Bit [15:8]
$001A TPM1C1VL Bit [7:0]
$001B Reserved
$001C PWUDIV WDIV[5:0]
$001D PWUCS0 WUF WUFAK WUT[5:0]
$001E PWUCS1 PRF PRFAK PRST[5:0]
$001F PWUS PSEL 0 CSTAT[5:0]
$0020-27 LFR Registers LFR Registers, see Table 4 and Table 5
$0028 ADSC1 COCO AIEN ADCO ADCH[4:0]
$0029 ADSC2 ADACT ADTRG ACFE ADCFGT 0 0 0 0
$002A ADRH 0 0 0 0 ADR[11:8]
$002B ADRL ADR[7:0]
$002C ADCVH 0 0 0 0 ADCV[11:8]
$002D ADCVL ADCV[7:0]
$002E ADCFG ADLPC ADIV[1:0] ADLSMP MODE[1:0] ADICLK[1:0]
$002F ADPCTL1 ADPC[7:0]
$0030-4F RFM Registers RFM Registers, see Table 6 and Table 7
$0050-8F Parameter Reg PARAM[63:0]
Note: Shaded bits are recommended to only be controlled by firmware or factory test.

Table 4. LFR Register Summary - LPAGE = 0

Address Register Name Bit 7 6 5 4 3 2 1 Bit 0

$0020 LFCTL1 LFEN SRES CARMOD LPAGE IDSEL[1:0] SENS[1:0]
$0021 LFCTL2 LFSTM[3:0] LFONTM[3:0]
$0022 LFCTL3 LFDO TOGMOD SYNC[1:0] LFCDTM[3:0]
$0023 LFCTL4 LFDRIE LFERIE LFCDIE LFIDIE DECEN VALEN TIMOUT[1:0]
$0024 LFS LFDRF LFERF LFCDF LFIDF LFOVF LFEOMF LPSM LFIAK
$0025 LFDATA RXDATA[7:0]
$0026 LFIDL ID[7:0]
$0027 LFIDH ID[15:8]

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Table 5. LFR Register Summary - LPAGE = 1

Address Register Name Bit 7 6 5 4 3 2 1 Bit 0

$0020 LFCTL1 LFEN SRES CARMOD LPAGE IDSEL[1:0] SENS[1:0]
$0021 LFCTRLE TRIMEE AZSC[2:0]
$0022 LFCTRLD AVFOF[1:0} DEQS AZDC[1:0] ONMODE CHK125[1:0]
$0023 LFCTRLC AMPGAIN[1:0] FINSEL[1:0] AZEN LOWQ[1:0] DEQEN
$0024 LFCTRLB HYST[1:0] LFFAF LFCAF LFPOL LFCPTAZ[2:0]
$0025 LFCTRLA TESTSEL[3:0] LFCC[3:0]
$0026 Reserved
$0027 Reserved
Note: Shaded bits are recommended to only be controlled by firmware or factory test.

Table 6. RFM Register Summary - RPAGE = 0

Address Register Name Bit 7 6 5 4 3 2 1 Bit 0

$0030 RFCR0 BPS[7:0]
$0031 RFCR1 FRM[7:0]
$0032 RFCR2 SEND RPAGE EOM PWR[4:0]
$0033 RFCR3 DATA IFPD ISPC IFID FNUM[3:0]
$0034 RFCR4 RFBT[7:0]
$0035 RFCR5 BOOST LFSR[6:0]
$0036 RFCR6 VCO_GAIN[1:0] RFFT[5:0]
$0037 RFCR7 RFIF RFEF RFVF RFIAK RFIEN RFLVDEN RCTS RFMRST
$0038 PLLCR0 AFREQ[12:5]
$0039 PLLCR1 AFREQ[4:0] POL CODE[1:0]
$003A PLLCR2 BFREQ[12:5]
$003B PLLCR3 BFREQ[4:0] CF MOD CKREF
$003C RFD0 RFD[7:0]
$003D RFD1 RFD[15:8]
$003E RFD2 RFD[23:16]
$003F RFD3 RFD[31:24]
$0040 RFD4 RFD[39:32]
$0041 RFD5 RFD[47:40]
$0042 RFD6 RFD[55:48]
$0043 RFD7 RFD[63:56]
$0044 RFD8 RFD[71:64]]
$0045 RFD9 RFD[79:72]
$0046 RFD10 RFD[87:80]
$0047 RFD11 RFD[95:88]
$0048 RFD12 RFD[103:96]
$0049 RFD13 RFD[111:104]
$004A RFD14 RFD[119:112]
$004B RFD15 RFD[127:120]
$004C Reserved
$004D Reserved
$004E Reserved
$004F Reserved
Note: Shaded bits are recommended to only be controlled by firmware or factory test.

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Table 7. RFM Register Summary - RPAGE = 1

Address Register Name Bit 7 6 5 4 3 2 1 Bit 0

$0030 RFCR0 BPS[7:0]
$0031 RFCR1 FRM[7:0]
$0032 RFCR2 SEND RPAGE EOM PWR[4:0]
$0033 RFCR3 DATA IFPD ISPC IFID FNUM[3:0]
$0034 RFCR4 RFBT[7:0]
$0035 RFCR5 BOOST LFSR[6:0]
$0036 RFCR6 VCO_GAIN[1:0] RFFT[5:0]
$0037 RFCR7 RFIF RFEF RFVF RFIAK RFIEN RFLVDEN RCTS RFMRST
$0038 EPR —/VCD3 PLL_LPF_[2:0]/VCD[2:0] PA_SLOPE VCD_EN
$0039 Reserved
$003A Reserved
$003B Reserved
$003C RFD0 RFD[135:128]
$003D RFD1 RFD[143:136]
$003E RFD2 RFD[151:144]
$003F RFD3 RFD[159:152]
$0040 RFD4 RFD[167:160]
$0041 RFD5 RFD[175:168]
$0042 RFD6 RFD[183:176]
$0043 RFD7 RFD[191:184]
$0044 RFD8 RFD[199:192]
$0045 RFD9 RFD[207:200]
$0046 RFD10 RFD[215:208]
$0047 RFD11 RFD[223:216]
$0048 RFD12 RFD[231:224]
$0049 RFD13 RFD[239:232]
$004A RFD14 RFD[247:240]
$004B RFD15 RFD[255:248]
$004C Reserved
$004D Reserved
$004E Reserved
$004F Reserved
Note: Shaded bits are recommended to only be controlled by firmware or factory test.

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4.4 High Address Registers
High-page registers are used much less often, so they are located above $1800 in the memory map. This leaves more room in
the direct page for more frequently used registers and variables. The registers control system level features as given in Table 8.

Table 8. MCU High Address Register Summary

Address Register Name Bit 7 6 5 4 3 2 1 Bit 0

$1800 SRS POR PIN COP ILOP ILAD PWU LVD 0
$1801 SBDFR 0 0 0 0 0 0 0 BDFR
$1802 SIMOPT1 COPE COPCLKS STOPE RFEN TRE TRH BKGDPE 1
$1803 SIMOPT2 0 COPT[2:0] LFOSEL TCLKDIV BUSCLKS[1:0]
$1804 Reserved
$1805 Reserved
$1806 SDIDH REV[3:0] ID[11:8]
$1807 SDIDL ID[7:0]
$1808 SRTISC RTIF RTIACK RTICLKS RTIE 0 RTIS{2:0]
$1809 SPMSC1 LVDF LVDACK LVDIE LVDRE LVDSE LVDE 0 BGBE
$180A SPMSC2 0 0 0 PDF 0 PPDACK PDC 0
$180B Reserved
$180C SPMSC3 LVWF LVWACK LVDV LVWV 0 0 0 0
$180D SIMSES KBF IRQF TRF PWUF LFF RFF
$180E SOTRM SOTRM[7:0]
$180F SIMTST TRH[2:0] TRO
$1810-1F Reserved
$1820 FCDIV DIVLD PRDIV8 DIV[5:0]
$1821 FOPT KEYEN FNORED 0 0 0 0 SEC0[1:0}
$1822 Reserved
$1823 FCNFG 0 0 KEYACC 0 0 0 0 0
$1824 FPROT FPS[7:1] FPDIS
$1825 FSTAT FCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0
$1826 FCMD FERASE FCMD[6:0]
$1827-3F Reserved
Note: Reserved bits shown as 0 must always be written to 0.
Reserved bits shown as 1 must always be written to 1.
Shaded bits are recommended to only be controlled by firmware or factory test.

4.5 MCU Parameter Registers

The 64 bytes of parameter registers are located at addresses $0050 through $008F. These registers are powered up at all times
and may be used to store temporary or history data during the times that the MCU is in any of the STOP modes. The parameter
register at $008F is used by the firmware for interrupt flags.

4.6 MCU RAM

The FXTH870xD includes static RAM. The locations in RAM below $0100 can be accessed using the more efficient direct
addressing mode, and any single bit in this area can be accessed with the bit-manipulation instructions (BCLR, BSET, BRCLR,
and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred.
The RAM retains data when the MCU is in low-power WAIT, STOP3 or STOP4 modes. At power-on or after wakeup from STOP1,
the contents of RAM are not initialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below
the minimum value for RAM retention (VRAM).
When security is enabled, the RAM is considered a secure memory resource and is not accessible through BDM or through code
executing from non-secure memory. See Section 4.8 for a detailed description of the security feature.

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None of the RAM locations are used directly by the firmware provided by Freescale. The firmware routines utilize RAM only
through stack operations; and the user needs to be aware of stack depth required by each routine as described in the
CodeWarrior project files supplied by Freescale.

4.7 FLASH
The FLASH memory is intended primarily for program storage. The operating program can be loaded into the FLASH memory
after final assembly of the application product using the single-wire BACKGROUND DEBUG interface. Because no special
voltages are needed for FLASH erase and programming operations, in-application programming is also possible through other
software-controlled communication paths. For a more detailed discussion of in-circuit and in-application programming, refer to
the HCS08 Family Reference Manual, Volume I, Freescale document order number HCS08RMV1/D.

4.7.1 Features
Features of the FLASH memory include:
• User Program FLASH Size — 8192 bytes (16 pages of 512 bytes each)
• Single power supply program and erase
• Command interface for fast program and erase operation
• Up to 100,000 program/erase cycles at typical voltage and temperature
• Flexible block protection
• Security feature for FLASH and RAM
• Auto power-down for low-frequency read accesses

4.7.2 Program and Erase Times

Before any program or erase command can be accepted, the FLASH clock divider register (FCDIV) must be written to set the
internal clock for the FLASH module to a frequency (fFCLK) between 150 kHz and 200 kHz. This register can be written only once,
so normally this write is performed during reset initialization. FCDIV cannot be written if the access error flag, FACCERR in
FSTAT, is set. The user must ensure that FACCERR is not set before writing to the FCDIV register. One period of the resulting
clock (1/fFCLK) is used by the command processor to time program and erase pulses. An integer number of these timing pulses
are used by the command processor to complete a program or erase command.
Table 9 shows program and erase times. The bus clock frequency and FCDIV determine the frequency of FCLK (fFCLK). The time
for one cycle of FCLK is tFCLK = 1/fFCLK. The times are shown as a number of cycles of FCLK and as an absolute time for the
case where tFCLK = 5 s. Program and erase times shown include overhead for the command state machine and enabling and
disabling of program and erase voltages.

Table 9. Program and Erase Times

Parameter Cycles of FCLK Time if FCLK = 200 kHz

Byte program 9 45 s
Byte program (burst) 4 20 s(1)
Page erase 4000 20 ms
Mass erase 20,000 100 ms
1. Excluding start/end overhead

4.7.3 Program and Erase Command Execution

The steps for executing any of the commands are listed below. The FCDIV register must be initialized and any error flags cleared
before beginning command execution. The command execution steps are:
1. Write a data value to an address in the FLASH array. The address and data information from this write is latched into
the FLASH interface. This write is a required first step in any command sequence. For erase and blank check
commands, the value of the data is not important. For page erase commands, the address may be any address in the
512-byte page of FLASH to be erased. For mass erase and blank check commands, the address can be any address
in the FLASH memory. Whole pages of 512 bytes are the smallest block of FLASH that may be erased.
Do not program any byte in the FLASH more than once after a successful erase operation. Reprogramming bits to a
byte which is already programmed is not allowed without first erasing the page in which the byte resides or mass
erasing the entire FLASH memory. Programming without first erasing may disturb data stored in the FLASH.

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 2. Write the command code for the desired command to FCMD. The five valid commands are blank check (0x05), byte
program (0x20), burst program (0x25), page erase (0x40), and mass erase (0x41). The command code is latched into
the command buffer.
3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its address and data
information).
A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the write to the memory array and
before writing the 1 that clears FCBEF and launches the complete command. Aborting a command in this way sets the FACCERR
access error flag which must be cleared before starting a new command.
A strictly monitored procedure must be obeyed or the command will not be accepted. This minimizes the possibility of any
unintended changes to the FLASH memory contents. The command complete flag (FCCF) indicates when a command is
complete. The command sequence must be completed by clearing FCBEF to launch the command. Figure 9 is a flowchart for
executing all of the commands except for burst programming. The FCDIV register must be initialized before using any FLASH
commands. This must be done only once following a reset.

4.7.4 Burst Program Execution

The burst program command is used to program sequential bytes of data in less time than would be required using the standard
program command. This is possible because the high voltage to the FLASH array does not need to be disabled between program
operations. Ordinarily, when a program or erase command is issued, an internal charge pump associated with the FLASH
memory must be enabled to supply high voltage to the array. Upon completion of the command, the charge pump is turned off.
When a burst program command is issued, the charge pump is enabled and then remains enabled after completion of the burst
program operation if these two conditions are met:
• The next burst program command has been queued before the current program operation has completed.
• The next sequential address selects a byte on the same physical row as the current byte being programmed. A row of FLASH
memory consists of 64 bytes. A byte within a row is selected by addresses A5 through A0. A new row begins when addresses
A5 through A0 are all zero.
The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as
a byte programmed in standard mode. Subsequent bytes will program in the burst program time provided that the conditions
above are met. In the case the next sequential address is the beginning of a new row, the program time for that byte will be the
standard time instead of the burst time. This is because the high voltage to the array must be disabled and then enabled again.
If a new burst command has not been queued before the current command completes, then the charge pump will be disabled
and high voltage removed from the array.

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 WRITE TO FCDIV (1) Note 1: Required only once after reset.

FLASH PROGRAM AND

ERASE FLOW START

0
FACCERR?
1

CLEAR ERROR

WRITE TO FLASH
TO BUFFER ADDRESS AND DATA

WRITE COMMAND TO FCMD

WRITE 1 TO FCBEF Note 2: Wait at least four bus cycles

TO LAUNCH COMMAND before checking FCBEF or FCCF.
AND CLEAR FCBEF (2)

FPVIOL OR YES
FACCERR? ERROR EXIT

NO

0
FCCF?
1

DONE

Figure 9. FLASH Program and Erase Flowchart

Programming time for the FLASH through the BDM function is dependent on the specific external BDM interface tool and
software being used. Consult tool vendor for programming times.

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 WRITE TO FCDIV (1) Note 1: Required only once after reset.

FLASH BURST START

PROGRAM FLOW

0
FACCERR?
1

CLEAR ERROR

0
FCBEF?
1

WRITE TO FLASH
TO BUFFER ADDRESS AND DATA

WRITE COMMAND ($25) TO FCMD

WRITE 1 TO FCBEF Note 2: Wait at least four bus cycles before

TO LAUNCH COMMAND checking FCBEF or FCCF.
AND CLEAR FCBEF (2)

FPVIO OR YES
FACCERR? ERROR EXIT
NO
YES
NEW BURST COMMAND?
NO

0 FCCF?
1

DONE

Figure 10. FLASH Burst Program Flowchart

4.7.5 Access Errors

An access error occurs whenever the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERR must be cleared
by writing a 1 to FACCERR in FSTAT before any command can be processed.
• Writing to a FLASH address before the internal FLASH clock frequency has been set by writing to the FCDIV register
• Writing to a FLASH address while FCBEF is not set (A new command cannot be started until the command buffer is empty.)
• Writing a second time to a FLASH address before launching the previous command (There is only one write to FLASH for
every command.)
• Writing a second time to FCMD before launching the previous command (There is only one write to FCMD for every
command.)
• Writing to any FLASH control register other than FCMD after writing to a FLASH address
• Writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41) to FCMD
• Accessing (read or write) any FLASH control register other than the write to FSTAT (to clear FCBEF and launch the
command) after writing the command to FCMD.
• The MCU enters STOP mode while a program or erase command is in progress (The command is aborted.)

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• Writing the byte program, burst program, or page erase command code (0x20, 0x25, or 0x40) with a BACKGROUND
DEBUG command while the MCU is secured (the BACKGROUND DEBUG controller can only do blank check and mass
erase commands when the MCU is secure.)
• Writing 0 to FCBEF to cancel a partial command.

4.7.6 FLASH Block Protection

The block protection feature prevents the protected region of FLASH from program or erase changes. Block protection is
controlled through the FLASH Protection Register (FPROT). When enabled, block protection begins at any 512-byte boundary
below the last address of FLASH, 0xFFFF. (see Section 4.9.4).
After exit from reset, FPROT is loaded with the contents of the NVPROT location which is in the nonvolatile register block of the
FLASH memory. FPROT cannot be changed directly from application software so a runaway program cannot alter the block
protection settings. Because NVPROT is within the last 512 bytes of FLASH, if any amount of memory is protected, NVPROT is
itself protected and cannot be altered (intentionally or unintentionally) by the application software. FPROT can be written through
BACKGROUND DEBUG commands which allows a way to erase and reprogram a protected FLASH memory.
The block protection mechanism is illustrated below. The FPS bits are used as the upper bits of the last address of unprotected
memory. This address is formed by concatenating FPS7:FPS1 with logic 1 bits as shown. For example, in order to protect the
last 8192 bytes of memory (addresses 0xE000 through 0xFFFF), the FPS bits must be set to 1101 111 which results in the value
0xDFFF as the last address of unprotected memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit
0 of NVPROT) must be programmed to logic 0 to enable block protection. Therefore the value 0xDE must be programmed into
NVPROT to protect addresses 0xE000 through 0xFFFF.

FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 1 1 1 1 1 1 1 1 1

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Figure 11. Block Protection Mechanism

One use for block protection is to block protect an area of FLASH memory for a bootloader program. This bootloader program
then can be used to erase the rest of the FLASH memory and reprogram it. Because the bootloader is protected, it remains intact
even if MCU power is lost in the middle of an erase and reprogram operation.

4.7.7 Vector Redirection

NOTE
Not recommended for TPMS applications where Freescale firmware has been included in
the final image.
Whenever any block protection is enabled, the reset and interrupt vectors will be protected. Vector redirection allows users to
modify interrupt vector information without unprotecting bootloader and reset vector space. Vector redirection is enabled by
programming the FNORED bit in the NVOPT register located at address 0xFFBF to zero. For redirection to occur, at least some
portion but not all of the FLASH memory must be block protected by programming the NVPROT register located at address
0xFFBD. All of the interrupt vectors (memory locations 0xFFC0–0xFFFD) are redirected, though the reset vector (0xFFFE:FFFF)
is not.
For example, if 512 bytes of FLASH are protected, the protected address region is from 0xFE00 through 0xFFFF. The interrupt
vectors (0xFFC0–0xFFFD) are redirected to the locations 0xFDC0–0xFDFD. Now, if an SPI interrupt is taken for instance, the
values in the locations 0xFDE0:FDE1 are used for the vector instead of the values in the locations 0xFFE0:FFE1. This allows
the user to reprogram the unprotected portion of the FLASH with new program code including new interrupt vector values while
leaving the protected area, which includes the default vector locations, unchanged.

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4.8 Security
The FXTH870xD includes circuitry to prevent unauthorized access to the contents of FLASH and RAM memory. When security
is engaged, FLASH and RAM are considered secure resources. Direct-page registers, high-page registers, and the
BACKGROUND DEBUG controller are considered unsecured resources. Programs executing within secure memory have
normal access to any MCU memory locations and resources. Attempts to access a secure memory location with a program
executing from an unsecured memory space or through the BACKGROUND DEBUG interface are blocked (writes are ignored
and reads return all 0s).
Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC0[1:0]) in the FOPT register. During
reset, the contents of the nonvolatile location NVOPT are copied from FLASH into the working FOPT register in high-page
register space. A user engages security by programming the NVOPT location, which can be done at the same time the FLASH
memory is programmed. The 1:0 state disengages security and the other three combinations engage security. Notice the erased
state (1:1) makes the MCU secure. During development, whenever the FLASH is erased, it is good practice to immediately
program the SEC00 bit to 0 in NVOPT so SEC[1:0] = 1:0. This would allow the MCU to remain unsecured after a subsequent
reset.
The on-chip debug module cannot be enabled while the MCU is secure. The separate BACKGROUND DEBUG controller can
still be used for background memory access commands, but the MCU cannot enter ACTIVE BACKGROUND mode except by
holding BKGD/MS low at the rising edge of reset.
A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security key. If the nonvolatile
KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there is no way to disengage security without completely
erasing all FLASH locations. If KEYEN is 1, a secure user program can temporarily disengage security by:
1. Writing 1 to KEYACC in the FCNFG register. This makes the FLASH module interpret writes to the backdoor
comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be compared against the key rather
than as the first step in a FLASH program or erase command.
2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations. These writes must be
done in order starting with the value for NVBACKKEY and ending with NVBACKKEY+7. STHX must not be used for
these writes because these writes cannot be done on adjacent bus cycles. User software normally would get the key
codes from outside the MCU system through a communication interface such as a serial I/O.
3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was just written matches the key stored in the
FLASH locations, SEC[1:0] are automatically changed to 1:0 and security will be disengaged until the next reset.
The security key can be written only from secure memory (either RAM or FLASH), so it cannot be entered through
BACKGROUND commands without the cooperation of a secure user program.
The backdoor comparison key (NVBACKKEY through NVBACKKEY+7) is located in FLASH memory locations in the nonvolatile
register space so users can program these locations exactly as they would program any other FLASH memory location. The
nonvolatile registers are in the same 512-byte block of FLASH as the reset and interrupt vectors, so block protecting that space
also block protects the backdoor comparison key. Block protects cannot be changed from user application programs, so if the
vector space is block protected, the backdoor security key mechanism cannot permanently change the block protect, security
settings, or the backdoor key.
Security can always be disengaged through the BACKGROUND DEBUG interface by taking these steps:
1. Disable any block protections by writing FPROT. FPROT can be written only with BACKGROUND DEBUG commands,
not from application software.
2. Mass erase FLASH if necessary.
3. Blank check FLASH. Provided FLASH is completely erased, security is disengaged until the next reset.
To avoid returning to secure mode after the next reset, program NVOPT so SEC[1:0] = 1:0.

NOTE
Enabling the security feature disables Freescale ability to perform failure analysis without
first completely erasing all flash memory contents. If the security feature is implemented,
customer shall be responsible for providing to Freescale unsecured parts for any failure
analysis to begin or supplying the entire contents of the device flash memory data as part of
the return process, to allow Freescale to erase and subsequently restore the device to its
original condition.

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4.9 FLASH Registers and Control Bits
The FLASH module has nine 8-bit registers in the high-page register space, three locations in the nonvolatile register space in
FLASH memory which are copied into three corresponding high-page control registers at reset. There is also an 8-byte
comparison key in FLASH memory. Refer to Table 8 and Table 9 for the absolute address assignments for all FLASH registers.
This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file
normally is used to translate these names into the appropriate absolute addresses.

4.9.1 FLASH Clock Divider Register (FCDIV)

Bit 7 of this register is a read-only status flag. Bits 6 through 0 can be read at any time but can be written only once. Before any
erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory
system within acceptable limits.

$1820 7 6 5 4 3 2 1 0
R DIVLD
PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0
W
Reset: 0 0 0 0 0 0 0 0
= Reserved

Figure 12. FLASH Clock Divider Register (FCDIV)

Table 10. FCDIV Register Field Descriptions

Field Description
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been written since
7 reset. Reset clears this bit and the first write to this register causes this bit to become set regardless of the data written.
DIVLD 0 FCDIV has not been written since reset; erase and program operations disabled for FLASH
1 FCDIV has been written since reset; erase and program operations enabled for FLASH
Prescale (Divide) FLASH Clock by 8
6
0 Clock input to the FLASH clock divider is the bus rate clock
PRDIV8
1 Clock input to the FLASH clock divider is the bus rate clock divided by 8
Divisor for FLASH Clock Divider — The FLASH clock divider divides the bus rate clock (or the bus rate clock divided by 8 if
PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the internal FLASH clock must fall
within the range of 200 kHz to 150 kHz for proper FLASH operations. Program/Erase timing pulses are one cycle of this internal
5:0 FLASH clock which corresponds to a range of 5 s to 6.7 s. The automated programming logic uses an integer number of
these pulses to complete an erase or program operation.
DIV[5:0]
• if PRDIV8 = 0 — fFCLK = fBus  ([DIV5:DIV0] + 1)
• if PRDIV8 = 1 — fFCLK = fBus  (8  ([DIV5:DIV0] + 1))
Table 11 shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies.

Table 11. FLASH Clock Divider Settings

PRDIV8 DIV5:DIV0 Program/Erase Timing Pulse

fBus fFCLK
(Binary) (Decimal) (5 s Min, 6.7s Max)
20 MHz 1 12 192.3 kHz 5.2 s
10 MHz 0 49 200 kHz 5 s
8 MHz 0 39 200 kHz 5 s
4 MHz 0 19 200 kHz 5 s
2 MHz 0 9 200 kHz 5 s
1 MHz 0 4 200 kHz 5 s
200 kHz 0 0 200 kHz 5 s
150 kHz 0 0 150 kHz 6.7 s

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4.9.2 FLASH Options Register (FOPT and NVOPT)
During reset, the contents of the nonvolatile location NVOPT are copied from FLASH into FOPT. Bits 5 through 2 are not used
and always read 0. This register may be read at any time, but writes have no meaning or effect. To change the value in this
register, erase and reprogram the NVOPT location in FLASH memory as usual and then issue a new MCU reset.

$1821 7 6 5 4 3 2 1 0
R KEYEN FNORED 0 0 0 0 SEC01 SEC00
W
Reset: This register is loaded from nonvolatile location NVOPT during reset.
= Reserved

Figure 13. FLASH Options Register (FOPT)

Table 12. FOPT Register Field Descriptions

Field Description
Backdoor Key Mechanism Enable — When this bit is 0, the backdoor key mechanism cannot be used to disengage security.
The backdoor key mechanism is accessible only from user (secured) firmware. BDM commands cannot be used to write key
comparison values that would unlock the backdoor key. For more detailed information about the backdoor key mechanism, refer
7
to Section 4.8.”
KEYEN
0 No backdoor key access allowed
1 If user firmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through NVBACKKEY+7
in that order), security is temporarily disengaged until the next MCU reset
Vector Redirection Disable — When this bit is 1, then vector redirection is disabled.
6
0 Vector redirection enabled
FNORED
1 Vector redirection disabled
Security State Code — This 2-bit field determines the security state of the MCU as shown in Table 13. When the MCU is
1:0 secure, the contents of RAM and FLASH memory cannot be accessed by instructions from any unsecured source including the
SEC0[1:0] BACKGROUND DEBUG interface. For more detailed information about security, refer to Section 4.8. SEC01:SEC00 changes
to 1:0 after successful backdoor key entry or a successful blank check of FLASH.

Table 13. Security States

SEC01:SEC00 Description
0:0 secure
0:1 secure
1:0 unsecured
1:1 secure

4.9.3 FLASH Configuration Register (FCNFG)

Bits 7 through 5 can be read or written at any time. Bits 4 through 0 always read 0 and cannot be written.

$1823 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
KEYACC
W
Reset: 0 0 0 0 0 0 0 0
= Reserved

Figure 14. FLASH Configuration Register (FCNFG)

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Table 14. FCNFG Register Field Descriptions

Field Description
Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed information about
5 the backdoor key mechanism, refer to Section 4.8.
KEYACC 0 Writes to 0xFFB0–0xFFB7 are interpreted as the start of a FLASH programming or erase command
1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes

4.9.4 FLASH Protection Register (FPROT and NVPROT)

During reset, the contents of the nonvolatile location NVPROT is copied from FLASH into FPROT. Bits 0, 1, and 2 are not used
and each always reads as 0. This register can be read at any time, but user program writes have no meaning or effect.
BACKGROUND DEBUG commands can write to FPROT.

$1824 7 6 5 4 3 2 1 0
R FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS
(1) (1) (1) (1) (1) (1) (1) (1)
W
Reset: This register is loaded from nonvolatile location NVPROT during reset.
1. Background commands can be used to change the contents of these bits in FPROT.

Figure 15. FLASH Protection Register (FPROT)

Table 15. FPROT Register Field Descriptions

Field Description
7:1 FLASH Protect Select Bits — When FPDIS = 0, this 7-bit field determines the ending address of unprotected FLASH locations
FPS[7:1] at the high address end of the FLASH. Protected FLASH locations cannot be erased or programmed.
FLASH Protection Disable
0
0 FLASH block specified by FPS[7:1] is block protected (program and erase not allowed)
FPDIS
1 No FLASH block is protected

4.9.5 FLASH Status Register (FSTAT)

Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining five bits are status bits that can be read at
any time. Writes to these bits have special meanings that are discussed in the bit descriptions.

$1825 7 6 5 4 3 2 1 0
R FCCF 0 FBLANK 0 0
FCBEF FPVIOL FACCERR
W
Reset: 1 1 0 0 0 0 0 0
= Reserved

Figure 16. FLASH Status Register (FSTAT)

Table 16. FSTAT Register Field Descriptions

Field Description
FLASH Command Buffer Empty Flag — The FCBEF bit is used to launch commands. It also indicates that the command
buffer is empty so that a new command sequence can be executed when performing burst programming. The FCBEF bit is
7 cleared by writing a one to it or when a burst program command is transferred to the array for programming. Only burst program
FCBEF commands can be buffered.
0 Command buffer is full (not ready for additional commands)
1 A new burst program command can be written to the command buffer

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Table 16. FSTAT Register Field Descriptions (continued)

Field Description
FLASH Command Complete Flag — FCCF is set automatically when the command buffer is empty and no command is being
processed. FCCF is cleared automatically when a new command is started (by writing 1 to FCBEF to register a command).
6
Writing to FCCF has no meaning or effect.
FCCF
0 Command in progress
1 All commands complete
Protection Violation Flag — FPVIOL is set automatically when FCBEF is cleared to register a command that attempts to erase
5 or program a location in a protected block (the erroneous command is ignored). FPVIOL is cleared by writing a 1 to FPVIOL.
FPVIOL 0 No protection violation
1 An attempt was made to erase or program a protected location
Access Error Flag — FACCERR is set automatically when the proper command sequence is not obeyed exactly (the
erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register has been initialized,
or if the MCU enters STOP while a command was in progress. For a more detailed discussion of the exact actions that are
4
considered access errors, see Section 4.7.5. FACCERR is cleared by writing a 1 to FACCERR. Writing a 0 to FACCERR has
FACCERR no meaning or effect.
0 No access error
1 An access error has occurred
FLASH Verified as All Blank (erased) Flag — FBLANK is set automatically at the conclusion of a blank check command if
the entire FLASH array was verified to be erased. FBLANK is cleared by clearing FCBEF to write a new valid command. Writing
2 to FBLANK has no meaning or effect.
FBLANK 0 After a blank check command is completed and FCCF = 1, FBLANK = 0 indicates the FLASH array is not completely erased
1 After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the FLASH array is completely erased
(all 0xFF)

4.9.6 FLASH Command Register (FCMD)

Only five command codes are recognized in normal user modes as shown in Table 17. Refer to Section 4.7.3, for a detailed
discussion of FLASH programming and erase operations.

$1826 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
W FCMD7 FCMD6 FCMD5 FCMD4 FCMD3 FCMD2 FCMD1 FCMD0
Reset: 0 0 0 0 0 0 0 0

Figure 17. FLASH Command Register (FCMD)

Table 17. FLASH Commands

Command FCMD Equate File Label

Blank check 0x05 mBlank
Byte program 0x20 mByteProg
Byte program — burst mode 0x25 mBurstProg
Page erase (512 bytes/page) 0x40 mPageErase
Mass erase (all FLASH) 0x41 mMassErase

All other command codes are illegal and generate an access error.
It is not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the
security unlocking mechanism.

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5 Reset, Interrupts and System Configuration
This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the FXTH870xD.
Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this product specification.
This section gathers basic information about all reset and interrupt sources in one place for easy reference. A few reset and
interrupt sources, including the computer operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip
peripheral systems, but are part of the system control logic.

5.1 Features
Reset and interrupt features include:
• Multiple sources of reset for flexible system configuration and reliable operation
• Reset status register (SRS) to indicate source of most recent reset
• Separate interrupt vectors for each module (reduces polling overhead)

5.2 MCU Reset

Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset, most control and status
registers are forced to initial values and the program counter is loaded from the reset vector ($DFFE:$DFFF). On-chip peripheral
modules are disabled and any I/O pins are initially configured as general-purpose high-impedance inputs with any pullup devices
disabled. The I bit in the condition code register (CCR) is set to block maskable interrupts so the user program has a chance to
initialize the stack pointer (SP) and system control settings. The SP is forced to $00FF at reset. The FXTH870xD has seven
sources for reset:
• Power-on reset (POR)
• Low-voltage detect (LVD)
• Computer operating properly (COP) timer
• Periodic hardware reset (PRST)
• Illegal opcode detect
• Illegal address detect
• BACKGROUND DEBUG forced reset
Each of these sources has an associated bit in the system reset status register with the exception of the BACKGROUND DEBUG
forced reset and the periodic hardware reset, PRST, that is indicated by the PRF bit in the PWUCS1 register.

5.3 Computer Operating Properly (COP) Watchdog

The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a
system reset from the COP timer (when it is enabled), application software must reset the COP timer periodically. If the
application program gets lost and fails to reset the COP before it times out, a system reset is generated to force the system back
to a known starting point. The COP watchdog is enabled by the COPE bit in SIMOPT1 register. The COP timer is reset by writing
any value to the address of SRS. This write does not affect the data in the read-only SRS. Instead, the act of writing to this
address is decoded and sends a reset signal to the COP timer.
The timeout period can be selected by the COPCLKS and the COPT[2:0] bits as shown in Table 18. The COPCLKS bit selects
either the LFO or the CPU bus clock as the clocking source and the COPT[2:0] bits select the clock count required for a timeout.
The tolerances of these timeout periods is dependent on the selected clock source (LFO or HFO).

Table 18. COP Watchdog Timeout Period

COPT COP
Clock COP Overflow Time
COPCLKS Overflow
2 1 0 Source (ms, nominal)
Count
0 0 0 0 LFO 25 32
0 0 0 1 LFO 26 64
7
0 0 1 0 LFO 2 128
0 0 1 1 LFO 28 256
9
0 1 0 0 LFO 2 512
0 1 0 1 LFO 210 1024

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Table 18. COP Watchdog Timeout Period (continued)

COPT COP
Clock COP Overflow Time
COPCLKS Overflow
2 1 0 Source (ms, nominal)
Count
0 1 1 0 LFO 211 2048
11
0 1 1 1 LFO 2 2048
BUSCLKS[1:0]
1:1 (0.5 MHz) 1:0 (1 MHz) 0:1 (2 MHz) 0:0 (4MHz)
13
1 0 0 0 Bus Clock 2 16.384 8.192 4.096 2.048
1 0 0 1 Bus Clock 214 32.768 16.384 8.192 4.096
1 0 1 0 Bus Clock 215 65.536 32.768 16.384 8.192
1 0 1 1 Bus Clock 216 131.072 65.536 32.768 16.384
1 1 0 0 Bus Clock 217 262.144 131.072 65.536 32.768
1 1 0 1 Bus Clock 218 524.288 262.144 131.072 65.536
1 1 1 0 Bus Clock 219 1048.576 524.288 262.144 131.072
1 1 1 1 Bus Clock 219 1048.576 524.288 262.144 131.072

After any reset, the COP timer is enabled. This provides a reliable way to detect code that is not executing as intended. If the
COP watchdog is not used in an application, it can be disabled by clearing the COPE bit in the write-once SIMOPT1 register.
Even if the application will use the reset default settings in COPE, COPCLKS and COPT[2:0], the user should still write to write-
once SIMOPT1 during reset initialization to lock in the settings. That way, they cannot be changed accidentally if the application
program gets lost.
The write to SRS that services (clears) the COP timer should not be placed in an interrupt service routine (ISR) because the ISR
could continue to be executed periodically even if the main application program fails. When the MCU is in ACTIVE
BACKGROUND DEBUG mode, the COP timer is temporarily disabled.

5.4 SIM Test Register (SIMTST)

The output of the temperature monitor is available using the SIM Test register as shown in Figure 18.

$180F Bit 7 6 5 4 3 2 1 Bit 0

R TRO
TRH
W
RESET: 0 0 1 1 1 0 0 1
= Reserved

Figure 18. SIM Test Register (SIMTST)

Table 19. SIMTST Register Field Descriptions

Field Description
7
Reserved Bit — These bits are reserved for factory trim and should not be altered by the user.
reserved
6:4 Temperature Restart High threshold — Binary coded from 0x00 to 0x07; recommend applications overwrite to 0x06 at each
TRH wakeup cycle.
3:1
Reserved Bit — These bits are reserved for factory trim and should not be altered by the user.
reserved
Temperature Restart Outside
1 TR module is outside the TREARM temperature range and will restart the MCU if the TRE bit is set and
0
temperature falls back within the TRESET temperature range.
TRO
0 TR module is within the TRESET temperature range and the MCU cannot be armed to restart when
temperature falls back to the TRESET range. The TRE bit cannot be set.

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5.5 Interrupts
Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine (ISR), and then restore
the CPU status so processing resumes where it left off before the interrupt. Other than the software interrupt (SWI), which is a
program instruction, interrupts are caused by hardware events. The debug module can also generate an SWI under certain
circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The CPU will not respond
until and unless the local interrupt enable is a logic 1 to enable the interrupt. The I bit in the CCR must be a logic 0 to allow
interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset which masks (prevents) all maskable interrupt
sources. The user program initializes the stack pointer and performs other system setup before clearing the I bit to allow the CPU
to respond to interrupts. When the CPU receives a qualified interrupt request, it completes the current instruction before
responding to the interrupt. The interrupt sequence follows the same cycle-by-cycle sequence as the SWI instruction and consists
of:
• Saving the CPU registers on the stack
• Setting the I bit in the CCR to mask further interrupts
• Fetching the interrupt vector for the highest-priority interrupt that is currently pending
• Filling the instruction queue with the first three bytes of program information starting from the address fetched from the
interrupt vector locations
While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of another interrupt interrupting
the ISR itself (this is called nesting of interrupts). Normally, the I bit is restored to 0 when the CCR is restored from the value
stacked on entry to the ISR. In rare cases, the I bit may be cleared inside an ISR (after clearing the status flag that generated the
interrupt) so that other interrupts can be serviced without waiting for the first service routine to finish. This practice is not
recommended for anyone other than the most experienced programmers because it can lead to subtle program errors that are
difficult to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR, A, X, and PC registers
to their pre interrupt values by reading the previously saved information off the stack.
When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced first.
For compatibility with the M68HC08, the H register is not automatically saved and restored. It is good programming practice to
push H onto the stack at the start of the interrupt service routine (ISR) and restore it just before the RTI that is used to return from
the ISR.

5.5.1 Interrupt Stack Frame

Figure 18 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer (SP) points at the next
available byte location on the stack. The current values of CPU registers are stored on the stack starting with the low-order byte
of the program counter (PCL) and ending with the CCR. After stacking, the SP points at the next available location on the stack
which is the address that is one less than the address where the CCR was saved. The PC value that is stacked is the address
of the instruction in the main program that would have executed next if the interrupt had not occurred.
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part of the RTI sequence,
the CPU fills the instruction pipeline by reading three bytes of program information, starting from the PC address just recovered
from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR. Typically, the flag should be
cleared at the beginning of the ISR so that if another interrupt is generated by this same source, it will be registered so it can be
serviced after completion of the current ISR.

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 UNSTACKING Towards LOWER Addresses
ORDER
7 0
SP after
5 1 CONDITION CODE REGISTER interrupt stacking
4 2 ACCUMULATOR
3 3 INDEX REGISTER* (LOW BYTE X)
2 4 PROGRAM COUNTER HIGH
1 5 PROGRAM COUNTER LOW
SP before
the interrupt
STACKING
ORDER Towards HIGHER Addresses
* High byte (H) of index register is not automatically stacked.
Figure 19. Interrupt Stack Frame

5.5.2 Vector Summary

Table 20 provides a summary of all interrupt sources. Higher-priority sources are located toward the bottom of the table (at the
higher vector addresses). All of these vectors are a 2-byte address that the firmware uses as the destination address. This allows
the firmware to intercept all vectors and add additional processing as needed. The additional process latency for each interrupt
will be described in Section 14.
Therefore, the high-order byte of the address for the user’s interrupt service routine is located at the lower address in the vector
address column, and the low-order byte of the address for the interrupt service routine is located at the higher address. When an
interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt enable is set, an interrupt request
is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in the CCR) is 0, the CPU will finish the current instruction,
stack the PCL, PCH, X, A, and CCR CPU registers, set the I bit, and then fetch the interrupt vector for the highest priority pending
interrupt. Processing then continues in the interrupt service routine.
The triggering of any of these vector fetches will wake the MCU from any of the STOP modes.

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Table 20. Vector Summary
Jump Table
Vector Vector Vector Module
Vector Addr Flags Enables Description
Priority No. Name Source
(High/Low)
15 $DFE0 - $DFE1 Vkbi KBI KBF KBIE Keyboard interrupt pins PTA[3:0]
14 $DFE2 - $DFE3 Reserved
13 $DFE4 - $DFE5 Reserved
Interrupt from the RTI when the periodic
12 $DFE6 - $DFE7 Vrti Sys Ctrl RTIF RTIE
wakeup timer has timed out.
Interrupt from LFR in data mode when a valid
LFIDF LFIDIE
wake ID has been received.
Interrupt from LFR in carrier mode when a
LFCDF LFCDIE
carrier present for the required time.
11 $DFE8 - $DFE9 Vlfrcvr LFR Interrupt from LFR in the manchester decode
LFERF LFERIE
mode when an error is detected.
Interrupt from LFR in the manchester decode
Lower LFDRF LFDRIE mode when an 8-bit data byte has been
successfully received.
10 $DFEA - $DFEB Reserved
Interrupt from the RFM when the data buffer
RFIF
has been completely sent.
9 $DFEC - $DFED Vrf RFM RFIEN
Interrupt from the RFM when transmission
RFEF
error detected.
8 $DFEE - $DFEF Reserved
Interrupt from the TPM1 when the timer
7 $DFF0 - $DFF1 Vtpm1ovf TPM1 TOF TOIE
overflows.
Interrupt from the TPM1 when the selected
6 $DFF2 - $DFF3 Vtpm1ch1 TPM1 CH1F CH1IE
event for channel 1 occurs.
Interrupt from the TPM1 when the selected
5 $DFF4 - $DFF5 Vtpm1ch0 TPM1 CH0F CH0IE
event for channel 0 occurs.
Interrupt from the PWU when the wakeup time
4 $DFF6 - $DFF7 Vwuktmr PWU WUKI WUK[5:0]
interval has elapsed.
Interrupt from the LVD when the supply
3 $DFF8 - $DFF9 Vlvd Sys Ctrl LVDF LVDIE
voltage has dropped below the LVD threshold.
2 $DFFA - $DFFB Reserved
Interrupt from the CPU when an SWI
1 $DFFC - $DFFD Vswi SWI opcode — —
Higher instruction has been executed.
Sys Ctrl - POR — — Reset from power on sequence.
Reset from PWU when the reset interval
Sys Ctrl - PRF PRF PRST[5:0]
elapsed.
Sys Ctrl - COP — COPE Reset when COP watchdog times out.
Reset from the LVD when the supply voltage
Sys Ctrl - LVD — LVDRE
has dropped below the LVD threshold.
0 $DFFE -$DFFF Vreset
Reset when the temperature falls below the
Temp Restart — TRE
temperature restart threshold
Reset from the CPU when trying to execute an
Illegal opcode — —
illegal opcode.
Reset from the CPU when trying to access an
Illegal address — —
illegal address.

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5.6 Low-Voltage Detect (LVD) System
The FXTH870xD includes a system to detect low voltage conditions in order to protect memory contents and control MCU system
states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and an LVD circuit with a user
selectable trip voltage, either high (VLVDH) or low (VLVDL). The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip
voltage is selected by LVDV in SPMSC3. The LVD is disabled upon entering any of the STOP modes unless the LVDSE bit is
set. If LVDSE and LVDE are both set, then the MCU cannot enter STOP1.

5.6.1 Power-On Reset Operation

When power is initially applied to the FXTH870xD, or when the supply voltage drops below the VPOR level, the POR circuit will
cause a reset condition. As the supply voltage rises, the LVD circuit will hold the chip in reset until the supply has risen above the
level determined by LVDV bit. Both the POR bit and the LVD bit in SRS are set following a POR.

5.6.2 LVD Reset Operation

The LVD can be configured to generate a reset upon detection of a low voltage condition has occurred by setting LVDRE to 1
when the supply voltage has fallen below the level determined by LVDV bit. After an LVD reset has occurred, the LVD system will
hold the FXTH870xD in reset until the supply voltage has risen above the level determined by LVDV bit. The threshold for falling
and rising differ by a small amount of hysteresis. The LVD bit in the SRS register is set following either an LVD reset or POR.

5.6.3 LVD Interrupt Operation

When a low voltage condition is detected and the LVD circuit is configured for interrupt operation (LVDE set, LVDIE set, and
LVDRE clear), then LVDF will be set and an LVD interrupt will occur.

5.6.4 Low-Voltage Warning (LVW)

The LVD system has a low voltage warning flag, LVWF, to indicate to the user that the supply voltage is approaching, but is still
above, the LVD reset voltage. The LVWF can be reset by writing a logical one to the LVWACK bit. The LVW does not have an
interrupt associated with it. There are two user selectable trip voltages for the LVW as selected by LVWV in SPMSC3. The LVWF
is set when the supply voltage falls below the selected level and cannot be reset until the supply voltage has risen above the
selected level. The threshold for falling and rising differ by a small amount of hysteresis.

5.7 System Clock Control

Several clock rate selections are possible with the FXTH870xD using the BUSCLKS[1:0] control bits to select the clock frequency
division of the HFO as given in Table 21. These bits are cleared by any MCU reset.

Table 21. HFO Frequency Selections

HFO Frequency
CPU Bus Frequency (MHz)
BUSCLKS1 BUSCLKS0 (MHz)
0 0 8 4
0 1 4 2
1 0 2 1
1 1 1 0.5

5.8 Keyboard Interrupts

The keyboard interrupts can be used to wake the MCU. These are assigned to specific general I/O pins as given in Table 22.

Table 22. Keyboard Interrupt Assignments

KBI Pin Pin Function

0 PTA0 General I/O
1 PTA1 General I/O
2 PTA2 General I/O
3 PTA3 General I/O

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5.9 Real Time Interrupt
The RTI uses the internal low frequency oscillator (LFO) as its clock source. The RTI can be used as a periodic interrupt in MCU
RUN mode, or can be used as a periodic wakeup from all low power modes. The LFO is always active and cannot be powered
off by any software control. The control bits for the RTI are shown in Figure 20.

$1808 Bit 7 6 5 4 3 2 1 Bit 0

R RTIF 0
RTICLKS RTIE 0 RTIS[2:0]
W RTIACK
RESET: 0 0 0 0 0 0 0 0
POR: 0 0 0 0 0 0 0 0
= Reserved

Figure 20. RTI Status/Control Register (SRTISC)

Table 23. SRTISC Register Field Descriptions

Field Description
RTI Interrupt Flag — The RTIF bit indicates when a wakeup interrupt has been generated by the RTI. This bit is cleared by
7 writing a one to the RTIACK bit. Writing a zero to this bit has no effect. Reset clears this bit.
RTIF 0 Wakeup interrupt not generated or was previously acknowledged.
1 Wakeup interrupt generated.
Acknowledge RTIF Interrupt Flag — The RTIACK bit clears the RTIF bit if written with a one. Writing a zero to the RTIACK bit
6 has no effect on the RTIF bit. Reading the RTIACK bit returns a zero. Reset has no effect on this bit.
RTIACK 0 No effect.
1 Clear RTIF bit.
RTI Interrupt Clock Select — This read-write bit selects the clock source for the real-time interrupt request
5
0 Real-time interrupt request clock source is the LFO.
RTICLKS
1 Real-time interrupt request clock source is the HFO (MCU must be in the RUN mode).
RTIF Interrupt Enable — The RTIE bit enables RTI interrupts if written with a one. Reset clears this bit.
4
0 Disable RTI interrupts.
RTIE
1 Enable RTI interrupts.
3
Unused
Unused
2:0 RTI Interrupt Delay Selects — The RTIS[2:0] bits select the timing of the RTI interrupts as given
RTIS[2:0] in Table 24. Reset clears these bits.

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 Table 24. Real-Time Interrupt Period

Delay Timing (ms)

RTIS2 RTIS1 RTIS0
(Dependent on 1-kHz LFO)
0 0 0 OFF
0 0 1 2
0 1 0 4
0 1 1 8
1 0 0 16
1 0 1 32
1 1 0 64
1 1 1 128

5.10 Temperature Sensor and Restart System

The FXTH870xD has two temperature sensing mechanisms. The first is an accurate sensor which is accessible through the
ADC10 channel 1. The second is a less accurate, very low power sensor which generates a wakeup from STOP1 when the
temperature crosses its threshold of detection. This is the temperature restart wakeup which is used as follows:
1. The temperature restart wakeup is enabled by software following detection of an over temperature condition using the
temperature sensor connected to the ADC10.
2. User software enables the temperature restart detector and then instructs the MCU to enter STOP1 mode to halt
execution during the out-of-range temperature condition.
3. When the temperature crosses the temperature restart threshold back into the normal range of operation, a wakeup is
generated to wake the MCU. Exit from STOP1 will reset the device.
The temperature sensor is enabled whenever the ADC10 is enabled. The temperature restart wakeup is enabled by setting the
TRE bit in SIMOPT1 register and whether the detector interrupts the MCU from a very low or a very high temperature is
determined by the TRH bit in the SIMOPT1 register.

5.11 Reset, Interrupt and System Control Registers And Bits

One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space are related to reset
and interrupt systems.

5.11.1 System Reset Status Register (SRS)

The SRS register at $1800 includes seven read-only status flags to indicate the source of the most recent reset. When a debug
host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this
register address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits
depends on what caused the MCU to reset.

$1800 Bit 7 6 5 4 3 2 1 Bit 0

R 0
POR PIN COP ILOP ILAD PWU LVD
W
POR Reset: 1 0 0 0 0 0 1 0
LVD Reset: 1 0 0 0 0 0 1 0
Any Other (1) (1) (1) (1)
0 0 0 0
Reset:
= Reserved
1. Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding to sources that
are not active at the time of reset will be cleared.

Figure 21. System Reset Status Register (SRS)

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Table 25. SRS Register Field Descriptions

Field Description
Power-On Reset — This bit indicates reset was caused by the power-on detection logic. Because the internal supply voltage
was ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while the internal
7
supply was below the LVR threshold.
POR
0 Reset not caused by POR
1 POR caused reset
External Reset Pin — This bit indicates reset was caused by an active-low level on the external reset pin if the device was in
6 either the STOP1 or RUN modes. This bit is not set if the external reset pin is pulled low when the device is in the STOP1 mode.
PIN 0 Reset not caused by external reset pin
1 Reset came from external reset pin
Computer Operating Properly (COP) Watchdog — This bit indicates that reset was caused by the COP watchdog timer timing
5 out. This reset source may be blocked by COPE = 0.
COP 0 Reset not caused by COP timeout
1 Reset caused by COP timeout
Illegal Opcode — This bit indicates reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if STOP is disabled by STOPE = 0 in the SOPT register. The BGND instruction is considered
4
illegal if ACTIVE BACKGROUND mode is disabled by ENBDM = 0 in the BDCSC register.
ILOP
0 Reset not caused by an illegal opcode
1 Reset caused by an illegal opcode
Illegal Address — This bit indicates reset was caused by an attempt to access either data or an instruction at an unimplemented
3 memory address.
ILAD 0 Reset not caused by an illegal address
1 Reset caused by an illegal address
Programmable Wakeup — This bit indicates reset was caused by a PWU reset in run, WAIT, STOP4, and STOP3. After STOP1
2 exit, PRF in PWUCSI indicates PWU was the source of a wakeup.
PWU 0 Reset not caused by PWU.
1 Reset caused by PWU.
Low Voltage Detect — If the LVDRE and LVDSE bits are set and the supply drops below the LVD trip voltage, an LVD reset will
1 occur. This bit is also set by POR.
LVD 0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
0
Unused Bit — This bit always reads as a logical zero. Writes
Unused

5.11.2 System Options Register 1 (SIMOPT1)

The following clock source and frequency selections are available using the system option register 1 as shown in Figure 22.

$1802 Bit 7 6 5 4 3 2 1 Bit 0

R
COPE COPCLKS STOPE RFEN TRE TRH BKGDPE
W
RESET: 1 0 0 - 0 0 1 1
= Reserved

Figure 22. System Option Register 1 (SIMOPT1)

Table 26. SIMOPT1 Register Field Descriptions

Field Description
COP Enable — This control bit enables the COP watchdog. This bit is a write-once bit so that only the first write after reset is
7 honored. Reset sets the COPE bit.
COPE 0 COP Watchdog disabled.
1 COP Watchdog enabled.

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Table 26. SIMOPT1 Register Field Descriptions (continued)

Field Description
COP Clock Select — This control bit selects the clock source for the COP watchdog timer. This bit is a write-once bit so that
6 only the first write after reset is honored. This bit is cleared by an MCU reset.
COPCLKS 0 Select the LFO oscillator output.
1 Select the CPU bus clock.
STOP Mode Select — This control bit enables/disables the STOP instruction to enter a STOP mode defined by the SPMSCR2
5 register. This bit is a write-once bit so that only the first write after reset is honored. This bit is cleared by an MCU reset.
STOPE 0 Disable STOP modes.
1 Enable STOP modes.
RF Module Enable — This bit enables or disables the RF module. This bit is not affected by any reset or power on after STOP
4 exit. It is only initialized at the first power up. This bit can be written anytime.
RFEN 1 RF module enabled.
0 RF module disabled.
Temperature Restart Enable — This control bit enables the temperature restart circuit to interrupt the MCU after being
3 shutdown at either a very high or very low temperature. This bit is cleared by an MCU reset.
TRE 0 Temperature restart disabled.
1 Temperature restart enabled.
Temperature Restart Level — This control bit selects whether the temperature restart circuit will interrupt the MCU after being
2 shutdown on returning from either a very high or very low temperature. This bit is cleared by an MCU reset.
TRH 0 Temperature restart interrupts MCU on return from a very low temperature.
1 Temperature restart interrupts MCU on return from a very high temperature.
BKGD Pin Enable — BKGDPE can be used to allow the BKGD/PTA4 pin to be shared in applications as an input-only general
1 purpose I/O pin:
BKGDPE 0 BKGD function disabled, PTA4 enabled.
1 BKGD function enabled, PTA4 disabled.
0
Reserved register bit, always reads 1.
Reserved

5.11.3 System Operation Register 2 (SIMOPT2)

The following clock source and frequency selections are available using the system option register 2 as shown in Figure 23.

$1803 Bit 7 6 5 4 3 2 1 Bit 0

R
0 COPT[2:0] LFOSEL TCLKDIV BUSCLKS[1:0]
W
RESET: 0 1 1 1 0 0 0 0

Figure 23. System Option Register 2 (SIMOPT2)

Table 27. SIMOPT2 Register Field Descriptions

Field Description
7
Unused Bit — This bit is unused and reads as a logic zero.
Unused
6:4 COP Watchdog Time Out — These control bits select the timeout period for the COP watchdog timer as given in Table 18.
COPT[2:0] These bits are set by an MCU reset to select the longest watchdog timeout period. These bits are write-once after power up.
TPM1 Channel 0 Clock Source — This bit determines which signal is connected to the TPM1 Channel 0, see Section 9.
3
0 Select clock input driven by PTA2.
LFOSEL
1 Select clock input driven by the LFO.
TPM1 Channel 0 CLock Source Divider — The divider for the clock Source for TPM1 Channel 0, see Section 9.
2
0 Select RFM Dx clock source divided by 1.
TCLKDIV
1 Select RFM Dx clock source divided by 8.

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Table 27. SIMOPT2 Register Field Descriptions (continued)

Field Description
Bus Clock Select — Bus clock frequency selection by changing HFO FLL ratio as shown in Figure 2. The bus clock frequency
is always the HFO frequency divided by two. These bits are cleared by a reset and can be written at any time.
1:0
00 Bus Frequency = 4 MHz (HFO = 8 MHz)
BUSCLKS
01 Bus Frequency = 2 MHz (HFO = 4 MHz)
[1:0]
10 Bus Frequency = 1 MHz (HFO = 2 MHz)
11 Bus Frequency = 0.5 MHz (HFO = 1 MHz)

5.11.4 System Power Management Status and Control 1 Register (SPMSC1)

$1809 7 6 5 4 3 2 1(1) 0

R LVDF 0
LVDIE LVDRE(2) LVDSE LVDE(2) 0 BGBE
W LVDACK
Reset: 0 0 0 1 1 1 0 0
= Reserved
1. Bit 1 is a reserved bit that must always be written to 0.
2. This bit can be written only one time after reset. Additional writes are ignored.

Figure 24. System Power Management Status and Control 1 Register (SPMSC1)

Table 28. SPMSC1 Register Field Descriptions

Field Description
7
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
LVDF
6 Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors (write 1 to clear
LVDACK LVDF). Reads always return logic 0.
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
5
0 Hardware interrupt disabled (use polling)
LVDIE
1 Request a hardware interrupt when LVDF = 1
Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset (provided LVDE
4 = 1).
LVDRE 0 LVDF does not generate hardware resets
1 Force an MCU reset when LVDF = 1
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage detect function
3 operates when the MCU is in STOP mode.
LVDSE 0 Low-voltage detect disabled during STOP mode
1 Low-voltage detect enabled during STOP mode
Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the operation of other bits in
2 this register.
LVDE 0 LVD logic disabled
1 LVD logic enabled
0 Reserved Bit — This bit is reserved should not be altered by the user. Any read returns a logical zero. Any write should be a
Reserved logical zero.
Bandgap Buffer Enable — The BGBE bit is used to enable an internal buffer for the bandgap voltage reference for use by the
0 ADC module on one of its internal channels.
BGBE 0 Bandgap buffer disabled
1 Bandgap buffer enabled

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5.11.5 System Power Management Status and Control 2 Register (SPMSC2)
This register is used to configure the STOP mode behavior of the MCU.

$180A 7 6 5 4 3 2 1 0

R 0 0 0 PDF 0 0
PDC(1) 0
W PPDACK
Power-on reset: 0 0 0 0 0 0 0 0
Any other reset: 0 0 U U 0 0 0 0
= Reserved U = Unaffected by reset
1. This bit can be written only one time after reset. Additional writes are ignored.

Figure 25. System Power Management Status and Control 2 Register (SPMSC2)

Table 29. SPMSC2 Register Field Descriptions

Field Description
7:5
Reserved Bits — These bits are reserved should not be altered by the user. Any read returns a logical zero.
Reserved
Power Down Flag — This read-only status bit indicates the MCU has recovered from STOP1 mode.
4
0 MCU has not recovered from STOP1 mode
PDF
1 MCU recovered from STOP1 mode
3
Reserved Bit — This bit is reserved should not be altered by the user. Any read returns a logical zero.
Reserved
2
Partial Power Down Acknowledge — Writing a logic 1 to PPDACK clears the PDF bit.
PPDACK
Power Down Control — The PDC bit controls entry into the power down (STOP1) mode
1
0 Power down mode are disabled
PDC
1 Power down mode are enabled
0 Reserved Bit — This bit is reserved should not be altered by the user. Any read returns a logical zero. Any write should be a
Reserved logical zero.

5.11.6 System Power Management Status and Control 3 Register (SPMSC3)

$180C 7 6 5 4 3 2 1 0

R LVWF 0 0 0 0 0
LVDV LVWV
W LVWACK
Power-on reset: 0(1) 0 0 0 0 0 0 0
LVD reset: 0(1) 0 U U 0 0 0 0
Any other reset: 0(1) 0 U U 0 0 0 0
= Reserved U = Unaffected by reset
1. LVWF will be set in the case when VSupply transitions below the trip point or after reset and VSupply is already below VLVW.

Figure 26. System Power Management Status and Control 3 Register (SPMSC3)

Table 30. SRTISC Register Field Descriptions

Field Description
Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.
7
0 Low voltage warning not present
LVWF
1 Low voltage warning is present or was present

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Table 30. SRTISC Register Field Descriptions (continued)

Field Description
6 Low-Voltage Warning Acknowledge — The LVWF bit indicates the low voltage warning status.
LVWACK Writing a logic 1 to LVWACK clears LVWF to a logic 0 if a low voltage warning is not present.
Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (VLVD).
5
0 Low trip point selected (VLVD = VLVDL)
LVDV
1 High trip point selected (VLVD = VLVDH)
Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (VLVW).
4
0 Low trip point selected (VLVW = VLVDL)
LVWV
1 High trip point selected (VLVW = VLVDH)
3:0
Reserved Bits — These bits are reserved should not be altered by the user. Any read returns a logical zero.
Reserved

5.12 System STOP Exit Status Register (SIMSES)

The SIMSES register at $180D can be used to determine the source of an MCU wakeup from the STOP modes. The flags are
as shown in Figure 27. All of the flags are automatically cleared when the MCU goes into a STOP mode. Writes to any of these
bits are ignored.

$180D Bit 7 6 5 4 3 2 1 Bit 0

R Reserved KBF IRQF TRF PWUF LFF RFF
W
RESET: 0 0 0 0 0 0 0 0
= Reserved

Figure 27. SIM STOP Exit Status (SIMSES)

Table 31. SIMSES Register Field Descriptions

Field Description
7:6 Reserved Bits — These bits are reserved for Freescale firmware control. Application software shall assure these two bits are
Reserved never overwritten.
Keyboard Flag — This bit indicates that any keyboard pin caused the last exit from STOP mode.
5
0 Keyboard pin did not cause the last exit from STOP mode
KBF
1 Keyboard pin caused the last exit from STOP mode
IRQ Flag — This bit indicates that IRQ pin caused the last exit from STOP mode.
4
0 IRQ pin did not cause the last exit from STOP mode
IRQF
1 IRQ pin caused the last exit from STOP mode
Temperature Restart Flag — This bit indicates that the temperature restart module caused the last exit from STOP mode.
3
0 TR module did not cause the last exit from STOP mode
TRF
1 TR module caused the last exit from STOP mode
PWU Flag — This bit indicates that the PWU module caused the last exit from STOP mode.
2
0 PWU module did not cause the last exit from STOP mode
PWUF
1 PWU module caused the last exit from STOP mode
LFR Flag — This bit indicates that the LFR module caused the last exit from STOP mode.
1
0 LFR module did not cause the last exit from STOP mode
LFF
1 LFR module caused the last exit from STOP mode
RFM Flag — This bit indicates that the RFM module caused the last exit from STOP mode.
0
0 RFM module did not cause the last exit from STOP mode
RFF
1 RFM module caused the last exit from STOP mode

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6 General Purpose I/O
This section explains software controls related to general purpose input/output (I/O) and pin control. The FXTH870xD has seven
general-purpose I/O pins which are comprised of a general use 5-bit port A and a 2-bit port B.
PTA[4:0] pins are shared with on-chip peripheral functions. PTB[1:0] pins are GPIO only, and are multiplexed with the LF receiver
block (see Section 6.5 for additional details regarding mutually exclusive operations).The peripheral modules have priority over
the general purpose I/O so that when a peripheral is enabled, the general purpose I/O functions associated with the shared pins
are disabled. After reset, the shared peripheral functions are disabled so that the pins are controlled by the general purpose I/O.
All of the general purpose I/O are configured as inputs (PTxDDn = 0) with pullup devices disabled (PTxPEn = 0).
To avoid extra current drain from floating input pins, the user’s application software must configure these pins so that they do not
float (see Section 6.1).
Reading and writing of general purpose I/O is performed through the port data registers. The direction, either input or output, is
controlled through the port data direction registers. The general purpose I/O port function for an individual pin is illustrated in the
block diagram in Figure 28.

PTxDDn
D Q Output Enable

PTxDn
D Q Output Data

1
Port Read
Data 0 Synchronizer Input Data

BUSCLKS

Figure 28. General Purpose I/O Block Diagram

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 PTA[3:0] KBEDEy
only
KBIPGy
VDD
PTxPEn

RPU

PTxDDn

Write
PTxDn

Read Port pin

PTxDn

PTA[3:0] KBEDGy
only
KBIPEy

PTxPEn
RPD

KBI interrupt

KBACK KBMOD

Figure 29. General Purpose I/O Logic

Table 32. Truth Table for Pullup and Pulldown Resistors

PTAPE[3:0] PTADD[3:0] KBIPE[3:0] KBEDG[3:0]

Pullup Pulldown
(pull enable) (data direction) (KBI pin enable) (KBI Edge Select)
0 0 x x disabled disabled
1 0 0 x enabled disabled
x 1 x x disabled disabled
1 0 1 0 enabled disabled
1 0 1 1 disabled enabled
PTBPE[1:0] PTBDD[1:0]
(pull enable) (data direction)
0 0 x x disabled x
1 0 x x enabled x
x 1 x x disabled x

The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is enabled, and also controls
the source for port data register reads. The input buffer for the associated pin is always enabled unless the pin is enabled as an
analog function.
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function. However, the data
direction register bit still controls the source for reads of the port data register.
When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value of 0 is read for any
port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled. In general, whenever a pin is shared with
both an alternate digital function and an analog function, the analog function has priority such that if both the digital and analog
functions are enabled, the analog function controls the pin.
It is a good programming practice to write to the port data register before changing the direction of a port pin to become an output.
This ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register.

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An internal pullup device can be enabled for each port pin by setting the corresponding bit in one of the pullup enable registers
(PTxPEn). The pullup device is disabled if the pin is configured as an output by the general purpose I/O control logic or any shared
peripheral function regardless of the state of the corresponding pullup enable register bit. The pullup device is also disabled if the
pin is controlled by an analog function.

6.1 Unused Pin Configuration

Any general purpose I/O pins which are not used in the application must be properly configured to avoid a floating input that could
cause excessive supply current, IDD.
When the device comes out of the reset state the Freescale supplied firmware will not configure any of the general purpose I/O
pins.
Recommended configuration methods are:
1. Configure the general purpose I/O pin as an input (PTxDDn = 0) with the pin connected to the VDD source; use a
pullup resistor of 10-51 k to assure sufficient noise immunity.
2. Configure the general purpose I/O pin as an input (PTxDDn = 0) with the internal pullup activated (PTxPEn = 1) and
leave the pin disconnected.
3. Configure the general purpose I/O pin as an output (PTxDDn = 1) and drive the pin low (PTxDn = 0) and leave the pin
disconnected.
In cases where GPIOs are directly connected to AVDD, VDD, AVSS, VSS or RVSS, user application should configure the GPIO as
an input with the internal pull-up disabled, in order to prevent software code faults from causing excessive supply current states
should these pins become outputs.

6.2 Pin Behavior in STOP Modes

Pin behavior following execution of a STOP instruction depends on the STOP mode that is entered. An explanation of pin
behavior for the various STOP modes follows:
• In STOP1 mode, all internal registers including general purpose I/O control and data registers are powered off. Each of the
pins assumes its default reset state (input buffer, output buffer and internal pullup disabled). Upon exit from STOP1, all pins
must be reconfigured the same as if the MCU had been reset.
• In STOP4 mode, all pin states are maintained because internal logic stays powered up. Upon recovery, all pin functions are
the same as before entering STOP4.

6.3 General Purpose I/O Registers

This section provides information about the registers associated with the general purpose I/O ports and pin control functions.
These general purpose I/O registers are located in page zero of the memory map and the pin control registers are located in the
high page register section of memory.

6.4 Port A Registers

Port A general purpose I/O function is controlled by the registers described in this section.

$0000 Bit 7 6 5 4 3 2 1 Bit 0

R
PTAD[4:0]
W
Reset: 0 0 0 0 0 0 0 0
= Reserved

Figure 30. Port A Data Register (PTAD)

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Table 33. Port A Data Register Field Descriptions

Field Description
Port A Data Register Bit — For port A pins that are inputs, reads return the logic level on the pin. For port A pins that are
configured as outputs, reads return the last value written to this register.
4:0
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is driven out the
PTAD
corresponding MCU pin.
[4:0]
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins
as high-impedance inputs with pullups disabled.

$0001 Bit 7 6 5 4 3 2 1 Bit 0

R
PTAPE[3:0]
W
Reset: 0 0 0 0 0 0 0 0
= Reserved

Figure 31. Internal Pullup Enable for Port A Register (PTAPE)

Table 34. Port A Register Pullup Enable Field Descriptions

Field Description
Internal Pullup Enable for Port A Bit n — Each of these control bits determines if the internal pullup device is enabled for the
3:0 associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and the internal pullup devices are
PTAPE disabled.
[3:0] 0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.

$0003 Bit 7 6 5 4 3 2 1 Bit 0

R
PTADD[3:0]
W
Reset: 0 0 0 0 0 0 0 0
= Reserved

Figure 32. Data Direction for Port A Register (PTADD)

Table 35. Port A Data Direction Field Descriptions

Field Description
Data Direction for Port A Bit n — These read/write bits control the direction of port A pins and what is read for PTADD reads.
3:0
0 Input (output driver disabled) and reads return the pin value.
PTADD
1 Output driver enabled for port A bit n and PTADD reads return the contents of PTADDn. PTA4 is input-only, therefore bit 4 will
[3:0]
always be 0.

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6.5 Port B Registers
Port B PTB[1:0] functions are multiplexed with the LF receiver block such that the port B GPIOs become high impedance when
the LF block has been enabled. When the LF block is disabled, port B pins operate as described here.

$0004 Bit 7 6 5 4 3 2 1 Bit 0

R
PTBD[1:0]
W
Reset: 0 0 0 0 0 0 0 0
= Reserved

Figure 33. Port B Data Register (PTBD)

Table 36. Port B Data Register Field Descriptions

Field Description
Port B Data Register Bit n — For port B pins that are inputs, reads return the logic level on the pin. For port B pins that are
1:0 configured as outputs, reads return the last value written to this register.
PTBD Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is driven out the
[1:0] corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins
as high-impedance inputs with pullups disabled.

$0005 Bit 7 6 5 4 3 2 1 Bit 0

R
PTBPE[1:0]
W
Reset: 0 0 0 0 0 0 0 0
= Reserved

Figure 34. Internal Pullup Enable for Port B Register (PTBPE)

Table 37. Port B Register Pullup Enable Field Descriptions

Field Description
Internal Pullup Enable for Port B Bit n — Each of these control bits determines if the internal pullup device is enabled for the
1:0 associated PTB pin. For port B pins that are configured as outputs, these bits have no effect and the internal pullup devices are
PTBPE disabled.
[1:0] 0 Internal pullup device disabled for port B bit n.
1 Internal pullup device enabled for port B bit n.

$0007 Bit 7 6 5 4 3 2 1 Bit 0

R
PTBDD[1:0]
W
Reset: 0 0 0 0 0 0 0 0
= Reserved

Figure 35. Data Direction for Port B Register (PTBDD)

Table 38. Port B Data Direction Field Descriptions

Field Description
1:0 Data Direction for Port B Bit n — These read/write bits control the direction of port B pins and what is read for PTBDD reads.
PTBDD 0 Input (output driver disabled) and reads return the pin value.
[1:0] 1 Output driver enabled for port B bit n and PTBDD reads return the contents of PTBDDn.

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7 Keyboard Interrupt
The FXTH870xD has a KBI module with general purpose I/O pins.

7.1 Features
The KBI features include:
• Up to four keyboard interrupt pins with individual pin enable bits.
• Each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling edge and low level (or both
rising edge and high level) interrupt sensitivity.
• One software enabled keyboard interrupt.
• Exit from low-power modes.

7.2 Modes of Operation

This section defines the KBI operation in WAIT, STOP, and BACKGROUND DEBUG modes.

7.2.1 KBI in STOP Modes

The KBI operates asynchronously in STOP4 mode if enabled before executing the STOP instruction. Therefore, an enabled KBI
pin (KBPE[3:0]) can be used to bring the MCU out of STOP4 mode if the KBI interrupt is enabled (KBIE = 1).
During STOP1 mode, the KBI is disabled. In some systems, the pins associated with the KBI may be sources of wakeup from
STOP1, see the STOP modes section in the Section 3. Upon wakeup from STOP1 mode, the KBI module will be in the reset
state.

7.2.2 KBI in ACTIVE BACKGROUND mode

When the microcontroller is in ACTIVE BACKGROUND mode, the KBI will continue to operate normally.

7.3 Block Diagram

The block diagram for the keyboard interrupt module is shown Figure 36.

KBACK BUSCLK

1 VDD RESET
KBF
KBIP0 0
S D CLR Q
KBIPE0
SYNCHRONIZER
CK
KBEDG0
KEYBOARD STOP STOP BYPASS KBI
INTERRUPT FF
1 INTERRUP
KBIPn 0
KBMOD
S KBIPEn
KBIE
KBEDGn

Figure 36. KBI Block Diagram

7.4 External Signal Description

The KBI input pins can be used to detect either falling edges, or both falling edge and low level interrupt requests. The KBI input
pins can also be used to detect either rising edges, or both rising edge and high level interrupt requests.
The signal properties of KBI are shown in Table 39.

Table 39. Signal Properties

Signal Function I/O

KBIPn Keyboard interrupt pins I

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7.5 Register Definitions
The KBI includes three registers:
• An 4-bit pin status and control register.
• An 4-bit pin enable register.
• An 4-bit edge select register.

7.5.1 KBI Status and Control Register (KBISC)

KBISC contains the status flag and control bits, which are used to configure the KBI.

$000C 7 6 5 4 3 2 1 0
R 0 0 0 0 KBF 0
KBIE KBMOD
W KBACK
Reset: 0 0 0 0 0 0 0 0
= Reserved

Figure 37. KBI Status and Control Register

Table 40. KBISC Register Field Descriptions

Field Description
7:4 Unused register bits, always read 0.
Keyboard Interrupt Flag — KBF indicates when a keyboard interrupt is detected. Writes have no effect on KBF.
3
0 No keyboard interrupt detected.
KBF
1 Keyboard interrupt detected.
2
Keyboard Acknowledge — Writing a 1 to KBACK is part of the flag clearing mechanism. KBACK always reads as 0.
KBACK
Keyboard Interrupt Enable — KBIE determines whether a keyboard interrupt is requested.
1
0 Keyboard interrupt request not enabled.
KBIE
1 Keyboard interrupt request enabled.
Keyboard Detection Mode — KBMOD (along with the KBEDG bits) controls the detection mode of the keyboard interrupt pins.
0
0 Keyboard detects edges only.
KBMOD
1 Keyboard detects both edges and levels.

7.5.2 KBI Pin Enable Register (KBIPE)

KBIPE contains the pin enable control bits.

$000D 7 6 5 4 3 2 1 0
R
KBIPE3 KBIPE2 KBIPE1 KBIPE0
W
Reset: 0 0 0 0 0 0 0 0

Figure 38. KBI Pin Enable Register

Table 41. KBIPE Register Field Descriptions

Field Description
Keyboard Pin Enables — Each of the KBIPEn bits enable the corresponding keyboard interrupt pin.
3:0
0 Pin not enabled as keyboard interrupt.
KBIPEn
1 Pin enabled as keyboard interrupt.

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7.5.3 KBI Edge Select Register (KBIES)
KBIES contains the edge select control bits.

$000E 7 6 5 4 3 2 1 0
R
KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0
W
Reset: 0 0 0 0 0 0 0 0

Figure 39. KBI Edge Select Register

Table 42. KBIES Register Field Descriptions

Field Description
Keyboard Edge Selects — Each of the KBEDGn bits selects the falling edge/low level or rising edge/high level function of the
7:0 corresponding pin).
KBEDGn 0 Falling edge/low level.
1 Rising edge/high level.

7.6 Functional Description

This on-chip peripheral module is called a keyboard interrupt (KBI) module because originally it was designed to simplify the
connection and use of row-column matrices of keyboard switches. However, these inputs are also useful as extra external
interrupt inputs and as an external means of waking the MCU from STOP or WAIT low-power modes.
The KBI module allows up to eight pins to act as additional interrupt sources. Writing to the KBIPE[3:0] bits in the keyboard
interrupt pin enable register (KBIPE) independently enables or disables each KBI pin. Each KBI pin can be configured as edge
sensitive or edge and level sensitive based on the KBMOD bit in the keyboard interrupt status and control register (KBISC). Edge
sensitive can be software programmed to be either falling or rising; the level can be either low or high. The polarity of the edge
or edge and level sensitivity is selected using the KBEDG[3:0] bits in the keyboard interrupt edge select register (KBIES).
Synchronous logic is used to detect edges. Prior to detecting an edge, enabled keyboard inputs must be at the reset logic level.
A falling edge is detected when an enabled keyboard input signal is seen as a logic 1 (the reset level) during one bus cycle and
then a logic 0 (the asserted level) during the next cycle. A rising edge is detected when the input signal is seen as a logic 0 during
one bus cycle and then a logic 1 during the next cycle.

7.6.1 Edge Only Sensitivity

A valid edge on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the
CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in KBISC.

7.6.2 Edge and Level Sensitivity

A valid edge or level on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented
to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in KBISC provided all enabled keyboard inputs are at their
reset levels. KBF will remain set if any enabled KBI pin is asserted while attempting to clear by writing a 1 to KBACK.

7.6.3 KBI Pullup/Pulldown Resistors

The KBI pins can be configured to use an internal pullup/pulldown resistor using the associated I/O port pullup enable register.
If an internal resistor is enabled, the KBIES register is used to select whether the resistor is a pullup (KBEDG[3:0] = 1) or a
pulldown (KBEDG[3:0] = 0).

7.6.4 KBI Initialization

When a keyboard interrupt pin is first enabled it is possible to get a false keyboard interrupt flag. To prevent a false interrupt
request during keyboard initialization, the user should do the following:
1. Mask keyboard interrupts by clearing KBIE in KBISC.
2. Enable the KBI polarity by setting the appropriate KBEDGn bits in KBIES.
3. If using internal pullup/pulldown device, configure the associated pullup enable bits in PTAPE[3:0].
4. Enable the KBI pins by setting the appropriate KBIPE[3:0] bits in KBIPE.
5. Write to KBACK in KBISC to clear any false interrupts.
6. Set KBIE in KBISC to enable interrupts.

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8 Central Processing Unit
8.1 Introduction
This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08
Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor
document order number HCS08RMV1/D.
The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructions and enhanced
addressing modes were added to improve C compiler efficiency and to support a new BACKGROUND DEBUG system which
replaces the monitor mode of earlier M68HC08 microcontrollers (MCU).

8.2 Features
Features of the HCS08 CPU include:
• Object code fully upward-compatible with M68HC05 and M68HC08 Families
• All registers and memory are mapped to a single 64-Kbyte address space
• 16-bit stack pointer (any size stack anywhere in 64-Kbyte address space)
• 16-bit index register (H:X) with powerful indexed addressing modes
• 8-bit accumulator (A)
• Many instructions treat X as a second general-purpose 8-bit register
• Seven addressing modes:
— Inherent — Operands in internal registers
— Relative — 8-bit signed offset to branch destination
— Immediate — Operand in next object code byte(s)
— Direct — Operand in memory at 0x0000–0x00FF
— Extended — Operand anywhere in 64-Kbyte address space
— Indexed relative to H:X — Five submodes including auto-increment
— Indexed relative to SP — Improves C efficiency dramatically
• Memory-to-memory data move instructions with four address mode combinations
• Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed,
unsigned, and binary-coded decimal (BCD) operations
• Efficient bit manipulation instructions
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• STOP and WAIT instructions to invoke low-power operating modes

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8.3 Programmer’s Model and CPU Registers
Figure 40 shows the five CPU registers. CPU registers are not part of the memory map.

7 0
ACCUMULATOR A

16-BIT INDEX REGISTER H:X

H INDEX REGISTER (HIGH) INDEX REGISTER (LOW) X
15 8 7 0
STACK POINTER SP
15 0
PROGRAM COUNTER PC

7 0
CONDITION CODE REGISTER V 1 1 H I N Z C CCR

CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO’S COMPLEMENT OVERFLOW

Figure 40. CPU Registers

8.3.1 Accumulator (A)

The A accumulator is a general-purpose 8-bit register. One operand input to the arithmetic logic unit (ALU) is connected to the
accumulator and the ALU results are often stored into the A accumulator after arithmetic and logical operations. The accumulator
can be loaded from memory using various addressing modes to specify the address where the loaded data comes from, or the
contents of A can be stored to memory using various addressing modes to specify the address where data from A will be stored.
Reset has no effect on the contents of the A accumulator.

8.3.2 Index Register (H:X)

This 16-bit register is actually two separate 8-bit registers (H and X), which often work together as a 16-bit address pointer where
H holds the upper byte of an address and X holds the lower byte of the address. All indexed addressing mode instructions use
the full 16-bit value in H:X as an index reference pointer; however, for compatibility with the earlier M68HC05 Family, some
instructions operate only on the low-order 8-bit half (X).
Many instructions treat X as a second general-purpose 8-bit register that can be used to hold 8-bit data values. X can be cleared,
incremented, decremented, complemented, negated, shifted, or rotated. Transfer instructions allow data to be transferred from
A or transferred to A where arithmetic and logical operations can then be performed.
For compatibility with the earlier M68HC05 Family, H is forced to 0x00 during reset. Reset has no effect on the contents of X.

8.3.3 Stack Pointer (SP)

This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack
may be located anywhere in the 64-Kbyte address space that has RAM and can be any size up to the amount of available RAM.
The stack is used to automatically save the return address for subroutine calls, the return address and CPU registers during
interrupts, and for local variables. The AIS (add immediate to stack pointer) instruction adds an 8-bit signed immediate value to
SP. This is most often used to allocate or deallocate space for local variables on the stack.
SP is forced to 0x00FF at reset for compatibility with the earlier M68HC05 Family. HCS08 programs normally change the value
in SP to the address of the last location (highest address) in on-chip RAM during reset initialization to free up direct page RAM
(from the end of the on-chip registers to 0x00FF).
The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 Family and is seldom used in new
HCS08 programs because it only affects the low-order half of the stack pointer.

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8.3.4 Program Counter (PC)
The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched.
During normal program execution, the program counter automatically increments to the next sequential memory location every
time an instruction or operand is fetched. Jump, branch, interrupt, and return operations load the program counter with an
address other than that of the next sequential location. This is called a change-of-flow.
During reset, the program counter is loaded with the reset vector that is located at 0xFFFE and 0xFFFF. The vector stored there
is the address of the first instruction that will be executed after exiting the reset state.

8.3.5 Condition Code Register (CCR)

The 8-bit condition code register contains the interrupt mask (I) and five flags that indicate the results of the instruction just
executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code bits in
general terms. For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference
Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1.

7 0
CONDITION CODE REGISTER V 1 1 H I N Z C CCR

CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO’S COMPLEMENT OVERFLOW

Figure 41. Condition Code Register

Table 43. CCR Register Field Descriptions

Field Description
Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs. The signed
7 branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
V 0 No overflow
1 Overflow
Half-Carry Flag — The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-
carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic
4 operations. The DAA instruction uses the states of the H and C condition code bits to automatically add a correction value to the
H result from a previous ADD or ADC on BCD operands to correct the result to a valid BCD value.
0 No carry between bits 3 and 4
1 Carry between bits 3 and 4
Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when
the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are
saved on the stack, but before the first instruction of the interrupt service routine is executed.
3
Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This ensures that the next
I
instruction after a CLI or TAP will always be executed without the possibility of an intervening interrupt, provided I was set.
0 Interrupts enabled
1 Interrupts disabled
Negative Flag — The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces
a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value causes N to be set if the most
2
significant bit of the loaded or stored value was 1.
N
0 Non-negative result
1 Negative result
Zero Flag — The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result
1 of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the loaded or stored value was all 0s.
Z 0 Non-zero result
1 Zero result

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Table 43. CCR Register Field Descriptions (continued)

Field Description
Carry/Borrow Flag — The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate
0
— also clear or set the carry/borrow flag.
C
0 No carry out of bit 7
1 Carry out of bit 7

8.4 Addressing Modes

Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers,
and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit binary address can uniquely identify any
memory location. This arrangement means that the same instructions that access variables in RAM can also be used to access
I/O and control registers or nonvolatile program space.
Some instructions use more than one addressing mode. For instance, move instructions use one addressing mode to specify the
source operand and a second addressing mode to specify the destination address. Instructions such as BRCLR, BRSET, CBEQ,
and DBNZ use one addressing mode to specify the location of an operand for a test and then use relative addressing mode to
specify the branch destination address when the tested condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing
mode listed in the instruction set tables is the addressing mode needed to access the operand to be tested, and relative
addressing mode is implied for the branch destination.

8.4.1 Inherent Addressing Mode (INH)

In this addressing mode, operands needed to complete the instruction (if any) are located within CPU registers so the CPU does
not need to access memory to get any operands.

8.4.2 Relative Addressing Mode (REL)

Relative addressing mode is used to specify the destination location for branch instructions. A signed 8-bit offset value is located
in the memory location immediately following the opcode. During execution, if the branch condition is true, the signed offset is
sign-extended to a 16-bit value and is added to the current contents of the program counter, which causes program execution to
continue at the branch destination address.

8.4.3 Immediate Addressing Mode (IMM)

In immediate addressing mode, the operand needed to complete the instruction is included in the object code immediately
following the instruction opcode in memory. In the case of a 16-bit immediate operand, the high-order byte is located in the next
memory location after the opcode, and the low-order byte is located in the next memory location after that.

8.4.4 Direct Addressing Mode (DIR)

In direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page (0x0000–0x00FF).
During execution a 16-bit address is formed by concatenating an implied 0x00 for the high-order half of the address and the direct
address from the instruction to get the 16-bit address where the desired operand is located. This is faster and more memory
efficient than specifying a complete 16-bit address for the operand.

8.4.5 Extended Addressing Mode (EXT)

In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the
opcode (high byte first).

8.4.6 Indexed Addressing Mode

Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack
pointer as the base reference.
8.4.6.1 Indexed, No Offset (IX)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of the operand needed
to complete the instruction.
8.4.6.2 Indexed, No Offset with Post Increment (IX+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of the operand needed
to complete the instruction. The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched.
This addressing mode is only used for MOV and CBEQ instructions.

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8.4.6.3 Indexed, 8-Bit Offset (IX1)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned 8-bit offset included in
the instruction as the address of the operand needed to complete the instruction.
8.4.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned 8-bit offset included in
the instruction as the address of the operand needed to complete the instruction. The index register pair is then incremented
(H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is used only for the CBEQ instruction.
8.4.6.5 Indexed, 16-Bit Offset (IX2)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset included in the
instruction as the address of the operand needed to complete the instruction.
8.4.6.6 SP-Relative, 8-Bit Offset (SP1)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the
instruction as the address of the operand needed to complete the instruction.
8.4.6.7 SP-Relative, 16-Bit Offset (SP2)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction
as the address of the operand needed to complete the instruction.

8.5 Special Operations

The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions.
In addition, a few instructions such as STOP and WAIT directly affect other MCU circuitry. This section provides additional
information about these operations.

8.5.1 Reset Sequence

Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer operating properly)
watchdog, or by assertion of an external active-low reset pin. When a reset event occurs, the CPU immediately stops whatever
it is doing (the MCU does not wait for an instruction boundary before responding to a reset event). For a more detailed discussion
about how the MCU recognizes resets and determines the source, refer to the Section 5.
The reset event is considered concluded when the sequence to determine whether the reset came from an internal source is
done and when the reset pin is no longer asserted. At the conclusion of a reset event, the CPU performs a 6-cycle sequence to
fetch the reset vector from 0xFFFE and 0xFFFF and to fill the instruction queue in preparation for execution of the first program
instruction.

8.5.2 Interrupt Sequence

When an interrupt is requested, the CPU completes the current instruction before responding to the interrupt. At this point, the
program counter is pointing at the start of the next instruction, which is where the CPU should return after servicing the interrupt.
The CPU responds to an interrupt by performing the same sequence of operations as for a software interrupt (SWI) instruction,
except the address used for the vector fetch is determined by the highest priority interrupt that is pending when the interrupt
sequence started.
The CPU sequence for an interrupt is:
1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order.
2. Set the I bit in the CCR.
3. Fetch the high-order half of the interrupt vector.
4. Fetch the low-order half of the interrupt vector.
5. Delay for one free bus cycle.
6. Fetch three bytes of program information starting at the address indicated by the interrupt vector to fill the instruction
queue in preparation for execution of the first instruction in the interrupt service routine.
After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt
service routine. Although it is possible to clear the I bit with an instruction in the interrupt service routine, this would allow nesting
of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain).
For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H) is not saved on the stack
as part of the interrupt sequence. The user must use a PSHH instruction at the beginning of the service routine to save H and
then use a PULH instruction just before the RTI that ends the interrupt service routine. It is not necessary to save H if you are

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certain that the interrupt service routine does not use any instructions or auto-increment addressing modes that might change
the value of H.
The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the global I bit in the CCR and
it is associated with an instruction opcode within the program so it is not asynchronous to program execution.

8.5.3 WAIT Mode Operation

The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the CPU to reduce overall
power consumption while the CPU is waiting for the interrupt or reset event that will wake the CPU from WAIT mode. When an
interrupt or reset event occurs, the CPU clocks will resume and the interrupt or reset event will be processed normally.
If a serial BACKGROUND command is issued to the MCU through the BACKGROUND DEBUG interface while the CPU is in
WAIT mode, CPU clocks will resume and the CPU will enter ACTIVE BACKGROUND mode where other serial BACKGROUND
commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in
WAIT mode.

8.5.4 STOP Mode Operation

Usually, all system clocks, including the crystal oscillator (when used), are halted during STOP mode to minimize power
consumption. In such systems, external circuitry is needed to control the time spent in STOP mode and to issue a signal to
wakeup the target MCU when it is time to resume processing. Unlike the earlier M68HC05 and M68HC08 MCUs, the HCS08 can
be configured to keep a minimum set of clocks running in STOP mode. This optionally allows an internal periodic signal to wake
the target MCU from STOP mode.
When a host debug system is connected to the BACKGROUND DEBUG pin (BKGD) and the ENBDM control bit has been set
by a serial command through the BACKGROUND interface (or because the MCU was reset into ACTIVE BACKGROUND mode),
the oscillator is forced to remain active when the MCU enters STOP mode. In this case, if a serial BACKGROUND command is
issued to the MCU through the BACKGROUND DEBUG interface while the CPU is in STOP mode, CPU clocks will resume and
the CPU will enter ACTIVE BACKGROUND mode where other serial BACKGROUND commands can be processed. This
ensures that a host development system can still gain access to a target MCU even if it is in STOP mode.
Recovery from STOP mode depends on the particular HCS08 and whether the oscillator was stopped in STOP mode. Refer to
the Section 3 for more details.

8.5.5 BGND Instruction

The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs
because it forces the CPU to stop processing user instructions and enter the ACTIVE BACKGROUND mode. The only way to
resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial
command through the BACKGROUND DEBUG interface.
Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When
the program reaches this breakpoint address, the CPU is forced to ACTIVE BACKGROUND mode rather than continuing the
user program.

8.6 HCS08 Instruction Set Summary

Instruction Set Summary Nomenclature
The nomenclature listed here is used in the instruction descriptions in Table 44.
Operators
() = Contents of register or memory location shown inside parentheses
 = Is loaded with (read: “gets”)
& = Boolean AND
| = Boolean OR
 = Boolean exclusive-OR
 = Multiply
 = Divide
: = Concatenate
+ = Add
– = Negate (two’s complement)
CPU registers
A = Accumulator
CCR = Condition code register
H = Index register, higher order (most significant) 8 bits

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 X = Index register, lower order (least significant) 8 bits
PC = Program counter
PCH = Program counter, higher order (most significant) 8 bits
PCL = Program counter, lower order (least significant) 8 bits
SP = Stack pointer
Memory and addressing
M = A memory location or absolute data, depending on addressing mode
M:M + 0x0001 = A 16-bit value in two consecutive memory locations. The higher-order (most significant) 8 bits are
located at the address of M, and the lower-order (least significant) 8 bits are located at the next higher
sequential address.

Condition code register (CCR) bits

V = Two’s complement overflow indicator, bit 7
H = Half carry, bit 4
I = Interrupt mask, bit 3
N = Negative indicator, bit 2
Z = Zero indicator, bit 1
C = Carry/borrow, bit 0 (carry out of bit 7)

CCR activity notation

– = Bit not affected
0 = Bit forced to 0
1 = Bit forced to 1
Þ = Bit set or cleared according to results of operation
U = Undefined after the operation

Machine coding notation

dd = Low-order 8 bits of a direct address 0x0000–0x00FF (high byte assumed to be 0x00)
ee = Upper 8 bits of 16-bit offset
ff = Lower 8 bits of 16-bit offset or 8-bit offset
ii = One byte of immediate data
jj = High-order byte of a 16-bit immediate data value
kk = Low-order byte of a 16-bit immediate data value
hh = High-order byte of 16-bit extended address
ll = Low-order byte of 16-bit extended address
rr = Relative offset

Source form
Everything in the source forms columns, except expressions in italic characters, is literal information that must appear in the
assembly source file exactly as shown. The initial 3- to 5-letter mnemonic is always a literal expression. All commas, pound signs
(#), parentheses, and plus signs (+) are literal characters.
n — Any label or expression that evaluates to a single integer in the range 0–7
opr8i — Any label or expression that evaluates to an 8-bit immediate value
opr16i — Any label or expression that evaluates to a 16-bit immediate value
opr8a — Any label or expression that evaluates to an 8-bit value. The instruction treats this 8-bit value as
the low order 8 bits of an address in the direct page of the 64-Kbyte address space (0x00xx).
opr16a — Any label or expression that evaluates to a 16-bit value. The instruction treats this value as an
address in the 64-Kbyte address space.
oprx8 — Any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing
oprx16 — Any label or expression that evaluates to a 16-bit value. Because the HCS08 has a 16-bit
address bus, this can be either a signed or an unsigned value.
rel — Any label or expression that refers to an address that is within –128 to +127 locations from the
next address after the last byte of object code for the current instruction. The assembler will
calculate the 8-bit signed offset and include it in the object code for this instruction.

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Address modes
INH = Inherent (no operands)
IMM = 8-bit or 16-bit immediate
DIR = 8-bit direct
EXT = 16-bit extended
IX = 16-bit indexed no offset
IX+ = 16-bit indexed no offset, post increment (CBEQ and MOV only)
IX1 = 16-bit indexed with 8-bit offset from H:X
IX1+ = 16-bit indexed with 8-bit offset, post increment
(CBEQ only)
IX2 = 16-bit indexed with 16-bit offset from H:X
REL = 8-bit relative offset
SP1 = Stack pointer with 8-bit offset
SP2 = Stack pointer with 16-bit offset

Table 44. HCS08 Instruction Set Summary (Sheet 1 of 8)

Bus Cycles(1)
Effect

Operand
Address

Opcode
on CCR

Mode
Source
Operation Description
Form
V H I N Z C

ADC #opr8i IMM A9 ii 2

ADC opr8a DIR B9 dd 3
ADC opr16a EXT C9 hh ll 4
ADC oprx16,X IX2 D9 ee ff 4
Add with Carry A  (A) + (M) + (C) Þ Þ – Þ Þ Þ
ADC oprx8,X IX1 E9 ff 3
ADC ,X IX F9 3
ADC oprx16,SP SP2 9ED9 ee ff 5
ADC oprx8,SP SP1 9EE9 ff 4
ADD #opr8i IMM AB ii 2
ADD opr8a DIR BB dd 3
ADD opr16a EXT CB hh ll 4
ADD oprx16,X IX2 DB ee ff 4
Add without Carry A  (A) + (M) Þ Þ – Þ Þ Þ
ADD oprx8,X IX1 EB ff 3
ADD ,X IX FB 3
ADD oprx16,SP SP2 9EDB ee ff 5
ADD oprx8,SP SP1 9EEB ff 4
Add Immediate Value SP  (SP) + (M)
AIS #opr8i – – – – – – IMM A7 ii 2
(Signed) to Stack Pointer M is sign extended to a 16-bit value
Add Immediate Value
H:X  (H:X) + (M)
AIX #opr8i (Signed) to Index – – – – – – IMM AF ii 2
M is sign extended to a 16-bit value
Register (H:X)
AND #opr8i IMM A4 ii 2
AND opr8a DIR B4 dd 3
AND opr16a EXT C4 hh ll 4
AND oprx16,X IX2 D4 ee ff 4
Logical AND A  (A) & (M) 0 – – Þ Þ –
AND oprx8,X IX1 E4 ff 3
AND ,X IX F4 3
AND oprx16,SP SP2 9ED4 ee ff 5
AND oprx8,SP SP1 9EE4 ff 4
ASL opr8a DIR 38 dd 5
ASLA INH 48 1
ASLX Arithmetic Shift Left INH 58 1
C 0 Þ – – Þ Þ Þ
ASL oprx8,X (Same as LSL) IX1 68 ff 5
b7 b0
ASL ,X IX 78 4
ASL oprx8,SP SP1 9E68 ff 6

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Table 44. HCS08 Instruction Set Summary (Sheet 2 of 8)

Bus Cycles(1)
Effect

Operand
Address

Opcode
on CCR

Mode
Source
Operation Description
Form
V H I N Z C

ASR opr8a DIR 37 dd 5

ASRA INH 47 1
ASRX C INH 57 1
Arithmetic Shift Right Þ – – Þ Þ Þ
ASR oprx8,X b7 b0 IX1 67 ff 5
ASR ,X IX 77 4
ASR oprx8,SP SP1 9E67 ff 6
BCC rel Branch if Carry Bit Clear Branch if (C) = 0 – – – – – – REL 24 rr 3
DIR (b0) 11 dd 5
DIR (b1) 13 dd 5
DIR (b2) 15 dd 5
DIR (b3) 17 dd 5
BCLR n,opr8a Clear Bit n in Memory Mn  0 – – – – – –
DIR (b4) 19 dd 5
DIR (b5) 1B dd 5
DIR (b6) 1D dd 5
DIR (b7) 1F dd 5
Branch if Carry Bit Set
BCS rel Branch if (C) = 1 – – – – – – REL 25 rr 3
(Same as BLO)
BEQ rel Branch if Equal Branch if (Z) = 1 – – – – – – REL 27 rr 3
Branch if Greater Than or
BGE rel Equal To Branch if (N V – – – – – – REL 90 rr 3
(Signed Operands)
Waits For and Processes BDM
Enter ACTIVE BACK-
BGND Commands Until GO, TRACE1, or – – – – – – INH 82 5+
GROUND if ENBDM = 1
TAGGO
Branch if Greater Than
BGT rel Branch if (Z)| (N V – – – – – – REL 92 rr 3
(Signed Operands)
Branch if Half Carry Bit
BHCC rel Branch if (H) = 0 – – – – – – REL 28 rr 3
Clear
Branch if Half Carry Bit
BHCS rel Branch if (H) = 1 – – – – – – REL 29 rr 3
Set
BHI rel Branch if Higher Branch if (C) | (Z) = 0 – – – – – – REL 22 rr 3
Branch if Higher or Same
BHS rel Branch if (C) = 0 – – – – – – REL 24 rr 3
(Same as BCC)
BIH rel Branch if IRQ Pin High Branch if IRQ pin = 1 – – – – – – REL 2F rr 3
BIL rel Branch if IRQ Pin Low Branch if IRQ pin = 0 – – – – – – REL 2E rr 3
BIT #opr8i IMM A5 ii 2
BIT opr8a DIR B5 dd 3
BIT opr16a EXT C5 hh ll 4
(A) & (M)
BIT oprx16,X IX2 D5 ee ff 4
Bit Test (CCR Updated but Operands 0 – – Þ Þ –
BIT oprx8,X IX1 E5 ff 3
Not Changed)
BIT ,X IX F5 3
BIT oprx16,SP SP2 9ED5 ee ff 5
BIT oprx8,SP SP1 9EE5 ff 4
Branch if Less Than
BLE rel or Equal To Branch if (Z)| (N V 1 – – – – – – REL 93 rr 3
(Signed Operands)
Branch if Lower
BLO rel (Same as BCS) Branch if (C) = 1 – – – – – – REL 25 rr 3

BLS rel Branch if Lower or Same Branch if (C) | (Z) = 1 – – – – – – REL 23 rr 3

Branch if Less Than Branch if (N V 1
BLT rel
(Signed Operands) – – – – – – REL 91 rr 3

Branch if Interrupt Mask

BMC rel
Clear
Branch if (I) = 0 – – – – – – REL 2C rr 3

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Table 44. HCS08 Instruction Set Summary (Sheet 3 of 8)

Bus Cycles(1)
Effect

Operand
Address

Opcode
on CCR

Mode
Source
Operation Description
Form
V H I N Z C

BMI rel Branch if Minus Branch if (N) = 1 – – – – – – REL 2B rr 3

Branch if Interrupt Mask
BMS rel Set Branch if (I) = 1 – – – – – – REL 2D rr 3

BNE rel Branch if Not Equal Branch if (Z) = 0 – – – – – – REL 26 rr 3

BPL rel Branch if Plus Branch if (N) = 0 – – – – – – REL 2A rr 3
BRA rel Branch Always No Test – – – – – – REL 20 rr 3
DIR (b0) 01 dd rr 5
DIR (b1) 03 dd rr 5
DIR (b2) 05 dd rr 5
Branch if Bit n in Memory DIR (b3) 07 dd rr 5
BRCLR n,opr8a,rel Branch if (Mn) = 0 – – – – – Þ
Clear DIR (b4) 09 dd rr 5
DIR (b5) 0B dd rr 5
DIR (b6) 0D dd rr 5
DIR (b7) 0F dd rr 5
BRN rel Branch Never Uses 3 Bus Cycles – – – – – – REL 21 rr 3
DIR (b0) 00 dd rr 5
DIR (b1) 02 dd rr 5
DIR (b2) 04 dd rr 5
Branch if Bit n in Memory DIR (b3) 06 dd rr 5
BRSET n,opr8a,rel Branch if (Mn) = 1 – – – – – Þ
Set DIR (b4) 08 dd rr 5
DIR (b5) 0A dd rr 5
DIR (b6) 0C dd rr 5
DIR (b7) 0E dd rr 5
DIR (b0) 10 dd 5
DIR (b1) 12 dd 5
DIR (b2) 14 dd 5
DIR (b3) 16 dd 5
BSET n,opr8a Set Bit n in Memory Mn  1 – – – – – –
DIR (b4) 18 dd 5
DIR (b5) 1A dd 5
DIR (b6) 1C dd 5
DIR (b7) 1E dd 5
PC (PC) + 0x0002
push (PCL); SP  (SP) – 0x0001
BSR rel Branch to Subroutine – – – – – – REL AD rr 5
push (PCH); SP  (SP) – 0x0001
PC  (PC) + rel
CBEQ opr8a,rel Branch if (A) = (M) DIR 31 dd rr 5
CBEQA #opr8i,rel Branch if (A) = (M) IMM 41 ii rr 4
CBEQX #opr8i,rel Compare and Branch if Branch if (X) = (M) IMM 51 ii rr 4
– – – – – –
CBEQ oprx8,X+,rel Equal Branch if (A) = (M) IX1+ 61 ff rr 5
CBEQ ,X+,rel Branch if (A) = (M) IX+ 71 rr ff 5
CBEQ oprx8,SP,rel Branch if (A) = (M) SP1 9E61 rr 6
CLC Clear Carry Bit C0 – – – – – 0 INH 98 1
CLI Clear Interrupt Mask Bit I0 – – 0 – – – INH 9A 1
CLR opr8a M  0x00 DIR 3F dd 5
CLRA A  0x00 INH 4F 1
CLRX X  0x00 INH 5F 1
CLRH Clear H  0x00 0 – – 0 1 – INH 8C 1
CLR oprx8,X M  0x00 IX1 6F ff 5
CLR ,X M  0x00 IX 7F 4
CLR oprx8,SP M  0x00 SP1 9E6F ff 6

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Table 44. HCS08 Instruction Set Summary (Sheet 4 of 8)

Bus Cycles(1)
Effect

Operand
Address

Opcode
on CCR

Mode
Source
Operation Description
Form
V H I N Z C

CMP #opr8i IMM A1 ii 2

CMP opr8a DIR B1 dd 3
CMP opr16a EXT C1 hh ll 4
(A) – (M)
CMP oprx16,X Compare Accumulator IX2 D1 ee ff 4
(CCR Updated But Operands Not Þ – – Þ Þ Þ
CMP oprx8,X with Memory IX1 E1 ff 3
Changed)
CMP ,X IX F1 3
CMP oprx16,SP SP2 9ED1 ee ff 5
CMP oprx8,SP SP1 9EE1 ff 4
COM opr8a M  (M)= 0xFF – (M) DIR 33 dd 5
COMA A  (A) = 0xFF – (A) INH 43 1
COMX Complement X  (X) = 0xFF – (X) INH 53 1
0 – – Þ Þ 1
COM oprx8,X (One’s Complement) M  (M) = 0xFF – (M) IX1 63 ff 5
COM ,X M  (M) = 0xFF – (M) IX 73 4
COM oprx8,SP M  (M) = 0xFF – (M) SP1 9E63 ff 6
CPHX opr16a EXT 3E hh ll 6
(H:X) – (M:M + 0x0001)
CPHX #opr16i Compare Index Register IMM 65 jj kk 3
(CCR Updated But Operands Not Þ – – Þ Þ Þ
CPHX opr8a (H:X) with Memory DIR 75 dd 5
Changed)
CPHX oprx8,SP SP1 9EF3 ff 6
CPX #opr8i IMM A3 ii 2
CPX opr8a DIR B3 dd 3
CPX opr16a EXT C3 hh ll 4
Compare X (Index (X) – (M)
CPX oprx16,X IX2 D3 ee ff 4
Register Low) with (CCR Updated But Operands Not Þ – – Þ Þ Þ
CPX oprx8,X IX1 E3 ff 3
Memory Changed)
CPX ,X IX F3 3
CPX oprx16,SP SP2 9ED3 ee ff 5
CPX oprx8,SP SP1 9EE3 ff 4
Decimal Adjust
DAA Accumulator After ADD (A)10 U – – Þ Þ Þ INH 72 1
or ADC of BCD Values
DBNZ opr8a,rel DIR 3B dd rr 7
DBNZA rel INH 4B rr 4
Decrement A, X, or M
DBNZX rel Decrement and Branch if INH 5B rr 4
Branch if (result) 0 – – – – – –
DBNZ oprx8,X,rel Not Zero IX1 6B ff rr 7
DBNZX Affects X Not H
DBNZ ,X,rel IX 7B rr 6
DBNZ oprx8,SP,rel SP1 9E6B ff rr 8
DEC opr8a M  (M) – 0x01 DIR 3A dd 5
DECA A  (A) – 0x01 INH 4A 1
DECX X  (X) – 0x01 INH 5A 1
Decrement Þ – – Þ Þ –
DEC oprx8,X M  (M) – 0x01 IX1 6A ff 5
DEC ,X M  (M) – 0x01 IX 7A 4
DEC oprx8,SP M  (M) – 0x01 SP1 9E6A ff 6
A  (H:A)(X)
DIV Divide – – – – Þ Þ INH 52 6
H  Remainder
EOR #opr8i IMM A8 ii 2
EOR opr8a DIR B8 dd 3
EOR opr16a EXT C8 hh ll 4
Exclusive OR
EOR oprx16,X IX2 D8 ee ff 4
Memory with A  (A  M) 0 – – Þ Þ –
EOR oprx8,X IX1 E8 ff 3
Accumulator
EOR ,X IX F8 3
EOR oprx16,SP SP2 9ED8 ee ff 5
EOR oprx8,SP SP1 9EE8 ff 4
INC opr8a M  (M) + 0x01 DIR 3C dd 5
INCA A  (A) + 0x01 INH 4C 1
INCX X  (X) + 0x01 INH 5C 1
Increment Þ – – Þ Þ –
INC oprx8,X M  (M) + 0x01 IX1 6C ff 5
INC ,X M  (M) + 0x01 IX 7C 4
INC oprx8,SP M  (M) + 0x01 SP1 9E6C ff 6

FXTH870xD

Sensors
62 Freescale Semiconductor, Inc.
Table 44. HCS08 Instruction Set Summary (Sheet 5 of 8)

Bus Cycles(1)
Effect

Operand
Address

Opcode
on CCR

Mode
Source
Operation Description
Form
V H I N Z C

JMP opr8a DIR BC dd 3

JMP opr16a EXT CC hh ll 4
JMP oprx16,X Jump PC  Jump Address – – – – – – IX2 DC ee ff 4
JMP oprx8,X IX1 EC ff 3
JMP ,X IX FC 3
JSR opr8a DIR BD dd 5
PC  (PC) + n (n = 1, 2, or 3)
JSR opr16a EXT CD hh ll 6
Push (PCL); SP  (SP) – 0x0001
JSR oprx16,X Jump to Subroutine – – – – – – IX2 DD ee ff 6
Push (PCH); SP  (SP) – 0x0001
JSR oprx8,X IX1 ED ff 5
PC  Unconditional Address
JSR ,X IX FD 5
LDA #opr8i IMM A6 ii 2
LDA opr8a DIR B6 dd 3
LDA opr16a EXT C6 hh ll 4
LDA oprx16,X Load Accumulator from IX2 D6 ee ff 4
A  (M) 0 – – Þ Þ –
LDA oprx8,X Memory IX1 E6 ff 3
LDA ,X IX F6 3
LDA oprx16,SP SP2 9ED6 ee ff 5
LDA oprx8,SP SP1 9EE6 ff 4
LDHX #opr16i IMM 45 jj kk 3
LDHX opr8a DIR 55 dd 4
LDHX opr16a EXT 32 hh ll 5
Load Index Register
LDHX ,X H:X M:M+ 0x0001 0 – – Þ Þ – IX 9EAE 5
(H:X) from Memory
LDHX oprx16,X IX2 9EBE ee ff 6
LDHX oprx8,X IX1 9ECE ff 5
LDHX oprx8,SP SP1 9EFE ff 5
LDX #opr8i IMM AE ii 2
LDX opr8a DIR BE dd 3
LDX opr16a EXT CE hh ll 4
LDX oprx16,X Load X (Index Register IX2 DE ee ff 4
X  (M) 0 – – Þ Þ –
LDX oprx8,X Low) from Memory IX1 EE ff 3
LDX ,X IX FE 3
LDX oprx16,SP SP2 9EDE ee ff 5
LDX oprx8,SP SP1 9EEE ff 4
LSL opr8a DIR 38 dd 5
LSLA INH 48 1
LSLX Logical Shift Left C 0 INH 58 1
Þ – – Þ Þ Þ
LSL oprx8,X (Same as ASL) b7 b0 IX1 68 ff 5
LSL ,X IX 78 4
LSL oprx8,SP SP1 9E68 ff 6
LSR opr8a DIR 34 dd 5
LSRA INH 44 1
LSRX 0 C INH 54 1
Logical Shift Right Þ – – 0 Þ Þ
LSR oprx8,X b7 b0 IX1 64 ff 5
LSR ,X IX 74 4
LSR oprx8,SP SP1 9E64 ff 6
MOV opr8a,opr8a (M)destination (M)source DIR/DIR 4E dd dd 5
MOV opr8a,X+ DIR/IX+ 5E dd 5
Move 0 – – Þ Þ –
MOV #opr8i,opr8a H:X  (H:X) + 0x0001 in IMM/DIR 6E ii dd 4
MOV ,X+,opr8a IX+/DIR and DIR/IX+ Modes IX+/DIR 7E dd 5
MUL Unsigned multiply X:A  (X)  (A) – 0 – – – 0 INH 42 5
NEG opr8a M  – (M) = 0x00 – (M) DIR 30 dd 5
NEGA A  – (A) = 0x00 – (A) INH 40 1
NEGX Negate X  – (X) = 0x00 – (X) INH 50 1
Þ – – Þ Þ Þ
NEG oprx8,X (Two’s Complement) M  – (M) = 0x00 – (M) IX1 60 ff 5
NEG ,X M  – (M) = 0x00 – (M) IX 70 4
NEG oprx8,SP M  – (M) = 0x00 – (M) SP1 9E60 ff 6
NOP No Operation Uses 1 Bus Cycle – – – – – – INH 9D 1

FXTH870xD

Sensors
Freescale Semiconductor, Inc. 63
Table 44. HCS08 Instruction Set Summary (Sheet 6 of 8)

Bus Cycles(1)
Effect

Operand
Address

Opcode
on CCR

Mode
Source
Operation Description
Form
V H I N Z C

Nibble Swap
NSA A  (A[3:0]:A[7:4]) – – – – – – INH 62 1
Accumulator
ORA #opr8i IMM AA ii 2
ORA opr8a DIR BA dd 3
ORA opr16a EXT CA hh ll 4
ORA oprx16,X Inclusive OR IX2 DA ee ff 4
A  (A) | (M) 0 – – Þ Þ –
ORA oprx8,X Accumulator and Memory IX1 EA ff 3
ORA ,X IX FA 3
ORA oprx16,SP SP2 9EDA ee ff 5
ORA oprx8,SP SP1 9EEA ff 4
Push Accumulator onto
PSHA Push (A); SP (SP) – 0x0001 – – – – – – INH 87 2
Stack
Push H (Index Register
PSHH Push (H); SP (SP) – 0x0001 – – – – – – INH 8B 2
High) onto Stack
Push X (Index Register
PSHX Push (X); SP (SP) – 0x0001 – – – – – – INH 89 2
Low) onto Stack
Pull Accumulator from
PULA SP (SP + 0x0001); PullA – – – – – – INH 86 3
Stack
Pull H (Index Register
PULH SP (SP + 0x0001); PullH – – – – – – INH 8A 3
High) from Stack
Pull X (Index Register
PULX SP (SP + 0x0001); PullX – – – – – – INH 88 3
Low) from Stack
ROL opr8a DIR 39 dd 5
ROLA INH 49 1
ROLX C INH 59 1
Rotate Left through Carry Þ – – Þ Þ Þ
ROL oprx8,X b7
IX1 69 ff 5
b0
ROL ,X IX 79 4
ROL oprx8,SP SP1 9E69 ff 6
ROR opr8a DIR 36 dd 5
RORA INH 46 1
RORX Rotate Right through C INH 56 1
Þ – – Þ Þ Þ
ROR oprx8,X Carry b7 b0
IX1 66 ff 5
ROR ,X IX 76 4
ROR oprx8,SP SP1 9E66 ff 6
SP  0xFF
RSP Reset Stack Pointer – – – – – – INH 9C 1
(High Byte Not Affected)
SP  (SP) + 0x0001; Pull (CCR)
SP  (SP) + 0x0001; Pull (A)
RTI Return from Interrupt SP  (SP) + 0x0001; Pull (X) Þ Þ Þ Þ Þ Þ INH 80 9
SP  (SP) + 0x0001; Pull (PCH)
SP  (SP) + 0x0001; Pull (PCL)
SP  SP + 0x0001PullPCH)
RTS Return from Subroutine – – – – – – INH 81 6
SP  SP + 0x0001; Pull (PCL)
SBC #opr8i IMM A2 ii 2
SBC opr8a DIR B2 dd 3
SBC opr16a EXT C2 hh ll 4
SBC oprx16,X IX2 D2 ee ff 4
Subtract with Carry A  (A) – (M) – (C) Þ – – Þ Þ Þ
SBC oprx8,X IX1 E2 ff 3
SBC ,X IX F2 3
SBC oprx16,SP SP2 9ED2 ee ff 5
SBC oprx8,SP SP1 9EE2 ff 4
SEC Set Carry Bit C1 – – – – – 1 INH 99 1
SEI Set Interrupt Mask Bit I1 – – 1 – – – INH 9B 1

FXTH870xD

Sensors
64 Freescale Semiconductor, Inc.
Table 44. HCS08 Instruction Set Summary (Sheet 7 of 8)

Bus Cycles(1)
Effect

Operand
Address

Opcode
on CCR

Mode
Source
Operation Description
Form
V H I N Z C

STA opr8a DIR B7 dd 3

STA opr16a EXT C7 hh ll 4
STA oprx16,X IX2 D7 ee ff 4
Store Accumulator in
STA oprx8,X M (A) 0 – – Þ Þ – IX1 E7 ff 3
Memory
STA ,X IX F7 2
STA oprx16,SP SP2 9ED7 ee ff 5
STA oprx8,SP SP1 9EE7 ff 4
STHX opr8a DIR 35 dd 4
STHX opr16a Store H:X (Index Reg.) (M:M + 0x0001)  (H:X) 0 – – Þ Þ – EXT 96 hh ll 5
STHX oprx8,SP SP1 9EFF ff 5
Enable Interrupts:
Stop Processing
STOP I bit  0; Stop Processing – – 0 – – – INH 8E 2+
Refer to MCU Documen-
tation
STX opr8a DIR BF dd 3
STX opr16a EXT CF hh ll 4
STX oprx16,X Store X (Low 8 Bits of IX2 DF ee ff 4
STX oprx8,X Index Register) M (X) 0 – – Þ Þ – IX1 EF ff 3
STX ,X in Memory IX FF 2
STX oprx16,SP SP2 9EDF ee ff 5
STX oprx8,SP SP1 9EEF ff 4
SUB #opr8i IMM A0 ii 2
SUB opr8a DIR B0 dd 3
SUB opr16a EXT C0 hh ll 4
SUB oprx16,X IX2 D0 ee ff 4
Subtract A  (A) – (M) Þ – – Þ Þ Þ
SUB oprx8,X IX1 E0 ff 3
SUB ,X IX F0 3
SUB oprx16,SP SP2 9ED0 ee ff 5
SUB oprx8,SP SP1 9EE0 ff 4
PC  (PC) + 0x0001
Push (PCL); SP  (SP) – 0x0001
Push (PCH); SP  (SP) – 0x0001
Push (X); SP  (SP) – 0x0001
SWI Software Interrupt Push (A); SP  (SP) – 0x0001 – – 1 – – – INH 83 11
Push (CCR); SP  (SP) – 0x0001
I  1;
PCH  Interrupt Vector High Byte
PCL  Interrupt Vector Low Byte
Transfer Accumulator to
TAP CCR  (A) Þ Þ Þ Þ Þ Þ INH 84 1
CCR
Transfer Accumulator to
TAX X  (A) – – – – – – INH 97 1
X (Index Register Low)
Transfer CCR to Accu-
TPA A  (CCR) – – – – – – INH 85 1
mulator
TST opr8a (M) – 0x00 DIR 3D dd 4
TSTA (A) – 0x00 INH 4D 1
TSTX (X) – 0x00 INH 5D 1
Test for Negative or Zero 0 – – Þ Þ –
TST oprx8,X (M) – 0x00 IX1 6D ff 4
TST ,X (M) – 0x00 IX 7D 3
TST oprx8,SP (M) – 0x00 SP1 9E6D ff 5
Transfer SP to Index
TSX H:X  (SP) + 0x0001 – – – – – – INH 95 2
Reg.
Transfer X (Index Reg.
TXA A  (X) – – – – – – INH 9F 1
Low) to Accumulator
Transfer Index Reg. to
TXS SP  (H:X) – 0x0001 – – – – – – INH 94 2
SP

FXTH870xD

Sensors
Freescale Semiconductor, Inc. 65
 Table 44. HCS08 Instruction Set Summary (Sheet 8 of 8)

Bus Cycles(1)
Effect

Operand
Address

Opcode
on CCR

Mode
Source
Operation Description
Form
V H I N Z C

Enable Interrupts; Wait

WAIT I bit  0; Halt CPU – – 0 – – – INH 8F 2+
for Interrupt
1. Bus clock frequency is one-half of the CPU clock frequency.

Table 45. Opcode Map (Sheet 1 of 2)

Bit-Manipulation Branch Read-Modify-Write Control Register/Memory
00 5 10 5 20 3 30 5 40 1 50 1 60 5 70 4 80 9 90 3 A0 2 B0 3 C0 4 D0 4 E0 3 F0 3
BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG RTI BGE SUB SUB SUB SUB SUB SUB
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

01 5 11 5 21 3 31 5 41 4 51 4 61 5 71 5 81 6 91 3 A1 2 B1 3 C1 4 D1 4 E1 3 F1 3
BRCLR0 BCLR0 BRN CBEQ CBEQA CBEQX CBEQ CBEQ RTS BLT CMP CMP CMP CMP CMP CMP
3 DIR 2 DIR 2 REL 3 DIR 3 IMM 3 IMM 3 IX1+ 2 IX+ 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

02 5 12 5 22 3 32 5 42 5 52 6 62 1 72 1 82 5+ 92 3 A2 2 B2 3 C2 4 D2 4 E2 3 F2 3
BRSET1 BSET1 BHI LDHX MUL DIV NSA DAA BGND BGT SBC SBC SBC SBC SBC SBC
3 DIR 2 DIR 2 REL 3 1 INH 1 INH 1 INH 1 INH 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
EXT

03 5 13 5 23 3 33 5 43 1 53 1 63 5 73 4 83 11 93 3 A3 2 B3 3 C3 4 D3 4 E3 3 F3 3
BRCLR1 BCLR1 BLS COM COMA COMX COM COM SWI BLE CPX CPX CPX CPX CPX CPX
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

04 5 14 5 24 3 34 5 44 1 54 1 64 5 74 4 84 1 94 2 A4 2 B4 3 C4 4 D4 4 E4 3 F4 3
BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR TAP TXS AND AND AND AND AND AND
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

05 5 15 5 25 3 35 4 45 3 55 4 65 3 75 5 85 1 95 2 A5 2 B5 3 C5 4 D5 4 E5 3 F5 3
BRCLR2 BCLR2 BCS STHX LDHX LDHX CPHX CPHX TPA TSX BIT BIT BIT BIT BIT BIT
3 DIR 2 DIR 2 REL 2 DIR 3 IMM 2 DIR 3 IMM 2 DIR 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

06 5 16 5 26 3 36 5 46 1 56 1 66 5 76 4 86 3 96 5 A6 2 B6 3 C6 4 D6 4 E6 3 F6 3
BRSET3 BSET3 BNE ROR RORA RORX ROR ROR PULA STHX LDA LDA LDA LDA LDA LDA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 3 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
EXT

07 5 17 5 27 3 37 5 47 1 57 1 67 5 77 4 87 2 97 1 A7 2 B7 3 C7 4 D7 4 E7 3 F7 2
BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR PSHA TAX AIS STA STA STA STA STA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

08 5 18 5 28 3 38 5 48 1 58 1 68 5 78 4 88 3 98 1 A8 2 B8 3 C8 4 D8 4 E8 3 F8 3
BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL PULX CLC EOR EOR EOR EOR EOR EOR
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

09 5 19 5 29 3 39 5 49 1 59 1 69 5 79 4 89 2 99 1 A9 2 B9 3 C9 4 D9 4 E9 3 F9 3
BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL PSHX SEC ADC ADC ADC ADC ADC ADC
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

0A 5 1A 5 2A 3 3A 5 4A 1 5A 1 6A 5 7A 4 8A 3 9A 1 AA 2 BA 3 CA 4 DA 4 EA 3 FA 3
BRSET5 BSET5 BPL DEC DECA DECX DEC DEC PULH CLI ORA ORA ORA ORA ORA ORA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

0B 5 1B 5 2B 3 3B 7 4B 4 5B 4 6B 7 7B 6 8B 2 9B 1 AB 2 BB 3 CB 4 DB 4 EB 3 FB 3
BRCLR5 BCLR5 BMI DBNZ DBNZA DBNZX DBNZ DBNZ PSHH SEI ADD ADD ADD ADD ADD ADD
3 DIR 2 DIR 2 REL 3 DIR 2 INH 2 INH 3 IX1 2 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

0C 5 1C 5 2C 3 3C 5 4C 1 5C 1 6C 5 7C 4 8C 1 9C 1 BC 3 CC 4 DC 4 EC 3 FC 3
BRSET6 BSET6 BMC INC INCA INCX INC INC CLRH RSP JMP JMP JMP JMP JMP
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

0D 5 1D 5 2D 3 3D 4 4D 1 5D 1 6D 4 7D 3 9D 1 AD 5 BD 5 CD 6 DD 6 ED 5 FD 5
BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST NOP BSR JSR JSR JSR JSR JSR
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

0E 5 1E 5 2E 3 3E 6 4E 5 5E 5 6E 4 7E 5 8E 2+ 9E AE 2 BE 3 CE 4 DE 4 EE 3 FE 3
BRSET7 BSET7 BIL CPHX MOV MOV MOV MOV STOP Page 2 LDX LDX LDX LDX LDX LDX
3 DIR 2 DIR 2 REL 3 3 DD 2 DIX+ 3 IMD 2 IX+D 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
EXT

0F 5 1F 5 2F 3 3F 5 4F 1 5F 1 6F 5 7F 4 8F 2+ 9F 1 AF 2 BF 3 CF 4 DF 4 EF 3 FF 2
BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR WAIT TXA AIX STX STX STX STX STX
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset

IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment
DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with
IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment

Opcode in Hexadecimal F0 3 HCS08 Cycles

SUB Instruction Mnemonic
Number of Bytes 1 IX Addressing Mode

FXTH870xD

Sensors
66 Freescale Semiconductor, Inc.
Table 45. Opcode Map (Sheet 2 of 2)
Bit-Manipulation Branch Read-Modify-Write Control Register/Memory
9E60 6 9ED0 5 9EE0 4
NEG SUB SUB
3 SP1 4 SP2 3 SP1

9E61 6 9ED1 5 9EE1 4

CBEQ CMP CMP
4 SP1 4 SP2 3 SP1

9ED2 5 9EE2 4
SBC SBC
4 SP2 3 SP1

9E63 6 9ED3 5 9EE3 4 9EF3 6

COM CPX CPX CPHX
3 SP1 4 SP2 3 SP1 3 SP1

9E64 6 9ED4 5 9EE4 4

LSR AND AND
3 SP1 4 SP2 3 SP1

9ED5 5 9EE5 4
BIT BIT
4 SP2 3 SP1

9E66 6 9ED6 5 9EE6 4

ROR LDA LDA
3 SP1 4 SP2 3 SP1

9E67 6 9ED7 5 9EE7 4

ASR STA STA
3 SP1 4 SP2 3 SP1

9E68 6 9ED8 5 9EE8 4

LSL EOR EOR
3 SP1 4 SP2 3 SP1

9E69 6 9ED9 5 9EE9 4

ROL ADC ADC
3 SP1 4 SP2 3 SP1

9E6A 6 9EDA 5 9EEA 4

DEC ORA ORA
3 SP1 4 SP2 3 SP1

9E6B 8 9EDB 5 9EEB 4

DBNZ ADD ADD
4 SP1 4 SP2 3 SP1

9E6C 6
INC
3 SP1

9E6D 5
TST
3 SP1

9EAE 5 9EBE 6 9ECE 5 9EDE 5 9EEE 4 9EFE 5

LDHX LDHX LDHX LDX LDX LDHX
2 IX 4 IX2 3 IX1 4 SP2 3 SP1 3 SP1

9E6F 6 9EDF 5 9EEF 4 9EFF 5

CLR STX STX STHX
3 SP1 4 SP2 3 SP1 3 SP1

INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset

IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment
DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with
IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment

Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E)

Prebyte (9E) and 9E60 6 HCS08 Cycles

Opcode in NEG Instruction Mnemonic
Hexadecimal 3 SP1 Addressing Mode
Number of Bytes

FXTH870xD

Sensors
Freescale Semiconductor, Inc. 67
9 Timer Pulse-Width Module
The timer pulse-width module (TPM1) is a two channel timer system that supports traditional input capture, output compare, or
edge-aligned PWM on each channel. All the features and functions of the TPM1 are as described in the MC9S08RC16 product
specification. The user has the option to connect the two timer channels to the PTA2:3 pins, if those pins are not needed for an
LFR channel or other general purpose I/O function. The following clock source and frequency selections are available using the
system option register 2 as shown in Figure 23 and Table 27.
In addition one channel of the TPM1 can be connected to a 500 kHz clock (DX) derived from the crystal oscillator on the RFM.
This selection is made by setting the TPM1 to use an external clock. This clock source allows time calibration of the LFO as
described in the Section 14.

9.1 Features
The TPM1 has the following features:
• May be configured for buffered, center-aligned pulse-width modulation (CPWM) on all channels
• Clock sources independently selectable
• Selectable clock sources (device dependent): bus clock, fixed system clock
• Clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128
• 16-bit free-running or up/down (CPWM) count operation
• 16-bit modulus register to control counter range
• Timer system enable
• One interrupt per channel plus a terminal count interrupt
• Channel features:
— Each channel may be input capture, output compare, or buffered edge-aligned PWM
— Rising-edge, falling-edge, or any-edge input capture trigger
— Set, clear, or toggle output compare action
— Selectable polarity on PWM outputs

9.2 TPM1 Configuration Information

The device provides one two-channel timer/pulse-width modulator (TPM1).
An easy way to measure the low frequency oscillator (LFO) is to connect the LFO directly to TPM1 channel 0. The LFOSEL bit
in the SOPTZ determines whether TPM1CH0 is connected to PTAZ or the LFO.
TPM1 clock source selection for the TPM1 is shown in the table below.

Table 46. TPM1 Clock Source Selection

CLKSB CLKSA Clock Source

0 0 No source; TPM1 disabled
0 1 BUSCLK
1 0 unused
1 1 Internal DX pin

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9.2.1 Block Diagram
Figure 42 shows the structure of a TPM1.

BUSCLK CLOCK SOURCE PRESCALE AND SELECT

SELECT DIVIDE BY
SYNC OFF, BUS, XCLK, EXT 1, 2, 4, 8, 16, 32, 64, or 128
DX

CLKSB CLKSA PS2 PS1 PS0

CPWMS

MAIN 16-BIT COUNTER TOF

COUNTER RESET INTERRUPT
TOIE LOGIC
16-BIT COMPARATOR
TPMMODH:TPMMO

ELS0B ELS0A
CHANNEL 0
PORT TPMCH0
16-BIT COMPARATOR LOGIC
TPMC0VH:TPMC0VL CH0F
16-BIT LATCH INTERRUPT
LOGIC
MS0B MS0A CH0IE
INTERNAL BUS

CHANNEL 1 ELS1B ELS1A

PORT TPMCH1
16-BIT COMPARATOR LOGIC

TPMC1VH:TPMC1VL CH1F

16-BIT LATCH INTERRUPT

LOGIC
MS1B MS1A CH1IE

Figure 42. TPM1 Block Diagram

The central component of the TPM1 is the 16-bit counter that can operate as a free-running counter, a modulo counter, or an up-
/down-counter when the TPM1 is configured for center-aligned PWM. The TPM1 counter (when operating in normal up-counting
mode) provides the timing reference for the input capture, output compare, and edge-aligned PWM functions. The timer counter
modulo registers, TPMMODH:TPMMODL, control the modulo value of the counter. (The values 0x0000 or 0xFFFF effectively
make the counter free running.) Software can read the counter value at any time without affecting the counting sequence. Any
write to either byte of the TPMCNT counter resets the counter regardless of the data value written.
All TPM1 channels are programmable independently as input capture, output compare, or buffered edge-aligned PWM channels.

9.3 External Signal Description

When any pin associated with the timer is configured as a timer input, a passive pullup can be enabled. After reset, the TPM1
modules are disabled and all pins default to general-purpose inputs with the passive pullups disabled.
Each TPM1 channel is associated with an I/O pin on the MCU. The function of this pin depends on the configuration of the
channel. In some cases, no pin function is needed so the pin reverts to being controlled by general-purpose I/O controls. When
a timer has control of a port pin, the port data and data direction registers do not affect the related pin(s). See the Section 2 for
additional information about shared pin functions.

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9.4 Register Definition
The TPM1 includes:
• An 8-bit status and control register (TPMSC)
• A 16-bit counter (TPMCNTH:TPMCNTL)
• A 16-bit modulo register (TPMMODH:TPMMODL)
Each timer channel has:
• An 8-bit status and control register (TPMCnSC)
• A 16-bit channel value register (TPMCnVH:TPMCnVL)

9.4.1 Timer Status and Control Register (TPM1SC)

TPM1SC contains the overflow status flag and control bits that are used to configure the interrupt enable, TPM1 configuration,
clock source, and prescale divisor. These controls relate to all channels within this timer module.

$0010 7 6 5 4 3 2 1 0
R TOF
TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
W
Reset 0 0 0 0 0 0 0 0
= Reserved

Figure 43. Timer Status and Control Register (TPM1SC)

Table 47. TPM1SC Register Field Descriptions

Field Description
Timer Overflow Flag — This flag is set when the TPM1 counter changes to 0x0000 after reaching the modulo value
programmed in the TPM1 counter modulo registers. When the TPM1 is configured for CPWM, TOF is set after the counter has
reached the value in the modulo register, at the transition to the next lower count value. Clear TOF by reading the TPM1 status
7 and control register when TOF is set and then writing a 0 to TOF. If another TPM1 overflow occurs before the clearing sequence
TOF is complete, the sequence is reset so TOF would remain set after the clear sequence was completed for the earlier TOF. Reset
clears TOF. Writing a 1 to TOF has no effect.
0 TPM1 counter has not reached modulo value or overflow
1 TPM1 counter has overflowed
Timer Overflow Interrupt Enable — This read/write bit enables TPM1 overflow interrupts. If TOIE is set, an interrupt is
6 generated when TOF equals 1. Reset clears TOIE.
TOIE 0 TOF interrupts inhibited (use software polling)
1 TOF interrupts enabled
Center-Aligned PWM Select — This read/write bit selects CPWM operating mode. Reset clears this bit so the TPM1 operates
in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting CPWMS reconfigures the
5 TPM1 to operate in up-/down-counting mode for CPWM functions. Reset clears CPWMS.
CPWMS 0 All TPM channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the MSnB:MSnA
control bits in each channel’s status and control register
1 All TPM channels operate in center-aligned PWM mode
Clock Source Select — As shown in Table 46, this 2-bit field is used to disable the TPM1 system or select one of three clock
4:3
sources to drive the counter prescaler. The internal DX source is synchronized to the bus clock by an on-chip synchronization
CLKS[B:A]
circuit.
Prescale Divisor Select — This 3-bit field selects one of eight divisors for the TPM1 clock input as shown in Table 48. This
2:0
prescaler is located after any clock source synchronization or clock source selection, so it affects whatever clock source is
PS[2:0]
selected to drive the TPM1 system.

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 Table 48. Prescale Divisor Selection

PS2:PS1:PS0 TPM1 Clock Source Divided-By

0:0:0 1
0:0:1 2
0:1:0 4
0:1:1 8
1:0:0 16
1:0:1 32
1:1:0 64
1:1:1 128

9.4.2 Timer Counter Registers (TPM1CNTH:TPM1CNTL)

The two read-only TPM1 counter registers contain the high and low bytes of the value in the TPM1 counter. Reading either byte
(TPM1CNTH or TPM1CNTL) latches the contents of both bytes into a buffer where they remain latched until the other byte is
read. This allows coherent 16-bit reads in either order. The coherency mechanism is automatically restarted by an MCU reset, a
write of any value to TPM1CNTH or TPM1CNTL, or any write to the timer status/control register (TPM1SC).
Reset clears the TPM1 counter registers.

$0011 7 6 5 4 3 2 1 0
R Bit 15 14 13 12 11 10 9 Bit 8
W Any write to TPMCNTH clears the 16-bit counter.
Reset 0 0 0 0 0 0 0 0

Figure 44. Timer Counter Register High (TPM1CNTH)

$0012 7 6 5 4 3 2 1 0
R Bit 7 6 5 4 3 2 1 Bit 0
W Any write to TPMCNTL clears the 16-bit counter.
Reset 0 0 0 0 0 0 0 0

Figure 45. Timer Counter Register Low (TPM1CNTL)

When BACKGROUND mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches
remain in the state they were in when the BACKGROUND mode became active even if one or both bytes of the counter are read
while BACKGROUND mode is active.

9.4.3 Timer Counter Modulo Registers (TPM1MODH:TPM1MODL)

The read/write TPM1 modulo registers contain the modulo value for the TPM1 counter. After the TPM1 counter reaches the
modulo value, the TPM1 counter resumes counting from 0x0000 at the next clock (CPWMS = 0) or starts counting down
(CPWMS = 1), and the overflow flag (TOF) becomes set. Writing to TPM1MODH or TPM1MODL inhibits TOF and overflow
interrupts until the other byte is written. Reset sets the TPM1 counter modulo registers to 0x0000, which results in a free-running
timer counter (modulo disabled).

$0013 7 6 5 4 3 2 1 0
R
Bit 15 14 13 12 11 10 9 Bit 8
W
Reset 0 0 0 0 0 0 0 0

Figure 46. Timer Counter Modulo Register High (TPM1MODH)

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 $0014 7 6 5 4 3 2 1 0
R
Bit 7 6 5 4 3 2 1 Bit 0
W
Reset 0 0 0 0 0 0 0 0

Figure 47. Timer Counter Modulo Register Low (TPM1MODL)

It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well before a new overflow.
An alternative approach is to reset the TPM1 counter before writing to the TPM1 modulo registers to avoid confusion about when
the first counter overflow will occur.

9.4.4 Timer Channel 0 Status and Control Register (TPM1C0SC)

TPM1C0SC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel
configuration, and pin function.

$0015 7 6 5 4 3 2 1 0
R 0 0
CH0F CH0IE MS0B MS0A ELS0B ELS0A
W
Reset 0 0 0 0 0 0 0 0
= Reserved

Figure 48. Timer Channel 0 Status and Control Register (TPM1C0SC)

Table 49. TPM1C0SC Register Field Descriptions

Field Description
Channel 0 Flag — When channel n is configured for input capture, this flag bit is set when an active edge occurs on the channel
n pin. When channel 0 is an output compare or edge-aligned PWM channel, CH0F is set when the value in the TPM1 counter
registers matches the value in the TPM1 channel 0 value registers. This flag is seldom used with center-aligned PWMs because
it is set every time the counter matches the channel value register, which correspond to both edges of the active duty cycle
period.
7 A corresponding interrupt is requested when CH0F is set and interrupts are enabled (CH0IE = 1). Clear CH0F by reading
CH0F TPM1C0SC while CH0F is set and then writing a 0 to CH0F. If another interrupt request occurs before the clearing sequence
is complete, the sequence is reset so CH0F would remain set after the clear sequence was completed for the earlier CH0F.
This is done so a CH0F interrupt request cannot be lost by clearing a previous CH0F. Reset clears CH0F. Writing a 1 to CH0F
has no effect.
0 No input capture or output compare event occurred on channel 0
1 Input capture or output compare event occurred on channel 0
Channel 0 Interrupt Enable — This read/write bit enables interrupts from channel 0. Reset clears CH0IE.
6
0 Channel 0 interrupt requests disabled (use software polling)
CH0IE
1 Channel 0 interrupt requests enabled
5 Mode Select B for TPM1 Channel 0 — When CPWMS = 0, MS0B = 1 configures TPM1 channel 0 for edge-aligned PWM
MS0B mode. For a summary of channel mode and setup controls, refer to Table 50.
4 Mode Select A for TPM1 Channel 0 — When CPWMS = 0 and MS0B = 0, MS0A configures TPM1 channel 0 for input capture
MS0A mode or output compare mode. Refer to Table 50 for a summary of channel mode and setup controls.
Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by CPWMS:MS0B:MSnA and shown
in Table 50, these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven
3:2
in response to an output compare match, or select the polarity of the PWM output.
ELS0[B:A]
Setting ELS0B:ELS0A to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer channel
functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a
general-purpose I/O pin when the associated timer channel is set up as a software timer that does not require the use of a pin.

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Table 50. Mode, Edge, and Level Selection

CPWMS MS0B:MS0A ELS0B:ELS0A Mode Configuration

Pin not used for TPM1 channel; use as an external clock for the TPM1 or revert
X XX 00
to general-purpose I/O
01 Capture on rising edge only
00 10 Input capture Capture on falling edge only
11 Capture on rising or falling edge
00 Software compare only
0 01 Toggle output on compare
01 Output compare
10 Clear output on compare
11 Set output on compare
10 Edge-aligned High-true pulses (clear output on compare)
1X
X1 PWM Low-true pulses (set output on compare)
10 Center-aligned High-true pulses (clear output on compare-up)
1 XX
X1 PWM Low-true pulses (set output on compare-up)

If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to
get an unexpected indication of an edge trigger. Typically, a program would clear status flags after changing channel configuration
bits and before enabling channel interrupts or using the status flags to avoid any unexpected behavior.

9.4.5 Timer Channel Value Registers (TPM1C0VH:TPM1C0VL)

These read/write registers contain the captured TPM1 counter value of the input capture function or the output compare value
for the output compare or PWM functions. The channel value registers are cleared by reset.

$0016 7 6 5 4 3 2 1 0
R
Bit 15 14 13 12 11 10 9 Bit 8
W
Reset 0 0 0 0 0 0 0 0

Figure 49. Timer Channel 0 Value Register High (TPM1C0VH)

$0017 7 6 5 4 3 2 1 0
R
Bit 7 6 5 4 3 2 1 Bit 0
W
Reset 0 0 0 0 0 0 0 0

Figure 50. Timer Channel 0 Value Register Low (TPM1C0VL)

In input capture mode, reading either byte (TPM1C0VH or TPM1C0VL) latches the contents of both bytes into a buffer where
they remain latched until the other byte is read. This latching mechanism also resets (becomes unlatched) when the TPM1C0SC
register is written.
In output compare or PWM modes, writing to either byte (TPM1C0VH or TPM1C0VL) latches the value into a buffer. When both
bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching
mechanism may be manually reset by writing to the TPM1C0SC register.
This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations.

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9.4.6 Timer Channel 1 Status and Control Register (TPM1C1SC)
TPM1C1SC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel
configuration, and pin function.

$0018 7 6 5 4 3 2 1 0
R 0 0
CH1F CH1IE MS1B MS1A ELS1B ELS1A
W
Reset 0 0 0 0 0 0 0 0
= Reserved

Figure 51. Timer Channel 1 Status and Control Register (TPM1C1SC)

Table 51. TPM1C1SC Register Field Descriptions

Field Description
Channel 1 Flag — When channel n is configured for input capture, this flag bit is set when an active edge occurs on the channel
n pin. When channel 1 is an output compare or edge-aligned PWM channel, CH1F is set when the value in the TPM1 counter
registers matches the value in the TPM1 channel 1 value registers. This flag is seldom used with center-aligned PWMs because
it is set every time the counter matches the channel value register, which correspond to both edges of the active duty cycle
period.
7 A corresponding interrupt is requested when CH1F is set and interrupts are enabled (CH1IE = 1). Clear CH1F by reading
CH1F TPM1C1SC while CH1F is set and then writing a 0 to CH1F. If another interrupt request occurs before the clearing sequence
is complete, the sequence is reset so CH1F would remain set after the clear sequence was completed for the earlier CH1F.
This is done so a CH1F interrupt request cannot be lost by clearing a previous CH1F. Reset clears CH1F. Writing a 1 to CH1F
has no effect.
0 No input capture or output compare event occurred on channel 1
1 Input capture or output compare event occurred on channel 1
Channel 1 Interrupt Enable — This read/write bit enables interrupts from channel 1. Reset clears CH1IE.
6
0 Channel 1 interrupt requests disabled (use software polling)
CH1IE
1 Channel 1 interrupt requests enabled
5 Mode Select B for TPM1 Channel 1 — When CPWMS = 0, MS1B = 1 configures TPM1 channel 1 for edge-aligned PWM
MS1B mode. For a summary of channel mode and setup controls, refer to Table 50.
4 Mode Select A for TPM1 Channel 1 — When CPWMS = 0 and MS1B = 0, MS1A configures TPM1 channel 1 for input capture
MS1A mode or output compare mode. Refer to Table 50 for a summary of channel mode and setup controls.
Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by CPWMS:MS1B:MS1A and shown
in Table 50, these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven
3:2 in response to an output compare match, or select the polarity of the PWM output.
ELS1[B:A] Setting ELS1B:ELS1A to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer channel
functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a
general-purpose I/O pin when the associated timer channel is set up as a software timer that does not require the use of a pin.

Table 52. Mode, Edge, and Level Selection

CPWMS MS1B:MS1A ELS1B:ELS1A Mode Configuration

Pin not used for TPM1 channel; use as an external clock for the TPM1 or revert
X XX 00
to general-purpose I/O
01 Capture on rising edge only
00 10 Input capture Capture on falling edge only
11 Capture on rising or falling edge
00 Software compare only
0 01 Toggle output on compare
01 Output compare
10 Clear output on compare
11 Set output on compare
10 Edge-aligned High-true pulses (clear output on compare)
1X
X1 PWM Low-true pulses (set output on compare)

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Table 52. Mode, Edge, and Level Selection (continued)

CPWMS MS1B:MS1A ELS1B:ELS1A Mode Configuration

10 Center-aligned High-true pulses (clear output on compare-up)
1 XX
X1 PWM Low-true pulses (set output on compare-up)

If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to
get an unexpected indication of an edge trigger. Typically, a program would clear status flags after changing channel configuration
bits and before enabling channel interrupts or using the status flags to avoid any unexpected behavior.

9.4.7 Timer Channel Value Registers (TPM1C1VH:TPM1C1VL)

These read/write registers contain the captured TPM1 counter value of the input capture function or the output compare value
for the output compare or PWM functions. The channel value registers are cleared by reset.

$0019 7 6 5 4 3 2 1 0
R
Bit 15 14 13 12 11 10 9 Bit 8
W
Reset 0 0 0 0 0 0 0 0

Figure 52. Timer Channel 1 Value Register High (TPM1C1VH)

$001A 7 6 5 4 3 2 1 0
R
Bit 7 6 5 4 3 2 1 Bit 0
W
Reset 0 0 0 0 0 0 0 0

Figure 53. Timer Channel 1 Value Register Low (TPM1C1VL)

In input capture mode, reading either byte (TPM1C1VH or TPM1C1VL) latches the contents of both bytes into a buffer where
they remain latched until the other byte is read. This latching mechanism also resets (becomes unlatched) when the TPM1C1SC
register is written.
In output compare or PWM modes, writing to either byte (TPM1C1VH or TPM1C1VL) latches the value into a buffer. When both
bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching
mechanism may be manually reset by writing to the TPM1C1SC register.
This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations.

9.5 Functional Description

All TPM1 functions are associated with a main 16-bit counter that allows flexible selection of the clock source and prescale divisor.
A 16-bit modulo register also is associated with the main 16-bit counter in the TPM1. Each TPM1 channel is optionally associated
with an MCU pin and a maskable interrupt function.
The TPM1 has center-aligned PWM capabilities controlled by the CPWMS control bit in TPM1SC. When CPWMS is set to 1,
timer counter TPM1CNT changes to an up-/down-counter and all channels in the associated TPM1 act as center-aligned PWM
channels. When CPWMS = 0, each channel can independently be configured to operate in input capture, output compare, or
buffered edge-aligned PWM mode.
The following sections describe the main 16-bit counter and each of the timer operating modes (input capture, output compare,
edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend on the operating
mode, these topics are covered in the associated mode sections.

9.5.1 Counter
All timer functions are based on the main 16-bit counter (TPM1CNTH:TPM1CNTL). This section discusses selection of the clock
source, up-counting vs. up-/down-counting, end-of-count overflow, and manual counter reset.
After any MCU reset, CLKSB:CLKSA = 0:0 so no clock source is selected and the TPM1 is inactive. Normally, CLKSB:CLKSA
would be set to 0:1 so the bus clock drives the timer counter. The clock source for the TPM1 can be selected to be off, the bus

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clock (BUSCLK), the fixed system clock (XCLK), or an external input. The maximum frequency allowed for the external clock
option is one-fourth the bus rate. Refer to Section 9.4.1 and Table 49 for more information about clock source selection.
When the microcontroller is in ACTIVE BACKGROUND mode, the TPM1 temporarily suspends all counting until the
microcontroller returns to normal user operating mode. During STOP mode, all TPM1 clocks are stopped; therefore, the TPM1
is effectively disabled until clocks resume. During WAIT mode, the TPM1 continues to operate normally.
The main 16-bit counter has two counting modes. When center-aligned PWM is selected (CPWMS = 1), the counter operates in
up-/down-counting mode. Otherwise, the counter operates as a simple up-counter. As an up-counter, the main 16-bit counter
counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value
in TPM1MODH:TPM1MODL.
When center-aligned PWM operation is specified, the counter counts upward from 0x0000 through its terminal count and then
counts downward to 0x0000 where it returns to up-counting. Both 0x0000 and the terminal count value (value in
TPM1MODH:TPM1MODL) are normal length counts (one timer clock period long).
An interrupt flag and enable are associated with the main 16-bit counter. The timer overflow flag (TOF) is a software-accessible
indication that the timer counter has overflowed. The enable signal selects between software polling (TOIE = 0) where no
hardware interrupt is generated, or interrupt-driven operation (TOIE = 1) where a static hardware interrupt is automatically
generated whenever the TOF flag is 1.
The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-counting mode, the main 16-
bit counter counts from 0x0000 through 0xFFFF and overflows to 0x0000 on the next counting clock. TOF becomes set at the
transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the
modulus register to 0x0000. When the main 16-bit counter is operating in up-/down-counting mode, the TOF flag gets set as the
counter changes direction at the transition from the value set in the modulus register and the next lower count value. This
corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.)
Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built into the timer counter for read operations.
Whenever either byte of the counter is read (TPM1CNTH or TPM1CNTL), both bytes are captured into a buffer so when the other
byte is read, the value will represent the other byte of the count at the time the first byte was read. The counter continues to count
normally, but no new value can be read from either byte until both bytes of the old count have been read.
The main timer counter can be reset manually at any time by writing any value to either byte of the timer count TPM1CNTH or
TPM1CNTL. Resetting the counter in this manner also resets the coherency mechanism in case only one byte of the counter was
read before resetting the count.

9.5.2 Channel Mode Selection

Provided CPWMS = 0 (center-aligned PWM operation is not specified), the MSnB and MSnA control bits in the channel n status
and control registers determine the basic mode of operation for the corresponding channel. Choices include input capture, output
compare, and buffered edge-aligned PWM.
Input Capture Mode
With the input capture function, the TPM1 can capture the time at which an external event occurs. When an active edge occurs
on the pin of an input capture channel, the TPM1 latches the contents of the TPM1 counter into the channel value registers
(TPM1CnVH:TPM1CnVL). Rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input
capture.
When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support coherent 16-bit accesses
regardless of order. The coherency sequence can be manually reset by writing to the channel status/control register
(TPM1CnSC).
An input capture event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request.
Output Compare Mode
With the output compare function, the TPM1 can generate timed pulses with programmable position, polarity, duration, and
frequency. When the counter reaches the value in the channel value registers of an output compare channel, the TPM1 can set,
clear, or toggle the channel pin.
In output compare mode, values are transferred to the corresponding timer channel value registers only after both 8-bit bytes of
a 16-bit register have been written. This coherency sequence can be manually reset by writing to the channel status/control
register (TPM1CnSC).
An output compare event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request.

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Edge-Aligned PWM Mode
This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS = 0) and can be used when other
channels in the same TPM1 are configured for input capture or output compare functions. The period of this PWM signal is
determined by the setting in the modulus register (TPM1MODH:TPM1MODL). The duty cycle is determined by the setting in the
timer channel value register (TPM1CnVH:TPM1CnVL). The polarity of this PWM signal is determined by the setting in the ELSnA
control bit. Duty cycle cases of 0 percent and 100 percent are possible.
As Figure 54 shows, the output compare value in the TPM1 channel registers determines the pulse width (duty cycle) of the PWM
signal. The time between the modulus overflow and the output compare is the pulse width. If ELSnA = 0, the counter overflow
forces the PWM signal high and the output compare forces the PWM signal low. If ELSnA = 1, the counter overflow forces the
PWM signal low and the output compare forces the PWM signal high.

OVERFLOW OVERFLOW OVERFLOW

PERIOD
PULSE
WIDTH

TPMCH

OUTPUT OUTPUT OUTPUT

COMPARE COMPARE COMPARE

Figure 54. PWM Period and Pulse Width (ELSnA = 0)

When the channel value register is set to 0x0000, the duty cycle is 0 percent. By setting the timer channel value register
(TPMCnVH:TPMCnVL) to a value greater than the modulus setting, 100% duty cycle can be achieved. This implies that the
modulus setting must be less than 0xFFFF to get 100% duty cycle.
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit
updates and to avoid unexpected PWM pulse widths. Writes to either register, TPM1CnVH or TPM1CnVL, write to buffer
registers. In edge-PWM mode, values are transferred to the corresponding timer channel registers only after both 8-bit bytes of
a 16-bit register have been written and the value in the 1TPMCNTH:TPM1CNTL counter is 0x0000. (The new duty cycle does
not take effect until the next full period.)

9.5.3 Center-Aligned PWM Mode

This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The output compare value in
TPM1CnVH:TPM1CnVL determines the pulse width (duty cycle) of the PWM signal and the period is determined by the value in
TPM1MODH:TPM1MODL. TPM1MODH:TPM1MODL should be kept in the range of 0x0001 to 0x7FFF because values outside
this range can produce ambiguous results. ELS0A will determine the polarity of the CPWM output.
pulse width =2 x (TPM1CnVH:TPM1CnVL)
period = 2 x (TPM1MODH:TPM1MODL);
for TPM1MODH:TPM1MODL = 0x0001–0x7FFF
If the channel value register TPM1CnVH:TPM1CnVL is zero or negative (bit 15 set), the duty cycle will be 0%. If
TPM1CnVH:TPM1CnVL is a positive value (bit 15 clear) and is greater than the (nonzero) modulus setting, the duty cycle will be
100% because the duty cycle compare will never occur. This implies the usable range of periods set by the modulus register is
0x0001 through 0x7FFE (0x7FFF if generation of 100% duty cycle is not necessary). This is not a significant limitation because
the resulting period is much longer than required for normal applications.
TPM1MODH:TPM1MODL = 0x0000 is a special case that should not be used with center-aligned PWM mode. When
CPWMS = 0, this case corresponds to the counter running free from 0x0000 through 0xFFFF, but when CPWMS = 1 the counter
needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to
down-counting.
Figure 55 shows the output compare value in the TPM1 channel registers (multiplied by 2), which determines the pulse width
(duty cycle) of the CPWM signal. If ELSnA = 0, the compare match while counting up forces the CPWM output signal low and a
compare match while counting down forces the output high. The counter counts up until it reaches the modulo setting in
TPM1MODH:TPM1MODL, then counts down until it reaches zero. This sets the period equal to two times
TPM1MODH:TPM1MODL.

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 TPMMODH:TPMMODL COUNT = 0
OUTPUT OUTPUT
COUNT = COMPARE COMPARE COUNT =
TPMMODH:TPMMODL (COUNT DOWN) (COUNT UP) TPMMODH:TPMMODL

TPM1CHn
PULSE WIDTH
2x
PERIOD 2x

Figure 55. CPWM Period and Pulse Width (ELSnA = 0)

Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin transitions are lined
up at the same system clock edge. This type of PWM is also required for some types of motor drives.
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit
updates and to avoid unexpected PWM pulse widths. Writes to any of the registers, TPM1MODH, TPM1MODL, TPM1CnVH, and
TPM1CnVL, actually write to buffer registers. Values are transferred to the corresponding timer channel registers only after both
8-bit bytes of a 16-bit register have been written and the timer counter overflows (reverses direction from up-counting to down-
counting at the end of the terminal count in the modulus register). This TPM1CNT overflow requirement only applies to PWM
channels, not output compares.
Optionally, when TPM1CNTH:TPM1CNTL = TPM1MODH:TPM1MODL, the TPM1 can generate a TOF interrupt at the end of
this count. The user can choose to reload any number of the PWM buffers, and they will all update simultaneously at the start of
a new period.
Writing to TPM1SC cancels any values written to TPM1MODH and/or TPM1MODL and resets the coherency mechanism for the
modulo registers. Writing to TPM1C0SC cancels any values written to the channel value registers and resets the coherency
mechanism for TPM1C0VH:TPM1C0VL.

9.6 TPM1 Interrupts

The TPM1 generates an optional interrupt for the main counter overflow and an interrupt for each channel. The meaning of
channel interrupts depends on the mode of operation for each channel. If the channel is configured for input capture, the interrupt
flag is set each time the selected input capture edge is recognized. If the channel is configured for output compare or PWM
modes, the interrupt flag is set each time the main timer counter matches the value in the 16-bit channel value register. See
Section 5 for absolute interrupt vector addresses, priority, and local interrupt mask control bits.
For each interrupt source in the TPM1, a flag bit is set on recognition of the interrupt condition such as timer overflow, channel
input capture, or output compare events. This flag may be read (polled) by software to verify that the action has occurred, or an
associated enable bit (TOIE or CHnIE) can be set to enable hardware interrupt generation. While the interrupt enable bit is set,
a static interrupt will be generated whenever the associated interrupt flag equals 1. It is the responsibility of user software to
perform a sequence of steps to clear the interrupt flag before returning from the interrupt service routine.

9.6.1 Clearing Timer Interrupt Flags

TPM1 interrupt flags are cleared by a two-step process that includes a read of the flag bit while it is set (1) followed by a write of
0 to the bit. If a new event is detected between these two steps, the sequence is reset and the interrupt flag remains set after the
second step to avoid the possibility of missing the new event.

9.6.2 Timer Overflow Interrupt Description

The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-counting mode, the 16-bit
timer counter counts from 0x0000 through 0xFFFF and overflows to 0x0000 on the next counting clock. TOF becomes set at the
transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the
modulus register to 0x0000. When the counter is operating in up-/down-counting mode, the TOF flag gets set as the counter
changes direction at the transition from the value set in the modulus register and the next lower count value. This corresponds
to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.)

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9.6.3 Channel Event Interrupt Description
The meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned
PWM, or center-aligned PWM).
When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising edges, falling edges, any
edge, or no edge (off) as the edge that triggers an input capture event. When the selected edge is detected, the interrupt flag is
set. The flag is cleared by the two-step sequence described in Section 9.6.1.
When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches
the 16-bit value in the channel value register. The flag is cleared by the two-step sequence described in Section 9.6.1.

9.6.4 PWM End-of-Duty-Cycle Events

For channels that are configured for PWM operation, there are two possibilities:
• When the channel is configured for edge-aligned PWM, the channel flag is set when the timer counter matches the channel
value register that marks the end of the active duty cycle period.
• When the channel is configured for center-aligned PWM, the timer count matches the channel value register twice during
each PWM cycle. In this CPWM case, the channel flag is set at the start and at the end of the active duty cycle, which are
the times when the timer counter matches the channel value register.
The flag is cleared by the two-step sequence described in Section 9.6.1.

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10 Other MCU Resources
It is not intended that physical parameter measurements be made during the time that LFR may be actively receiving/decoding
LF signals; or during the time that the RFM may be actively powered up and/or transmitting RF data. The resulting interactions
will degrade the accuracy of the measurements.
The FXTH870xD measures six physical parameters for use in the tire pressure monitoring application: pressure, temperature,
battery voltage, two external voltages and an optional X- and/or Z-axis acceleration. Each parameter is accessed in a different
manner and all use firmware subroutine calls as described in Section 14. These subroutines initialize some control bits within the
sensor measurement interface, SMI, and then place the MCU into the STOP4 mode until the measurement is completed with an
interrupt back to the MCU.
The accuracy, power consumption and timing specified for any measurement given in the electrical specifications in Section 17
are only guaranteed if the user obtains a reading using the specified firmware subroutine call in Section 14.
The FXTH870xD uses a 6-channel, 10-bit analog-to-digital converter (ADC10) module. The ADC10 module is an analog-to-digital
converter using a successive approximation register (SAR) architecture with sample and hold. Capture of pressure and
acceleration sensor readings is controlled by the sensor measurement interface (SMI) and capture of temperature and voltage
readings are controlled by the MCU.
When making measurements of the various analog voltages the individual blocks. will first be powered up long enough to stabilize
their outputs before a conversion is started. The ADC channels are connected in hardware. Conversions are started and ended
synchronously with the sampling of the voltages.
The accuracy, power consumption and timing specifications given in the electrical specifications in Section 17 are based on using
the assigned firmware subroutines in Section 14 to make these measurements and convert them into an 8-bit, 9-bit or 10-bit
transfer function. These measurement accuracy specifications cannot be guaranteed if the user creates custom software routines
to convert these measurements.

Table 53. ADC10 Channel Assignments

ADC10 Channel Input Select Firmware Call(s) Characteristic

Pressure Sensor TPMS_READ_COMP_PRESSURE PCODE
AD0 Optional X-axis Acceleration Sensor TPMS_READ_COMP_ACCEL_X AXCODE
Optional Z-axis Acceleration Sensor TPMS_READ_COMP_ACCEL_Z AZCODE
AD1 Temperature Sensor TPMS_READ_COMP_TEMP_8 TCODE
AD2 Bandgap Reference TPMS_READ_COMP_VOLTAGE VCODE
AD3 GPIO PTA0 TPMS_READ_V0 G0CODE
AD4 GPIO PTA1 TPMS_READ_V1 G1CODE
AD5 VREG Monitor TPMS_WIRE_CHECK

10.1 Pressure Measurement

The pressure measurement consists of an interface to a pressure sensing element. Control bits on the MCU operate the SMI to
power up the P-Cell and capture a voltage which is converted by the ADC10. The resulting pressure transfer equation for the
100-450 kPa range:

P = P P +  100 – P  Eqn. 1
450 CODE 450
The transfer equation of the 100-900 kPa range is:

P = P P +  100 – P  Eqn. 2
900 CODE 900
Due to calibration routines and parameters stored in the FXTH870xD, the pressure range is selected at production and cannot
be changed in the field.

NOTE
Lack of change of the pressure measurement over time may indicate the package pressure
port to be blocked or the internal section of the sensor to be contaminated. User application
should maintain either locally or at the system data receiver a record of pressure
measurements along with temperature and/or accelerometer measurements, and possibly
identify the pressure port as blocked or contaminated if no changes are recorded over time.

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10.2 Temperature Measurements
The temperature is measured from a VB sensor built into channel 1 of the ADC10 in the same manner as is done in the
FXTH870xD devices with the resulting transfer equation:

T = T  T – 55 Eqn. 3
CODE

10.3 Voltage Measurements

Voltage measurements can be made on the internal bandgap to estimate the supply voltage on VDD.

10.3.1 Internal Bandgap

An internal bandgap voltage reference is provided to take measurements of the supply voltage. The resulting transfer equation:

V = V V + 1.22 Eqn. 4
INT INT CODE
10.3.2 External Voltages
Measurements of an external voltage on either the PTA0 or PTA1 pins can be made and referenced to the internal bandgap
voltage. The resulting transfer equation:

V = V  Gx Eqn. 5
PTAx EXT CODE
where x = 0, 1 refers to PTA0 or PTA1.

10.4 Optional Acceleration Measurements

The acceleration measurement consists of an interface to an optional acceleration sensing element. Control bits on the MCU
operate the SMI to power up the g-Cell and capture a voltage which is converted by the ADC10. The data from the ADC10 is
then pre-processed by a dynamic range firmware routine that will return the two values necessary to calculate the acceleration,
Ay, (y = X-axis or Z-axis, depending on selection) in conjunction with values taken from the table in Section 17.10.1.
The first value from the firmware routine is the offset step identifier, STEP, with integer values 0 to 15 (i.e. the 16 offset steps).
The other value is the ADC10 data, AyCODE, with integer values 0 to 511. AyCODE values 1 through 510 are usable; values 0 and
511 indicate fault conditions. The X-axis acceleration is scaled for ~20g range within each of the 16 offset steps, ~10g per step.
The Z-axis acceleration is scaled for ~80g range within each of the 16 offset steps, ~80g or ~60g. The steps are at ~40g or ~30g
increments, allowing for adequate overlaps. Section 17.10.1 provides a table of acceleration values resulting from
characterizations.
Acceleration sensitivity, Ay-STEP, varies between each offset step, and should be calculated by dividing the range of g’s for each
offset step by the usable AyCODE range (i.e. 510):

A = A @A 510 – A @A 1   510 Eqn. 6

y-STEP y-STEP yCODE y-STEP yCODE
Once the sensitivity Ay-STEP has been calculated, the acceleration Ay can be calculated by the re-using the Ay-STEP @ AyCODE
1 value of the offset step and the returned AyCODE value with the following transfer function:

A = A A + A @A 1 – A  Eqn. 7
y y-STEP yCODE y-STEP yCODE y-STEP
The pressure, and optional X or Z-axis accelerometer also share the same signal path in the Transducer interface and all the
sensors share the same ADC. Therefore only one of the sensors can be accessed at a given moment.

10.5 Optional Battery Condition Check

The condition of the battery can be periodically checked to determine the battery’s internal impedance, RBATT, which is a function
of both temperature and the remaining battery capacity. This can be performed by user supplied software routine and an external
load resistor, RLOAD, connected from the PTA0 pin to VSS as shown in Figure 56 (any of the PTA[3:0] can be used for this
purpose).

NOTE
The included accelerometers are designed with a self-test feature. Consult sales/application
support for information regarding the recommended use of the accelerometer self-test
features.

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 VDD VDD
FXTH870xxx FXTH870xxx

IDD IDD + ILOAD

PTA0 RBATT RBATT
PTA0

RLOAD VBATT ILOAD VBATT

+ RLOAD
+
VSS VSS

Port Pin Driven Low Port Pin Driven High

V = V –I R V = V – I +I R
DD0 BATT DD0 BATT DD1 BATT DD1 LOAD BATT
 V
DD1 
V = V – I + ---------------------  R
DD1 BATT  DD1 R BATT
LOAD

Figure 56. Battery Check Circuit

The battery voltage can first be checked using the method given in Section 10.3 with the selected PTA0 pin set as an output and
driven low and then high to determine VDD where only IDD flows or when IDD plus ILOAD flows. The resulting battery impedance
can then be calculated as:
V –V
DD1 DD0
R = --------------------------------------------------------------- Eqn. 8
BATT V
DD1
I –I + ---------------------
DD0 DD1 R
LOAD

If it is assumed that IDD0 and IDD1 are not appreciably different at the small change in VDD, then the resulting battery impedance
can be approximated as:
V –V R  V –V 
DD1 DD0 LOAD DD1 DD0
R = --------------------------------------- = ------------------------------------------------------------------------- Eqn. 9
BATT V V
DD1 DD1
---------------------
R
LOAD

where:
VDD0 is the voltage determined with the external load resistor connected to VSS
VDD1 is the voltage determined with the external load resistor connected to VDD
RLOAD is the resistance of the external load resistance in ohms
RBATT is the implied battery impedance in ohms
It is recommended that this calculation be performed with a reasonable current load on the battery of approximately 3 mA (RLOAD
approximately 1000 ohms).

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10.6 Measurement Firmware
The firmware for making measurements is comprised of two function calls as described in Section 14. Each measurement is a
combination of a “read” that returns the raw ADC output data and a “comp” routine which compensates that raw reading based
on information contained in the Universal Uncompensated Measurement Array (UUMA) assigned in RAM memory.
The read routines fill specific locations in the UUMA with raw data; but the compensation routines depend what is already present
in the UUMA as shown in the data flow in Figure 57.
The user therefore has the option to decide how often each measurement (and its component terms) are made. The resulting
power consumption is then the sum of using these components are defined in the electrical specifications in Section 17.
A typical flow for a compensated pressure measurement would be:
1. Call the TPMS_READ_PRESSURE routine which yields a raw pressure value and fills the UUMA with this data.
2. Call the TPMS_READ_TEMPERATURE routine which yields a raw temperature value and fills the UUMA with this
data.
3. Call the TPMS_READ_VOLTAGE routine which yields a raw voltage value and fills the UUMA with this data.
4. Call the TPMS_COMP_PRESSURE routine which then takes the raw pressure, temperature and voltage values from
the UUMA and compensates to provide a true pressure reading to the accuracy as specified in Section 17.

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 Figure 57. Data Flow For Measurements

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10.7 Thermal Shutdown
When the package temperature becomes too low or too high the MCU can be placed into a STOP mode to suspend operation
and prevent transmission of RF signals which may be corrupted at the temperature extremes. Return to normal operation after
the temperature falls back within the recovery temperature range. The presence of either the low or high temperature shutdown
will disable the PWU from causing either a periodic wakeup or a periodic reset. The MCU, temperature sensor and ADC10 are
all functional over the full temperature range from TL to TH.

10.7.1 Low Temperature Shutdown

Low temperature shutdown is achieved using temperature readings taken by the ADC10 as described in Section 10.2 and
enabling the thermal restart circuit by setting the TRE bit and selecting the low temperature threshold by clearing the TRH bit.
When the software programmed low temperature is reached the MCU will turn off all operating functions and enter the STOP1
mode.

10.7.2 High Temperature Shutdown

The high temperature shutdown level is determined from a measurement of the temperature sensor by the ADC10 as described
in Section 10.2 and enabling the thermal restart circuit by setting the TRE bit and selecting the high temperature threshold by
setting the TRH bit. When the software programmed high temperature is reached the MCU will turn off all operating functions and
enter the STOP1 mode.

10.7.3 Temperature Shutdown Recovery

The MCU can be restarted by the Temperature Restart (TR) module when the temperature returns within the normal temperature
range, TRESET. When this occurs the MCU will be reset and begin execution from the reset vector located at $DFFE/$DFFF. The
TR module can be enabled using the TRE bit in the SIMOPT1 register. The TR module can be powered on and off by setting or
clearing the TRE bit located at bit 3 in the SIMOPT1 register at address $1802. The TRE bit is cleared by an MCU reset.
When the TRE bit is set the TR module can then be set to detect a recovery from either a high temperature or a low temperature
using the TRH in the SIMOPT1 register. The TRH bit is cleared by an MCU reset.
The TR module does not activate an MCU restart and reset unless it has first moved outside the re-arming temperature range,
TREARM, as shown in Figure 58. The status of the TR can be checked by reading the TRO bit located at bit 0 in the SIMTST
register at address $180F. The TRO bit is set high by an MCU reset. The state of the TRO bit is as follows:
1 = TR module is outside the TREARM temperature range and will restart the MCU if the TRE bit is set and
temperature falls back within the TRESET temperature range.
0 = TR module is within the TRESET temperature range and the MCU cannot be armed to restart when
temperature falls back to the TRESET range. The TRE bit cannot be set.

TRH = 0 TRH = 1
TRO TREARML TRESETL TRESETH TREARMH

TREARM
TRESET
TRO = 1

SHUTDOWN ACTIVE SHUTDOWN

TRO = 0 TEMPERATURE

Figure 58. Temperature Restart Response

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This sequence is further explained by the user software flowchart in Figure 59.

Figure 59. Flowchart for Using TR Module

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11 Periodic Wakeup Timer
The periodic wakeup timer (PWU) generates a periodic interrupt to wakeup the MCU from any of the STOP modes. It also has
an optional periodic reset to restart the MCU. It is driven by the LFO oscillator in the RTI module which generates a clock at a
nominal one millisecond interval. The LFO and the wakeup timer are always active and cannot be powered off by any software
control. The control bits are set so that there is either a periodic wakeup, a periodic reset, or both a wakeup interrupt and a
periodic reset. No combination of control bits will disable both the wakeup interrupt and the periodic reset. In addition, there is no
hardware control that can mask a wakeup interrupt once it is generated by the PWU.

11.1 Block Diagram

The block diagram of the wakeup timer is shown in Figure 60. This consists of a programmable prescaler with 64 steps that can
be used to adjust for variations in the value of the LFO period. Finally there are two cascaded programmable 6-bit dividers to set
wakeup and/or reset time intervals.

WCLK 6-BIT RCLK 6-BIT

LFO PROGRAMMBLE WAKEUP PERIODIC
PRESCALER DIVIDER RESET
DIVIDER

TRE PRST
TRO PRF
CONTROL
PRFAK LOGIC WUKI
WUFAK WUF

WDIV[5:0] WUT[5:0] PRST[5:0]

Figure 60. Wakeup Timer Block Diagram

The wakeup divider (PWUDIV) register selects a division of the incoming 1 ms clock to generate a wakeup clock, WCLK. The
WCLK frequency can be calibrated against the more precise external oscillator using the TPMS_LFOCOL firmware subroutine
as described in Section 14. This subroutine turns on the RFM crystal oscillator and feeds a 500 kHz clock to the TPM1 for one
cycle of the LFO. The measured time is used to calculate the correct value for the WDIV[5:0] bits for a WCLK period of 1 second.
The TPMS_LFOCOL subroutine cannot be used while the RFM is transmitting or the TPM1 is being used for another task.
The wakeup time register (PWUSC0) selects the number of WCLK pulses that are needed to generate a wakeup interrupt to the
MCU. The periodic reset register (PWUSC1) selects the number of wakeup pulses that are needed to generate a periodic reset
of the MCU. Both the wakeup time counter and the periodic reset timer are incrementing counters that generate their interrupt or
reset when the desired count is reached and are then reset to zero. Reading the status of either of these counters will return a
zero content if done immediately after the interrupt or reset is generated.
If both the reset and the interrupt occur on the same clock cycle the reset will have precedence and the interrupt will not be
generated.
In order to prevent wakeup or reset from an extreme temperature event both the wakeup interrupt or periodic reset are disabled
if the thermal restart is activated and the TRO bit indicates that the device is still outside of the TRESET range. The wakeup and
periodic reset counters will still run. The state of these counters can be read using the PSEL bit in the PWUS register.
The wakeup interrupt (WUKI) cannot be masked by clearing the I-bit.

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11.2 Wakeup Divider Register - PWUDIV
The PWUDIV register contains six bits to select the division of the incoming 1 ms clock period as described in Figure 61.

$0038 Bit 7 6 5 4 3 2 1 Bit 0

R 0 0
WDIV[5:0]
W
RESET: — — — — — — — —
POR: 0 0 0 1 1 1 1 1
= Reserved

Figure 61. PWU Divider Register (PWUDIV)

Table 54. PWUDIV Register Field Descriptions

Field Description
7:6 Unused
Unused
Wakeup Divider Value — The WDIV[5:0] bits select an incoming prescaler for the incoming 1 ms clock period from 504 to 1512.
This results in a clocking of the 6-bit wakeup divider at rates from a nominal 0.504 to 1.512 sec per wakeup clock, WCLK. The
user can use this prescaler to fine tune the wakeup time based on the variation in the LFO frequency. The conversion from the
decimal value of the WDIV bits to the nominal WCLK period is given as:
5:0
WDIV[5:0]  504 + 16  WDIV 
t = -------------------------------------------------
WCLK f
LFO
A power on reset presets these bits to a value of $1F (decimal 31) which yields a nominal 1 second output period for WCLK.
Other resets have no effect on these bits.

11.3 PWU Control/Status Register 0 - PWUCS0

The PWUCS0 register contains six bits to select the division of the incoming WCLK clock period and provide interrupt flag and
acknowledge bits as described in Figure 62. The period of the resulting interrupt also generates the clock, RCLK, for the periodic
reset timing.

$0039 Bit 7 6 5 4 3 2 1 Bit 0

R 0
WUF WUT[5:0]
W WUFAK
RESET: 0 — 1 1 1 1 1 1

Figure 62. PWU Control/Status Register 0 (PWUCS0)

Table 55. PWUSC0 Register Field Descriptions

Field Description
Wakeup Interrupt Flag — The WUF bit indicates when a wakeup interrupt has been generated by the PWU. This bit is cleared
7 by writing a one to the WUFAK bit. Writing a zero to this bit has no effect. Reset clears this bit.
WUF 0 Wakeup interrupt not generated or was previously acknowledged.
1 Wakeup interrupt generated.
Acknowledge WUF Interrupt Flag — The WUFAK bit clears the WUF bit if written with a one. Writing a zero to the WUFAK bit
6 has no effect on the WUF bit. Reading the WUFAK bit returns a zero. Reset has no effect on this bit.
WUFAK 0 No effect.
1 Clear WUF bit.

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Table 55. PWUSC0 Register Field Descriptions (continued)

Field Description
WUF Time Interval — These control bits select the number of WCLK clocks that are needed before the next wakeup interrupt
is generated. The count gives a range of wakeup times from 1 to 63 WCLK clocks.
Depending on the value of the bits for the WDIV[5:0] this time interval can nominally be from 1 to 63 seconds in 1 second steps.
Whenever the WUT[5:0] bits are changed the timeout period is restarted. Writing the same data to the WUT[5:0] bits has no
5:0
effect.
WUT[5:0]
Writing zeros to all of the WUT[5:0] bits forces the wakeup divider to a value of $3F and disables the wakeup interrupt. However,
writing all zeros to the WUT[5:0] bits is inhibited if all of the PRST[5:0] bits are already cleared to zero. This prevents disabling
both the periodic wakeup and the periodic reset at the same time. See Table 56.
The WUT[5:0] bits are preset to a value of $3F (decimal 63) by any resets.

Table 56. Limitations on Clearing WUT/PRST

Control Bits to be Resulting Wakeup Resulting Periodic

Control Bits State of Control Bits Resulting Action
Cleared Interrupt Reset
non-zero Allowed Enabled(1) Disabled
WUT[5:0] PRST[5:0] (2)
all zero Inhibited Disabled Enabled(1)
non-zero Allowed Disabled Enabled(1)
PRST[5:0] WUT[5:0]
all zero Inhibited Enabled(1) Disabled
1. Using previous values.
2. Wakeup divider preset to $3F.

11.4 PWU Control/Status Register 1 - PWUCS1

The PWUSC1 register contains six bits to select the division of the incoming RCLK clock period and provide interrupt flag and
acknowledge bits as described in Figure 63.

$003A Bit 7 6 5 4 3 2 1 Bit 0

R PRF 0
PRST[5:0]
W PRFAK
RESET: 0 0 1 1 1 1 1 1
= Reserved

Figure 63. PWU Control/Status Register 1 (PWUCS1)

Table 57. PWUSC1 Register Field Descriptions

Field Description
Periodic Reset Flag — The PRF bit indicates when a periodic reset has been generated by the PWU. MCU writes to this bit
have no effect. This bit is cleared by writing a one to the PRFAK bit. This bit is cleared by a power on reset, but is unaffected by
7
other resets.
PRF
0 Periodic reset not generated or previously acknowledged.
1 Periodic reset generated.
Acknowledge PRF Interrupt Flag — The PRFAK bit clears the PRF bit if written with a one. Writing a zero to the PRFAK bit
6 has no effect on the PRF bit. Reading the PRFAK bit returns a zero. Reset has no effect on this bit.
PRFAK 0 No effect.
1 Clear PRF bit.
Periodic Reset Time Interval — These control bits select the number of wakeup interrupts that are needed before the next
periodic reset is generated. The decimal count gives a range of periodic reset times from 1 to 63 wakeup interrupts. Depending
on the value of the bits for the WDIV[5:0] and WUT[5:0] this time interval can nominally be from 1 second to 66 minutes with
steps from 1 to 63 seconds. Whenever the PRST[5:0] bits are changed the timeout period is restarted. Writing the same data to
5:0
the PRST[5:0] bits has no effect.
PRST[5:0]
Writing zeros to all of the PRST[5:0] bits forces the periodic reset to be disabled if at least one of the WUT[5:0] bits is set to a
one. This assures that there will be at least a wakeup interrupt. However, writing all zeros to the PRST[5:0] bits is inhibited if all
of the WUT[5:0] bits are already cleared to zero. This prevents disabling both the periodic wakeup and the periodic reset at the
same time. See Table 56. The PRST[5:0] bits are preset to a value of 63 by any resets.

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11.5 PWU Wakeup Status Register - PWUS
The PWUS register shows the current status of the two PWU counters as described in Figure 63. The counter contents are
captured when the register is read.

$001F Bit 7 6 5 4 3 2 1 Bit 0

R 0
PSEL CSTAT
W
RESET: 0 - - - - - - -
= Reserved

Figure 64. PWU Wakeup Status Register (PWUS)

Table 58. PWUS Register Field Descriptions

Field Description
Page Selection — The PSEL read/write bit selects whether the other bits are read from the WUT or PRST counters. This bit is
7 cleared by a power on reset that is not created by an exit from the STOP mode, but is unaffected by other resets.
PSEL 0 CSTAT = WUT counter status
1 CSTAT = PRST counter status
6
Unused — An unused bit that always reads as a logical zero.
unused
Counter Status — These read-only bits show the status of the counter selected by the PSEL bit. The effects of any reset on
5:0
these bits depends on how the reset affects the selected counter. Reading these counters immediately after a WUF or PRF
CSTAT
generated flag will return zero contents.

11.6 Functional Modes

PWU module will work in each of the MCU operating modes as follows:

11.6.1 RUN Mode

If the module generates a wakeup interrupt the PC (Program Counter) will be redirected to the wakeup timer interrupt vector. The
WUF flag will be set to indicate wakeup timer interrupt; write 1 to WUFACK to clear this flag.
If the module generates a reset the PC will be redirected to the reset vector. The PRF flag will be set to indicate periodic reset;
write 1 to PRFACK to clear this flag.
All registers will continue to hold their programmed values after interrupt or reset is taken.

11.6.2 STOP4 Mode

If the module generates a wakeup interrupt the bus and core clocks will be restarted and the PC will be redirected to the wakeup
timer interrupt vector. The WUF flag will be set to indicate wakeup timer interrupt, write 1 to WUFACK to clear this flag.
If the module generates a periodic reset the bus and core clocks will be restarted and the PC will be redirected to the reset vector.
The PRF flag will be set to indicate periodic reset; write 1 to PRFACK to clear this flag.
All registers will continue to hold their programmed values after interrupt or reset is taken.

11.6.3 STOP1 Mode

If the module generates a wakeup interrupt the module will cause the MCU to exit the power saving mode as a POR. MCU will
have the wakeup interrupt pending and once CLI opcode is executed PC will be redirected to wakeup interrupt vector address.
The WUF flag will be set to indicate wakeup timer interrupt, write 1 to WUFACK to clear this flag.
If the module generates a periodic reset the module will cause the MCU to exit the power saving mode as a POR. The PRF flag
will be set to indicate periodic reset; write 1 to PRFACK to clear this flag. The SRS register will have just the POR bit set.
In this STOP mode exit all registers will continue to hold their programmed values.

11.6.4 Active BDM/Foreground Commands

The PWU is frozen in ACTIVE BACKGROUND mode or executing foreground commands, so PWU counters will also be stopped.
Normal PWU operation will resume as MCU exits BDM or foreground command is finished.

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12 LF Receiver
The low-frequency receiver (LFR) is a very low-power, low-frequency, receiver system for short-range communication in TPMS.
The module allows an external coil to be connected to two dedicated differential input pins. In TPMS systems a single coil may
be oriented for optimal coupling between the receiver in the tire or wheel and a transmitter coil on the vehicle body or chassis.
This LFR system minimizes power consumption by allowing flexibility in choosing the ratio of on to off times and by turning off
power to blocks of circuitry until they are needed during signal reception and protocol recognition. In addition, this LFR system
can autonomously listen for valid LF signals, check for protocol and ID information so the main MCU can remain in a very low
power standby mode until valid message data has been received.
The LFR can be configured for various message protocols and telegrams to allow it to be used in a broad range of applications.
The message preamble must be a series of Manchester coded bits at the nominal 3.906-kbps data rate. A synchronization pattern
is used to mark the boundary between the preamble and the beginning of Manchester encoded information in the message body.
The synchronization pattern is a non-Manchester specific TPMS pattern. Messages can optionally include none, an 8-bit or a 16-
bit ID value. Messages may contain any number of data bytes with the end-of-message indicated by detecting an illegal
Manchester bit at a data byte boundary.
It is not intended that LFR may be actively receiving/decoding LF signals while physical parameter measurements are being
made; or during the time that the RFM may be actively powered up and/or transmitting RF data. The resulting interactions will
degrade the accuracy of the LF detection.

Data
Data
Summator
Average Slicer
Slicer
Filter

Clamp
Clamp Rectifier0 Rectifier1 Rectifier2 Rectifier3
R

LFA
Amp1 Buff1 Amp2 Buff2 Amp3 Buff3
LFB

Sensitivity

Vref_sensitivity

Logic Block 1:
Carrier
Carrier - On/Off cycling MFO
129 kHz Logic Block 2:
Detector
- Carrier Detection 32kHz
Typ - Data decoding

11kHz_clock
kHz_clock Typ

Figure 65. Block Diagram

For definitions of the acronyms and detailed descriptions of the bits and/or byte registers, please refer to Section 12.17.

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12.1 Features
Major features of the LFR module include:
• Differential input LF detector (two dedicated pins):
— Selectable sensitivity (two levels: Low Sens (LS) and High Sens (HS)).
— Thresholds trimmed at the factory with trim setting saved in nonvolatile memory.
— LFR has a reference oscillator (LFRO) trimmed at the factory with trim setting saved in nonvolatile memory.
— Selectable signal sampling time interval and on-time.
— Sample interval and on times controlled by LFR state machine or directly by the MCU.
• Configurable receive mode:
— Simple LF carrier detection/Telegram decode. (CARMOD)
• Configurable message protocol (telegram structure):
— Various SYNC decoding (SYNC[1:0])
6-bit time SYNC requirements
7.5-bit time SYNC requirements
9-bit time SYNC requirements
— Optional ID (ID[1:0])
8-bit or 16-bit ID
On or off
— 0-n bytes of message data. End-of-data marked by loss of Manchester at a byte boundary.
• Optional continuous monitoring and decode of the LF detector.
• Selectable MCU interrupt when a received data byte is ready in an LFR buffer, when a Manchester error is detected in the
frame, when an ID is received or when a valid carrier has been detected.

12.2 Modes of Operation

The LFR is a peripheral module on an MCU. After being configured by application software, the LFR can operate autonomously
to detect and verify incoming LF messages. When a valid message or carrier pulse is received and verified the LFR can wake
the MCU from standby modes to read received data or act upon a carrier detection.
The primary modes of operation for the LFR are:
• Disabled. Everything off and drawing minimal leakage current. LFR register contents will be retained.
• Carrier detect/listen. Minimum circuitry enabled to detect any incoming LF signal, check it for the appropriate signal level,
frequency and duration.
• TPMS protocol verification.
• Data reception.

12.3 Power Management

In addition to using low power circuit design techniques, the LFR module provides system-level features to minimize system
energy requirements. In an MCU that includes the LFR module, all MCU circuitry except a very low current 1-kHz oscillator (LFO)
and minimum regulator circuitry can be disabled. After a reset, the MCU would initialize the LFR module and then enter a very
low power standby mode (depending upon the MCU, this could be lower than 1 uA for the MCU portion). The LFR module
includes everything it needs to periodically listen for LF messages, perform Manchester decoding, verify the message telegram,
and assemble incoming data into 8-bit bytes. The LFR does not wake the MCU unless a valid message is being received and a
data byte is ready to be read.
The LFR cycles between an off state, where everything is disabled, and an on state, where it listens for a carrier signal. The on
time is controlled by LFONTM[3:0] control bits in the LFCTL2 register. The time between the start of each sample on time is
controlled by LFSTM[3:0] control bits in the LFCTL2 register. Even lower duty cycles can be achieved by using the MCU to wake
once per second and maintain a software counter to delay for an arbitrarily long time before enabling the LFR to perform a series
of carrier detect cycles.
Within the LFR, circuits remain disabled until they are needed. When the LFR is listening for a carrier signal, only a 1-kHz clock
source, a portion of the input amplifier and a periodic auto-zero are running. After a carrier signal is detected, with high enough
amplitude, frequency and duration the LFRO oscillator is enabled so the LFR can begin to decode the incoming information.
The LFR module has a power up settling time of 2-LFO period before any active operations. In the ON/OFF cycle, those 2 ms
are hidden in the sampling time during the off time.

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12.4 Input Amplifier
The LFR module receives LF modulated signals through a dedicated differential pair of inputs which is connected to an external
coil. The enable control (LFEN) allows the user to enable the LF input depending on the application requirements. The SENS[1:0]
bits in the LFCTL1 register allows the user to select one of two input sensitivity thresholds which determines the signal level
required before the input carrier will be detected. The sensitivity setting is used during carrier detection but does not affect
reception after the carrier has been detected. When the CARMOD bit is cleared, after a carrier with sufficient amplitude,
frequency and duration has been detected the output stage of the amplifier is turned on to allow data reception.

12.5 LFR Data Mode States

The modes of operation the LFR state machine will sequence as shown in Figure 66.

12.6 Carrier Detect

Carrier detection includes a check for a certain number of edges on a signal that is greater than the input sensitivity threshold.
During the check for carrier edges, only the 1kHz low frequency oscillator (LFO) clock source is running so power consumption
remains very low.
During carrier detection the incoming signal is amplified and passed through a sensitivity threshold comparator. The SENS[1:0]
bits in the LFCTL1 register selects two levels of sensitivity and determines the signal amplitude that is needed to allow edges to
be seen at the output of the sensitivity threshold comparator. When a carrier is above this threshold, a block is powered on and
validates the carrier. This frequency and duration check function can be disabled by clearing the VALEN bit. If VALEN is set, the
block checks for the carrier duration and the carrier frequency. The time needed to validate a carrier is programmed by the
LFCDTM register. The carrier frequency should be 125 kHz. If the signal above the threshold is not within the frequency range
or not present during enough time, then the carrier will not be validated and the validation block will turn off.
If no carrier signal is validated within the on time of the LFR, the state machine returns to the off state and the alternating cycle
of on time and off time continues. Carrier edge counts start at zero when a new on time begins.
In the data mode (CARMOD = 0), if the required number of carrier edges are detected before the end of the ON time, the LFR
will remain ON to complete the reception of a message telegram.
In the carrier detect mode (CARMOD = 1) there is no need to enable other LFR circuitry to evaluate any other message
components after the required number of carrier edges are detected. One or several consecutive carriers can be validated by
this process before the LFCDF flag is set. The LFCC control bits are used to program the number of consecutive ON times where
a complete carrier validation is needed before interrupting the MCU. In this case, the LFCDF flag is set and, provided the LFCDIE
interrupt enable is also set, an interrupt is issued to wake the MCU. In carrier detect mode, the LFCDIE control bit should always
be set because the intended purpose of the carrier detect mode is to wake the MCU when a carrier is detected. When LFCDF is
set, the LFR waits until it is cleared before it continues the alternating cycle of on time and off time, starting with an off time.
In data mode, when a carrier is detected the averaging filter is powered on and the LFR continues to the next state to look for the
rest of a message telegram; and the LFR module will search for valid SYNC word (with length programmed through the SYNC
bits in the LFCTL3 register depending on preamble type). If the external LF field is not a TPMS frame, a timeout will turn off the
LFR module. This timeout can be program through TIMOUT bit the LFCTL4 register.

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12.7 Auto-Zero Sequence
An auto-zero sequence is performed periodically on the input amplifier to cancel offset errors. During reception of the SYNC
pattern and body of the message, auto-zero operations are synchronized to data edges of the incoming signal to avoid interfering
with normal reception. During the auto-zero sequence, the input amplifier is temporarily disconnected from the external coil and
connected to ground. The auto-zero sequence takes roughly 64 sec. It is performed at each LFO period in carrier mode and on
one over four decoded data edges in data mode.
When the DECEN bit is cleared, the auto-zero sequence is performed at each LFO period. During the 64 sec of the auto-zero
sequence, the receiver is holding the state “0” or “1”' previously decoded. Since the LFR receiver is not active during this time,
the possible data-rate that the analog can detect is at least limited by this duration.

12.8 Data Recovery

Rectified signals from the amplifier output are connected to the input of an averaging filter and data slicer. The slicer thus
compares the rectified signal with its own average value to decode the data. When a carrier is present, the slicer output voltage
rises and when the carrier stops the slicer output voltage falls. The output of this comparator provides a binary digital signal that
indicates whether the carrier is present or not. This digital signal is connected to the data clock recovery circuit, the SYNC detect
circuit, and the Manchester decoder circuit.
The Manchester decoder uses the digital output of the data slicer to detect the logic level of each incoming data bit and to
synchronize the decoder state machine. The LFPOL polarity bit in the LFCTRLA register selects the expected encoding of the
Manchester data bit.
If a strong signal (above roughly 100 mV p-p differential) is entered into the LFR, the input impedance will switch instantaneously
to a lower programmed value (the LOWQ[1:0] bits in the LFCTRLC) and be maintained during the current data packet if the
DEQEN bit is set. At the next ON time, the default high input impedance will be set again. The strong signal detection and the
automatic impedance change can be disabled by clearing the DEQEN bit.

12.9 Data Clock Recovery and Synchronization

Data clock recovery and synchronization takes place during the SYNC portion of an incoming message. The preamble must be
modulated Manchester data. The type of required SYNC pattern determines the allowed preamble type depending on the
SYNC[1:0] control bits.
The design data rate is 3.906 kbps which gives a bit time equivalent to about 32 cycles of the LF carrier frequency. In a
Manchester encoded bit time, the carrier should be present for either the first half or the second half of the bit time depending on
whether the bit is a logic zero or a logic one.
The LFRO clock source is 32 times the target data rate. The LFRO is used for decoding data and also sequencing auto-zero
operations.

12.10 Manchester Decode

When the LFPOL bit is clear, a logic one bit is defined as no LF carrier present for the first half of the bit time; and a logic zero
bit is defined as LF carrier present for the first half of the bit time as shown in Figure 67. Another way to say this from the point
of view of the data slicer output is that a logic zero bit has a falling edge at the middle of the bit time and a logic one bit has a
rising edge at the middle of the bit time. The data slicer threshold is dynamically adjusted to the midpoint between the carrier-
present and no-carrier levels at the summing node for the rectified output of the LF input amplifier.

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 Data Slicer Threshold

LF Input
(shaded area
is LF
carrier)
0.5T 0.5T

T T
Logic “1” Logic “0”
Data Bit
(data slicer
output)
T = 1 Bit Time at the data rate (ex. 256 us at data rate of 3.906 kbps)
Figure 67. Manchester Encoded Datagram for LFPOL = 0
When the LFPOL bit is set, a logic one bit is defined as LF carrier present for the first half of the bit time; and a logic zero bit is
defined as no LF carrier present for the first half of the bit time as shown in Figure 68.

Data Slicer Threshold

LF Input
(shaded area
is LF
carrier)
0.5T 0.5T

T T
Logic “0” Logic “1”
Data Bit
(data slicer
output)
T = 1 Bit Time at the data rate (ex. 256 s at data rate of 3.906 kbps)
Figure 68. Manchester Encoded Datagram for LFPOL = 1

12.11 Duty-Cycle For Data Mode

The definition of the duty-cycle for the Manchester encoded data depends on the relative rise and fall times of the incoming LF
carrier as shown in Figure 69.

60 40

40 60

1 0
Figure 69. Definition of Duty-Cycle of 40%
Regarding the SYNC pattern which is non-Manchester coded, the duty cycle is applied on all falling edges with the same
proportion as a 1T Manchester symbol, as shown in Figure 70.

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 Figure 70. Impact of Duty-Cycle on SYNC Pattern

12.12 Input Signal Envelope

The combination of the external LF antenna and any external components as shown in Figure 71 should not significantly filter
the envelope of the LF carrier as shown in Figure 72. Excessive filtering will cause the received message error rate (MER) to
increase.

LFA
• Antenna Q-factor acts as a 1st order
low pass filter on the LF envelop
C R
• Filter time constant : t = R.C

LFB 
Recommended < 15.3 sec

Antenna model SUZUKA

Figure 71. Antenna Q-factor Equivalent Model for the LF Envelope

Recommended< 15.3 sec

Figure 72. LF Envelope Filtering

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12.13 Telegram Verification
The LFR has control bits to allow flexibility in the telegram format and protocol to allow the LFR to adapt to a variety of systems.
The LFR can operate in a normal data receive mode where it receives complete telegrams, or in a carrier detect mode where it
only checks for a carrier. In the carrier detect mode, as soon as a carrier is detected, the LFCDF flag is set. If LFCDIE is also set,
an interrupt request is sent to wake the MCU
The format of the complete Manchester encoded datagram is comprised of a Manchester data preamble (series of Manchester
1’s or 0’s), a synchronization period, an optional ID, and zero to n data bytes.
The synchronization period can be used for synchronizing the beginning of the data packet. The SYNC pattern that follows the
preamble can be either a 6-, 7.5- or 9 bit-time non-Manchester pattern as shown in Figure 73.

6-bit
(6T)
Pattern T T
SYNC[1:0] = 01
T 2T 2T T

7.5-bit
(7.5T)
Pattern T T
SYNC[1:0] = 10 1.5T
T 2T 2T T

9-bit
(9T)
Pattern 1.5T T T
SYNC[1:0] = 11
3T T 2T 2T T
Figure 73. SYNC Patterns
These patterns would normally not appear anywhere in the Manchester encoded portion of a message so there is no possibility
that the LFR could accidentally synchronize to a message that was already in progress when the LFR started listening for a
message. These patterns are also complex enough so that it is very unlikely that noise or interference could be mistaken for these
SYNC patterns. In the data mode and after the detection of a valid carrier, the LFR will decode the data stream waiting for the
SYNC word. Should this carrier not be an accepted TPMS type, no SYNC will be received and the LFR module will stay in data
receive mode forever. A timeout counter is thus started after a carrier detection and will stop the receiver if reaching the
programmed value selected by the TIMOUT[1:0] bits in the LFCTL4 register. This timeout counter is clocked by the internal LFRO
clock.
The LFR can be configured to have an optional 0, 8-bit or 16-bit ID after the SYNC pattern. If the ID value matches the received
ID, the message is accepted. The ID value can be used to identify a specific receiver, a message type, or some other identifier
as defined by application software.
Any number of data bytes can be included after the ID. The LFR begins to assemble data bytes from the incoming signal as soon
as the ID check is complete. If the first bit-time after the last bit of the ID does not conform to Manchester coding requirements,
the LFR considers the message complete and terminates the LFR operation without setting the data ready flag (LFDRF). If data
follows the ID, it is serially received and when 8 bits have been received the LFR copies this byte into the LFDATA register and
sets the LFDRF flag. If the LFDRIE interrupt enable is also set (and it should be), an interrupt request is sent to wake the MCU
so it can read the data and process it according to the instructions in the application program. Additional bytes are received until
a bit time that is not Manchester encoded is found. If a non-Manchester bit time is found, the LFERF bit will be set and indicates
a Manchester coding error. If this happens on the first bit of the next byte of the message the LFEOMF bit will also be set.
The preamble is a period of Manchester bits before the SYNC pattern as shown in Figure 74. The SYNC pattern will only be
matched for the bit times specified by the SYNC[1:0] control bits. Depending on the expected SYNC pattern the allowed
preambles is as described for the SYNC[1:0] bits in the LFCTL3 register.

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 PREAMBLE SYNC HIGH ID LOW ID DATA DATA

tLFPRE 6, 7.5 or 9T 0, 8T or 16T 8T

IDSEL[1:0] Repeat for 0-n bytes

Figure 74. Telegram Format (Carrier Preamble)

12.14 Error Detection and Handling

When the DECEN bit is set, LFR messages are monitored for data rate or SYNC errors, incorrect message ID, and Manchester
coding errors. When an error is detected the LFR goes back to sniff mode until the end of ON time completion, if ONMODE is
set; or turns off until the start of the next scheduled sampling interval, if ONMODE is cleared. Because the MCU uses more power
than the LFR module, it is desirable to keep the MCU in low power standby modes as much as possible. Therefore the handling
of these errors will be performed by the LFR and not require additional software processing by the MCU.
When the DECEN bit is clear, there is no monitoring on data. The MCU needs to poll the state of the LFDO bit and create its own
decoding scheme within software on the detected signal. To be able to start the polling only when data are received, the carrier
detection flag is enabled in data mode when DECEN = 0. During data reception, the auto-zero sequence is performed at each
LFO period. The MCU needs also to determine the end of the telegram and turn off the LFR (LFEN = 0) during two LFO cycles
before any other operations.

12.15 Continuous ON Mode

In the Continuously ON mode, the LFR module will remain on continuously while the LFEN bit is set. The Continuously ON mode
is controlled by setting the LFSTM[3:0] bits.
In the Continuously ON mode, if a signal is successfully processed by the digital, the LFR module will stop and restart
automatically. The gap is 2-3 LFO periods. Also if TOGMOD bit is set, the LFR module will stop after the ON time cycle and re-
start automatically, after having changed the CARMOD bit.

12.16 Initialization Information

When power is applied to the MCU, the LFR must be initialized and configured before it can begin to receive LF messages.
Several systems in the LFR require factory trimming to ensure operation within specified limits. After these trim values are written,
they remain constant until the next MCU reset.
The application program must set up control bits and registers to configure the LFR to determine the structure of the message
telegram, the input sensitivity, and other LFR options. It is good practice to clear the flags in the LFS register before enabling
interrupt sources in order to avoid any immediate interrupt requests.

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12.17 LFR Register Definition
The LFR module uses eight addresses in the MCU memory map for data, control, and status registers.This section consists of
register descriptions. Each control register (LFCTLx) should be modify when the LF is off (LFEN = 0). Modification of the control
registers “on-the-fly” might lead to unknown state. Each turn off of the LFR (LFEN = 0) should be followed by at least two LFO
cycles before trying to restart the LFR (LFEN = 1).

12.17.1 LF Control Register 1 (LFCTL1)

LFCTL1 contains the main LF enable control, detection protocol format controls, and input sensitivity controls. The LFCTL1
register also contains a register select bit, LPAGE.

$0020 Bit 7 6 5 4 3 2 1 Bit 0

R 0
LFEN CARMOD LPAGE IDSEL[1:0] SENS[1:0]
W SRES
Reset: 0 0 0 0 0 0 0 0

Figure 75. LFR Control Register 1 (LFCTL1)

Table 59. LFCTL1 Register Field Descriptions

Field Description
LF Enable — This read-write control bit is used to enable or disable the LF receiver. Once this bit is set the LFR will go through
a power-up sequence that starts on the next rising edge of the LFO clock. The first complete cycle of the LFO is used to power
up the LFR circuits. Following this startup time the auto-zero sequence is performed for 64sec and then the LFR is ready to
7
receive signals.
LFEN
0 LF receiver in standby.
1 LF receiver active.
Note: Enabling the LF receiver function disables the GPIO Port B functions - see Section 6.5.
Soft Reset — This read/write bit controls the soft reset of the LFR. The bit is self reset and always reads as a logical zero.
6
0 Reset completed
SRES
1 Start a soft reset.
Carrier Mode — This read/write control bit selects the basic operating mode for the LFR.
5
0 Data receive mode.
CARMOD
1 Carrier detect mode - wake the MCU when a carrier signal is detected if LFCDIE is set.
LFR Page Select — This read/write bit is used is used to select the register page access. The LPAGE bit has no effect on the
4 LFCTL1 and LFCTL2 registers. This bit is cleared by LFR reset.
LPAGE 0 Access page 0.
1 Access page 1.
Wakeup ID Selection — Selects the existence and length of the wakeup ID. Reset clears these bits.
00 No ID expected
3:2
01 8-bit ID based on the contents of the LFIDL register
IDSEL[1:0]
10 16-bit ID based on the contents of the LFIDH and LFIDL registers
11 8-bit ID matches the contents of either the LFIDH or LFIDL registers
Sensitivity Control — These two read/write control bits select the sensitivity thresholds for the LFR input. These thresholds
apply to the detection portion of a message. If the input level is below the SNODET_x level, no signal will be detected. If the level
is above SDET_x, the signal will be detected. Sensitivity settings are only used in the carrier detect path and do not affect reception
1:0 of the message body.
SENS[1:0] 00 Performance not specified.
01 Low sensitivity (SDET_L; SNODET_L)
10 High sensitivity (SDET_H; SNODET_H)
11 Performance not specified.

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12.17.2 LF Control Register 2 (LFCTL2)
LFCTL2 contains the selection bits for the length of the LF sampling ON time and the time interval between samples as shown
in Figure 76.

$0021 Bit 7 6 5 4 3 2 1 Bit 0

R
LFSTM[3:0] LFONTM[3:0]
W
Reset: 0 1 1 0 0 0 0 0

Figure 76. LFR Control Register 2 (LFCTL2)

Table 60. LFCTL2 Register Field Descriptions

Field Description
LF Sampling Time Interval Select— These read/write control bits select the length of time between when the LFR input detector
is turned on as set by the LFONTM bits in LFCTL2 register. The initial sampling interval starts with the LFO clock following a write
to these bits. A reset of the LFR results in the value being set to binary 0110.
0000 Continuous ON mode (see Section 12.15)
0001 Sampled decoding mode every 16 LFO clock periods (16 milliseconds nominal)
0010 Sampled decoding mode every 32 LFO clock periods (32 milliseconds nominal)
7:4 0011 Sampled decoding mode every 64 LFO clock periods (64 milliseconds nominal)
LFSTM
0100 Sampled decoding mode every 128 LFO clock periods (128 milliseconds nominal)
[3:0]
0101 Sampled decoding mode every 256 LFO clock periods (256 millisecond nominal)
0110 Sampled decoding mode every 512 LFO clock periods (512 milliseconds nominal)
0111 Sampled decoding mode every 1024 LFO clock periods (1024 milliseconds nominal)
1000 Sampled decoding mode every 2048 LFO clock periods (2048 milliseconds nominal)
1001 Sampled decoding mode every 4096 LFO clock periods (4096 milliseconds nominal)
1010-1xxxContinuous ON mode (see Section 12.15)
LF Sampling ON Time Select — These read/write control bits select the length of time that the LFR input
detector is turned on at the beginning of each sampling interval set by the LFSTM bits. This ON time is the net sampling time
with any initialization time (maximum of 2 ms) included in the OFF time prior to the sample ON time (see Figure 77). If a signal
is successfully detected, the length of time the detector remains ON depends on the operating mode. In carrier detect mode
(CARMOD = 1) the detector will be turned off early if the evaluation of the carrier signal is completed before the end of the
scheduled ON time. In data receive mode (CARMOD = 0) the detector will remain ON until the end of the message, an error is
detected or timeout occurrence. Reset forces the LFONTM bits to 0:0:0.
0000 1 LFO clock cycle (1 millisecond nominal)
0001 2 LFO clock cycle (2 milliseconds nominal)
0010 4 LFO clock cycle (4 milliseconds nominal)
3:0 0011 8 LFO clock cycle (8 milliseconds nominal)
LFONTM 0100 16 LFO clock cycle (16 milliseconds nominal)
[3:0] 0101 32 LFO clock cycle (32 milliseconds nominal)
0110 64 LFO clock cycle (64 milliseconds nominal)
0111 128 LFO clock cycle (128 milliseconds nominal)
1000 256 LFO clock cycle (256 milliseconds nominal)
1001 512 LFO clock cycle (512 milliseconds nominal)
1010 1024 LFO clock cycles (1024 milliseconds nominal)
1011 1024 LFO clock cycles (1024 milliseconds nominal)
11xx 1024 LFO clock cycles (1024 milliseconds nominal)

Note: The LFONTM selected time must be less than the LFSTM selected time, otherwise the Continuously ON mode is present.

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 LFR Detector Active tDEC
LFONTM
Power Up Power Up
Settling Time Settling Time

LFSTM
LFONTM LF searching for
time segments not to scale SYNC pattern
Figure 77. LF Detector Sampling Timing

12.17.3 LF Control Register 3 (LFCTL3)

LFCTL3 contains the control bits for the LF sampling interval and the minimum required carrier detection time when using the
carrier detect mode.

$0022 Bit 7 6 5 4 3 2 1 Bit 0

R LFDO
TOGMOD SYNC[1:0] LFCDTM[3:0]
W
Reset: — 0 0 1 0 0 0 0
= Reserved

Figure 78. LFR Control Register 3 (LFCTL3)

Table 61. LFCTL3 Register Field Descriptions

Field Description
LF Detector Output — This read-only bit follows the bit slicer output signal that goes high during the presence of a carrier. It
7 may change at any time. This bit is read only and unaffected by any reset.
LFDO 0 LF detector output low (no signal above threshold)
1 LF detector output high (received signal above threshold)
LFR Mode Toggle — This read/write bit enables the toggling of the CARMOD bit at each new LFON sequence. Reset clears
this bit.
6
0 CARMOD bit does not change and determines detector mode.
TOGMOD
1 CARMOD bit will be toggled every LFON detection sequence, starting by CARMOD selection.
Therefore the reception chain will alternately look for a carrier frame or for a data frame.
LF SYNC Selection — Selects the type of SYNC pattern as described in Figure 73. Reset presets these bits to the 01 (6T SYNC)
option. Compatible with preamble consisting of minimum 2 ms Manchester data to allow for proper averaging filter operation.
5:4 00 For factory test purposes, not intended for use in any application.
SYNC[1:0] 01 6T SYNC pattern
10 7.5T SYNC pattern
11 9T SYNC pattern

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Table 61. LFCTL3 Register Field Descriptions (continued)

Field Description
LF Carrier Detect Time — These read/write control bits select the length of time which the LFR input detector must detect a
carrier before validating it. In carrier mode (CARMOD = 1), if the carrier is active for at least the time selected by the LFCDTM[3:0]
bits and the LFCC counter value is reached, the LFCDF flag in the LFS register will be set; and if the LFCDIE control bit is also
set, the MCU will be interrupted (wakeup).

In the data receive mode (CARMOD = 0) the LFCDTM[3:0] bits select the length of time which the LFR input detector must detect
a carrier before the effective receive chain is powered on. Once the carrier has been validated the LFCDTM[3:0] bits ignored
during the decode of the rest of the data.

Reset of the LFR results in LFCDTM[3:0] being reset to 0:0:0:0. The resulting carrier detect times are defined by the following
number of carrier periods needed to validate the carrier, with the corresponding time for a carrier at 125 kHz in parenthesis:

0000 Carrier detect = 8 (64 sec)Data mode detect = 8 (64 sec)

3:0 0001 Carrier detect = 16 (128 sec)Data mode detect = 8 (64 sec)
LFCDTM 0010 Carrier detect = 32 (256 sec)Data mode detect = 8 (64 sec)
[3:0] 0011 Carrier detect = 64 (512 sec)Data mode detect = 8 (64 sec)
0100 Carrier detect = 128 (1024 sec)Data mode detect = 8 (64 sec)
0101 Carrier detect = 256 (2048 sec)Data mode detect = 8 (64 sec)
0110 Carrier detect = 512 (4096 sec)Data mode detect = 8 (64 sec)
0111 Carrier detect = 1024 (8192 sec)Data mode detect = 8 (64 sec)

1000 Carrier detect = 8 (64 sec)Data mode detect = 8 (64 sec)

1001 Carrier detect = 16 (128 sec)Data mode detect = 16 (128 sec)
1010 Carrier detect = 32 (256 sec)Data mode detect = 32 (256 sec)
1011 Carrier detect = 64 (512 sec)Data mode detect = 64 (512 sec)
1100 Carrier detect = 128 (1024 sec)Data mode detect = 128 (1024 sec) (see note)
1101 Carrier detect = 256 (2048 sec)Data mode detect = 256 (2048 sec) (see note)
1110 Carrier detect = 512 (4096 sec)Data mode detect = 512 (4096 sec) (see note)
1111 Carrier detect = 1024 (8192 sec)Data mode detect = 1024 (8192 sec) (see note)

NOTE
The auto-zero sequence needs to be performed every 1 ms. Therefore LFR detection times
of 1024, 2048, 4096 and 8192 sec the auto-zero sequence will be done at each 1 ms
interval. This auto-zero sequence lasts for 64 sec. If the carrier is detected again at the end
of the auto-zero sequence it is assumed that the carrier was there for the complete 64 sec
period of the auto-zero.

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12.17.4 LFR Control Register 4 (LFCTL4)
LFCTL4 contains local interrupt enable control bits. The provided I-interrupts are not globally masked by the I bit in the CPU’s
CCR, setting one or more of these interrupt enable control bits will cause a CPU interrupt to be requested whenever the flag bit
associated with the corresponding LFR interrupt source becomes set. It is good practice to clear any flag bits in the LFS register
before setting interrupt enable bits in this register in order to avoid an immediate interrupt request.

$0023 Bit 7 6 5 4 3 2 1 Bit 0

R
LFDRIE LFERIE LFCDIE LFIDIE DECEN VALEN TIMOUT[1:0]
W
Reset: 0 0 0 0 1 1 0 0

Figure 79. LFR Control Register 4 (LFCTL4)

Table 62. LFCTL4 Register Field Descriptions

Field Description
LFR Data Register Full Interrupt Enable — This read/write bit enables interrupts to be requested when the LFR data register
is full. Reset clears LFDRIE.
7
0 LFDRF interrupts disabled. Use software polling.
LFDRIE
1 LFR Data Register Full interrupts are enabled. If LFDRIE is set,
then an interrupt is requested when LFDRF = 1.
LFR Error Interrupt Enable — This read/write bit enables interrupts to be requested when the LFR detects an error in reception
6 of a non-Manchester encoded bit time following the SYNC time. Reset clears LFERIE.
LFERIE 0 LFERF interrupts disabled. Use software polling.
1 LFERF interrupts are enabled. If LFERIE is set, then an interrupt is requested when LFERF = 1.
LFR Carrier Detect Interrupt Enable — This read/write bit enables the LFCDF interrupt when the LFR detects the number of
samples with an LF signal defined by the LFCDTM bits in the LFCTL3 register. The LFCDIE is ignored when the LFR is operating
5
in the data mode (CARMOD = 0), except when DECEN is cleared. Reset clears LFCDIE.
LFCDIE
0 LFCDF interrupts disabled.
1 LFR LFCDF interrupts are enabled. If LFCDIE is set, then an interrupt is requested when LFCDF = 1.
LFR ID Detect Interrupt Enable — This read/write bit enables interrupts to be requested when the LFR detects a match to the
4 ID code selected in the LFIDH:L registers. Reset clears LFIDIE.
LFIDIE 0 LFIDF interrupts disabled.
1 LFIDF interrupts are enabled. If LFIDIE is set, then an interrupt is requested when LFIDF = 1.
LF Digital Decode Enable — This read/write bit enables the data processing by the digital decoder. When
disabled, the frame format (Manchester, data-rate, SYNC, data) is not checked. There is no more error flag assertion (data, error,
3
ID). The MCU should then poll the LFDO bit to extract from the analog detector the bit stream. Reset sets the DECEN bit.
DECEN
0 Digital decoder is disabled.
1 Digital decoder is enabled.
LF Validation Enable — This read/write bit enables the carrier validation process. Reset sets this bit.
2
0 Carrier Validation disabled.
VALEN
1 Carrier Validation enabled.
SYNC Time Out Select — These two read/write bits select the period of time that the LFR will search for a SYNC pattern in the
data mode. If the SYNC pattern is not detected the LFR will be turned off after this delay time. These time intervals are clocked
1:0 by the internal LFRO clock. Reset clears TIMOUT bit.
TIMOUT 00 SYNC word is continuously searched — no timeout.
[1:0] 01 SYNC search time set to nominal 8 milliseconds.
10 SYNC search time set to nominal 24 milliseconds.
11 SYNC search time set to nominal 48 milliseconds.

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12.17.5 LFR Status Register (LFS, LPAGE = 0)
LFS contains the data ready status flags. It is only accessible when the LPAGE bit is clear.

$0024 Bit 7 6 5 4 3 2 1 Bit 0

R LFDRF LFERF LFCDF LFIDF LFOVF LFEOMF 0
LPSM
W LFIAK
Reset: 0 0 0 0 0 0 1 0
= Reserved

Figure 80. LFR Status Register (LFS, LPAGE = 0)

Table 63. LFS Register Field Descriptions

Field Description
LF Data Ready Flag — This read-only status flag is set when a complete byte of data has been received by the LFR. An interrupt
is sent to the MCU if the LFDRIE bit is set. Clear LFDRF by writing a one to the LFIAK bit or reading the LFDATA register. LFDRF
7
is also cleared by reset.
LFDRF
0 No new data in LFDATA register.
1 A new byte of data has been received and can be read from the LFDATA register.
LF Receive Error Flag — In data receive mode, this read-only status flag is set when a non-standard bit time is detected in the
Manchester data mode. Any received data bits before the error occurs are placed in the data buffer. In carrier detect mode, this
6 read-only status flag is not used and remains clear. An interrupt is sent to the MCU if the LFERIE bit is set. Clear LFERF by
LFERF writing a one to the LFIAK bit. LFERF is also cleared by reset.
0 Normal operation.
1 Error detected in the Manchester data mode.
LF Carrier Pulse Detect Flag — In carrier detect mode, this read-only status flag is set when the number of consecutive carrier
validations set by the LFCC bits in is reached. Note that the LFCC function is not working if TOGMOD = 1. Clear LFCDF by writing
5
a one to the LFIAK bit. LFCDF is also cleared by reset.
LFCDF
0 Normal operation.
1 Carrier detection has occurred.
LF ID Detect Flag — In data receive mode, this read-only status flag is set when the received ID matches the stored value. This
interrupt can be generated even if no data bits follow the ID. An interrupt is sent to the MCU if the LFIDIE bit is set. Clear LFIDF
4
by writing a one to the LFIAK bit. LFIDF is also cleared by reset.
LFIDF
0 Normal operation.
1 wakeup ID has been detected.
LF Receive Data Overflow Flag — In data receive mode, this read-only status flag is set when a complete byte of data has
been received and written into the LFDATA register, but the previously received byte was not read from LFDATA register yet.
This indicates that the MCU has lost the previously received data byte. In carrier detect mode, this read-only status flag is not
3
used and remains cleared. No separate interrupt is generated by this specific flag bit because the LFDRF flag would serve that
LFOVF purpose. Clear LFOVF by writing a one to the LFIAK bit. LFOVF is also cleared by reset.
0 Normal operation.
1 Previous data over-written before MCU read it.
LF Receive Data EOM Flag — In data receive mode, this read-only status flag is set when a complete byte of data has been
received and written into the LFDATA register and an end-of-message Manchester encoding error occurs. In carrier detect mode,
2 this read-only status flag is not used and remains clear. No interrupt is generated by this flag bit because the LFERF flag would
LFEOMF serve that purpose. Clear LFEOMF by writing a one to the LFIAK bit. LFEOMF is also cleared by reset.
0 No EOM detected.
1 EOM detected.
Low Power Sniff Mode — This bit used to activate the low power consumption during SNIFF mode. It saves approximately 1
1 A with a trade-off of an additional 200 s in transition from carrier to data mode. LPSM is set by reset.
LPSM 0 Low time transition from carrier to data mode
1 Low consumption during sniff mode
LF Interrupt Acknowledge — Writing a one to the LFIAK bit clears the LFDRF, LFERF, LFCDF, LFIDF, LFOVF and LFEOMF
flag bits. When a one is written to the LFIAK, it is automatically cleared at the next positive edge of the MCU bus clock. Then,
0 reading the LFIAK bit is allowed but will always return zero. Writing a zero the LFIAK bit has no effect. Reset has no effect on
LFIAK this bit.
0 No effect.
1 Clears the LFDRF, LFERF, LFCDF, LFIDF, LFOVF and LFEOMF flag bits.

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12.17.6 LFR Data Register (LFDATA, LPAGE = 0)
The LFDATA is a read-only register that contains the most recent received data value. It is only accessible when the LPAGE bit
is clear. As data is serially received by the LFR, it is assembled into 8-bit values. When a new complete 8-bit value is received,
it is moved into the LFDATA register, over-writing any previous value, and the LFDRF data ready flag is set to indicate a value is
available for the MCU to read. If a previous value was ready but was not read out of the LFDATA register before a new data byte
is ready, the LFOVF overflow flag is also set to indicate this overflow condition. Writes to LFDATA have no meaning or effect.

$0025 Bit 7 6 5 4 3 2 1 Bit 0

R RXDATA[7:0]
W
Reset: 0 0 0 0 0 0 0 0
= Reserved

Figure 81. LFR Data Register (LFDATA) when LPAGE = 0

Table 64. LFDATA Register Field Descriptions

Field Description
7:0
Receive Data [7:0] — This is the received data from the LFR when in the data mode. All bits are read-only and any writes to
RXDATA
these bits will be ignored. Reading this register will clear the LFDRF.
[7:0]

12.17.7 LFR ID Registers (LFIDH:LFIDL, LPAGE = 0)

These two 8-bit read/write registers hold one of two ID values for LF messages. They are only accessible when the LPAGE bit
is clear. The type of ID checking can be selected or disabled by using the IDSEL[1:0] bits in the LFCTL1 register. When ID
checking is enabled, the ID value received through the LFR must match the contents of the LFIDH and/or LFIDL registers
depending on the IDSEL bits or the message will be ignored and the MCU will remain in standby mode to minimize power
consumption. All these bits are cleared by a reset.

$0026 Bit 7 6 5 4 3 2 1 Bit 0

R
ID[0:7]
W
Reset: 0 0 0 0 0 0 0 0

Figure 82. LFR ID Low Byte (LFIDL)

$0027 Bit 7 6 5 4 3 2 1 Bit 0

R
ID[15:8]
W
Reset: 0 0 0 0 0 0 0 0

Figure 83. LFR ID High Byte (LFIDH)

Table 65. LFR ID Register Field Description

Field Description
ID[15:0] ID bits 15 through 0 — These read/write bits contain bits 15 through 0 of the 16-bit ID value.

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12.17.7.1 LF Control E - LFCTRLE

$0021 Bit 7 6 5 4 3 2 1 Bit 0

R
AZSC2 AZSC1 AZSC0
W
Reset: 0 0 0 0 0 0 0 0
= Reserved

Figure 84. LF Control E (LFCTRLE)

Table 66. LFCTRLE Register Field Description

Field Description
7-3
Reserved bits — Not for user access.
Reserved
LOGAMP AZ Sequencer Control — Control bits for AZ and trim within the LOGAMP.
X00 Nominal AZ sequence - recommended setting
X01 Short amp output release, max delay with Rects
2-0
X10 Short amp output release, max delay with Amp input
AZSC
X11 All short, max delay with end of AZ
0XX Nominal sensitivity trim - recommended setting
1XX Sensitivities shifted by - 4 trim steps

12.17.8 LFR Control Register D (LFCTRLD, LPAGE = 1)

The LFCTRLD register contains two control bits for the LF detector and decoder. It is only accessible when the LPAGE bit is set.

$0022 Bit 7 6 5 4 3 2 1 Bit 0

R DEQS
AVFOF[1:0] AZDC[1:0] ONMODE CHK125[1:0]
W
Reset: 0 0 0 0 0 0 0 0

Figure 85. LFR Control Register D (LFCTRLD, LPAGE = 1)

Table 67. LFCTRLD Register Field Descriptions

Field Description
SUM AZ release delay — Control the delay between falling edge of SUM d_az_en input and falling edge of internal AZ control
line.
7-6
00 No delay
AVFOF
01 No delay
[1:0]
10 One-half of 125 kHz clock period delay - recommended setting
11 One and one-half of 125 kHz clock periods delay
DeQing status register — This read-only status bit allows the reading of the effective activation of the DeQing System.
5
0 DeQing system not activated
DEQS
1 DeQing system activated
AZ Digital Control of AZ triggering — In data receive mode, this bits control the triggering of AZ sequence with respect to both
LFCPTAZ value (ref. LFCTRLB register) and the state of the demodulation input data state.
4-3 00 AZ starts after LFCPTAZ numbers of input data edges.
AZDC 01 Z starts randomly adding -1, 0 or 1 to LFCPTAZ value between each AZ.
[1:0] 10 AZ starts after LFCPTAZ numbers of input data edges and when the input data (d_data) state is 0.
11 AZ starts after LFCPTAZ numbers of input data edges and when the input data (d_data) state is 1 -
recommended setting.
ON Behavior Mode — This read/write bit selects how an error will affect the ON time. This bit is cleared by reset.
2
0 Any error will stop the ON time.
ONMODE
1 If remaining ON time, the LFR will go back to sniff mode at any error - recommended setting.

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Table 67. LFCTRLD Register Field Descriptions (continued)

Field Description
Accurate 125 kHz Check — The bit controls the CARVAL frequency check method.
00 CARVAL validates on n (2*32 s packets), n depending on LFCDTM value - recommended setting for Low
Sensitivity mode.
1-0
01 CARVAL validates on n (1*32 s packet + 4*8 s packets), n depending on LFCDTM value - optional recommended
CHK125
setting for High Sensitivity mode.
[1:0]
10 CARVAL validates n (8*8 s packet), n depending on LFCDTM value - optional recommended
setting for High Sensitivity mode.
11 Same as 00.

NOTE
Setting CHK125[1:0] to either 0x01 or 0x10 increases the immunity to noise and therefore
carries the side effect of narrowing the 125 kHz carrier bandwidth tolerance.

12.17.9 LFR Control Register C (LFCTRLC, LPAGE = 1 )

The LFCTRLC register contains control bits for the LF detector and decoder. It is only accessible when the LPAGE bit is set.

$0023 Bit 7 6 5 4 3 2 1 Bit 0

R
AMPGAIN[1:0] FINSEL[1:0] AZEN LOWQ[1:0] DEQEN
W
Reset: 1 1 0 0 1 0 0 1

Figure 86. LFR Control Register C (LFCTRLC, LPAGE = 1)

Table 68. LFCTRLC Register Field Descriptions

Field Description
3rd Amplifier gain — These bits controls the 3rd amplifier gain.
7-6 00 Gain of 2 - recommended setting
AMPGAIN 01 Gain of 3
[1:0] 10 Gain of 4
11 Gain of 6
Final stage select — These bits select the final stage of the LOGAMP.
5-4 00 Continuous time biasing - Fixed Gain 6
FINSEL 01 Continuous time biasing - Programmable Gain - recommended setting
[1:0] 10 4th rectifier disabled
11 4th rectifier disabled
Data AZ enable — This bit allows the AZ sequence during data frame.
3
0 AZ during data disabled
AZEN
1 AZ during data enabled - recommended setting
DeQing Resistor — These bits select the resistor added in parallel to the input network.
2-1 00 4 k
LOWQ 01 2 k
[1:0] 10 1 k
11 500 
DeQing System enable — The bit controls the DeQing system.
0
0 DeQing disabled.
DEQEN
1 DeQing enabled.

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12.17.10 LFR Control Register B (LFCTRLB, LPAGE = 1)
The LFCTRLB register contains control bits for the LF detector and decoder. It is only accessible when the LPAGE bit is set.

$0024 Bit 7 6 5 4 3 2 1 Bit 0

R
HYST[1:0] LFFAF LFCAF LFPOL LCPTAZ[2:0]
W
Reset: 1 1 0 0 0 1 0 0

Figure 87. LFR Control Register B (LFCTRLB, LPAGE = 1)

Table 69. LFCTRLB Register Field Descriptions

Field Description
Control slicer hysteresis
7-6 00 20 mV hysteresis
HYST 01 40 mV hysteresis
[1:0] 10 50 mV hysteresis
11 30 mV hysteresis - recommended setting
Average filter bi-phase filtering control — Activates bi-phase filtering and control offset value
5-4 00 Standard low pass filtering activated - recommended setting
LFFAF; 01 Standard low pass filtering activated
LFCAF 10 Bi-phase filtering activated - Low offset from input signal low level
11 Bi-phase filtering activated - High offset from input signal low level
LF Manchester Polarity Select — This read/write bit selects the polarity of the transition in the middle of the bit time. The LFPOL
3 is not used in Carrier mode. Reset clears LFPOL bit.
LFPOL 0 Zero is falling edge in middle of a bit time, one is a rising edge in the middle of bit time.
1 Zero is rising edge in middle of a bit time, one is a falling edge in the middle of bit time.
2-0
LF auto-zero counter — Applications to set these bits to 0x06 for proper LF operation. These bits tune the minimum number of
LFCPTAZ
data edges between two auto-zero requests during a data frame.
[2:0]

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12.17.11 LFR Control Register A (LFCTRLA, LPAGE = 1)
The LFCTRLA register contains control bits for the LF detector and factory test selects. It is only accessible when the LPAGE bit
is set.

$0025 Bit 7 6 5 4 3 2 1 Bit 0

R
LFCC[3:0]
W
Reset: 0 0 0 0 0 0 0 0
= Reserved

Figure 88. LFR Control Register A (LFCTRLA, LPAGE = 1)

Table 70. LFCTRLA Register Field Descriptions

Field Description
7-4
Reserved bits — Not for user access.
Reserved
LF Successive Carrier Validations Counter — The value of the LFCC[3:0] bits define how many times the carrier detect
sample ON time detected an LF carrier signal before the LFCDF flag bit set. The flag will be risen when the number of ON
samples with a detected carrier greater than the LFCDTM[3:0] reaches the value of the LFCC[3:0] bits plus one. The internal
3-0 count of detected carrier pulses will increment the count as long as they are consecutive samples. When a sample is encountered
LFCC without any detected carrier the count will be reset.
[3:0] The LFCC register is considered reset in data mode. The first carrier validation will lead to start up of the receiver chain.
This feature allows the user to define a number of consecutive carrier detections are required before the flag is risen; and is useful
in detecting long duration carrier pulses.
This counter is disabled if TOGMOD = 1.

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13 RF Module
It is not intended that the RFM may be actively powered up and/or transmitting RF data while physical parameter measurements
are being made; or during the time that the LFR may be actively receiving/decoding LF signals. The resulting interactions will
degrade the performance of the RF output spectrum.
The FXTH870xD consists of an RF module (RFM) with external crystal-driven oscillator, VCO, fractal-n PLL and RF output
amplifier (PA) for an antenna. It also contains a small state machine controller, random time generator and hardware data buffer
for automated output or direct control from the MCU. The overall block diagram is shown in Figure 89.

256-BIT
DATA BUFFER

RF LFSR MODULATION RF
RINT
STATE RANDOM CONTROL
MFO MACHINE GEN
RF
AMP

MCU CONTROL
REGISTERS
AND LOGIC
DX
500 kHz
FRACTIONAL-N
DIVIDER

XI
CRYSTAL PHASE LOW-PASS
VCO
OSCILLATOR DETECTOR FILTER
XO

RF
LVD

AVDD VOLT RF
REG AVDD
AVSS
VREG

Figure 89. RF Transmitter Block Diagram

13.1 RF Data Modes

There are two modes of operation in using the RF output in either the data buffer mode or MCU direct mode.

13.1.1 RF Data Buffer Mode

In the RF data buffer mode the transmissions are sent by dedicated logic hardware while the MCU can be put into a low power
mode until the transmission is completed. This RF state machine is clocked by the MFO which is enabled when the SEND bit is
set and when any of the LFR, SMI or MCU are operating.
The RF data buffer consists of a dedicated RFM state machine and a 256-bit data buffer. The RF data buffer is loaded with
whatever data pattern the user software creates. The number of data bits to be sent is selected by the FRM[7:0] control bits. The
control logic is triggered by the SEND control bit when it is time to transmit the data which is sent to the RF stage after being
encoded as either Manchester, Bi-Phase or NRZ data according to the method selected by the CODE[1:0] bits as described in
Section 13.17.
Before the data can be transmitted the RFM control logic enables the external crystal oscillator and phase-locked-loop to initialize
before the RF output stage can begin transmission.

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The external crystal connected to the X0 and XI pins provides the carrier frequency as well as the data rate clock needed for the
data rates associated with the OOK or FSK modulation. Therefore the tolerance on the data rate will depend on the
characteristics of the external crystal.
Once the data buffer is emptied the data transfer stops; the RF output stage is turned off; and the SEND control bit is cleared and
an interrupt of the MCU may be generated to wake it from the STOP1 mode. The user can test that the transmission has
completed by reading back the state of the SEND control bit or the RFIF status bit.
There is also the option to send the same data frame from 1 to 16 times with interlaced time intervals when the RF transmitter
PA output stage is off. If multiple frames of data are to be transmitted within a datagram the spacing before the first frame and
between subsequent frames can be controlled by the RFM state machine in several ways:
1. Use of a programmable timer (random, base time, time adder).
2. No time delays.
In addition, the RFM crystal oscillator, VCO and PLL can be turned off during any interframe timing by use of the IFPD bit.
When using the data buffer mode the user’s software should not change any bits in the RFM registers after the SEND has been
set and the transmission is still in progress. Changing RFM register contents during a transmission can lead to data faults or
errors.

13.1.2 MCU Direct Mode

When the CODE[1:0] bits are both set the encoding is controlled directly by the MCU where the data to the RF output depends
on the state of the DATA bit and the selected modulation scheme. In this mode the user software must control the RF output stage
to power up (using the SEND control bit), WAIT for the RF output stage to stabilize (monitor the RCTS status bit) and clock the
DATA to the RF output stage. In this mode the data rate and its stability will depend on the internal HFO oscillator.
Any transfers of data from the MCU will use the DATA bit which will be reflected as modulated data on the RF pin once the RF
output stage is set up to transmit. The maximum data rate in this mode will depend on the complexity of the user software and
the MCU clock rate.
The POL bit in this case simply inverts the state of the DATA bit before it drives the RF output stage.
The accuracy of the data rate in the MCU direct mode is directly dependant on the HFO accuracy.

13.2 RF Output Buffer Data Frame

When using the RF data buffer mode each frame of data is sent as 2 to 256 bits per frame with a possible two trailing bits for an
end-of-message, EOM, as shown in Figure 90. The actual data being transmitted in a given data frame and any combinations of
data frames into a single datagram is dependent on the user software.
The number of frames sent in a given datagram can be from 1 to 16 based on the FNUM[3:0] bits in the RFCR3. The 256-bit
buffer is divided into two pages of 128 bits as selected by the RPAGE bit in the RFCR2.
The data buffer is unloaded to the RF output starting with the least significant bit (RFD0) in the least significant byte (RFB0) up
through the most significant bit (RFD127) in the most significant byte (RFB15). This is often referred to as “little-endian” data
ordering.

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 256 2

EOM
Maximum RFB0 RFB1 RFB2 RFB3 RFB4 RFB5 RFBA RFBB RFBC RFBD RFBE RFBF
258-Bit Format

80
RFB0 RFB1 RFB2 RFB3 RFB4 RFB5 RFB6 RFB7 RFB8 RFB9
80-Bit Format

53 2

EOM
53-Bit Format RFB0 RFB1 RFB2 RFB3 RFB4 RFB5 Optional EOM
with all byte lengths

RFB6
Bits [2:0]
2
Minimum
2-Bit Format
Data in each byte defined by user software
RFB0
Bits [1:0]

Figure 90. Data Frame Formats

13.2.1 Data Buffer Length

The number of bits sent in a given transmission frame is selected by the FRM[7:0] control bits encoded as a direct binary number
plus one. This gives a range of 2 through 256 bits. Data written to data buffer bits above the highest bit number will be ignored.
Transmission always begins with the data written in the RFB0 location. When the requested number of bits have been transmitted
an interrupt to the MCU can be generated if the RFIE bit is set.

13.2.2 End of Message (EOM)

If the EOM control bit is set, then at the end of the data frame there will be carrier for a period of two bit times at level high for the
OOK modulation modes or fDATA1 for the FSK modulation modes. Following the EOM period there will be no carrier for either the
OOK or FSK modes. If the EOM control bit is clear, no EOM period will be added to the transmission.

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13.3 Transmission Randomization
When there are two or more different transmitters, the clock rates of each may drift into synchronism with each other; and there
is the possibility of RF data collisions and the loss of data from both transmitters. In order to reduce possible RF data collisions
each transmission will contain from 1 to 16 frames of data. Each frame may be spaced at after the initially timed transmission
start time and between any two data frames as shown in Figure 91.

Time Not To Scale 1 to 16 Data Frames

With Identical Data

t0

SPACE DATA FRAME SPACE DATA FRAME SPACE DATA FRAME

Start of Time
Interval for
Datagram Interframe Intervals

Initial Interval

tDATA

Space Intervals have No Carrier Frequency Output, equivalent to Data = 0

and may have the RFM crystal oscillator, VCO and PLL turned off by the IFPD bit.

Figure 91. Datagram Overview

The generation of the initial and interframe time intervals can be done with a combination of a programmable counter, a pseudo-
random interval generator and a frame counter as shown in Figure 92. The initial time interval can be done by adjusting the start
time using the MCU or using this interval timing generator.

Time Not To Scale

t0
Initial Interval Interframe Interval 1 Interframe Interval 2

tBASE 40 x tRAND tBASE tRAND tFN tBASE tRAND tFN

Start of Time
Interval for
Datagram
tBASE, tRAND and tFN may be all zero in the initial interval.
tBASE, tRAND and tFN may be all zero in an interframe interval.
All interframe intervals may have different tBASE, tRAND and tFN times.

Note: If tBASE and tFN are both set to non-zero, and tRAND is set to 0, the system
will decrement both tBASE and tFN simultaneously rather than serially, such that the
effective Interframe Interval will be equal to the larger of tBASE or tFN settings.

Figure 92. Initial and Interframe Timing

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13.3.1 Initial Time Interval
When generating an initial time interval the MCU loads the RFM interval generator variables and then goes into the STOP1 mode.
When the initial time interval ends the data in the RFM data buffer is automatically sent and the MCU will wake at the end of the
transmission. The initial time interval is made up of two components:

t = t + 40  t Eqn. 10
INIT BASE RAND
where:
tINIT = Total time interval before first frame is transmitted in ms
tBASE = Base time in ms; 5 ms not recommended
tRAND = Pseudo-random time in ms based on a Galois 7-bit LFSR
The components of this time are described in the following sections.

13.3.2 Interframe Time Intervals

When generating an interframe time interval the MCU loads the RFM interval generator variables and then goes to the STOP1
mode. When the interframe time interval ends the data in the RFM data buffer is automatically sent and the MCU will wake at the
end of the transmission. The interframe time interval is made up of three components:

t = t +t +t Eqn. 11
IFRM BASE RAND FN
where:
tIFRM = Total time interval between each transmitted frame in ms
tBASE = Base time in ms; 5 ms not recommended
tFN = Time adder in ms for frame number
tRAND = Pseudo-random time in ms based on a Galois 7-bit LFSR
The components of this time are described in the following sections.

13.3.3 Base Time Interval

The base time interval, tBASE, is used in the initial time interval and in datagram transmissions with two or more frames. The
programmable frame space interval is based on a simple 8-bit, count-down timer as described by the RFBT[7:0] control bits in
the RFCR4 register. This time interval is forced to zero when the RFBT[7:0] are all clear.
The range of the base time must be set to 0 or between 5 and 255 ms using a clock generated from the MFO divided by 125.

13.3.4 Pseudo-Random Time Interval

The pseudo-random time interval, tRAND, is used both in the initial and the interframe time intervals if the LFSR[6;0] bits are set
to something other than all zeros. When the ISPC bit is set the pseudo-random initial time interval before the first data frame will
be 40 times the value of tRAND.
When the LFSR[6:0] bits are used the tRAND time will vary based on a pseudo-random generated binary number using a Galois
linear feedback shift register (LFSR) implemented using the primitive polynomial for a 7-stage register as shown in Figure 93.
This LFSR creates a sequence of 127 binary numbers including $01 through $3F which are each repeated only once in each
sequence of 127 clocks of the shift register. The LFSR is initialized to $40 during power up of the device. When a random interval
is to be determined the contents of the LFSR are sampled as the “random number” for calculating the required interval time.
Following the use of the random interval the LFSR is clocked once to advance it to the next pseudo-random number.
The range of the pseudo-random time is 1 to 127 ms using a clock generated from the MFO divided by 125. The current value
of the LFSR can be changed and/or read by the LFSR[6:0] bits in the RFCR5 register.

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 7-BIT Random Number
S0 S1 S2 S3 S4 S5 S6

S
D Q D Q D Q D Q D Q D Q D Q

R R R R R R

CLK

RFMRST
7 3
Galois Primitive Polynomial = X + X + 1

Figure 93. LFSR Implementation

A value of all zeros in the LFSR will remain unchanged with every clock input and cannot be used as a starting “seed.”
The resulting range of times for the initial and interframe pseudo-random time will be as given in Table 71 for both the design
center and the variation resulting from the tolerance of the MFO clock.

Table 71. Randomization Interval Times

Time Randomization Time Interval Including MFO Tolerance (ms)

Ideal Time Interval (ms)
Interval Number Minimum Maximum

1 40 37.2 42.8
Initial
127 5080 4347.2 5434.6

1 1 0.93 1.07
Interframe
127 127 118.1 135.9

13.3.5 Frame Number Time

The frame number time, tFN, is only used between frames and is based on a selectable time from 0 to 63 ms and the number of
the frame that was just transmitted as given in Table 72. If the frame number time is not used, the value of the selected time
should be set to zero. The maximum number of frames is defined by the FNUM[3:0] control bits.
The range of the frame number time is a multiple of 0 to 63 ms using a clock generated from the MFO divided by 125. The value
of this time multiple can be changed by the RFFT[5:0] bits in the RFCR6 register.

Table 72. Frame Number Interval Times

Value of Number of Frame Interval Where Nominal Frame Number Time Interval Added (ms)
FNUM[3:0] Frames Time Added Minimum Maximum
0 1 None n/a n/a
1 2 1-2 1 63
2 3 2-3 2 126
3 4 3-4 3 189
4 5 4-5 4 252
5 6 5-6 5 315
6 7 6-7 6 378
7 8 7-8 7 441
8 9 8-9 8 504

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Table 72. Frame Number Interval Times (continued)

Value of Number of Frame Interval Where Nominal Frame Number Time Interval Added (ms)
FNUM[3:0] Frames Time Added Minimum Maximum
9 10 9 - 10 9 567
10 11 10 - 11 10 630
11 12 11 - 12 11 693
12 13 12 - 13 12 756
13 14 13 - 14 13 819
14 15 14 - 15 14 882
15 16 15 - 16 15 945

13.4 RFM in STOP1 Mode

The entire RF transmitter digital section can remain powered up, if enabled by the RFEN bit (see Section 5.3), when the MCU
goes into the STOP1 mode.

13.5 Data Encoding

The CODE[1:0] control bits select either Manchester, Bi-Phase, NRZ or MCU direct data encoding of each data bit being
transferred from the RF data buffer to the RF output stage. Further, the polarity of the selected encoding method can be inverted
using the POL control bit.

13.5.1 Manchester Encoding

When the CODE[1:0] bits are both clear the data is Manchester encoded format, with data transmitted as a transition in voltage
occurring in the middle of the bit time. The polarity of this transition is selected by the POL bit. When the POL bit is cleared, then
a logical LOW is defined as an increase in signal in the middle of a bit time and a logical HIGH is defined as a decrease in signal
in the middle of a bit time as shown in Figure 94. When the POL bit is set, then a logical LOW is defined as an decrease in signal
in the middle of a bit time and a logical HIGH is defined as a increase in signal in the middle of a bit time as shown in Figure 95.
Since there is always a transition in the middle of the bit time there must also be a transition at the start of a bit time if consecutive
“1” or “0” data are present.

13.5.2 Bi-Phase Encoding

When the CODE[1:0] bits are 0:1 then the data is Bi-Phase encoded format, with data transmitted as the presence or absence
of a transition in signal in the middle of the bit time. The polarity of this transition is selected by the POL bit. Unlike Manchester
coding there is always a signal transition at the boundaries of each bit time. When the POL bit is cleared, then a logical HIGH is
defined as no change in signal in the middle of a bit time and a logical LOW is defined as a change in the signal in the middle of
a bit time as shown in Figure 96. When the POL bit is set, then a logical HIGH is defined as a change in signal in the middle of
a bit time and a logical LOW is defined as no change in the signal in the middle of a bit time as shown in Figure 97. Since there
is always a transition at the ends of the bit time consecutive bits of the same state may have two signal states (high or low) during
the middle of the bit time.

13.5.3 NRZ Encoding

When the CODE[1:0] bits are 1:0 then the data is NRZ encoded format, with data transmitted as either a high or low for the
complete bit time. The polarity of this state is selected by the POL bit. The Manchester and Bi-Phase encoding can actually be
created using NRZ encoding running at twice the desired data rate.

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 LOW HIGH
BIT BIT
FSK = fRF+ f OOK = fRF

FSK = fRF - f OOK = OFF

Bit Time Bit Time

Consecutive “0”
Data Bits

Consecutive “1”
Data Bits

“001101”
Data Bits

Figure 94. Manchester Data Bit Encoding (POL = 0)

LOW HIGH
BIT BIT
FSK = fRF+ f OOK = fRF

FSK = fRF - f OOK = OFF

Bit Time Bit Time

Consecutive “0”
Data Bits

Consecutive “1”
Data Bits

“001101”
Data Bits

Figure 95. Manchester Data Bit Encoding (POL = 1)

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 LOW LOW HIGH HIGH
BIT BIT BIT BIT
FSK = fRF+ f OOK = fRF
FSK = fRF - f OOK = OFF

Bit Time Bit Time Bit Time Bit Time

Consecutive “0”
Data Bits

Consecutive “1”
Data Bits

“001101”
Data Bits

Figure 96. Bi-Phase Data Bit Encoding (POL = 0)

LOW LOW HIGH HIGH

BIT BIT BIT BIT
FSK = fRF+ f OOK = fRF
FSK = fRF - f OOK = OFF

Bit Time Bit Time Bit Time Bit Time

Consecutive “0”
Data Bits

Consecutive “1”
Data Bits

“001101”
Data Bits

Figure 97. Bi-Phase Data Bit Encoding (POL = 1)

13.6 RF Output Stage

The RF output stage consists of a PLL, control logic and an output RF amplifier. Data is sent to the RF output stage from either
the RF data buffer or the DATA bit in the RFCR3 depending on the selected mode of operation as described in Section 13.1.
The RF output stage is enabled by the state of the SEND control bit. The PLL in the RF output stage will signal back via the RCTS
status bit when the PLL is locked and ready to transmit.

13.6.1 Modulation Method

The modulation control bit, MOD, described in Section 13.18, sets the modulation of the RF signal will be either amplitude shift
keying (OOK) or frequency shift keying (FSK) with several options for the frequency shift.
When operating in the FSK mode the internal, fractional-n PLL divider will be used to create the two carrier frequencies for data
zero and data one. This method is more effective and robust than “pulling” the external crystal in order to shift the carrier
frequency.

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13.6.2 Carrier Frequency
The carrier frequency is established mainly by the external crystal used, but a centering of the fractional-n PLL provides more
precise control. If the CF control bit is clear the PLL will be configured for a carrier center frequency of the 315 MHz. If the CF
control bit is set the PLL will be configured for a carrier center frequency of the 434 MHz.

13.6.3 RF Power Output

The maximum power output from the RF pin can be adjusted to one of 21 levels using the PWR[4:0] bits.

13.6.4 Transmission Error

Any transmission will be aborted if one of the following occurs:
1. The RCTS signal does not become active within the tLOCK time.
2. The PLL falls out of lock after once being set and the SEND bit is still active.
3. The XCO monitor output falls.
If either of these cases occurs the RF output will be turned off; the SEND control bit will be cleared; and the transmission error
status flag, RFEF, will be set. The RFEF bit triggers an interrupt of the MCU if the RFIEN is set. The RFEF bit is cleared by writing
a logical one to the RFIAK bit.

13.6.5 Supply Voltage Check During RF Transmission

A separate low voltage detector can be enabled during the RF transmission and a status bit checked for low voltage drops due
to a weak battery during the higher transmission currents. This RF LVD can be enabled by setting the RFLVDEN bit and the
resulting status is reported on the RFVF bit. The RFVF bit can be cleared by writing a logical one to the RFIAK bit if the supply
voltage has risen above the detect threshold. Further, if the voltage falls far enough for the VCO and PLL to fall out-of-lock, then
the RF output will be turned off and the transmission will be terminated.

13.6.6 RF Reset (RFMRST)

The RF state machine, crystal oscillator, PLL and VCO can be reset to the initial off state by the RFMRST signal generated by
one of the following methods:
1. Internal RFM power-on reset (RFPOR).
2. Writing a one to the RFMRST bit in the RFCR7.
Any of these reset methods will not alter any data stored in the data buffer.

13.7 RF Interrupt
The RFM will interrupt the MCU when the SEND bit is cleared at the end of a data buffer transmission. This interrupt occurs at
the end of a programmed set of frames. If the number of frame count FNUM[3:0] is set to zero, then only one frame is sent and
the interrupt occurs at the end of that first frame transmitted. If the number of the frame count is greater than zero, then the
interrupt will be generated depending on the state of the IFID bit.
The interrupt will also create a flag bit, RFIF, which can be cleared by writing a logical one to the RFIAK bit. The interrupt can be
enabled/disabled by the RFIEN bit.

13.8 Datagram Transmission Times

In order to comply with FCC requirements in the US market the periodically transmitted datagram must be less than 1 second in
length and be separated by an off time that is at least 10 seconds or at least 30 times longer than the transmission time, whichever
is longer. The user software must adhere to this ruling for products intended for the US market.

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13.9 RFM Registers
The RFM contains twelve registers to control its functions and 32 registers to provide access to the output data buffer.

13.9.1 RFM Control Register 0 - RFCR0

The RFCR0 register contains eight control bits for setting the output data rate of the RFM as described in Figure 98.

$0030 Bit 7 6 5 4 3 2 1 Bit 0

R
BPS[7:0]
W
RFMRST: 0 0 1 1 0 1 0 0

Figure 98. RFM Control Register 0 (RFCR0)

Table 73. RFCR0 Field Descriptions

Field Description
Data Rate - The BPS[7:0] control bits select the data rate for the transmitted datagrams as described by the following equation:

f 5
XTAL 5x10
f = ------------------------------------- = -------------------------
7–0
DATA 52   BPS + 1   BPS + 1 
BPS[7:0] where:
fDATA= Data rate in bits/second
fXTAL= External crystal frequency in Hz = 26 MHz
BPS= Value of data rate code (BPS[7:0])
Examples of the value for common data rates are given in Table 74. The BPS[7:0] control bits are set to $34 by the RFMRST
signal which results in a default data rate of 9600 bits/sec.

Table 74. Data Rate Option Examples

BPS[7:0] BPS[7:0]
Data Rate Data Rate
Decimal Value Decimal Value
Target Nominal fXTAL = 26 MHz Target Nominal fXTAL = 26 MHz
2000 bps 2000.0 249 4800 bps 4807.7 103
2400 bps 2403.8 207 5000 bps 5000.0 99
4000 bps 4000.0 124 9600 bps 9615.4 51
4500 bps 4504.5 110 19200 bps 19230.8 25

The BPS[7:0] bits are set to $34 by an RFMRST signal which results in a default data rate of approximately 9600 bps.

13.10 RFM Control Register 1 - RFCR1

The RFCR1 register contains eight control bits for the RFM as described in Figure 99.

$0031 Bit 7 6 5 4 3 2 1 Bit 0

R
FRM[7:0]
W
RFMRST: 0 0 0 0 0 0 0 0

Figure 99. RFM Control Register 1 (RFCR1)

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Table 75. RFCR1 Field Descriptions

Field Description
Frame Bit Length - The FRM[7:0] control bits select the number of bits in each datagram. The number of bits is determined by
7-0
the binary value of the FRM[7:0] bits plus one. This makes the range of bits from 2 to 256. A value of $00 for the FRM[7:0] control
FRM[7:0]
bits will result in no frames being sent. The FRM[7:0] control bits are cleared by RFMRST signal.

13.11 RFM Control Register 2 - RFCR2

The RFCR2 register contains eight control bits for the RFM as described in Figure 100.

$0032 Bit 7 6 5 4 3 2 1 Bit 0

R
SEND RPAGE EOM PWR[4:0]
W
RFMRST: 0 0 0 0 0 0 0 0

Figure 100. RFM Control Register 2 (RFCR2)

Table 76. RFCR2 Field Descriptions

Field Description
Transmission Start Control- The SEND control bit starts the transmission of data held in the RFM data buffer according to the
bit length specified by the FRM[7:0] bits. The SEND control bit is automatically cleared when the data buffer transmission has
7
ended or by the RFMRST signal. A transmission can be prematurely interrupted by writing a logical zero to the SEND bit.
SEND
0 Data transmission ended or transmission not in progress.
1 Start data transmission or transmission in progress.
Buffer Page Select — The RPAGE bit will select the lower or upper 16 bytes of the RFM data buffer when writing/reading to the
RFD0-RD15 registers. This bit also selects between the lower and upper banks of RFM registers at addresses $0038 through
6
$003B. This bit is cleared by a reset of the MCU.
RPAGE
0 Select the lower 16 bytes of the RFM data buffer.
1 Select the upper 16 bytes of the RFM data buffer.
End Of Message - The EOM control bit selects whether there will be two data bit times of data 1 carrier state at the end of each
5 datagram. The EOM control bit is cleared by a RFMRST.
EOM 0 EOM bit times not added.
1 EOM bit times added.

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Table 76. RFCR2 Field Descriptions (continued)

Field Description
RF Amplifier Power Level - The PWR[4:0] control bits select the optimum power output of the RF power amplifier. These power
output levels assume optimal matching network to the RF pin. The PWR[4:0] control bits are cleared a RFM reset. The PWR
control bits are initially set to 0x00. This setting targets -10 dBm typical power output. The PWR control bits scale the typical
output power level from -1.5 to 8 dBm in steps of 0.5 dB and fixes the low power level mode to -10 dBm, The power control range
is defined as follows:
00000 set output power level to -10 dBm (Default Value)
00001 set output power level to -1.5 dBm
00010 set output power level to -1.0 dBm
00011 set output power level to -0.5 dBm
00100 set output power level to 0.0 dBm
00101 set output power level to 0.5 dBm
00110 set output power level to 1.0 dBm
00111 set output power level to 1.5 dBm
4:0 01000 set output power level to 2.0 dBm
PWR[4:0] 01001 set output power level to 2.5 dBm
01010 set output power level to 3.0 dBm
01011 set output power level to 3.5 dBm
01100 set output power level to 4.0 dBm
01101 set output power level to 4.5 dBm
01110 set output power level to 5.0 dBm
01111 set output power level to 5.5 dBm
10000 set output power level to 6.0 dBm
10001 set output power level to 6.5 dBm
10010 set output power level to 7.0 dBm
10011 set output power level to 7.5 dBm
10100 set output power level to 8.0 dBm
Codes greater than 10100 are reserved for test purposes and should not be used.

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13.11.1 Power Working Domains
The working areas of the RF transmitter are divided into several domains as defined in Figure 101.
PTYP
TA = 25 °C to 60 °C and VDD = 2.5 V to 3.6 V
PTYP is where the power step is adjusted to guarantee 5 dBm. The power consumption in this domain is specified at 5 dBm output
power step at nominal conditions of TA = 25 °C and VDD = 3 VDC.
PMIN
PMIN is where the power step is adjusted to guarantee a minimum of 3 dBm as shown in Figure 101. The power consumption in
this domain is given as the maximum consumption at whatever temperature of supply voltage condition. The PMIN domain is
subdivided into two areas according to the lowest supply voltage encountered (1.8 or 2.5 VDC).
PMIN_COLD
TA = -40 °C to 0 °C and VDD = 1.8 V to 3.6 V
PMIN_HOT
TA = 0 °C to 25 °C and VDD = 2.5 V to 3.6 V
TA = 60 °C to 125 °C and VDD = 2.5 V to 3.6 V

Typical Consumption

VDD = 3.6 V

VDD = 3.0 V
PTYP
PMIN_COLD PMIN_HOT PMIN_HOT

VDD = 2.5 V

VDD = 1.8 V

TA = -40 °C TA = 0 °C TA = 25 °C TA = 60 °C TA = 125°C

Figure 101. RF Power Domains

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13.12 RFM Control Register 3 - RFCR3
The RFCR3 register contains five control bits for the RFM as described in Figure 102 which sets the number of frames in each
RF datagram.

$0033 Bit 7 6 5 4 3 2 1 Bit 0

R
DATA IFPD ISPC IFID FNUM[3:0
W
RFMRST 0 0 0 0 0 0 0 0

Figure 102. RFM Control Register 3 (RFCR3)

Table 77. RFCR3 Field Descriptions

Field Description
Data State - The DATA bit determines the output state of the RF power amplifier when the RFM is in the MCU direct control mode
7 (CODE[1:0] = 11)
DATA 0 RF output state low.
1 RF output state high.
Interframe Power Down — The IFPD control bit selects whether the XCO and associated analog blocks are powered down
during interframe timing caused by the RFM. The IFPD control bit is cleared by the RFMRST signal.
6 0 The XCO remains powered up as long as the SEND bit is set.
IFPD 1 The XCO is powered down during RFM controlled interframe timing events.
The restart of these functions will start 1 ms before the end of the timing interval if another
frame is to be transmitted.
Initial Random Space— When the ISPC bit is set the initial time delay before the first frame will be enabled. This bit is cleared
5 by an RFM reset.
ISPC 0 No initial time interval.
1 Initial time interval enabled.
Interframe Interrupt Delay — The IFID control bit selects whether the RFIF bit is set and the MCU is interrupted at the end of
each frame sent or at the end of the last frame in a multiple frame message. The IFID control bit is cleared by the RFMRST signal.
4
0 The RFIF bit is set and the MCU interrupted if the RFIEN bit is set, after the last frame transmitted.
IFID
1 The RFIF bit is set and the MCU interrupted if the RFIEN bit is set, only after the last frame
plus an additional interframe message is transmitted.
3-0 FNUM[3:0] — The FNUM[3:0] bits set the number of frames transmitted in each RF datagram. The frames will be randomly
FNUM spaced apart as described it Section 13.3.These bits are cleared by an RFM reset. The number of frame transmitted is the binary
[3:0] number plus one.

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13.13 RFM Control Register 4 - RFCR4
The RFCR4 register contains eight control bits to set the initial and interframe timing base timing variable as described in
Figure 103. A RFMRST signal clears the RFBT[7:0] bits.

$0034 Bit 7 6 5 4 3 2 1 Bit 0

R
RFBT[7:0]
W
RFMRST: 1 0 0 0 0 0 0 0

Figure 103. RFCR4 Register - Base Time Variable

Table 78. RFCR4 Field Descriptions

Field Description
7:0 Base Timer - The RFBT[7:0] control bits select the interframe timing between multiple frames of transmission. The base time
RFBT value is equal to a nominal one millisecond for each count of the RFBT[7:0] bits. The RFBT[7:0] control bits are cleared by the
[7:0] RFMRST signal and must be set to either 0 or between 5 and 255.

13.14 RFM Control Register 5 - RFCR5

The RFCR5 register contains eight control bits to set the initial and interframe random timing variable as described in Figure 104.
A RFMRST signal clears the LFSR[6:0] bits causing the random time variable to be ignored.

$0035 Bit 7 6 5 4 3 2 1 Bit 0

R
BOOST LFSR[6:0]
W
RFMRST: 0 0 0 0 0 0 0 0

Figure 104. RFCR5 Register - Pseudo-Random Time Variable

Table 79. RFCR5 Field Descriptions

Field Description
BOOST - This bit controls the VCO power consumption in order to decrease the phase noise required by the Japanese
7 regulation. The BOOST control bit is cleared by the RFMRST signal.
BOOST 0 The VCO runs at its lower power consumption level (higher phase noise).
1 The VCO runs at its higher power consumption level (lower phase noise).
Pseudo-Random Timer- The LFSR[6:0] bits select the current seed value of the LFSR when enabling pseudo-random timing
intervals when any of the LFSR[6:0] bits are set. The value written to this register is loaded into the actual LFSR when the SEND
bit is set. The time value is equal to a nominal one millisecond for each count of the resulting LFSR[6:0] bits.

6:0 A value of $00 placed in the LFSR causes the LFSR to stay at the $00 state on each clocking of the LFSR. To cause the LFSR
LFSR[6:0] to cycle through its pseudo-random number sequence requires that any value other than $00 be written to the LFSR[6:0] bits.

Note: If RFBT[7:0] and RFFT[5:0] are both set to non-zero, and LFSR[6:0] is set to 0x00, the system will decrement both RFBT
and RFFT simultaneously rather than serially, such that the effective Interframe Interval will be equal to the larger of RFBT or
RFFT settings.

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13.15 RFM Control Register 6 - RFCR6
The RFCR6 register contains eight control bits to set the initial and interframe frame number timing variable as described in
Figure 105. A RFMRST signal clears the RFFT[5:0] bits.

$0036 Bit 7 6 5 4 3 2 1 Bit 0

R
VCO_GAIN[1:0] RFFT[5:0}
W
RFMRST: 1 0 0 0 0 0 0 0

Figure 105. RFCR6 Register - Frame Number Time - RFTS[1:0] = 1:0

Table 80. RFCR6 Field Descriptions

Field Description
7:6
VCO Gain Selection - These bits control the VCO gain. The VCO_GAIN[1] bit is set and the VCO_GAIN[0] bit is cleared by the
VCO_GAIN
RFMRST signal. Not normally need to be adjusted by the end user.
[1:0]
Frame Number Timer - The RFFT[5:0] control bits select the interframe timing between multiple frames of transmission. The
5:0
time value is equal to a nominal one millisecond for each count of the RFFT[5:0] bits multiplied by the frame number of the last
RFFT[5:0]
transmitted frame. The RFFT[5:0] control bits are cleared by the RFMRST signal.

13.16 RFM Control Register 7 - RFCR7

The RFCR7 register contains four control bits and four status bits for the RFM as described in Figure 106.

$0037 Bit 7 6 5 4 3 2 1 Bit 0

R RFIF RFEF RFVF 0 0
RFIEN RFLVDEN RCTS
W RFIAK RFMRST
RFMRST: 0 0 0 0 0 0 0 0
= Reserved

Figure 106. RFM Transmit Control Registers (RFCR7)

Table 81. RFCR7 Field Descriptions

Field Description
RF Interrupt Flag— The read-only RFIF status bit indicates if the RF transmission has ended properly when using the data buffer
mode and the SEND bit has been cleared. Writes to this bit will be ignored. The RFIF status bit is cleared by writing a logical one
7
to the RFIAK bit or the RFMRST bit. RFMRST signal clears this bit.
RFIF
0 RF transmission in progress or not in the data buffer mode.
1 RF transmission completed in the data buffer mode.
RF Transmission Error Flag— The read-only RFEF status bit indicates if there was an error in the current or prior RF
transmission as described in Section 13.6.4. Writes to this bit will be ignored. The RFEF status bit is cleared by writing a logical
6
one to the RFIAK bit or the RFMRST bit. RFMRST signal clears this bit.
RFEF
0 No RF transmission error occurred.
1 RF transmission error occurred.
RF LVD Trigger Flag— When the RF LVD is enabled and the supply voltage falls below the threshold, the read-only RFVF flag
will be set if the RFLVDEN bit is set. Writes to this bit will be ignored. The RFVF status bit is cleared by writing a logical one to
5
the RFIAK bit or the RFMRST bit. RFMRST signal clears this bit
RFVF
0 Voltage is and has been above RF LVD rising threshold or the RF LVD is disabled.
1 Voltage has dropped below the RF LVD falling threshold since last reset of this bit.
Acknowledge RF Interrupt Flags— Writing a one to the RFIAK bit clears the RFIF, RFEF and RFVF flag bits. Writing a zero to
4 the RFIAK bit has no effect on the RFIF, RFEF and RFVF flag bits. The RFMRST signal has no effect on this bit.
RFIAK 0 No effect.
1 Clear the RFIF, RFEF, and RFVF bits.

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Table 81. RFCR7 Field Descriptions (continued)

Field Description
RF Interrupt Enable— The RFIEN bit enables the RFIF, the RFEF and the RFVF bits to generate an interrupt to the MCU. The
3 RFMRST signal clears this bit.
RFIEN 0 RF interrupts disabled.
1 RF interrupts enabled.
RF LVD Enable — When the RFLVDEN bit is set, the RF LVD circuit will be enabled, and the RF LVD events are routed to the
2 RF LVD Trigger Flag. This bit is cleared by the RFMRST signal.
RFLVDEN 0 RF LVD disabled.
1 RF LVD enabled.
RF Clear To Send Status— When the RCTS bit is set the RF XCO, VCO and PLL have started and locked and the RFM is ready
1 to send data. This bit is cleared by the RFMRST signal.
RCTS 0 RFM not ready to send.
1 RFM ready to send.
RFM Reset — Writing a one to the RFMRST bit will completely reset the RFM and its registers. This bit is not affected by a reset
0 of the MCU. This bit will always read as a zero.
RFMRST 0 No effect.
1 Reset RFM.

13.17 PLL Control Registers A- PLLCR[1:0], RPAGE = 0

The PLLCR[1:0] registers contain 16 control bits for the RFM as described in Figure 107. These bits are only accessible when
the RPAGE bit is cleared.

$0038 Bit 7 6 5 4 3 2 1 Bit 0

R
AFREQ[12:5]
W
RFMRST: 0 0 0 0 0 0 0 0
$0039
R
AFREQ[4:0] POL CODE
W
RFMRST: 0 0 0 0 0 0 0 0

Figure 107. PLL Control Registers A (PLLCR[1:0], RPAGE = 0)

Table 82. PLLCR[1:0] Field Descriptions

Field Description
PLL Divider Ratio A- The AFREQ[12:0] control bits select the PLL divider ratio for a data zero in the FSK mode of modulation
PLLCR0
as described by the following equation:
7:0
where:
   12 + 4  CF  + ---------------------
AFREQ AFREQ
f = f
12:5 DATA0 XTAL  8192 
fDATA0 = RF Carrier frequency for a data zero in MHz
PLLCR1
fXTAL = External crystal frequency in MHz, 26 MHz
7:3
CF = State of the CF carrier select bit
AFREQ
AFREQ = Decimal value of the AFREQ[12:0] binary weighted bits
4:0
The AFREQ[12:0] control bits are cleared by the RFMRST signal. 1 LSB of AFREQ[12:0] = 3.17 kHz.
Data Polarity - The POL control bit selects the polarity of the data encoding selected by the CODE[1:0] bits. The POL control bit
is cleared by the RFMRST signal.
2 0 NRZ and MCU direct DATA bit data non-inverted and Manchester encoding polarity
POL as in Figure 95 and Bi-Phase encoding polarity as in Figure 97.
1 NRZ and MCU direct DATA bit data inverted and Manchester encoding polarity
as in Figure 94 and Bi-Phase encoding polarity as in Figure 96.

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Table 82. PLLCR[1:0] Field Descriptions (continued)

Field Description
Data Encoding and Source- The CODE[1:0] control bits select the type of data encoding and source of data for the RF output.
The CODE[1:0] control bits are cleared by the RFMRST signal.
1:0
00 Manchester encoded data from the RFM data buffer.
CODE
01 Bi-Phase encoded data from the RFM data buffer.
[1:0]
10 NRZ direct data from the RFM data buffer (can be mixed NRZ and Manchester at 2X the data rate).
11 MCU direct mode with RF output driven by the state of the DATA bit.

13.18 PLL Control Registers B- PLLCR[3:2], RPAGE = 0

The PLLCR[3:2] registers contain 16 control bits for the RFM as described in Figure 108. These bits are only accessible when
the RPAGE bit is cleared.

$003A Bit 7 6 5 4 3 2 1 Bit 0

R
BFREQ[12:5]
W
RFMRST: 0 0 0 0 0 0 0 0
$003B
R
BFREQ[4:0] CF MOD CKREF
W
RFMRST: 0 0 0 0 0 0 0 0

Figure 108. PLL Control Registers B (PLLCR[3:2], RPAGE = 0)

Table 83. PLLCR[3:2] Field Descriptions

Field Description
PLL Divider Ratio B- The BFREQ[12:0] control bits select the PLL divider ratio for a data one in either the OOK or FSK modes
of modulation as described by the following equation:
PLLCR2
7:0
BFREQ
   12 + 4  CF  + --------------------
BFREQ
12:5 f = f
DATA1 XTAL 8192
PLLCR3 where:
7:3 fCARRIER = RF Carrier frequency in MHz
BFREQ fXTAL = External crystal frequency in MHz
4:0 CF = State of the CF carrier select bit
BFREQ = Decimal value of the BFREQ[12:0] binary weighted bits
The BFREQ[12:0] control bits are cleared by the RFMRST signal. 1 LSB of BFREQ[12:0] = 3.17 kHz.
Carrier Frequency - The CF control bit selects the optimal VCO setup and correct divider for the 500 kHz reference clock to the
MCU on DX based on the external crystals required for the desired carrier frequency. The CF control bit is cleared by the
2
RFMRST signal.
CF
0 Configured for 315 MHz, 12.1154 PLL divider using a 26.000 MHz external crystal.
1 Configured for 434 MHz, 16.6923 PLL divider using a 26.000 MHz external crystal.
RF Modulation Method - The MOD control bit selects the method of modulating the RF. The MOD control bit is cleared by the
1 RFMRST signal.
MOD 0 Configured for OOK.
1 Configured for FSK.
Generated Clock Reference - Generates the DX signal to the TPM1 module for determining the other
0 clock frequencies:
CKREF 0 DX signal not generated.
1 DX 500 kHz signal connected to the TPM1 module.

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13.19 EPR Register - EPR (RPAGE = 1)
The EPR register contains eight control bits for the RFM as described in Figure 109. The function of the upper 4 bits depends on
the state of the VCD_EN bit.

$0038 Bit 7 6 5 4 3 2 1 Bit 0

R
PLL_LPF_[2:0] PA_SLOPE VCD_EN
W
RFMRST: 0 0 1 1 0 0 1 0
= Reserved

Figure 109. RFM EPR Registers (EPR, RPAGE = 1, VCD_EN = 0)

$0038 Bit 7 6 5 4 3 2 1 Bit 0

R VCD[3:0]
PA_SLOPE VCD_EN
W
RFMRST: — — — — 0 0 1 0
= Reserved

Figure 110. RFM EPR Registers (EPR, RPAGE = 1, VCD_EN = 1)

Table 84. EPR Field Descriptions

Field Description
7
Reserved bit — Not for user access if the VCD_EN bit is clear.
Reserved
6-4 Low Pass Filter Selection - These read/write bits select the PLL low pass filter. A reset sets these bits to $03. These bits
PLL_LPF_[2:0] are only accessible if the VCD_EN bit is clear.
VCO Calibration Count Difference - These read-only bits show the count difference from “ideal” when the VCO calibration
7-4
machine is finished (see Section 13.21). These bits are only accessible when the VCD_EN bit is set. Writing to these bits
VCD[3:0]
when the VCD_EN bit is set has no effect. The reset state is undefined.
3-2
Reserved bits — Not for user access.
Reserved
1 PA Output Slope Selection — This read/write bit controls the output slope of the RFM PA output. This bit is set by the
PA_SLOPE RFMRST signal.
VCD Enable bit — This bit allows access to the VCD[3:0] bits. This bit is cleared by the RFMRST signal.
0
0 PLL_LPF_[2:0] bits accessed.
VCD_EN
1 VCD[3:0] bits accessed.

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13.20 RF DATA Registers - RFD[31:0]
The RFD registers contain 256 read/write bits for the RFM to use when outputting data as described in Section 13.2. The 256-
bit buffer is divided into two pages of 128 bits as selected by the RPAGE bit in the RFCR2. These as described in Figure 111.
These bits are unaffected by any reset.
The data buffer is unloaded to the RF output starting with the least significant bit (RFD0) in the least significant byte (RFB0) up
through the most significant bit (RFD255) in the most significant byte (RFB31). This is often referred to as “little-endian” data
ordering. The output of this data by the RFM in all 256 bits locations is not dependent on the state of the RPAGE bit.

Bit 7 6 5 4 3 2 1 Bit 0
$003C RFD[7:0] for RPAGE = 0, RFD[135:128] for RPAGE = 1
$003D RFD[15:8] for RPAGE = 0, RFD[143:136] for RPAGE = 1
$003E RFD[23:16] for RPAGE = 0, RFD[151:144] for RPAGE = 1
$003F RFD[31:24] for RPAGE = 0, RFD[159:152] for RPAGE = 1
$0040 RFD[39:32] for RPAGE = 0, RFD[167:160] for RPAGE = 1
$0041 RFD[47:40] for RPAGE = 0, RFD[175:168] for RPAGE = 1
$0042 RFD[55:48] for RPAGE = 0, RFD[183:176] for RPAGE = 1
$0043 RFD[63:56] for RPAGE = 0, RFD[191:184] for RPAGE = 1
$0044 RFD[71:64] for RPAGE = 0, RFD[199:192] for RPAGE = 1
$0045 RFD[79:72] for RPAGE = 0, RFD[207:200] for RPAGE = 1
$0046 RFD[87:80] for RPAGE = 0, RFD[215:208] for RPAGE = 1
$0047 RFD[95:88] for RPAGE = 0, RFD[223:216] for RPAGE = 1
$0048 RFD[103:96] for RPAGE = 0, RFD[231:224] for RPAGE = 1
$0049 RFD[111:104] for RPAGE = 0, RFD[239:232] for RPAGE = 1
$004A RFD[119:112] for RPAGE = 0, RFD[247:240] for RPAGE = 1
$004B RFD[127:120] for RPAGE = 0, RFD[255:248] for RPAGE = 1

Figure 111. RF Data Registers (RFD[31:0])

Table 85. RFD[31:0] Field Descriptions

Field Description

RFD
15:0
RPAGE = 0 RF Data Registers Lower 128 bits - These are read/write bits that hold the lower 128 bits of possible data to be sent by the
RFM. Access to the lower 128 bits occurs when the RPAGE bit is clear. These bits are unaffected by any reset.
RFD
[127:0]

RFD
31:16
RPAGE = 1 RF Data Registers Upper 128 bits - These are read/write bits that hold the upper 128 bits of possible data to be sent by the
RFM. Access to the lower 128 bits occurs when the RPAGE bit is clear. These bits are unaffected by any reset.
RFD
[255:128]

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13.21 VCO Calibration Machine
The RFM incorporates a VCO calibration machine which works in conjunction with the VCO. The calibration machine selects the
optimal VCO sub-band with respect to a predefined reference voltage applied to the VCO.
• Calibration supports maxband VCO sub-bands. maxband corresponds to the band where the VCO frequency is maximum.
• A successive approximation algorithm is used to calculate the optimum sub-band.
• Fc, the Center Frequency (AFREQ+BFREQ)/2 is used as the reference frequency for the VCO calibration in FSK mode
(MOD = 1).
• BFREQ is used as the reference frequency for the VCO calibration in OOK mode (MOD = 0).
• Calibration occurs every time the VCO is enabled.
• The calibration takes approximately 5s.
The state machine of the calibration is shown in Figure 112.

- maxband is the number

of sub-band of the VCO VCOband=maxband/2
Bestband=maxband/2
- Bestband is the band which
is going to be chosen Difference=maxband/4
- Difference is an internal variable.
Count the number of cycles of the VCO

Compare
VCOcount and Targetedcount
Difference=Difference/2
VCOcount<Targetedcount
VCOcount>Targetedcount

VCOcount=Targetedcount
NO
VCOband=VCOband-Difference VCOband=VCOband+Difference

Bestband=VCOband
VCOband=VCOband-Difference
Difference=1?

Bestband is first best band found

YES or the closest band found

Figure 112. VCO Calibration State Machine

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14 Firmware
This section describes the software subroutines contained in the firmware section of the FLASH memory that the user can call
for various tasks and to reduce the software development time for the main internal operations.

14.1 Software Jump Table

All subroutines are accessed through a jump table located at the bottom of the firmware FLASH memory as described in Table 86.
This allows upgrades in firmware without changing the software code of the user. All subroutines should be accessed with the
JSR instruction.

14.2 Function Documentation

The following subsections describe the details of the firmware routines. Further details can be found in the latest version of the
FXTH870xD Embedded Firmware User Guide.

14.2.1 General Rules

1. No output parameter can use the extreme codes (all zero’s or all one’s).
2. The all zero’s output code will always indicate a fault and the status byte will indicate the source of the error.
3. While firmware is processing, CPU resources are unavailable for application.
4. Each measured parameter will return a limit code ($00, $FF or $1FF) if an error occurs in its acquisition, except for the
external ADC voltage measurements on the PTA[1:0] pins.
5. External ADC voltage measurements on the PTA[1:0] pins will return a full range code that is ratiometric to the supply
voltage.
14.2.1.1 FXTH870x02 Single Z-axis Firmware Routines
The details on the use and execution of each firmware routine is documented in the CodeWarrior project file that is supplied by
Freescale. Any future updates to these firmware routines will be contained in that file. A summary of the firmware routines
available is given in Table 86.
The firmware table is comprised of 3-byte entries where the first byte is the operational code for the JMP instruction, and the
following two bytes are the absolute address pointing to the location of the firmware function.

Table 86. FXTH870x02 Single Z-axis Firmware Summary and Jump Table

Address Routine Description

E000 TPMS_RESET Master reset of complete device
E003 TPMS_READ_VOLTAGE 10-bit uncompensated bandgap voltage reading
E006 TPMS_COMP_VOLTAGE 8-bit compensation of 10-bit voltage reading
E009 TPMS_READ_TEMPERATURE 10-bit uncompensated temperature reading
E00C TPMS_COMP_TEMPERATURE 8-bit compensation of 10-bit temperature reading
E00F TPMS_READ_PRESSURE 10-bit uncompensated pressure reading
E012 TPMS_COMP_PRESSURE 9-bit compensation of 10-bit pressure reading
E015 TPMS_READ_ACCELERATION 10-bit uncompensated acceleration reading
E018 TPMS_COMP_ACCELERATION 9-bit compensation of 10-bit acceleration reading
E01B TPMS_READ_V0 10-bit uncompensated voltage reading on PTA0 pin
E01E TPMS_READ_V1 10-bit uncompensated voltage reading on PTA1 pin
E021 TPMS_LFOCAL LFO clock calibration
E024 TPMS_MFOCAL MFO clock calibration
E027 TPMS_WAVG Weighted average (2, 4, 8, 16 or 32)
E02A TPMS_RF_RESET Master reset of RFM
E02D TPMS_RF_READ_DATA Read RFM data buffer
E030 TPMS_RF_READ_DATA_REVERSE Read RFM data buffer in reverse bit order
E033 TPMS_RF_WRITE_DATA Write RFM data buffer
E036 TPMS_RF_WRITE_DATA_REVERSE Write RFM data buffer in reverse bit order
E039 TPMS_RF_CONFIG_DATA Configure RFM

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Table 86. FXTH870x02 Single Z-axis Firmware Summary and Jump Table (continued)

Address Routine Description

E03C Reserved Reserved
E03F TPMS_RF_SET_TX Initiate RF transmission
E042 TPMS_RF_DYNAMIC_POWER Adjusts PA for uniform power output
E045 TPMS_MSG_INIT Initialization of the emulated serial communication
E048 TPMS_MSG_READ Reading data from emulated serial interface
E04B TPMS_MSG_WRITE Writing data on emulated serial interface
E04E TPMS_CHECKSUM_XOR Calculates a checksum for given buffer in XOR
E051 TPMS_CRC8 Calculates CRC8 on portion of memory
E054 TPMS_CRC16 Calculates CRC16 on portion of memory
E057 TPMS_SQUARE_ROOT Calculates square root
E05A TPMS_READ_ID Reads device ID stored in FLASH
E05D TPMS_LF_ENABLE Enable/Disable LF for Carrier or Data
E060 TPMS_LF_READ_DATA Reading LF data
E063 TPMS_WIRE_AND_ADC_CHECK Performs checks of internal bond wires
E066 TPMS_FLASH_WRITE Write to FLASH
E069 TPMS_FLASH_CHECK Performs checksum on Freescale firmware FLASH
E06C TPMS_FLASH_ERASE Erases one page (512 bytes) of FLASH at a time
E06F TPMS_READ_DYNAMIC_ACCEL Offsets Z-axis acceleration with one of 15 steps
E072 TPMS_RF_ENABLE Enable RFM
E075 TPMS_FLASH_PROTECTION Lock out FLASH
E078 Reserved Reserved
E07B TPMS_MULT_SIGN_INT16 Multiple two signed 16-bit numbers together
E07E TPMS_VREG_CHECK Verify that external capacitor connected to VREG pin
E081 TPMS_PRECHARGE_VREG Precharge external capacitor on VREG pin
E084 Reserved Reserved
E087 TPMS_READ_ACCEL_CONT_START Enable the TPMS_READ_ACCEL_CONT function.
E08A TPMS_READ_ACCEL_CONT Take continuous acceleration readings and store to assigned location.
E08D TPMS_READ_ACCEL_CONT_STOP Disable the TPMS_READ_ACCEL_CONT function.

14.2.1.2 FXTH870x11 Dual XZ-axis Firmware Routines

The details on the use and execution of each firmware routine is documented in the CodeWarrior project file that is supplied by
Freescale. Any future updates to these firmware routines will be contained in that file. A summary of the firmware routines
available is given in Table 87.
The firmware table is comprised of 3-byte entries where the first byte is the operational code for the JMP instruction, and the
following two bytes are the absolute address pointing to the location of the firmware function.

Table 87. FXTH870x11 Dual XZ-axis Firmware Summary and Jump Table

Address Routine Description

E000 TPMS_RESET Master reset of complete device
E003 TPMS_READ_VOLTAGE 10-bit uncompensated bandgap voltage reading
E006 TPMS_COMP_VOLTAGE 8-bit compensation of 10-bit voltage reading
E009 TPMS_READ_TEMPERATURE 10-bit uncompensated temperature reading
E00C TPMS_COMP_TEMPERATURE 8-bit compensation of 10-bit temperature reading
E00F TPMS_READ_PRESSURE 10-bit uncompensated pressure reading
E012 TPMS_COMP_PRESSURE 9-bit compensation of 10-bit pressure reading
E015 TPMS_READ_ACCELERATION_X 10-bit uncompensated X-axis accel reading

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Table 87. FXTH870x11 Dual XZ-axis Firmware Summary and Jump Table (continued)

Address Routine Description

10-bit uncompensated X-axis accel reading
E018 TPMS_READ_DYNAMIC_ACCEL_X
with dynamic offset adjustment.
E01B TPMS_COMP_ACCELERATION_X 9-bit compensation of 10-bit X-axis accel reading
E01E TPMS_READ_ACCELERATION_Z 10-bit uncompensated Z-axis accel reading
10-bit uncompensated Z-axis accel reading with dynamic offset
E021 TPMS_READ_DYNAMIC_ACCEL_Z
adjustment.
E024 TPMS_COMP_ACCELERATION_Z 9-bit compensation of 10-bit Z-axis accel reading
E027 TPMS_READ_ACCELERATION_XZ 10-bit uncompensated X-axis and Z-axis accel readings
10-bit uncompensated X-axis and Z-axis accel readings with dynamic
E02A TPMS_READ_DYNAMIC_ACCEL_XZ
offset adjustment.
E02D TPMS_COMP_ACCELERATION_XZ 9-bit compensation of 10-bit X-axis and Z-axis accel readings
E030 TPMS_READ_V0 10-bit uncompensated voltage reading on PTA0 pin
E033 TPMS_READ_V1 10-bit uncompensated voltage reading on PTA1 pin
E036 TPMS_LFOCAL LFO clock calibration
E039 TPMS_MFOCAL MFO clock calibration
E03C TPMS_RF_ENABLE Enable and set up RFM
E03F TPMS_RF_RESET Master reset of RFM
E042 TPMS_RF_READ_DATA Read RFM data buffer
E045 TPMS_RF_READ_DATA_REVERSE Read RFM data buffer in reverse bit order
E048 TPMS_RF_WRITE_DATA Write RFM data buffer
E04B TPMS_RF_WRITE_DATA_REVERSE Write RFM data buffer in reverse bit order
E04E TPMS_RF_CONFIG_DATA Configure RFM
E051 Reserved Reserved
E054 TPMS_RF_SET_TX Initiate RF transmission
E057 TPMS_RF_DYNAMIC_POWER Adjusts PA for uniform power output
E05A TPMS_MSG_INIT Initialization of the emulated serial communication
E05D TPMS_MSG_READ Reading data from emulated serial interface
E060 TPMS_MSG_WRITE Writing data on emulated serial interface
E063 TPMS_CHECKSUM_XOR Calculates a checksum for given buffer in XOR
E066 TPMS_CRC8 Calculates CRC8 on portion of memory
E069 TPMS_CRC16 Calculates CRC16 on portion of memory
E06C TPMS_SQUARE_ROOT Calculates square root
E06F TPMS_READ_ID Reads device ID stored in FLASH
E072 TPMS_LF_ENABLE Enable/Disable LF for Carrier or Data
E075 TPMS_LF_READ_DATA Reading LF data
E078 TPMS_WIRE_AND_ADC_CHECK Performs checks of internal bond wires
E07B TPMS_FLASH_WRITE Write to FLASH
E07E TPMS_FLASH_CHECK Performs checksum on Freescale firmware FLASH
E081 TPMS_FLASH_ERASE Erases one page (512 bytes) of FLASH at a time
E084 TPMS_FLASH_PROTECTION Lock out FLASH
E087 Reserved Reserved
E08A TPMS_MULT_SIGN_INT16 Multiple two signed 16-bit numbers together
E08D TPMS_WAVG Weighted average
E090 Reserved Reserved

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14.2.2 Device Identification
The bytes assigned to identify the device and its options are described below. This data can be read by use of the
TPMS_READ_ID routine.

Table 88. Device ID Coding Summary

ID Register Initial Updated

Address Name Address Address Bit 7 6 5 4 3 2 1 Bit 0
00 CODE0 $E0A0 $E0A0 Reserved - Firmware Revision/Software Information
01 CODE1 $FF10 $FDF2 ES2 ES1 ES0 PRESS ACC1 ACC0 SPCLA SPCLP
02 CODE2 $FF11 $FDF3 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
03 CODE3 $FF12 $FDF4 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8
04 CODE4 $FF13 $FDF5 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16
05 CODE5 $FF14 $FDF6 ID31 ID30 ID29 ID28 ID27 ID26 ID25 ID24

ID12:0 — Device ID within each lot, maximum 8,192 per lot

ID13:26 — Assembly lot ID, 100 through 16383
ID27 — Always 0 for FXTH87 family
ID28:31 — Always 0x08 to identify Freescale as supplier

Table 89. Device ID Coding Descriptions

Field Description
CODE0
7:0 Reserved for Freescale firmware description.
Reserved
CODE1 Revision number for the multiple-chip-module silicon.
7:5 000 - MCU version 0
ES 111 - MCU version 7
CODE1 Calibrated range for pressure. The range is a combination of this bit and the PRESS-L bit, below.
4 bit 0 = 0, bit 4 = 0 indicates a 100-450 kPa range
PRESS-H bit 0 = 0, bit 4 = 1 indicates a 100-900 kPa range
Type of accelerometer.
CODE1 00 - None
3:2 01 - One accelerometer with X-axis orientation
ACC 10 - One accelerometer with Z-axis orientation
11 - Two accelerometers with X- and Z-axis orientations
Special calibration for accelerometer.
CODE1
0 = standard -240 to +270 g Z-axis
1
1 = extended -270 to +400 g Z-axis
CODE1 Calibrated range for pressure. The range is a combination of this bit and the PRESS-H bit, above.
0 bit 0 = 0, bit 4 = 0 indicates a 100-450 kPa range
PRESS-L bit 0 = 0, bit 4 = 1 indicates a 100-900 kPa range
CODE2:4
7:0
28-bit serial number for each device. All numbers to be unique with numbering sequence being a sequential counter for each
CODE5
product type.
3:0
ID27:0
CODE5 4-bit number assigned to vendor type.
7:4 If these bits are unspecified as part of the complete FLASH programming by the customer, then these 4 bits are programmed
ID31:28 to binary 1 0 0 0.

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14.2.3 Definition of Signal Ranges
Each measured parameter (pressure, voltage, temperature, acceleration) results from an ADC10 conversion of an analog signal.
This ADC10 result may then be passed by the firmware to the application software as either the raw ADC10 result or further
compensated and scaled for an output between one and the maximum digital value minus one. The minimum digital value of zero
and the maximum digital value are reserved as error codes.
The signal ranges and their significant data points are shown in Figure 113. In this definition the signal source would normally
output a signal between SINLO and SINHI. Due to process, temperature and voltage variations this signal may increase its range
to SINMIN to SINMAX. In all cases the signal will be between the supply rails, so that the ADC10 will convert it to a range of digital
numbers between 0 and 1023. These digital numbers will have corresponding DINMIN, DINLO, DINHI, DINMAX values. The ADC10
digital value is taken by the firmware and compensated and scaled to give the required output code range.

UPPER ERROR CASE

FORCE
OUTPUT
TO 511

VDD 1023 511

OVERFLOW
CASE 510

SINMAX DINMAX

SINHI DINHI

NORMAL CASE

SIGNAL VDD/2 ADC10 512 FIRMWARE 256

SOURCE ROUTINE

SENSOR ADC10 RAW CALCULATED

ANALOG DIGITAL DIGITAL
VOLTAGE (10-BIT CONVERSION) (9-BIT EXAMPLE)

SINLO DINLO

SINMIN DINMIN

1
VDD 0 UNDERFLOW 0
CASE
FORCE
OUTPUT
TO ZERO

LOWER ERROR CASE

Figure 113. Measurement Signal Range Definitions

Digital input values below DINMIN and above DINMAX are immediately flagged as being out of range and generate error bits and
the output is forced to the 0 value.
Digital values below DINLO (but above DINMIN) or above DINHI (but not DINMAX) will most likely cause an output that would be less
than 1 or greater than 510, respectively. These cases are considered underflow or overflow, respectively. Underflow results will
be forced to a value of 1. Overflow results will be forced to a value of 510.

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Digital values between DINLO and DINHI will normally produce an output between 1 to 510 (for a 9-bit result). In some isolated
cases due to compensation calculations and rounding the result may be less than 1 or greater than 510, in which case the
underflow and overflow rule mentioned above is used.

14.3 Memory Resource Usage

The firmware uses the top 8192 bytes of the FLASH memory map.
The firmware uses no specific bytes of the RAM but will cause additional stacking of temporary values.
The firmware uses two bytes ($008E and $008F) of the Parameter Registers for global flags for all routines.
Software Stack
The RESET firmware function sets the SP register to the last address in the RAM. The user can change the default stack location
to meet its own application needs.

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15 Development Support
15.1 Introduction
This chapter describes the single-wire BACKGROUND DEBUG mode (BDM), which uses the on-chip BACKGROUND DEBUG
controller (BDC) module.

15.1.1 Features
Features of the BDC module include:
• Single pin for mode selection and background communications
• BDC registers are not located in the memory map
• SYNC command to determine target communications rate
• Non-intrusive commands for memory access
• ACTIVE BACKGROUND mode commands for CPU register access
• GO and TRACE1 commands
• BACKGROUND command can wake CPU from STOP or WAIT modes
• One hardware address breakpoint built into BDC
• Oscillator runs in STOP mode, if BDC enabled
• COP watchdog disabled while in ACTIVE BACKGROUND mode

15.2 Background Debug Controller (BDC)

All MCUs in the HCS08 Family contain a single-wire BACKGROUND DEBUG interface that supports in-circuit programming of
on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike debug interfaces on earlier 8-bit MCUs,
this system does not interfere with normal application resources. It does not use any user memory or locations in the memory
map and does not share any on-chip peripherals.
BDC commands are divided into two groups:
• ACTIVE BACKGROUND mode commands require that the target MCU is in ACTIVE BACKGROUND mode (the user
program is not running). ACTIVE BACKGROUND mode commands allow the CPU registers to be read or written, and allow
the user to trace one user instruction at a time, or GO to the user program from ACTIVE BACKGROUND mode.
• Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusive commands
allow a user to read or write MCU memory locations or access status and control registers within the BACKGROUND
DEBUG controller.
Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom
serial interface to the single-wire BACKGROUND DEBUG system. Depending on the development tool vendor, this interface pod
may use a standard RS-232 serial port, a parallel printer port, or some other type of communications such as a universal serial
bus (USB) to communicate between the host PC and the pod. The pod typically connects to the target system with ground, the
BKGD/PTA4 pin, RESET, and sometimes VDD. An open-drain connection to reset allows the host to force a target system reset,
which is useful to regain control of a lost target system or to control startup of a target system before the on-chip nonvolatile
memory has been programmed. Sometimes VDD can be used to allow the pod to use power from the target system to avoid the
need for a separate power supply. However, if the pod is powered separately, it can be connected to a running target system
without forcing a target system reset or otherwise disturbing the running application program.

BKGD 1 2 GND
NO CONNECT 3 4 RESET
NO CONNECT 5 6 VDD

Figure 114. BDM Tool Connector

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15.2.1 BKGD/PTA4 Pin Description
BKGD/PTA4 is the single-wire BACKGROUND DEBUG interface pin. The primary function of this pin is for bidirectional serial
communication of ACTIVE BACKGROUND mode commands and data. During reset, this pin is used to select between starting
in ACTIVE BACKGROUND mode or starting the user’s application program. This pin is also used to request a timed sync
response pulse to allow a host development tool to determine the correct clock frequency for BACKGROUND DEBUG serial
communications.
BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of microcontrollers. This
protocol assumes the host knows the communication clock rate that is determined by the target BDC clock rate. All
communication is initiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time.
Commands and data are sent most significant bit first (MSB first). For a detailed description of the communications protocol, refer
to Section 15.2.2.
If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC command may be sent
to the target MCU to request a timed sync response signal from which the host can determine the correct communication speed.
BKGD/PTA4 is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required. Unlike typical
open-drain pins, the external RC time constant on this pin, which is influenced by external capacitance, plays almost no role in
signal rise time. The custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without
risking harmful drive level conflicts. Refer to Section 15.2.2, for more detail.
When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD/PTA4 chooses normal
operating mode. When a debug pod is connected to BKGD/PTA4 it is possible to force the MCU into ACTIVE BACKGROUND
mode after reset. The specific conditions for forcing ACTIVE BACKGROUND depend upon the HCS08 derivative (refer to the
introduction to this Development Support section). It is not necessary to reset the target MCU to communicate with it through the
BACKGROUND DEBUG interface.

15.2.2 Communication Details

The BDC serial interface requires the external controller to generate a falling edge on the BKGD/PTA4 pin to indicate the start of
each bit time. The external controller provides this falling edge whether data is transmitted or received.
BKGD/PTA4 is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data is transferred
MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if 512 BDC clock cycles occur between falling
edges from the host. Any BDC command that was in progress when this timeout occurs is aborted without affecting the memory
or operating mode of the target MCU system.
The custom serial protocol requires the debug pod to know the target BDC communication clock speed.
The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the BDC clock source. The
BDC clock source can either be the bus or the alternate BDC clock source.
The BKGD/PTA4 pin can receive a high or low level or transmit a high or low level. The following diagrams show timing for each
of these cases. Interface timing is synchronous to clocks in the target BDC, but asynchronous to the external host. The internal
BDC clock signal is shown for reference in counting cycles.
Figure 115 shows an external host transmitting a logic 1 or 0 to the BKGD/PTA4 pin of a target HCS08 MCU. The host is
asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the
beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD/PTA4 pin. Typically, the
host actively drives the pseudo-open-drain BKGD/PTA4 pin during host-to-target transmissions to speed up rising edges.
Because the target does not drive the BKGD/PTA4 pin during the host-to-target transmission period, there is no need to treat the
line as an open-drain signal during this period.

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 BDC CLOCK
(TARGET MCU)

HOST
TRANSMIT 1

HOST
TRANSMIT 0

10 CYCLES
EARLIEST START
OF NEXT BIT
SYNCHRONIZATION TARGET SENSES BIT LEVEL
UNCERTAINTY
PERCEIVED START
OF BIT TIME

Figure 115. BDC Host-to-Target Serial Bit Timing

Figure 116 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU,
there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD/PTA4 to the perceived start of the bit time in the target
MCU. The host holds the BKGD/PTA4 pin low long enough for the target to recognize it (at least two target BDC cycles). The
host must release the low drive before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived
start of the bit time. The host should sample the bit level about 10 cycles after it started the bit time.

BDC CLOCK
(TARGET MCU)

HOST DRIVE
TO BKGD/PTA4 PIN HIGH-IMPEDANCE

TARGET MCU
SPEEDUP PULSE
HIGH-IMPEDANCE HIGH-IMPEDANCE

PERCEIVED START
OF BIT TIME

R-C RISE
BKGD/PTA4 PIN

10 CYCLES
EARLIEST START
OF NEXT BIT
10 CYCLES

HOST SAMPLES BKGD/PTA4 PIN

Figure 116. BDC Target-to-Host Serial Bit Timing (Logic 1)

Figure 117 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU,
there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD/PTA4 to the start of the bit time as perceived by the
target MCU. The host initiates the bit time but the target HCS08 finishes it. Because the target wants the host to receive a logic
0, it drives the BKGD/PTA4 pin low for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host
samples the bit level about 10 cycles after starting the bit time.

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 BDC CLOCK
(TARGET MCU)

HOST DRIVE
TO BKGD/PTA4 PIN HIGH-IMPEDANCE

SPEEDUP
TARGET MCU PULSE
DRIVE AND
SPEED-UP PULSE

PERCEIVED START
OF BIT TIME

BKGD/PTA4 PIN

10 CYCLES
EARLIEST START
10 CYCLES OF NEXT BIT

HOST SAMPLES BKGD/PTA4 PIN

Figure 117. BDM Target-to-Host Serial Bit Timing (Logic 0)

15.2.3 BDC Commands

BDC commands are sent serially from a host computer to the BKGD/PTA4 pin of the target HCS08 MCU. All commands and data
are sent MSB-first using a custom BDC communications protocol. ACTIVE BACKGROUND mode commands require that the
target MCU is currently in the ACTIVE BACKGROUND mode while non-intrusive commands may be issued at any time whether
the target MCU is in ACTIVE BACKGROUND mode or running a user application program. Table 90 shows all HCS08 BDC
commands, a shorthand description of their coding structure, and the meaning of each command.
Coding Structure Nomenclature
This nomenclature is used in Table 90 to describe the coding structure of the BDC commands. Commands begin with an 8-bit
hexadecimal command code in the host-to-target direction (most significant bit first)
/ = separates parts of the command
d = delay 16 target BDC clock cycles
AAAA = a 16-bit address in the host-to-target direction
RD = 8 bits of read data in the target-to-host direction
WD = 8 bits of write data in the host-to-target direction
RD16 = 16 bits of read data in the target-to-host direction
WD16 = 16 bits of write data in the host-to-target direction
SS = the contents of BDCSCR in the target-to-host direction (STATUS)
CC = 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL)
RBKP = 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint register)
WBKP = 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register)

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Table 90. BDC Command Summary

Command Active BDM/ Coding

Description
Mnemonic Non-intrusive Structure
Request a timed reference pulse to determine target
SYNC Non-intrusive n/a(1)
BDC communication speed
Enable acknowledge protocol. Refer to Freescale
ACK_ENABLE Non-intrusive D5/d
document order no. HCS08RMv1/D.
Disable acknowledge protocol. Refer to Freescale
ACK_DISABLE Non-intrusive D6/d
document order no. HCS08RMv1/D.
Enter ACTIVE BACKGROUND mode if enabled (ignore
BACKGROUND Non-intrusive 90/d
if ENBDM bit equals 0)
READ_STATUS Non-intrusive E4/SS Read BDC status from BDCSCR
WRITE_CONTROL Non-intrusive C4/CC Write BDC controls in BDCSCR
READ_BYTE Non-intrusive E0/AAAA/d/RD Read a byte from target memory
READ_BYTE_WS Non-intrusive E1/AAAA/d/SS/RD Read a byte and report status
READ_LAST Non-intrusive E8/SS/RD Re-read byte from address just read and report status
WRITE_BYTE Non-intrusive C0/AAAA/WD/d Write a byte to target memory
WRITE_BYTE_WS Non-intrusive C1/AAAA/WD/d/SS Write a byte and report status
READ_BKPT Non-intrusive E2/RBKP Read BDCBKPT breakpoint register
WRITE_BKPT Non-intrusive C2/WBKP Write BDCBKPT breakpoint register
Go to execute the user application program starting at
GO Active BDM 08/d
the address currently in the PC
Trace 1 user instruction at the address in the PC, then
TRACE1 Active BDM 10/d
return to ACTIVE BACKGROUND mode
Same as GO but enable external tagging (HCS08
TAGGO Active BDM 18/d
devices have no external tagging pin)
READ_A Active BDM 68/d/RD Read accumulator (A)
READ_CCR Active BDM 69/d/RD Read condition code register (CCR)
READ_PC Active BDM 6B/d/RD16 Read program counter (PC)
READ_HX Active BDM 6C/d/RD16 Read H and X register pair (H:X)
READ_SP Active BDM 6F/d/RD16 Read stack pointer (SP)
Increment H:X by one then read memory byte located
READ_NEXT Active BDM 70/d/RD
at H:X
Increment H:X by one then read memory byte located
READ_NEXT_WS Active BDM 71/d/SS/RD
at H:X. Report status and data.
WRITE_A Active BDM 48/WD/d Write accumulator (A)
WRITE_CCR Active BDM 49/WD/d Write condition code register (CCR)
WRITE_PC Active BDM 4B/WD16/d Write program counter (PC)
WRITE_HX Active BDM 4C/WD16/d Write H and X register pair (H:X)
WRITE_SP Active BDM 4F/WD16/d Write stack pointer (SP)
Increment H:X by one, then write memory byte located
WRITE_NEXT Active BDM 50/WD/d
at H:X
Increment H:X by one, then write memory byte located
WRITE_NEXT_WS Active BDM 51/WD/d/SS
at H:X. Also report status.
1. The SYNC command is a special operation that does not have a command code.

The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications
speed to use for BDC communications until after it has analyzed the response to the SYNC command.
To issue a SYNC command, the host:
• Drives the BKGD/PTA4 pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the
reference oscillator/64 or the self-clocked rate/64.)

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• Drives BKGD/PTA4 high for a brief speedup pulse to get a fast rise time (This speedup pulse is typically one cycle of the
fastest clock in the system.)
• Removes all drive to the BKGD/PTA4 pin so it reverts to high impedance
• Monitors the BKGD/PTA4 pin for the sync response pulse
The target, upon detecting the SYNC request from the host (which is a much longer low time than would ever occur during normal
BDC communications):
• Waits for BKGD/PTA4 to return to a logic high
• Delays 16 cycles to allow the host to STOP driving the high speedup pulse
• Drives BKGD/PTA4 low for 128 BDC clock cycles
• Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD/PTA4
• Removes all drive to the BKGD/PTA4 pin so it reverts to high impedance
The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for subsequent BDC
communications. Typically, the host can determine the correct communication speed within a few percent of the actual target
speed and the communication protocol can easily tolerate speed errors of several percent.

15.2.4 BDC Hardware Breakpoint

The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a 16-bit match value in the
BDCBKPT register. This breakpoint can generate a forced breakpoint or a tagged breakpoint. A forced breakpoint causes the
CPU to enter ACTIVE BACKGROUND mode at the first instruction boundary following any access to the breakpoint address.
The tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the CPU will enter ACTIVE
BACKGROUND mode rather than executing that instruction if and when it reaches the end of the instruction queue. This implies
that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any
address.
The breakpoint enable (BKPTEN) control bit in the BDC status and control register (BDCSCR) is used to enable the breakpoint
logic (BKPTEN = 1). When BKPTEN = 0, its default value after reset, the breakpoint logic is disabled and no BDC breakpoints
are requested regardless of the values in other BDC breakpoint registers and control bits. The force/tag select (FTS) control bit
in BDCSCR is used to select forced (FTS = 1) or tagged (FTS = 0) type breakpoints.

15.3 Register Definition

This section contains the descriptions of the BDC registers and control bits.
This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to
translate these names into the appropriate absolute addresses.

15.3.1 BDC Registers and Control Bits

The BDC has two registers:
• The BDC status and control register (BDCSCR) is an 8-bit register containing control and status bits for the BACKGROUND
DEBUG controller.
• The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address.
These registers are accessed with dedicated serial BDC commands and are not located in the memory space of the target MCU
(so they do not have addresses and cannot be accessed by user programs).
Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written at any time. For
example, the ENBDM control bit may not be written while the MCU is in ACTIVE BACKGROUND mode. (This prevents the
ambiguous condition of the control bit forbidding ACTIVE BACKGROUND mode while the MCU is already in ACTIVE
BACKGROUND mode.) Also, the four status bits (BDMACT, WS, WSF, and DVF) are read-only status indicators and can never
be written by the WRITE_CONTROL serial BDC command. The clock switch (CLKSW) control bit may be read or written at any
time.

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15.3.2 BDC Status and Control Register (BDCSCR)
This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to
user programs because it is not located in the normal memory map of the MCU.

7 6 5 4 3 2 1 0
R BDMACT WS WSF DVF
ENBDM BKPTEN FTS CLKSW
W
Normal Reset 0 0 0 0 0 0 0 0
Reset in
1 1 0 0 1 0 0 0
Active BDM:
= Reserved

Figure 118. BDC Status and Control Register (BDCSCR)

Table 91. BDCSCR Register Field Descriptions

Field Description
Enable BDM (Permit ACTIVE BACKGROUND Mode) — Typically, this bit is written to 1 by the debug host shortly after the
7 beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal reset clears it.
ENBDM 0 BDM cannot be made active (non-intrusive commands still allowed)
1 BDM can be made active to allow ACTIVE BACKGROUND mode commands
BACKGROUND Mode Active Status — This is a read-only status bit.
6
0 BDM not active (user application program running)
BDMACT
1 BDM active and waiting for serial commands
BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) control bit and
5 BDCBKPT match register are ignored.
BKPTEN 0 BDC breakpoint disabled
1 BDC breakpoint enabled
Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the BDCBKPT match
register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register causes the fetched opcode to be
4 tagged. If this tagged opcode ever reaches the end of the instruction queue, the CPU enters ACTIVE BACKGROUND mode
FTS rather than executing the tagged opcode.
0 Tag opcode at breakpoint address and enter ACTIVE BACKGROUND mode if CPU attempts to execute that instruction
1 Breakpoint match forces ACTIVE BACKGROUND mode at next instruction boundary (address need not be an opcode)
Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC clock source.
3
0 Alternate BDC clock source
CLKSW
1 MCU bus clock
WAIT or STOP Status — When the target CPU is in WAIT or STOP mode, most BDC commands cannot function. However,
the BACKGROUND command can be used to force the target CPU out of WAIT or STOP and into ACTIVE BACKGROUND
mode where all BDC commands work. Whenever the host forces the target MCU into ACTIVE BACKGROUND mode, the host
2 should issue a READ_STATUS command to check that BDMACT = 1 before attempting other BDC commands.
WS 0 Target CPU is running user application code or in ACTIVE BACKGROUND mode (was not in WAIT or STOP mode when
BACKGROUND became active)
1 Target CPU is in WAIT or STOP mode, or a BACKGROUND command was used to change from WAIT or STOP to ACTIVE
BACKGROUND mode
WAIT or STOP Failure Status — This status bit is set if a memory access command failed due to the target CPU executing a
WAIT or STOP instruction at or about the same time. The usual recovery strategy is to issue a BACKGROUND command to
1 get out of WAIT or STOP mode into ACTIVE BACKGROUND mode, repeat the command that failed, then return to the user
WSF program. (Typically, the host would restore CPU registers and stack values and re-execute the WAIT or STOP instruction.)
0 Memory access did not conflict with a WAIT or STOP instruction
1 Memory access command failed because the CPU entered WAIT or STOP mode
Data Valid Failure Status — This status bit is not used in the MC9S08RA16 because it does not have any slow access
0 memory.
DVF 0 Memory access did not conflict with a slow memory access
1 Memory access command failed because CPU was not finished with a slow memory access

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15.3.3 BDC Breakpoint Match Register (BDCBKPT)
This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS control bits in BDCSCR
are used to enable and configure the breakpoint logic. Dedicated serial BDC commands (READ_BKPT and WRITE_BKPT) are
used to read and write the BDCBKPT register but is not accessible to user programs because it is not located in the normal
memory map of the MCU. Breakpoints are normally set while the target MCU is in ACTIVE BACKGROUND mode before running
the user application program. For additional information about setup and use of the hardware breakpoint logic in the BDC, refer
to Section 15.2.4.

15.3.4 System Background Debug Force Reset Register (SBDFR)

This register contains a single write-only control bit. A serial BACKGROUND mode command such as WRITE_BYTE must be
used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00.

7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
W BDFR(1)
Reset 0 0 0 0 0 0 0 0
= Reserved
1. BDFR is writable only through serial BACKGROUND mode debug commands, not from user programs.

Figure 119. System Background Debug Force Reset Register (SBDFR)

Table 92. SBDFR Register Field Description

Field Description
Background Debug Force Reset — A serial ACTIVE BACKGROUND mode command such as WRITE_BYTE allows an
0
external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a
BDFR
user program.

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16 Battery Charge Consumption Modeling
The supply current consumed by the FXTH870xD can be estimated using the following basic model.

16.1 Standby Current

The overall charge consumed by the standby features is:
 I STDBY + I LF 
Q STDBY = t TOT  -------------------------------------------- Eqn. 12
1000
where:
QSTDBY = Standby charge over lifetime, tTOT, in mA-hr
tTOT = Total lifetime in hours
ISTDBY = General standby current in A
ILF = LFR detector (if used) current in A

16.2 Measurement Events

The overall charge consumed by the measurements is:
1
Q MEAS = ------------   n PRESS  Q PRESS + n TEMP  Q TEMP + n VOLT  Q VOLT  Eqn. 13
1000
where:
QMEAS = Total measurement charge over lifetime in mA-sec
QPRESS = Measurement charge per pressure measurement in A-sec
QTEMP = Measurement charge per temperature measurement in A-sec
QVOLT = Measurement charge per voltage measurement in A-sec
nPRESS = Total number of pressure measurements over lifetime
nTEMP = Total number of temperature measurements over lifetime
nVOLT = Total number of voltage measurements over lifetime

16.3 Transmission Events

The overall charge consumed by the transmissions is:
Q FRM
Q XMT = -----------------  F  n XMT Eqn. 14
1000
where:
QXMT = Transmit charge over lifetime, tTOT, in mA-hr
QFRM = Transmit charge per frame of data in A-sec
nXMT = Number of transmissions over lifetime
F = Frames transmitted during each datagram

16.4 Total Consumption

The overall charge consumed is:
 Q STDBY + Q MEAS + Q XMT 
Q TOT = ------------------------------------------------------------------------------------ Eqn. 15
 1 – Y  SD  100 
where:
QTOT = Total charge over lifetime, tTOT, in mA-hr
QSTDBY = Standby charge over lifetime in mA-hr
QMEAS = Measurement charge over lifetime in mA-hr
QXMT = Transmit charge over lifetime in mA-hr
Y = Lifetime in years
SD = Battery self-discharge rate in%/year
Additional margin in battery capacity can be added to the calculated value of QTOT.

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17 Electrical Specifications
17.1 Maximum Ratings
Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. The device
contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep VIN and VOUT within the range VSS  (VIN or VOUT)  VDD.

# Rating Symbol Value Unit

100 Supply Voltage (VDD, AVDD) VDD -0.3 to +3.8 V (3)

Input Voltage
101 X1 VIN -0.3 to VDD+0.3 V (3)
102 PTA0, PTA1, PTA2, PTA3, PTB0, PTB1 VIN -0.3 to VDD+0.3 V (3)
103 BKGD/PTA4, RESET VIN -0.3 to VDD+0.3 V (3)
104 LFA, LFB VIN -0.3 to VDD+0.3 V (3)

Input Current
105 X1 IIN ±10 mA (3)
106 PTA0, PTA1, PTA2, PTA3, PTB0, PTB1 IIN ±10 mA (3)
107 BKGD/PTA4, RESET IIN ±10 mA (3)
108 LFA, LFB IIN ±10 mA (3)

Substrate Current Injection

Current from any pin to VSS - 0.3 VDC
109 XI, PTA0, PTA1, PTA2, PTA3, PTB0, PTB1, BKGD/PTA4, RESET ISUB 600 µA (3)
110 LFA, LFB ISUB 2 mA (3)

Latchup Current
111 Current to/from any pin to supply rails + 0.3 VDC ILATCH ±100 mA (3)

Electrostatic Discharge
112 Human Body Model (HBM), all pins other than RF VESD ±2000 V (3)
113 Human Body Model (HBM), RF pin VESD ±3000 V (3)
114 Charged Device Model (CDM) VESD ±500 V (3)

115 Maximum Storage Temperature Range Tstg -50 to +150 °C (3)

Note: Refer to page 167 for description of notes.

17.2 Operating Range

The limits normally expected in the application which define range of operation.

# Characteristic Symbol Min Typ Max Units

Operating Supply Voltage (VDD = AVDD) VL VH

Measurements
200 Pressure, Temperature, Acceleration VDD 2.3 3.0 3.6 V (2)
201 Voltage VDD 1.8 3.0 3.6 V (2)
202 LFR Operation (-20 < TA< +85 °C) VDD 2.3 3.0 3.6 V (2)
203 RF Transmissions VDD 1.8 3.0 3.6 V (2)
MCU operation (CPU, ADC10, RAM, TPM1)
204 FLASH write (-40 to +125 °C) VDD 2.3 3.0 3.6 V (2)
205 FLASH write (-20 to +85 °C) VDD 2.1 3.0 3.6 V (2)
206 FLASH read VDD 1.8 3.0 3.6 V (2)
207 Parameter registers data retention VDD 1.2 — — V (2)

Operating Temperature Range TL TH

208 Continuous Temperature Range TA -40 — +125 °C (3)
209 STOP1 mode (note 5) TA -40 — +150 °C (3)

Note: Refer to page 167 for description of notes.

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17.3 Electrical Characteristics
1.8  VDD  3.6, TL  TA  TH, unless otherwise specified.

# Characteristic Symbol Min Typ Max Units

Output High Voltage (ILoad = 5 mA)

300 PTA0, PTA1, PTA2, PTA3, PTB0, PTB1 VOH VDD-0.35 — — V (2)

Output Low Voltage (ILoad = -5 mA)

301 PTA0, PTA1, PTA2, PTA3, PTB0, PTB1 VOL — — 0.35 V (2)

Input High Voltage (2.3  VDD  VH)

302 PTA0, PTA1, PTA2, PTA3, PTB0, PTB1, BKGD/PTA4 VIH 0.7 x VDD — — V (2)
Input High Voltage (VL  VDD  2.3)
303 PTA0, PTA1, PTA2, PTA3, PTB0, PTB1, BKGD/PTA4 VIH 0.85 x VDD — — V (3)

Input Low Voltage (2.3  VDD  VH)

304 PTA0, PTA1, PTA2, PTA3, PTB0, PTB1, BKGD/PTA4 VIL VSS — 0.35 x VDD V (2)
Input Low Voltage (VL  VDD  2.3)
305 PTA0, PTA1, PTA2, PTA3, PTB0, PTB1, BKGD/PTA4 VIL VSS — 0.28 x VDD V (3)

Input High Current (at min VIH)

306 BKGD/PTA4 IIH -1 — +1 µA (1)
307 PTA0, PTA1, PTA2, PTA3 (pulldown off) IIH -1 — +1 µA (2)
308 PTA0, PTA1, PTA2, PTA3 (pulldown active) IIH 0 — +120 µA (2)

Input Low Current (at max VIL)

309 BKGD/PTA4 IIL -120 — 0 µA (1)
310 PTA0, PTA1, PTA2, PTA3, PTB0, PTB1 (pullup off) IIL -1 — +1 µA (2)
311 PTA0, PTA1, PTA2, PTA3 (pullup active) IIL -120 — 0 µA (2)

Pin Capacitance (3 V)
312 BKGD/PTA4, PTA0, PTA1, PTA2, PTA3, PTB0, PTB1 C 0 — 15 pF (3)

Note: Refer to page 167 for description of notes.

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17.4 Power Consumption (MCU)
1.8  VDD  3.6, TA 0 to 125 °C unless otherwise specified.

# Characteristic Symbol Min Typ Max Units

Standby Supply Current

STOP1 mode, LFR, LVD and TR all off
400 TA = -40 °C, VDD = 3.0 V ISTDBY1 — — 0.9 µA (3)
401 TA = 0 °C, VDD = 3.0 V ISTDBY1 — — 0.9 µA (3)
402 TA = 25 °C, VDD = 1.8 V ISTDBY1 — — 0.8 µA (3)
403 TA = 25 °C, VDD = 3.0 V ISTDBY1 — 0.5 0.72 µA (2)
404 TA = 25 °C, VDD = 3.6 V ISTDBY1 — — 0.9 µA (3)
405 TA = 70 °C, VDD = 3.0 V ISTDBY1 — — 1.5 µA (3)
406 TA = 125 °C, 3.0 V  VDD  3.6 V ISTDBY1 — — 13 µA (3)

Standby Supply Current

STOP4 mode, LFR and TR off, LVD or RFLVD on
407 TA = -40 °C, VDD = 3.0 V ISTDBY4 — — 100 µA (3)
408 TA = 0 °C, VDD = 3.0 V ISTDBY4 — — 100 µA (3)
409 TA = 25 °C, VDD = 1.8 V ISTDBY4 — — 95 µA (3)
410 TA = 25 °C, VDD  3.0 V ISTDBY4 — 73 95 µA (2)
411 TA = 70 °C, VDD  3.0 V ISTDBY4 — — 100 µA (3)
412 TA = 125 °C, 3.0 V  VDD  3.6 V ISTDBY4 — — 140 µA (3)

MCU Operate Current (1.8  VDD  3.0 V, -40 °C  TA  125 °C)

Instruction Speed = 0.333 MIP/fBUS
413 0.5 MHz fBUS, BUSCLKS[1:0] = 11 IDD — 0.72 1.0 mA (3)
414 1 MHz fBUS, BUSCLKS[1:0] = 10 IDD — 0.94 1.1 mA (3)
415 2 MHz fBUS, BUSCLKS[1:0] = 01 IDD — 1.46 1.7 mA (3)
416 4 MHz fBUS, BUSCLKS[1:0] = 00 IDD — 2.50 2.9 mA (1)

Standby Current Adder for Temperature Restart

417 VDD = 1.8 V, TA = 125 °C IDD — 10 15 µA (3)
418 VDD = 3.0 V, TA = 125 °C IDD — 10 15 µA (3)

MCU Wakeup Consumption (+25 °C, 3 V)

419 From STOP1 to first instruction, fBUS = 4 MHz QWAKE 0 0.05 0.1 µA-sec (3)

External Battery Model

420 Series impedance at end-of-life ZEOL — — 60  (3)
421 Open circuit voltage at end-of-life VEOL 2.7 — — V (3)

Note: Refer to page 167 for description of notes.

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17.5 Control Timing
1.8  VDD  3.6, TL  TA  TH, unless otherwise specified.

# Characteristic Symbol Min Typ Max Units

Internal Clock Frequency

500 Initial startup frequency fOSCINIT 6 8 10 MHz (3)
501 Final frequency
502 Full temperature range, -40 °C to +125 °C fOSC 6.8 — 8.1 MHz (3)
503 Complete stabilization time (see Figure 120) tOSCSU — 300 1000 sec (3)

504 MCU Bus Frequency fBUS — 0.5 fOSC — MHz (2)

Medium frequency clock (MFO)

505 Full temperature range, -40 °C to +125 °C fMFO 106 — 128 kHz (3)

Low frequency clock (LFO)

506 Full temperature range, -40 °C to +125 °C fLFO 770 — 1429 Hz (3)

507 LFR clock (derived from LFRO) fLFRO 122 129 135 kHz (1)

Power-On Reset Response

508 Supply voltage rise time tVDDR — — 1 sec (3)
509 Recovery time below VDD = 0.5 V tVDDOFF 0 — 70 sec (3)

MCU Wakeup Time (see Figure 120)

510 From STOP1 to first instruction, fBUS = 4 MHz tMCUWAKE — 50 70 sec (3)
511 From STOP4 to first instruction, fBUS = 4 MHz tMCUWAKE — 100 155 sec (3)
512 FLASH Data Retention Time tDR 10 — — year (4)

Note: Refer to page 167 for description of notes.

HFO = fOSCINIT HFO = fOSC

HFO Clock
tOSCSU

STOP1 Wakeup
tMCUWAKE

execute instructions

Figure 120. MCU Startup Delays

VDD

6.32 k

TEST POINT

50 pF 10.91 k

Figure 121. Control Timing Test Load for Digital Pins

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17.6 Voltage Measurement Characteristics
1.8  VDD  3.6, TL  TA  TH, unless otherwise specified.

# Characteristic Symbol Min Typ Max Units

Lower LVD detect threshold (note 15)
600 VDD falling VLVDL 1.79 1.88 1.96 V (2)
601 VDD rising VLVDL 1.87 — 2.03 V (3)
602 Voltage drop detection time (note 16) tLVDL — — 10 sec (3)
Higher LVD detect threshold (note 15)
603 VDD falling VLVDH 2.05 — 2.3 V (1)
604 VDD rising VLVDH 2.12 — 2.3 V (3)
605 Voltage drop detection time (note 16) tLVDH — — 10 sec (3)
Lower LVW detect threshold (LVWV = 0, note 15)
606 VDD falling VLVWL 2.05 — 2.3 V (1)
607 VDD rising VLVWL 2.12 — 2.3 V (3)
608 Voltage drop detection time (note 16) tLVWL — — 10 sec (3)
Higher LVW detect threshold (LVWV = 1, note 15
609 VDD falling VLVWH 2.28 — 2.54 V (1)
610 VDD rising VLVWH 2.34 — 2.61 V (3)
611 Voltage drop detection time (note 16) tLVWH — — 10 sec (3)
612 RF LVD detect threshold, VDD falling (note 15) VLVDRF 1.60 1.79 1.95 V (2)
613 Voltage drop detection time (note 16) tLVDRF — — 10 sec (3)
Power-On Reset Voltage (note 15)
614 Rising Voltage to Recover VPORR — — 2.1 V (3)
615 Falling Voltage to Reset VPORF 0.8 — — V (3)
Internal Voltage (VDD, monotonic response).
616 VCODE= 0 VINT — FAULT — V (3)
617 = 58 VINT 1.6 1.8 2.0 V (3)
618 = 88 VINT 2.0 2.1 2.2 V (3)
619 = 108 VINT 2.2 2.3 2.4 V (3)
620 = 128 VINT 2.4 2.5 2.6 V (3)
621 = 158 VINT 2.7 2.8 2.9 V (1)
622 = 208 VINT 3.2 3.3 3.4 V (3)
623 = 238 VINT 3.5 3.6 3.7 V (3)
624 = 255 VINT — FAULT — V (3)
625 Voltage sensitivity VINT — 10 — mV/count (3)
External Voltage (PTA[1:0], monotonic response,
conversion is ratiometric to VDD)
626 GxCODE, where x = 0, 1 refers to PTA0 or PTA1 n — 1023 (VIN/VDD) — count (4)
627 Voltage sensitivity VEXT — VDD/1023 — V/count (4)
628 ADC INL INL -1 — +1 LSB (3)
629 ADC DNL DNL -1 — +1 LSB (3)
Voltage Measurement
(internal voltage or external pin)
630 Sensor measurement time (note 7) tVM — 0.45 0.53 ms (3)
631 Peak current (note 8) IV — 3.2 3.9 mA (3)
Power consumption (note 22)
632 Raw measurement, 10-bit QV — 0.13 0.3 µA-sec (3)
633 Compensation, 8-bit QV — 0.40 0.64 µA-sec (3)
634 Basic compensated reading, 8-bit QV — 0.53 0.9 µA-sec (3)
635 Full compensated reading, 8-bit QV — 0.53 0.9 µA-sec (3)

Note: Refer to page 167 for description of notes

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17.7 Temperature Measurement Characteristics
2.3  VDD  3.6, TL  TA  TH, unless otherwise specified.

# Characteristic Symbol Min Typ Max Units

Temperature measurement (monotonic response) (note 11)

700 TCODE = 0 T — FAULT — °C (3)
701 = 15 T -45 -40 -35 °C (3)
702 = 35 T -23 -20 -17 °C (1)
703 = 55 T -3 0 3 °C (3)
704 = 84 T 26 29 32 °C (3)
705 = 125 T 67 70 73 °C (3)
706 = 140 T 81 85 89 °C (1)
707 = 180 T 120 125 130 °C (3)
708 = 255 T — FAULT — °C (3)
709 Temperature sensitivity T — 1.0 — °C/count (3)

710 Temperature measurement stability range (note 10) TSTAB — — 2 count (3)

Thermal Shutdown Recovery (TRE = 1)

711 High Re-Arming Temperature (TRH = 1, note 13) TREARMH — — 125 °C (4)
712 High Reset Temperature (TRH = 1) TRESETH 95 — — °C (4)
713 Low Re-Arming Temperature (TRH = 0, note 13) TREARML -90 — — °C (4)
714 Low Reset Temperature (TRH = 0) TRESETL — — 4 °C (4)

Temperature Measurement
715 Sensor measurement time (note 7) tTM — 0.6 0.7 ms (3)
716 Peak current (note 8) IT — 3.0 3.9 mA (3)
Power consumption (note 22)
717 Raw measurement, 12-bit QT — 0.19 0.3 µA-sec (3)
718 Compensation, 8-bit QT — 0.43 0.6 µA-sec (3)
719 Basic compensated reading, 8-bit QT — 0.62 0.82 µA-sec (3)
720 Full compensated reading, 8-bit QT — 0.62 0.82 µA-sec (3)

Note: Refer to page 167 for description of notes.

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17.8 Pressure Measurement Characteristic (100 to 450 kPa ranges)
2.3  VDD  3.6, TL  TA  TH, unless otherwise specified.
Pressure accuracy specified for pressure drops slower than 1 kPa/sec.

# Characteristic Symbol Min Typ Max Units

Pressure Measurement (note 6)

0 °C TA +70 °C
800 PCODE = 0 P — FAULT — kPa (3)
801 =1 P 93 100 107 kPa (4)
802 = 10 P 100 107 114 kPa (3)
803 = 255 P 268 275 282 kPa (3)
804 = 499 P 436 443 450 kPa (3)
805 = 510 P 443 450 457 kPa (4)
806 = 511 P — FAULT — kPa (3)
-20 °C TA 0 °C, 70 °C TA 85 °C
807 PCODE = 0 P — FAULT — kPa (3)
808 =1 P 89.5 100 110.5 kPa (4)
809 = 10 P 96.5 107 117.5 kPa (3)
810 = 255 P 264.5 275 285.5 kPa (1)
811 = 499 P 432.5 443 453.5 kPa (3)
812 = 510 P 439.5 450 460.5 kPa (4)
813 = 511 P — FAULT — kPa (3)
-40 °C TA -20 °C, 85 °C TA 125 °C
814 PCODE = 0 P — FAULT — kPa (3)
815 =1 P 83.2 100 116.8 kPa (4)
816 = 10 P 90.2 107 123.8 kPa (3)
817 = 255 P 258.2 275 291.8 kPa (3)
818 = 499 P 426.2 443 459.8 kPa (3)
819 = 510 P 433.2 450 466.8 kPa (4)
820 = 511 P — FAULT — kPa (3)

821 Pressure Sensitivity PRANGE — 0.688 — kPa/count (3)

822 Pressure Measurement Stability Range PSTAB — — 6 count (3)

Note: Refer to page 167 for description of notes.

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17.9 Pressure Measurement Characteristic (100 to 900 kPa Ranges)
2.3  VDD  3.6, TL  TA  TH, unless otherwise specified.
Pressure accuracy specified for pressure drops slower than 1 kPa/sec.

# Characteristic Symbol Min Typ Max Units

Pressure Measurement (note 6)

0 °C TA +70 °C
900 PCODE = 0 P — FAULT — kPa (3)
901 =1 P 90 100 110 kPa (4)
902 = 10 P 106 116 126 kPa (3)
903 = 255 P 491 501 511 kPa (3)
904 = 499 P 874 884 894 kPa (3)
905 = 510 P 890 900 910 kPa (4)
906 = 511 P — FAULT — kPa (3)
-20 °C TA 0 °C, 70 °C TA 85 °C
907 PCODE = 0 P — FAULT — kPa (3)
908 =1 P 85 100 115 kPa (4)
909 = 10 P 101 116 131 kPa (3)
910 = 255 P 486 501 516 kPa (1)
911 = 499 P 869 884 899 kPa (3)
912 = 510 P 885 900 915 kPa (4)
913 = 511 P — FAULT — kPa (3)
-40 °C TA -20 °C, 85 °C TA 125 °C
914 PCODE = 0 P — FAULT — kPa (3)
915 =1 P 76 100 124 kPa (4)
916 = 10 P 92 116 140 kPa (3)
917 = 255 P 477 501 525 kPa (3)
918 = 499 P 860 884 908 kPa (3)
919 = 510 P 876 900 924 kPa (4)
920 = 511 P — FAULT — kPa (3)

921 Pressure Range PRANGE — 1.572 — kPa/count (3)

922 Pressure Measurement Stability Range PSTAB — — 4 count (3)

Pressure Sensitivity to Z-Axis Acceleration

(note 12)
923 0-500g PACC 0 — 0 Pa/g (3)
924 >500g PACC -6.5 -4.5 -2 Pa/g (3)

Pressure Measurement
925 Sensor measurement time (note 7) tPM — 4.0 4.4 ms (3)
926 Peak current (note 8) IP — 3.0 3.4 mA (3)
Power consumption (note 22)
927 Raw measurement, 10-bit QP — 2.1 3.35 µA-sec (3)
928 Compensation, 9-bit QP — 1.9 2.3 µA-sec (3)
929 Basic compensated reading, 9-bit QP — 4.0 5.4 µA-sec (3)
930 Full compensated reading QP — 4.4 6.0 µA-sec (3)

Note: Refer to page 167 for description of notes.

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17.10 Optional Acceleration Sensor Characteristics
17.10.1 Example Z-Axis Acceleration Sensor Calculations (similar for X-Axis)
As an example, consider that the dynamic firmware routine has returned STEP = 6 indicating offset step 6, and AZCODE = 256.
First, refer to lines 1000 and 1008 to retrieve the step number 6 values for AZCODE = 510 and for AZCODE = 1. Then apply the
following to calculate the sensitivity for offset step 6:

A = A @A 510 – A @A 1   510
Z-6 Z-6 ZCODE Z-6 ZCODE
=  42.1 –  – 42.9    510

= 0.167g per A integer

ZCODE Eqn. 16

Once the sensitivity AZ-6 has been calculated, the acceleration AZ can be calculated with the following transfer function:

A = A A + A @A 1 – A 
Z Z-6 ZCODE Z-6 ZCODE Z-6

= 0.167  256 +  – 42.9 – 0.167 

=  – 0.3g Eqn. 17

Another example where STEP has been returned as 15 and AZCODE has been returned as 256:

A = A @A 510 + – A @A 1   510
Z-15 Z-15 ZCODE Z-15 ZCODE

=  402 – 315   510

= 0.171g per A integer

ZCODE Eqn. 18

Then:
A = A A + A @A 1 – A 
Z Z-15 ZCODE Z-15 ZCODE Z-15

= 0.171  256 +  315 – 0.171 

=  359g Eqn. 19

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17.10.2 Acceleration Measurement Characteristics (Z and X ranges)
2.3  VDD  3.6, TL  TA  TH, unless otherwise specified.
Acceleration accuracy specified for pressure drops slower than 1 kPa/sec.

FXTH870x02 FXTH870x11 FXTH870x11

Symbol
# Characteristic family (Z-axis) family (Z-axis) family (X-axis) Units
Min Typ Max Min Typ Max Min Typ Max
Acceleration Measurement (note 9)
1000 ACODE = 0 A6 — FAULT — — FAULT — — FAULT — g (3)
1001 =1 A6 -51.9 -42.91 -33.2 g (3)
See See
1002 = 256 A6 -6 0 +6 g (1)
Offset STEP = 7 Offset STEP = 7
1003 = 510 A6 33.0 42.1 51.8 g (3)
1004 = 511 A6 — FAULT — — FAULT — — FAULT — (3)
1005 Average Accel Sensitivity (1 to 510 counts) Aaverage — 0.167 — — 0.118 — — 0.039 — g/count (3)
1006 Average Offset step at acceleration output AINCR 37 39.5 42 — 30 — — 10 — g/Offset (3)
= 256. VDD = 3 V Step
1007 Acceleration measurement stability range ASTAB — — 4 — — 5 — — 4 count (3)
(note 10)
Minimum range of acceleration
measurement for each offset code.
1008 Average Offset STEP= 0 g (3)
1009 ACODE =1 -304 -271 238 — -210 — — -80 —
A0
1010 = 256 — -231 — — -180 — — -70 —
1011 = 510 -215 -191 -167 — -150 — — -60 —
1012 Offset STEP =1 g (3)
1013 ACODE =1 -264 -234 -204 — -180 — — -70 —
A1
1014 = 256 — -193 — — -150 — — -60 —
1015 = 510 -173 -153 -133 — -120 — — -50 —
1016 Offset STEP =2 g (3)
1017 ACODE =1 -223 -197 170 — -150 — — -60 —
A2
1018 = 256 — -156 — — -120 — — -50 —
1019 = 510 -132 -114 97 — -90 — — -40 —
1020 Offset STEP =3 g (3)
1021 ACODE =1 -181 -158 -136 — -120 — — -50 —
A3
1022 = 256 — -117 — — -90 — — -40 —
1023 = 510 -88 -75 -62 — -60 — — -30 —
1024 Offset STEP =4 g (3)
1025 ACODE =1 -140 -120 -100 — -90 — — -40 —
A4
1026 = 256 — -78 — — -60 — — -30 —
1027 = 510 -48 -36 -24 — -30 — — -20 —
1028 Offset STEP =5 g (3)
1029 ACODE =1 -88 -81 -74 — -60 — — -30 —
A5
1030 = 256 -45 -39 -33 — -30 — — -20 —
1031 = 510 -2 4 9 — 0 — — -10 —
1032 Offset STEP =6 g (3)
1033 ACODE =1 See lines 1001-1003 — -30 — — -20 —
A6
1034 = 256 in this ‘D’ version — 0 — — -10 —
1035 = 510 — 30 — — 0 —
1036 Offset STEP =7 g (3)
1037 ACODE =1 -10 -5 1 -5 0 5 -14 -10 -6
A7
1038 = 256 32 38 44 22 30 38 -4 0 4
1039 = 510 74 80 87 46 60 74 6 10 14
1040 Offset STEP =8 g (3)
1041 ACODE =1 23 35 47 — 30 — — 0 —
A8
1042 = 256 — 78 — — 60 — — 10 —
1043 = 510 100 121 142 — 90 — — 20 —

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 FXTH870x02 FXTH870x11 FXTH870x11
Symbol
# Characteristic family (Z-axis) family (Z-axis) family (X-axis) Units
Min Typ Max Min Typ Max Min Typ Max
1044 Offset STEP =9 g (3)
1045 ACODE =1 61 75 88 — 60 — — 10 —
A9
1046 = 256 — 118 — — 90 — — 20 —
1047 = 510 138 160 183 — 120 — — 30 —
1048 Offset STEP = 10 g (3)
1049 ACODE =1 97 115 133 — 90 — — 20 —
A10
1050 = 256 — 158 — — 120 — — 30 —
1051 = 510 173 201 229 — 150 — — 40 —
1052 Offset STEP = 11 g (3)
1053 ACODE =1 134 155 176 — 120 — — 30 —
A11
1054 = 256 — 198 — — 150 — — 40 —
1055 = 510 210 241 273 — 180 — — 50 —
1056 Offset STEP = 12 g (3)
1057 ACODE =1 170 195 221 — 150 — — 40 —
A12
1058 = 256 — 238 — — 180 — — 50 —
1059 = 510 246 281 317 — 210 — — 60 —
1060 Offset STEP = 13 g (3)
1061 ACODE =1 204 235 267 — 180 — — 50 —
A13
1062 = 256 — 279 — — 210 — — 60 —
1063 = 51 280 322 364 — 240 — — 70 —
1064 Offset STEP = 14 g (3)
1065 ACODE =1 240 275 310 — 210 — — 60 —
A14
1066 = 256 — 319 — — 240 — — 70 —
1067 = 510 317 362 408 — 270 — — 80 —
1068 Offset STEP = 15 g (3)
1069 ACODE =1 274 315 356 — 240 — — 70 —
A15
1070 = 256 — 359 — — 270 — — 80 —
1071 = 510 350 402 455 — 300 — — 90 —
2.3  VDD  3.6, -20 °C  TA  85 °C, unless otherwise specified.
All families
# Characteristic Symbol Units
Min Typ Max
1072 Acceleration cross-axis sensitivity ACROSS -5 — 5 % (4)
1073 Acceleration Sensitivity Variation AZ -15 0 15 % (4)
Z-axis Acceleration Measurement
1074 Sensor measurement time (note 7) tAM — 4.0 4.8 ms (3)
1075 Peak current (note 7) IA — 3.0 3.4 mA (3)
Power consumption
1076 Raw measurement, 10-bit QC — 2.1 3.6 A-sec (3)
1077 Compensation, 9-bit QC — 1.9 2.3 A-sec (3)
1078 Basic compensated reading, 9-bit QC — 4.0 6.0 A-sec (3)
1079 Full compensated reading, 9-bit QC — 4.4 6.2 A-sec (3)
Note: Refer to page 167 for description of notes.

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17.11 LFR Sensitivity
2.3  VDD  3.6, -20 °C  TA  85 °C, unless otherwise specified. Detection and no detection criteria defined by notes 19 and 20.
# Characteristic Symbol Min Typ Max Units

LFR Input Sensitivity in carrier mode, 125 kHz carrier,

LFCDTM = 256 S UOS
Very Low Sensitivity, SENS(1:0) = 00
1100 Detect level, LFA:B SDET_VL — — 60 mV p-p (4)
1101 No detect level, LFA:B SNODET_VL 24 — — mV p-p (4)
Low Sensitivity, SENS(1:0) = 00
1102 Detect level, LFA:B SDET_L — — 14 mV p-p (4)
1103 No detect level, LFA:B SNODET_L 2 — — mV p-p (4)
High Sensitivity, SENS[1:0] = 10, CHK125 = 01
1104 Detect level, LFA:B SDET_H — — 3.5 mV p-p (2)
1105 No detect level, LFA:B SNODET_H 0.5 — — mV p-p (2)
Sensitivity Shift in High Sensitivity,
SENS[1:0] = 10, CHK125 = 00
1106 Detect level, LFA:B SDET_H — -0.12 — mV p-p (3)
1107 No detect level, LFA:B SNODET_H — -0.12 — mV p-p (3)

LFR Input Sensitivity in data mode

125 kHz carrier, LFCDTM = 64 sec
Valid reception of 10 consecutive frames of 16-bit
Manchester bit preamble + 9T SYNC +16-bit ID + 4 bytes of
data. Continuously ON
High Sensitivity, SENS[1:0] = 10, CHK125 = 01
1108 Data detect level SPER_H — — 3.5 mV p-p (2)
1109 Data no detect level SNOPER_H 0.25 — — mV p-p (2)

LFR Input Sensitivity in data mode

125 kHz carrier, LFCDTM = 64 sec
Valid reception of 10 consecutive frames of 16-bit
Manchester bit preamble + 9T SYNC +16-bit ID + 4 bytes of
data. Continuously ON
Low Sensitivity, SENS[1:0] = 01, CHK125 = 00
1110 Data detect level SPER_L — — 14 mV p-p (3)
1111 Data no detect level SNOPER_L 2 — — mV p-p (3)

Note: Refer to page 167 for description of notes.

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17.12 LFR Characteristics
2.3  VDD  3.6, -20 °C  TA  85 °C, unless otherwise specified.
# Characteristic Symbol Min Typ Max Units

LF Input Signal Characteristics

Relative to High Sensitivity Data Mode Always Detect, SPER_H
1200 Dynamic Range, DEQEN = 0 VIN 56 — — dB (3)

LFR Input Signal Characteristics

(Manchester Data Mode)
1201 Modulation Depth (Data 1 - Data 0)/Data 1 MR 70 — 100 % (3)
1202 Data bit time tDATA 248 256 264 sec (3)
1203 Bit Duty Cycle MDC 45 — 55 % (3)

LFR Differential Input (LFA to LFB, Figure 122)

1204 Differential Resistance RLFDF 1 — 4 M (3)
1205 Differential Capacitance (C3) CLFDF 2 3.8 6 pF (3)

LFR Carrier Frequency Range

VALEN = 1, LFCDTM = 256 sec
1206 Always accepted carrier fLFC 121.25 — 128.75 kHz (3)
1207 Always rejected carrier, low band limit fLFC — — 80 kHz (3)
1208 Always rejected carrier, high band limit fLFC 210 — — kHz (3)
VALEN = 0, LFCDTM = 256 ms
1209 High Cutoff Freq, 5 mV p-p input, SENS[1:0] = 00 fLFC — 350 — kHz (4)

1210 LFR Detector Power Up Settling Time (2 LFO cycles) tPU 1.4 2.0 2.6 ms (4)
LFR Preamble Decoder Settling Time
Data Mode Only, LFCDTM plus tDEC
1211 LPSM = 0 tDEC — — 200 sec (4)
1212 LPSM = 1 tDEC — — 400 sec (4)

Note: Refer to page 167 for description of notes.

17.13 LFR Power Consumption

2.3  VDD  3.6, -20 °C  TA  85 °C, unless otherwise specified. All parameters based upon DEQEN = 0 setting.

# Characteristic Symbol Min Typ Max Units

LFR Supply Current, Carrier Detect Mode
Monitor for carrier with VALEN = 0, LPSM = 1
1300 TA = 25 °C, 3.0 V VDD — 3.9 —
1301 TA = -40 °C to 125 °C, 2.3 to 3.6 V VDD ILFR — — 5.7 µA (3)
Frequency validation with
VALEN = 1, LPSM = 1 and CHK125 = 00
1302 TA = 25 °C, 3.0 V VDD — 5.6 —
1303 TA = -40 °C to 125 °C, 2.3 to 3.6 V VDD ILFR — — 7.5 µA (3)
Frequency validation with
VALEN = 1, LPSM = 1 and CHK125 = 01
1304 TA = 25 °C, 3.0 V VDD — 5.8 —
1305 TA = -40 °C to 125 °C, 2.3 to 3.6 V VDD ILFR — — 8.0 µA (1)

LFR Supply Current, Manchester Data Mode

Decoding of data stream after carrier detected
1306 TA = 25 °C, 3.0 V VDD — 11.8 —
1307 TA = -40 °C to 125 °C, 2.3 to 3.6 V VDD ILFR — — 13.5 µA (3)

Note: Refer to page 167 for description of notes.

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 SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
SIMPLIFIED
Pad
ZS leakage CHANNEL SELECT
RS, CS due to CIRCUIT
input
RADIN
protection
+ LFA
VLFIN
RS –
VAS
R1
L
C R CS
RLFDF
L S Input
CLFDF Amplifier
SIMPLIFIED
Pad
leakage CHANNEL SELECT
due to CIRCUIT R2
input
RADIN
LFB protection

Recommended RC < 15.3 sec

Figure 122. LFR Detector Input Equivalent Circuit

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17.14 RF Output Stage
1.8  VDD  3.6, TL  TA  TH, unless otherwise specified.
Power output based on using Dynamic RF Power Correction firmware routine.
Output load of 50  resistance as shown in Figure 125 unless otherwise specified.
MCU in STOP1 mode during all RF tests.
RF output will shutdown when the total RF IDD causes VDD to fall below 1.8 V (VDD = VBATT - IBATT x RBATT). See Figure 126.

# Characteristic Symbol Min Typ Max Units

Nominal Output Power with 50  matching network

(note 7)
(1)
1400 315 MHz, TA = 25 °C, VDD = 3 V, PWR[4:0] = 01110 PRF 4.0 5.2 6.0 dBm
(1)
1401 434 MHz, TA = 25 °C, VDD = 3 V, PWR[4:0] = 01111 PRF 3.5 4.9 6.0 dBm
(1)

Nominal Output Power with 50  matching network

at maximum power step, PWR[4:0] = 10100.
1402* Temperature and voltage range defined
by Figure 123 and Figure 124. PRF 3 — — dBm (3)
Programmable Power Adjustment
PWR[4:0] = 00000 through 11111
1403 Low Power Mode (PWR[4:0] = 00000) PLPM — -10 — dBm (3)
1404 Range (nominal, (PWR[4:0] > 00000) PRF -1.5 — 8.0 dBm (3)
1405 Adjustment step (-1.5 to +8 dBm) PADJ — 0.5 — dBm (3)

Programmable Frequency Steps

Carrier & FSK Deviation
1406 (AFREQ[12:0] and BFREQ[12:0]) fSTEP — 3.174 — kHz (3)

1407 External Crystal Frequency (note 14) fXTAL — 26.000 — MHz (3)
1408 Fixed portion of RF start process tS-RCTS — — 300 sec (3)

1409 Variable portion of RF start process Bits — 3 — bit times (4)

Total RF transmit start time from write of SEND bit to start of tRF2
1410 — — 1.8 msec (3)
RF @ 2,000 bps, tRF = tS-RCTS + (Bits * bps-1)

1411 Total RF transmit start time from write of SEND bit to start of tRF9.6 — — 613 sec (3)
RF @ 9,600 bps, tRF = tS-RCTS + (Bits * bps-1)

Total RF transmit start time from write of SEND bit to start of tRF20 — — 450 sec (3)
1412
RF @ 20,000 bps, tRF = tS-RCTS + (Bits * bps-1)

1413 OOK Modulation Depth MOOK 50 — — dBc (3)

Manchester Encoding Data Rate

1414 Bit Rate Dependent on accuracy of MFO (note 18) DR — — ±5 % (3)

1415 Modulation Duty-Cycle (OOK and FSK) DC 45 50 55 % (3)

1416 XTAL Oscillator Margin (over 26 MHz) (note 17) ML 600 — —  (4)

Harmonic 2 Level (315 and 434 MHz bands, with matching

reference network)
VDD = 3 V, TA = 25 °C, PWR[4:0] = 01110
1417 H2 — -35 -22 dBc (3)
1.8  VDD  3.6, TL  TA  TH, power step adjusted to
1418 H2 — -25 -20 dBc (3)
reach the targeted power in each domain

Harmonic 4 Level and above (315 and 434 MHz bands, with
matching reference network)
1419 VDD = 3 V, TA = 25 °C, PWR[4:0] = 01110 H4 — — -30 dBc (3)
1420 1.8  VDD  3.6, TL  TA  TH, power step adjusted to H4 — — -30 dBc (3)
reach the targeted power in each domain

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 # Characteristic Symbol Min Typ Max Units

Harmonic 3 Level (315 and 434 MHz bands, with matching

reference network)
1421 VDD = 3 V, TA = 25 °C, PWR[4:0] = 01110 H3 — -31 -28 dBc (3)
1422 1.8  VDD  3.6, TL  TA  TH, power step adjusted to H3 — -27 -25 dBc (3)
reach the targeted power in each domain

Noise for BOOST = 0

Phase Noise (315 MHz)
1423 fRF  10 kHz NPH — -86 -78 dBc/Hz (3)
1424 fRF  100 kHz NPH — -92 -86 dBc/Hz (3)
1425 fRF  1 MHz NPH — -84 -82 dBc/Hz (3)
Phase Noise (434 MHz)
1426 fRF  10 kHz NPH — -84 -76 dBc/Hz (3)
1427 fRF  100 kHz NPH — -89 -83 dBc/Hz (3)
1428 fRF  1 MHz NPH — -82 -80 dBc/Hz (3)
Spurious Noise (315 and 434 MHz bands)
1429 fRF fREF NSPUR — -45 -40 dBc (3)
Occupied Bandwidth (Korea, MIC 2007-63)
1430 For FSK up to 45 kHz and 9600 bit/sec and OBWK — — 180 kHz (3)
for OOK up to 9600 bit/sec
Analyzed setup: RBW = VBW up to 10 kHz,
Span up to 1.25 MHz, and MaxHold
Noise for BOOST = 1
Phase Noise (315 MHz)
1431 fRF  10 kHz NPH — -75 -67 dBc/Hz (3)
1432 fRF  100 kHz NPH — -80 -76 dBc/Hz (3)
1433 fRF  1 MHz NPH — -95 -93 dBc/Hz (3)
Spurious Noise (315 MHz bands)
1434 fRF fREF NSPUR — -45 -40 dBc (3)
Occupied Bandwidth (Japan, ARIB STD-T93)
1435 For FSK up to 45 kHz and 9600 bit/sec OBWJ — — 400 kHz (3)
1436 For OOK up to 9600 bit/sec OBWJ — — 600 kHz (3)
Analyzed setup: RBW = VBW up to 30 kHz,
Span up to 3.5 MHz, and MaxHold

1437 RF Oscillator Frequency Accuracy, XCO (note note 21)

fXCO -30 — +30 ppm (3)
excluding external crystal and component variations

Note: Refer to page 167 for description of notes.

* Freescale critical parameter.

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17.15 Power Consumption RF Transmissions
1.8  VDD  3.6, TA 25 °C unless otherwise specified.

# Characteristic Symbol Min Typ Max Units

RF Supply Transmission Current

VDD = 3.0 V, PWR[4:0] set for nominal 5 dBm
1500 315 MHZ Power delta for BOOST = 1 IDD — — 0.55 mA (2)
1501 315 MHZ Carrier Frequency, BOOST = 0
1502 Data 1, FSK or OOK IDD — 6.0 7.0 mA (1)
434 MHZ Carrier Frequency, BOOST = 0
1503 Data 1, FSK or OOK IDD — 6.6 7.6 mA (1)
1504 Interframe period, IFPD = 0. IDD — 617 696 A (3)
1505 Interframe period, IFPD = 0, 1.8 VDD 3.6, IDD — — 789 A (3)
TL  TA  TH
1506 Interframe period, IFPD = 1, DRLPEN = 1, IDD — 20 30 A (3)
1.8 VDD 3.6, TL  TA  TH
1507 Interframe period, IFPD = 1, DRLPEN = 0 IDD — 77 96 A (3)
1508 Interframe period, IFPD = 1, DRLPEN = 0, IDD — — 125 A (3)
1.8 VDD 3.6, TL  TA  TH

Note: Refer to page 167 for description of notes.

Using the TPMS_RF_DYNAMIC_POWER firmware routine (see Section 14) allows adjusting power step in order to compensate
variations of output power versus temperature and voltage. This routine will be associated to a part to part trimming that initially
adjusts the power step to compensate for process variations.
Both these trim and look-up table allow to guarantee by characterization the typical values of power consumption as presented
below (average values among 100 parts plus improvements prediction from design).

3.6V
5.3mA
5.0mA 5.5mA
5.3mA 6mA
6.2mA 6.2mA
6.4mA 5.8mA
5.8mA

3V
.6mA
6.2mA
5dBm
5dBm 3dBm

3dBm
3dBm
3dBm 6.4mA 6.5mA 5.8mA
6.3mA 6.6mA 5.7mA

2.5V

5.2mA
5.3mA 5.4mA
5.5mA
1.8V

-40°C 0°C 25°C 60°C 125°C

Figure 123. Dynamic Power Adjustment - 315 MHz

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 3.6V
5.5mA
5.6mA 5.7mA
5.8mA 6.7mA
6.9mA 6.8mA
7.1mA 6.4mA
6.6mA

3V . 6.6mA
6.9mA
5dBm
5dBm 3dBm
3dBm
3dBm
3dBm
7.0mA
7.1mA 7.5mA
7.8mA 7.0mA
6.8mA

2.5V

5.8mA
6.3mA 6.2mA
6.5mA
1.8V

-40°C 0°C 25°C 60°C 125°C

Figure 124. Dynamic Power Adjustment - 434 MHz

100 pF 100 nF
VDD

L1

RF L2
FXTH870xxx 1 nF

50 

RVSS

Figure 125. RF Output Power Measurement Configuration

IBATT
FXTH870xxx
AVDD
RBATT
VBATT
2.7V

1 F

AVSS

Figure 126. Battery Performance Test Configuration

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18 Mechanical Specifications
18.1 Maximum Ratings
Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. The device
contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep VIN and VOUT within the range VSS  (VIN or VOUT)  VDD.

# Rating Symbol Value Unit

Maximum Pressure (absolute)

1800 Continuous pmax 1500 kPa (3)
1801 Pulsed, 5 seconds, 25 °C pmax 2000 kPa (3)

Centrifugal Force Effects (Z-axis)

1802 Sustained acceleration (Z-axis) gCENT 2600 g (3)

1803 Powered Shock (peak, 0.1 ms, half-sine, 6-axis) gshock 6000 g (3)

1804 Drop Test (onto concrete, unpowered) hDROP 1.2 m (3)

Pressure Sensor Resonance

1805 Resonant frequency fP0 5.5 MHz (4)
1806 Damping Ratio QP 1 (4)

Optional X-axis Accelerometer Sensor Resonance

1807 Resonant frequency (no-peak, over-damped) fX0 12.5 kHz (4)
1808 Damping Ratio QX 0.1 (4)
1809 Maximum acceleration before limit stops are reached gMAX 180 g (4)

Optional Z-axis Accelerometer Sensor Resonance

1810 Resonant frequency (no-peak, over-damped) fZ0 9 kHz (4)
1811 Damping Ratio QZ 5 (4)
1812 Maximum acceleration before limit stops are reached gMAX 800 g (4)

1813 Package Weight w 0.30 gm (3)

Note: Refer to page 167 for description of notes.

18.2 Media Compatibility

Media compatibility is based on media and test method described in Freescale specification 12MWS10081G, Media Test for
TPMS MCM Automotive Pressure Sensors. Consult your sales representative for more details and specific requirements.

18.3 Mounting Recommendations

The package should be mounted with the pressure port pointing away from the axis of tire rotation so that centrifugal force will
propel any contaminants out of the pressure port. In cases where the application must orient the pressure port pointing inward,
care must be taken to assure contaminants do not reach inside the pressure port.
A plugged port will exhibit no change in pressure and can be cross checked in the user’s software using the method described
in Section 10.1.
Please refer to application note AN1902 for proper printed circuit board attributes and recommendations.

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 Notes:
1. Parameters tested 100% at final test.
2. Parameters tested 100% at unit probe.
3. Verified by characterization, not tested in production.
4. For information only, may be determined by simulation.
5. Total of three hours over the life of the device.
6. Fully compensated pressure reading using TPMS_READ_PRESSURE followed by TPMS_COMP_PRESSURE
routine with single reading and 500 Hz low-pass filter ON.
7. Measurement times for one complete compensated reading; and times dependent on clock tolerances.
8. Peak currents measured as the current over 10 MCU bus cycles immediately after the ADC wakes up the MCU
using the external network shown in Figure 126 with RBATT equal to zero-ohm resistance.
9. Fully compensated acceleration reading using TPMS_READ_ACCELERATION followed by
TPMS_COMP_ACCELERATION routine with single reading and 500 Hz low-pass filter ON.
10. Total range of variation over 30 consecutive measurements, using compensated output format.
11. Temperature error for MCU or RFM powered up at less the 10% duty-cycle
12. Package mounted with pressure port facing radially outward from axis of rotation.
13. Temperature shutdown points trimmed at final test. Limits when TRH ($180F bits 6:4) overwritten by customer
application to 0x06.
14. Suggested crystal is NDK NX3225SA, 26.000 MHz.
15. Low voltage detection and warning thresholds defined for voltage change rates less than 20 mV/s. Hysteresis
thresholds may decrease above 85 °C.
16. Response time to VDD of more than 100 mV below the minimum VDD falling threshold.
17. Crystal oscillator margin is the value of the total series resistance including the XTAL ESR, that can be applied
before the XCO does not start up. This definition does not define any specific start up time.
18. Accuracy of the RF data rate when using the data buffer is dependent on the overall oscillator function (i.e.
including external crystal and internal circuit tolerances).
19. LFR detection is tested to assure > 90% message success rate. LFR no detection is tested to assure < 10%
message success rate. In carrier detect mode the applied input pulse is at least 2x the LFCDTM selected. In all
cases the envelop of the input waveform must have a RC time constant less than 15.3 sec. LF sensitivity limits
are measured while the device is in the STOP1 mode, which is characterized as a worst-case condition; sensi-
tivity in the other modes are improved versus the STOP1 modes.
20. Using firmware release $28 or higher.
21. Actual final test value degraded by losses in the tester. Correlation study done as characterization to infer actual
value.
22. Power consumption values refer to the firmware data flow in Figure 57. The BASIC Compensated value includes
just the raw measurement and compensation routine for that parameter. Other raw readings needed for full com-
pensation will be pulled from the UUMA. The FULL Compensated value includes taking all required raw read-
ings and using the compensation routine for that parameter.

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19 Package Outline

Figure 127. QFN Case Outline

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 Figure 128. QFN Case Outline

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 Figure 129. QFN Case Outline

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20 Revision History
Rev. 0, 05/2014
• Initial data sheet.
Rev. 1, 05/2014
• Corrected Ordering Information table.
• Figure 5: Updated paragraph in figure to include PCB traces for the LFA/LFB.
• Section 5.4: Updated register figure to include TRO bit on Bit 0. Added Description to Table 19 and update reserved bit fields.
• Section 6.1: Updated last paragraph in section.
• Section 10.1: Added NOTE.
• Section 10.4: Added NOTE.
• Section 14.2.2: Added definitions for ID codes.
• Section 17.5: Added rows 510 and 511, renumbering 510 to 512.
• Section 17.10.2: Changed column content reference from See lines 1042-1045 to See Offset STEP = 7. Change column
content reference See lines1001-1009 to See lines 1001-1004 in this ‘D’ version.
• Section 17.12: Updated Characteristic and Min Value for line 1200. Updated Characteristic and note reference for line 1210.
• Section 17.4: Updated Symbols for lines 400 through 412 and lines 417 and 418. Updated Max value for line 403
• Section 17.6: Updated Max value for line 612 and updated note reference and Symbol for line 613.
• Section 17.7: Updated note references for lines 711-714.
• Section 17.9: Updated Typ and Max values for line 924. Updated Typ values for lines 927 through 930.
• Section 17.10.2: Deleted line 1073 and updated Typ values for lines 1078 through 1081.
• Section 17.11: Deleted lines 1108-1113, duplicated information. Updated Typ value for line 1106.
• Section 17.12: Updated Symbols for lines 1208 through 1210 and updated Characteristics for lines 1208 and 1209.
• Section 17.13: Updated Max value for line 1301.
• Section 18.1: Updated Max value for line 1800.
Rev. 1.2, 09/2014
• First page: Updated bullet “Six multipurpose GPIO pins” to “Seven multipurpose GPIO pins” and sub-bullets.
• Section 2.3.8: Updated paragraph with additional content.
• Section 2.3.9: Updated title and paragraphs with corrected pin numbers and added text to paragraph.
• Section 2.3.12: Updated content in paragraph.
• Section 3.5.4: Updated header title for I/O Pins, deleted (Optional PTA[3:0]).
• Section 4.3: Table 3, updated Bit contents for Address columns $0000 and $0003.
• Section 5.11.2: Table 26, updated Description for BKGDPE Field
• Section 6: Updated content in first two paragraphs. Updated Figure 29, added boxes and note for emphasis on PTA[3:0]
usage. Updated title and column heads in Table 32 and added rows for PTBPE and PTBDD. Figure 31 and Table 34, updated
Bit 4 to Reserved and updated Field name. Figure 32 and Table 35, updated Bit 4 to Reserved and updated Field name.
Updated first paragraph in Section 6.5.
• Section 7: Section 7.1: Updated 1st bullet. Section 7.2.1: Updated content in first paragraph. Section 7.5: Updated bulleted
text. Sections 7.5.2 and 7.5.3: Updated tables and figures to show bits reserved for firmware or factory test. Section 7.6:
Updated content in second paragraph. Section 7.6.3: Updated content in paragraph. Section 7.6.4: Updated list number 3
and 4.
• Section 12.17.1: Updated LF Enable description in Table 59.
• Section 12.17.4: Table 62, removed “Use Software polling” from LFCDIE and LFIDIE Descriptions.
• Section 12.17.8: Added Note after Table 67 regarding setting the CHK125 bits and updated Description for Field 1-0,
CHK125[1:0].
• Section 14.2.1.1: Table 86, changed Routine and Description columns for E084 to Reserved. Table 87, changed Routine and
Description columns for E090 to Reserved.
• Section 17.1: Added Value to line 108.
• Section 17.3: Updated Characteristic for line 311.
• Section 17.12: Updated Min and Max values for line 1206 and updated Characteristic.
• Section 17.4: Updated Characteristic for line 412.

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Rev. 1.2, 09/2014 (continued)
• Section 17.6 Updated Value for line 631.
• Section 17.8: Added asterisk notes to lines 821 and 822.
• Section 17.9: Added asterisk notes to lines 921 and 922.
• Section 17.13: Updated introduction paragraph.
• Section 17.14: Added asterisk note to line 1402. Redefined lines 1408 through 1411 and added line 1412.
• Section 17.15: Updated Characteristic for line 1500. Updated Typ value for line 1505.
• Section 18.1: Updated Value for line 1802.
• Notes page: Updated Notes 2, 18,19, 20 and added note 25.
Rev. 1.3, 01/2015
• Section 17.3: Updated Characteristic column for lines 303, 305, 307, 308, 310, and 311. Changed note reference for lines
306 and 309. Updated Min and Max values for lines 308 and 311.
• Section 17.6: Changed note reference for lines 603, 606, and 609.
• Section 17.6: Updated Max value for line 711. Updated Min Value for line 712.
• Section 17.10.2: Deleted line 1002.
• Section 17.15: Changed note reference for lines 1503 and 1505. Replaced Figures 123 and 124.
• Notes page: Updated note 13.
• Replaced case outline with current version.
Rev. 1.4, 02/2015
• Section 14.2.2: Table 88, added two columns, “Initial Address” and “Updated Address”.

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Document Number: FXTH870xD

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