Electronics Instrumentation System (MODULE 4)
Electronics Instrumentation System (MODULE 4)
Excitation
Sensor S/H
p Signal
conditioner General
Physical MUX Purpose
ADC
System Computer
Data-acquisition board
Pulse
Comparator
Oscillation Saw-
tooth Signal closes gate
wave Gate Pulse
Circuit High Freq.
pulse
Oscillation
volts volts
Sampling
t1 tn
Time Time
Figure 4.3.1 Sampling Process
The sampling process determines the quality of the
analogue signal that is converted. Higher sampling
frequency achieves better conversion of the analogue
signals. The minimum sampling frequency required
to represent the signal should at least be twice the
maximum frequency of the analogue signal under test
(this is called the Nyquist rate). If the sampling frequency
is equal or less than the twice the frequency of the input
signal, a signal of lower frequency is generated from such
a process.
4.3.2 Analog-to-Digital Conversion (ADC)
Once the signal has been sampled, one needs to covert
the analog samples into a digital code. This process is
called analog-to-digital conversion. This is shown in
Figure below:
volts
ADC
t0 tn
Time
Time Digital
sample Code
t
0 000
t
1
001
t
2 010
t3 011
t4 100
t5 101
t6 110
t7 111
4.3.3 Resolution
Precision of the analogue input signal converted into
digital format is dependent upon the number of bits
the ADC uses. The resolution of the converted signal
is a function of the number of bits the ADC uses to
represents the digital data. The higher the resolution,
the higher the number of division the voltage range is
broken into, and therefore, the smaller the detectable
voltage change. An 8-bit ADC gives 256 levels
compared to a 12-bit ADC that has 4096 levels.
Hence, 12-bit ADC will be able to detect smaller
increments of the input signals than an 8-bit ADC.
Sample hold
Figure 4.4 Basic Sample-and-Hold Circuits
The circuit uses two FET-input OPS-amp voltage
followers (IC1 and IC2), FET electronic switch (S)
and high-quality capacitor C.
Sample mode takes place when the switch S is closed
i.e S is conducting (during this mode the capacitor
charges up exponentially through the low output
impedance of IC1).
Hold mode occur when the switch is open i.e when S
is not conducting (the charged capacitor voltage
represents the value of the input signal at that instant).
EEE 520 TUTORIAL (MODULE 4)
(a)Explain:
(i) the main processes that take place during the conversion of
analogue signal from the sensor to digital signal required for
data processing with digital computer.
(ii) the term resolution for an analog-to-digital converter
(ADC).
(b) An analog voltage signal of 0-15V at 1 KHz is to be
measured by a digital voltmeter (DVM), with resolution of
0.1%. Determine the
(i) minimum sampling rate to avoid loss of signal.
(ii) minimum number of bits in the digital code.
(iii) number of decision levels.
(iv) range of most significant bit (MSB).
(v) number of bits if the converter divides a full scale of the
voltmeter.
(vi) dynamic range analog-digital converter (ADC) in dB.
(vii) rms value of the quantization error.