TPS74801-Q1

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1.5 A Low-Dropout Linear Regulator with Programmable Soft-Start

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1FEATURES APPLICATIONS
•
2 Qualified for Automotive Applications • FPGA Applications
• AEC-Q100 Qualified with the Following • DSP Core and I/O Voltages
Results: • Post-Regulation Applications
– Device Temperature Grade 1: –40°C to • Applications with Special Start-Up Time or
125°C Ambient Operating Temperature Sequencing Requirements
Range • Hot-Swap and Inrush Controls
– Device HBM ESD Classification Level H2
– Device HBM ESD Classification Level C4B DESCRIPTION
• VOUT Range: 0.8 V to 3.6 V The TPS74801-Q1 low-dropout (LDO) linear regulator
• Ultralow VIN Range: 0.8 V to 5.5 V provides an easy-to-use robust power management
solution for a wide variety of applications. User-
• VBIAS Range 2.7 V to 5.5 V programmable soft-start minimizes stress on the input
• Low Dropout: 60 mV typ at 1.5 A, VBIAS = 5 V power source by reducing capacitive inrush current
• Power Good (PG) Output Allows Supply on start-up. The soft-start is monotonic and well-
Monitoring or Provides a Sequencing Signal suited for powering many different types of
processors and ASICs. The enable input and power
for Other Supplies
good output allow easy sequencing with external
• 2% Accuracy Over Line/Load/Temperature regulators. This complete flexibility permits the user to
• Programmable Soft-Start Provides Linear configure a solution that meets the sequencing
Voltage Startup requirements of FPGAs, DSPs, and other
applications with special start-up requirements.
• VBIAS Permits Low VIN Operation with Good
Transient Response A precision reference and error amplifier deliver 2%
• Stable with Any Output Capacitor ≥ 2.2 μF accuracy over load, line, temperature, and process.
The device is stable with any type of capacitor
• Available in a Small 3-mm x 3-mm x 1-mm greater than or equal to 2.2 μF, and is fully specified
SON-10 and 5 x 5 QFN-20 Packages from –40°C to 105°C for the DRC package, and from
–40°C to 125°C for the RGW package. The
TPS74801-Q1 is offered in a small 3-mm × 3-mm
SON-10 package, yielding a highly compact, total
solution size. It is also available in a 5 x 5 QFN-20 for
compatibility with the TPS74401.

CSS = 0nF

VIN IN PG 0.5V/div CSS = 1nF VOUT

CIN BIAS R3
CSS = 2.2nF
TPS74801 OUT VOUT
EN
VBIAS R1
SS COUT
CBIAS GND FB 1.2V
VEN
CSS R2
1V/div 0V

Time (1ms/div)

Figure 1. Typical Application Circuit (Adjustable) Figure 2. Turn-On Response

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS (1)

At TA = –40°C to 105°C (for TPS74801TDRCRQ1), TA = –40°C to 125°C (for TPS74801QRGWRQ1), unless otherwise noted.
All voltages are with respect to GND.
TPS74801-Q1 UNIT
VIN, VBIAS Input voltage range –0.3 to 6 V
VEN Enable voltage range –0.3 to 6 V
VPG Power good voltage range –0.3 to 6 V
IPG PG sink current 0 to 1.5 mA
VSS Soft-start voltage range –0.3 to 6 V
VFB Feedback voltage range –0.3 to 6 V
VOUT Output voltage range –0.3 to VIN + 0.3 V
IOUT Maximum output current Internally limited
Output short-circuit duration Indefinite
PDISS Continuous total power dissipation See Thermal Information Table
TJ Operating junction temperature range –40 to 150 °C
TSTG Storage junction temperature range –55 to 150 °C
Electrostatic Human body model (HBM) classification level H2 2000 V
Discharge
(ESD) Ratings Charged device model (CDM) classification level C4B 750 V

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.

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THERMAL INFORMATION
TPS74801-Q1 (2)
(1)
THERMAL METRIC RGW DRC UNIT
20 PINS 10 PINS
θJA Junction-to-ambient thermal resistance (3) 35.6 41.5
(4)
θJCtop Junction-to-case (top) thermal resistance 33.3 78
θJB Junction-to-board thermal resistance (5) 15 N/A
°C/W
ψJT Junction-to-top characterization parameter (6) 0.4 0.7
ψJB Junction-to-board characterization parameter (7) 15.2 11.3
θJCbot Junction-to-case (bottom) thermal resistance (8) 3.8 6.6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) Thermal data for the RGW and DRC packages are derived by thermal simulations based on JEDEC-standard methodology as specified
in the JESD51 series. The following assumptions are used in the simulations:
(a) i. RGW: The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array.
MMii. DRC: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.
(b) i. RGW: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
MMii. DRC: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20%
MMcopper coverage.
(c) This data was generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-in × 3-in copper area.
To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction
Temperature sections of this data sheet.
(3) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(6) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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ELECTRICAL CHARACTERISTICS
At VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CNR = 1 nF, IOUT = 50 mA, VBIAS = 5 V, TA = –40°C to
105°C (DRC) and TA = –40°C to 125°C (RGW), unless otherwise noted. Typical values are at TA = 25°C.
TPS74801-Q1
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range VOUT + VDO 5.5 V
VBIAS Bias pin voltage range 2.7 5.5 V
VREF Internal reference (Adj.) TA = 25°C 0.796 0.8 0.804 V
Output voltage range VIN = 5 V, IOUT = 1.5 A VREF 3.6 V
VOUT 2.97 V ≤ VBIAS ≤ 5.5 V,
Accuracy (1) –2 ±0.5 2 %
50 mA ≤ IOUT ≤ 1.5 A
VOUT/VIN Line regulation VOUT (NOM) + 0.3 ≤ VIN ≤ 5.5 V 0.03 %/V
VOUT/IOUT Load regulation 50 mA ≤ IOUT ≤ 1.5 A 0.09 %/A
(2) IOUT = 1.5 A, 60 165 mV
VIN dropout voltage
VDO VBIAS – VOUT (NOM) ≥ 3.25 V (3)
VBIAS dropout voltage (2) IOUT = 1.5 A, VIN = VBIAS 1.31 1.6 V
ICL Current limit VOUT = 80% × VOUT (NOM) 2.0 5.5 A
IBIAS Bias pin current 1 2 mA
Shutdown supply current
ISHDN VEN ≤ 0.4 V 1 50 μA
(IGND)
IFB Feedback pin current –1 0.150 1 μA
1 kHz, IOUT = 1.5 A,
60
Power-supply rejection VIN = 1.8 V, VOUT = 1.5 V
dB
(VIN to VOUT) 300 kHz, IOUT = 1.5 A,
30
VIN = 1.8 V, VOUT = 1.5 V
PSRR
1 kHz, IOUT = 1.5 A,
50
Power-supply rejection VIN = 1.8 V, VOUT = 1.5 V
dB
(VBIAS to VOUT) 300 kHz, IOUT = 1.5 A,
30
VIN = 1.8 V, VOUT = 1.5 V
100 Hz to 100 kHz,
Noise Output noise voltage 25 × VOUT μVRMS
IOUT = 1.5 A, CSS = 0.001 μF
tSTR Minimum startup time RLOAD for IOUT = 1 A, CSS = open 200 μs
ISS Soft-start charging current VSS = 0.4 V 440 nA
VEN, HI Enable input high level 1.1 5.5 V
VEN, LO Enable input low level 0 0.4 V
VEN, HYS Enable pin hysteresis 50 mV
VEN, DG Enable pin deglitch time 20 μs
IEN Enable pin current VEN = 5 V 0.1 1 μA
VIT PG trip threshold VOUT decreasing 85 90 94 %VOUT
VHYS PG trip hysteresis 3 %VOUT
VPG, LO PG output low voltage IPG = 1 mA (sinking), VOUT < VIT 0.3 V
IPG, LKG PG leakage current VPG = 5.25 V, VOUT > VIT 0.1 1 μA
Thermal shutdown Shutdown, temperature increasing 165
TSD °C
temperature Reset, temperature decreasing 140

(1) Adjustable devices tested at 0.8 V; resistor tolerance is not taken into account.
(2) Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
(3) 3.25 V is a test condition of this device and can be adjusted by referring to Figure 8.

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BLOCK DIAGRAM

Current OUT
IN VOUT
Limit

BIAS UVLO
Thermal
0.44mA Limit R1
SS
CSS
Soft-Start 0.8V
Discharge Reference
FB

PG

Hysteresis
EN R2
and Deglitch

0.9 ´ VREF

GND

Table 1. Standard 1% Resistor Values for Programming the Output Voltage (1)
R1 (kΩ) R2 (kΩ) VOUT (V)
Short Open 0.8
0.619 4.99 0.9
1.13 4.53 1
1.37 4.42 1.05
1.87 4.99 1.1
2.49 4.99 1.2
4.12 4.75 1.5
3.57 2.87 1.8
3.57 1.69 2.5
3.57 1.15 3.3

(1) VOUT = 0.8 × (1 + R1 / R2).

Table 2. Standard Capacitor Values for Programming the Soft-Start Time (1)
CSS SOFT-START TIME
Open 0.1 ms
270 pF 0.5 ms
560 pF 1 ms
2.7 nF 5 ms
5.6 nF 10 ms
0.01 μF 18 ms
–7
(1) tSS(s) = 0.8 × CSS(F) / 4.4 × 10 .

DEVICE INFORMATION

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DRC PACKAGE RGW PACKAGE

3-mm x 3-mm SON 5 x 5 QFN
(TOP VIEW) (TOP VIEW)

OUT
NC

NC

NC
IN 1 10 OUT

IN
IN 2 9 OUT

1
Thermal
PG 3 8 FB
Pad
BIAS 4 7 SS
IN 6 20 OUT
EN 5 6 GND
IN 7 19 OUT

IN 8 TPS74801 18 OUT
GND
PG 9 17 NC

BIAS 10 16 FB

11

12

13

14

15
EN

GND

SS
NC

NC
PIN DESCRIPTIONS
NAME DRC (SON) RGW (QFN) DESCRIPTION
IN 1, 2 5-8 Input to the device.
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts
EN 5 11
the regulator into shutdown mode. This pin must not be left unconnected.
SS 7 15 Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time.
If this pin is left unconnected, the regulator output soft-start ramp time is typically
200 μs.
BIAS 4 10 Bias input voltage for error amplifier, reference, and internal control circuits.
Power Good pin. An open-drain, active-high output that indicates the status of
VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-
impedance state. When VOUT is below this threshold the pin is driven to a low-
PG 3 9 impedance state. A pull-up resistor from 10 kΩ to 1 MΩ should be connected
from this pin to a supply of up to 5.5 V. The supply can be higher than the input
voltage. Alternatively, the PG pin can be left unconnected if output monitoring is
not necessary.
Feedback pin. The feedback connection to the center tap of an external resistor
FB 8 16
divider network that sets the output voltage. This pin must not be left floating.
OUT 9, 10 1, 18-20 Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2 μF,
ceramic) is needed from this pin to ground to assure stability.
NC N/A 2-4, 13, 14, 17 No connection. This pin can be left floating or connected to GND to allow better
thermal contact to the top-side plane.
GND 6 12 Ground
Thermal Pad — Should be soldered to the ground plane for increased thermal performance.

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TYPICAL CHARACTERISTICS
At TA = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF,
unless otherwise noted.

VIN LINE REGULATION VBIAS LINE REGULATION

0.20 0.5

0.15 0.4
0.3
0.10
Change in VOUT (%)

Change in VOUT (%)

-40°C 0.2
-40°C
0.05 0.1
0 0
+25°C +125°C
-0.05 -0.1
+125°C +25°C
-0.2
-0.01
-0.3
-0.15
-0.4
-0.20 -0.5
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VIN - VOUT (V) VBIAS - VOUT (V)
Figure 3. Figure 4.

LOAD REGULATION LOAD REGULATION

1.2 0.5
0.4
1.0
0.3
Change in VOUT (%)

Change in VOUT (%)

0.2
0.8 +125°C
0.1
0.6 0
+25°C -40°C
-0.1
0.4
-0.2

0.2 -0.3
-0.4
0 -0.5
0 10 20 30 40 50 0.05 0.5 1.0 1.5
IOUT (mA) IOUT (A)
Figure 5. Figure 6.

VIN DROPOUT VOLTAGE vs VIN DROPOUT VOLTAGE vs

IOUT AND TEMPERATURE (TA) (VBIAS – VOUT) AND TEMPERATURE (TA)
100 200
IOUT = 1.5A
90 180
80 160
+125°C
VDO (VIN - VOUT) (mV)
VDO (VIN - VOUT) (mV)

70 140
60 120
+125°C
50 100
+25°C
40 80
+25°C
30 60
20 40
-40°C -40°C
10 20
0 0
0 0.5 1.0 1.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
IOUT (A) VBIAS - VOUT (V)
Figure 7. Figure 8.

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TYPICAL CHARACTERISTICS (continued)

At TA = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF,
unless otherwise noted.
VIN DROPOUT VOLTAGE vs VBIAS DROPOUT VOLTAGE vs
(VBIAS – VOUT) AND TEMPERATURE (TA) IOUT AND TEMPERATURE (TA)
200 2200
IOUT = 0.5A
180 2000
160

VDO (VBIAS - VOUT) (mV)

VDO (VIN - VOUT) (mV)

1800
140
120 1600
+125°C
100 1400
+25°C
80 1200
+125°C
60 +25°C
1000
40 -40°C
-40°C
800
20
0 600
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 1.0 1.5
VBIAS - VOUT (V) IOUT (A)
Figure 9. Figure 10.

VBIAS PSRR vs FREQUENCY VIN PSRR vs FREQUENCY

90 90
Power-Supply Rejection Ratio (dB)

Power-Supply Rejection Ratio (dB)

80 80
IOUT = 0.1A IOUT = 1.5A
70 70
IOUT = 100mA
60 60
50 50

40 40
IOUT = 0.5A
30 30
VIN = 1.8V
20 VOUT = 1.2V 20 VIN = 1.8V
10 VBIAS = 5V 10 VOUT = 1.2V
CSS = 1nF CSS = 1nF IOUT = 1.5A
0 0
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)
Figure 11. Figure 12.

VIN PSRR vs (VIN – VOUT) NOISE SPECTRAL DENSITY

90 1
Output Spectral Noise Density (mV/ÖHz)

VOUT = 1.2V IOUT = 100mA

Power-Supply Rejection Ratio (dB)

80 IOUT = 1.5A VOUT = 1.2V

CSS = 1nF
70 1kHz

60
10kHz CSS = 0nF
50
0.1
40
100kHz
30
CSS = 10nF
20 CSS = 1nF
500kHz
10

0 0.01
0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 100 1k 10k 100k
VIN - VOUT (V) Frequency (Hz)
Figure 13. Figure 14.

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TYPICAL CHARACTERISTICS (continued)

At TA = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF,
unless otherwise noted.
BIAS PIN CURRENT vs BIAS PIN CURRENT vs
IOUT AND TEMPERATURE (TA) VBIAS AND TEMPERATURE (TA)
2.0 2.0
1.8 1.8
+125°C +125°C
1.6 1.6
1.4 1.4

IBIAS (mA)
1.2 1.2
IBIAS (mA)

+25°C
1.0 1.0
0.8 0.8
-40°C +25°C
0.6 0.6
-40°C
0.4 0.4
0.2 0.2
0 0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
IOUT (A) VBIAS (V)
Figure 15. Figure 16.

SOFT-START CHARGING CURRENT (ISS) vs

TEMPERATURE (TA) LOW-LEVEL PG VOLTAGE vs CURRENT
500 1.0

475 0.9
VOL Low-Level PG Voltage (V)

0.8
450
0.7
425 0.6
ISS (nA)

400 0.5
0.4
375
0.3
350
0.2
325 0.1
300 0
-50 -25 0 25 50 75 100 125 0 2 4 6 8 10 12
Ambient Temperature (°C) PG Current (mA)
Figure 17. Figure 18.

CURRENT LIMIT vs (VBIAS – VOUT)

4.0
VOUT = 0.8V
3.8
+125°C
3.6
3.4
Current Limit (A)

3.2
3.0
-40°C +25°C
2.8
2.6
2.4
2.2
2.0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VBIAS - VOUT (V)
Figure 19.

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TYPICAL CHARACTERISTICS
At TA = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 1 A, VEN = VIN = 1.8 V, VOUT = 1.5 V, CIN = 1 μF, CBIAS = 4.7 μF, and
COUT = 10 μF, unless otherwise noted.
VBIAS LINE TRANSIENT VIN LINE TRANSIENT
CSS = 1nF

COUT = 10mF (Ceramic) COUT = 10mF (Ceramic)

100mV/div 100mV/div

COUT = 2.2mF (Ceramic)

100mV/div
CSS = 1nF

3.8V
5.0V

1V/div 1V/div
3.3V 1V/ms 1.8V 1V/ms

Time (50ms/div) Time (50ms/div)

Figure 20. Figure 21.

OUTPUT LOAD TRANSIENT RESPONSE TURN-ON RESPONSE

COUT = 470mF (OSCON) CSS = 0nF
100mV/div

COUT = 10mF (Ceramic)

100mV/div 0.5V/div CSS = 1nF VOUT

CSS = 2.2nF
COUT = 2.2mF (Ceramic)
100mV/div

1.2V
1.5A VEN
CSS = 1nF 0V
1A/div 1V/div
50mA 1A/ms

Time (50ms/div) Time (1ms/div)

Figure 22. Figure 23.

POWER-UP/POWER-DOWN

VPG (500mV/div) VIN = VBIAS = VEN

1V/div

VOUT

Time (20ms/div)
Figure 24.

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APPLICATION INFORMATION

The TPS74801-Q1 belongs to a family of low dropout regulators that feature soft-start capability. These
regulators use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to
regulate very low input and output voltages.
The use of an NMOS-pass FET offers several critical advantages for many applications. Unlike a PMOS topology
device, the output capacitor has little effect on loop stability. This architecture allows the TPS74801-Q1 to be
stable with any capacitor type of value 2.2 μF or greater. Transient response is also superior to PMOS
topologies, particularly for low VIN applications.
The TPS74801-Q1 features a programmable voltage-controlled soft-start circuit that provides a smooth,
monotonic start-up and limits startup inrush currents that may be caused by large capacitive loads. A power good
(PG) output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with
hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT
capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply
voltages often present in processor-intensive systems.
Figure 25 illustrates the typical application circuit for the TPS74801-Q1 adjustable output device.
VIN IN PG
CIN R3
BIAS
1mF
OUT VOUT
EN TPS74801
VBIAS R1 COUT
SS
CBIAS GND FB 10mF
1mF
CSS R2

R1
(
VOUT = 0.8 ´ 1 +
R2
)
Figure 25. Typical Application Circuit for the TPS74801-Q1 (Adjustable)

R1 and R2 can be calculated for any output voltage using the formula shown in Figure 25. Refer to Table 1 for
sample resistor values of common output voltages. In order to achieve the maximum accuracy specifications, R2
should be ≤ 4.99 kΩ.

INPUT, OUTPUT, AND BIAS CAPACITOR REQUIREMENTS

The device is designed to be stable for all available types and values of output capacitors ≥ 2.2 μF. The device is
also stable with multiple capacitors in parallel, which can be of any type or value.
The capacitance required on the IN and BIAS pins strongly depends on the input supply source impedance. To
counteract any inductance in the input, the minimum recommended capacitor for VIN and VBIAS is 1 μF. If VIN and
VBIAS are connected to the same supply, the recommended minimum capacitor for VBIAS is 4.7 μF. Good quality,
low ESR capacitors should be used on the input; ceramic X5R and X7R capacitors are preferred. These
capacitors should be placed as close the pins as possible for optimum performance.

TRANSIENT RESPONSE
The TPS74801-Q1 was designed to have excellent transient response for most applications with a small amount
of output capacitance. In some cases, the transient response may be limited by the transient response of the
input supply. This limitation is especially true in applications where the difference between the input and output is
less than 300 mV. In this case, adding additional input capacitance improves the transient response much more
than just adding additional output capacitance would do. With a solid input supply, adding additional output
capacitance reduces undershoot and overshoot during a transient event; refer to Figure 22 in the Typical

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Characteristics section. Because the TPS74801-Q1 is stable with output capacitors as low as 2.2 μF, many
applications may then need very little capacitance at the LDO output. For these applications, local bypass
capacitance for the powered device may be sufficient to meet the transient requirements of the application. This
design reduces the total solution cost by avoiding the need to use expensive, high-value capacitors at the LDO
output.

DROPOUT VOLTAGE
The TPS74801-Q1 offers very low dropout performance, making it well-suited for high-current, low VIN / low VOUT
applications. The low dropout of the TPS74801-Q1 allows the device to be used in place of a DC-DC converter
and still achieve good efficiency. This provides designers with the power architecture for their application to
achieve the smallest, simplest, and lowest cost solution.
There are two different specifications for dropout voltage with the TPS74801-Q1. The first specification (shown in
Figure 26) is referred to as VIN Dropout and is used when an external bias voltage is applied to achieve low
dropout. This specification assumes that VBIAS is at least 3.25 V (1) above VOUT, which is the case for VBIAS when
powered by a 5-V rail with 5% tolerance and with VOUT = 1.5 V. If VBIAS is higher than VOUT 3.25 V (1), VIN dropout
is less than specified.
BIAS IN
VBIAS = 5V ±5%
VIN = 1.8V
VOUT = 1.5V
IOUT = 1.5A
Reference Efficiency = 83%
OUT
VOUT

COUT

FB
Simplified Block Diagram

Figure 26. Typical Application of the TPS74801-Q1 Using an Auxiliary Bias Rail

VIN

VBIAS = 3.3V ±5%

BIAS IN
VIN = 3.3V ± 5V
VOUT = 1.5V
IOUT = 1.5A
Reference Efficiency = 45%
OUT
VOUT

COUT

FB
Simplified Block Diagram

Figure 27. Typical Application of the TPS74801-Q1 Without an Auxiliary Bias Rail

The second specification (shown in Figure 27) is referred to as VBIAS Dropout and applies to applications where
IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary bias
voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because
VBIAS provides the gate drive to the pass FET; therefore, VBIAS must be 1.6 V above VOUT. Because of this usage,
IN and BIAS tied together easily consume huge power. Pay attention not to exceed the power rating of the IC
package.

(1) 3.25 V is a test condition of this device and can be adjusted by referring to Figure 8.
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PROGRAMMABLE SOFT-START
The TPS74801-Q1 features a programmable, monotonic, voltage-controlled soft-start that is set with an external
capacitor (CSS). This feature is important for many applications because it eliminates power-up initialization
problems when powering FPGAs, DSPs, or other processors. The controlled voltage ramp of the output also
reduces peak inrush current during start-up, minimizing start-up transient events to the input power bus.
To achieve a linear and monotonic soft-start, the TPS74801-Q1 error amplifier tracks the voltage ramp of the
external soft-start capacitor until the voltage exceeds the internal reference. The soft-start ramp time depends on
the soft-start charging current (ISS), soft-start capacitance (CSS), and the internal reference voltage (VREF), and
can be calculated using Equation 1:
(VREF ´ CSS)
tSS =
ISS (1)
If large output capacitors are used, the device current limit (ICL) and the output capacitor may set the start-up
time. In this case, the start-up time is given by Equation 2:
(VOUT(NOM) ´ COUT)
tSSCL =
ICL(MIN) (2)
where:
VOUT(NOM) is the nominal output voltage,
COUT is the output capacitance, and
ICL(MIN) is the minimum current limit for the device.
In applications where monotonic startup is required, the soft-start time given by Equation 1 should be set greater
than Equation 2.
The maximum recommended soft-start capacitor is 0.015 μF. Larger soft-start capacitors can be used and do not
damage the device; however, the soft-start capacitor discharge circuit may not be able to fully discharge the soft-
start capacitor when enabled. Soft-start capacitors larger than 0.015 μF could be a problem in applications where
it is necessary to rapidly pulse the enable pin and still require the device to soft-start from ground. CSS must be
low-leakage; X7R, X5R, or C0G dielectric materials are preferred. Refer to Table 2 for suggested soft-start
capacitor values.

SEQUENCING REQUIREMENTS
VIN, VBIAS, and VEN can be sequenced in any order without causing damage to the device. However, for the soft-
start function to work as intended, certain sequencing rules must be applied. Connecting EN to IN is acceptable
for most applications, as long as VIN is greater than 1.1 V and the ramp rate of VIN and VBIAS is faster than the
set soft-start ramp rate. If the ramp rate of the input sources is slower than the set soft-start time, the output
tracks the slower supply minus the dropout voltage until it reaches the set output voltage. If EN is connected to
BIAS, the device soft-starts as programmed, provided that VIN is present before VBIAS. If VBIAS and VEN are
present before VIN is applied and the set soft-start time has expired, then VOUT tracks VIN. If the soft-start time
has not expired, the output tracks VIN until VOUT reaches the value set by the charging soft-start capacitor.
Figure 28 shows the use of an RC-delay circuit to hold off VEN until VBIAS has ramped. This technique can also
be used to drive EN from VIN. An external control signal can also be used to enable the device after VIN and
VBIAS are present.

NOTE
When VBIAS and VEN are present and VIN is not supplied, this device outputs approximately
50 μA of current from OUT. Although this condition does not cause any damage to the
device, the output current may charge up the OUT node if total resistance between OUT
and GND (including external feedback resistors) is greater than 10 kΩ.

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VIN IN OUT VOUT

CIN R1
COUT
BIAS TPS74801 FB

VBIAS R R2

CBIAS EN GND SS

C CSS

Figure 28. Soft-Start Delay Using an RC Circuit to Enable the Device

OUTPUT NOISE
The TPS74801-Q1 provides low output noise when a soft-start capacitor is used. When the device reaches the
end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 0.001-μF
soft-start capacitor, the output noise is reduced by half and is typically 30-μVRMS for a 1.2-V output (10 Hz to 100
kHz). Further increasing CSS has little effect on noise. Because most of the output noise is generated by the
internal reference, the noise is a function of the set output voltage. The RMS noise with a 0.001-μF soft-start
capacitor is given in Equation 3:
mVRMS
VN(mVRMS) = 25 ( V
)x V
OUT(V)
(3)
The low output noise of the TPS74801-Q1 makes it a good choice for powering transceivers, PLLs, or other
noise-sensitive circuitry.

ENABLE AND SHUTDOWN

The enable (EN) pin is active high and is compatible with standard digital signaling levels. VEN below 0.4 V turns
the regulator off, while VEN above 1.1 V turns the regulator on. Unlike many regulators, the enable circuitry has
hysteresis and deglitching for use with relatively slowly ramping analog signals. This configuration allows the
TPS74801-Q1 to be enabled by connecting the output of another supply to the EN pin. The enable circuitry
typically has 50 mV of hysteresis and a deglitch circuit to help avoid on-off cycling as a result of small glitches in
the VEN signal.
The enable threshold is typically 0.8 V and varies with temperature and process variations. Temperature
variation is approximately –1 mV/°C; process variation accounts for most of the rest of the variation to the 0.4-V
and 1.1-V limits. If precise turn-on timing is required, a fast rise-time signal must be used to enable the
TPS74801-Q1.
If not used, EN can be connected to either IN or BIAS. If EN is connected to IN, it should be connected as close
as possible to the largest capacitance on the input to prevent voltage droops on that line from triggering the
enable circuit.

POWER GOOD
The power good (PG) pin is an open-drain output and can be connected to any 5.5-V or lower rail through an
external pull-up resistor. This pin requires at least 1.1 V on VBIAS in order to have a valid output. The PG output is
high-impedance when VOUT is greater than VIT + VHYS. If VOUT drops below VIT or if VBIAS drops below 1.9 V, the
open-drain output turns on and pulls the PG output low. The PG pin also asserts when the device is disabled.
The recommended operating condition of PG pin sink current is up to 1 mA, so the pull-up resistor for PG should
be in the range of 10 kΩ to 1 MΩ. If output voltage monitoring is not needed, the PG pin can be left floating.

INTERNAL CURRENT LIMIT

The TPS74801-Q1 features a factory-trimmed, accurate current limit that is flat over temperature and supply
voltage. The current limit allows the device to supply surges of up to 2 A and maintain regulation. The current
limit responds in approximately 10 μs to reduce the current during a short-circuit fault.

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The internal current limit protection circuitry of the TPS74801-Q1 is designed to protect against overload
conditions. It is not intended to allow operation above the rated current of the device. Continuously running the
TPS74801-Q1 above the rated current degrades device reliability.

THERMAL PROTECTION
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is enabled.
Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit may
cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of
overheating.
Activation of the thermal protection circuit indicates excessive power dissipation or inadequate heatsinking. For
reliable operation, junction temperature should be limited to 150°C maximum. To estimate the margin of safety in
a complete design (including heatsink), increase the ambient temperature until thermal protection is triggered;
use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 40°C
above the maximum expected ambient condition of the application. This condition produces a worst-case junction
temperature of 150°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS74801-Q1 is designed to protect against overload conditions. It is not
intended to replace proper heatsinking. Continuously running the TPS74801-Q1 into thermal shutdown degrades
device reliability.

LAYOUT RECOMMENDATIONS AND POWER DISSIPATION

An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage drop on
the input of the device during load transients, the capacitance on IN and BIAS should be connected as close as
possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the
input source and can, therefore, improve stability. To achieve optimal transient performance and accuracy, the
top side of R1 in Figure 25 should be connected as close as possible to the load. If BIAS is connected to IN, it is
recommended to connect BIAS as close to the sense point of the input supply as possible. This connection
minimizes the voltage drop on BIAS during transient conditions and can improve the turn-on response.
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the thermal pad
is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends
on input voltage and load conditions and can be calculated using Equation 4:
PD = (VIN - VOUT) ´ IOUT (4)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
The primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can
be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper
PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance
depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of
the device and can be calculated using Equation 5:
(150°C - TA)
RθJA =
PD (5)
Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can
be estimated using Figure 29.

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140

120

100

qJA (°C/W)
80

60

40

20

0
0 1 2 3 4 5 6 7 8 9 10
Board Copper Area (in2)

Note: θJA value at board size of 9 in2 (that is, 3-in × 3-in) is a JEDEC standard.

Figure 29. θJA vs Board Size

Figure 29 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as
a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate
actual thermal performance in real application environments.

NOTE
When the device is mounted on an application PCB, it is strongly recommended to use
ΨJT and ΨJB, as explained in the Estimating Junction Temperature section.

ESTIMATING JUNCTION TEMPERATURE

Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can
be estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older θJC,Top
parameter is listed as well.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD (6)
Where PD is the power dissipation shown by Equation 4, TT is the temperature at the center-top of the IC
package, and TB is the PCB temperature measured 1mm away from the IC package on the PCB surface (see
Figure 31).

NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).

For more information about measuring TT and TB, see the application note SBVA025, Using New Thermal
Metrics, available for download at www.ti.com.
By looking at Figure 30, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That
is, using ΨJT or ΨJB with Equation 6 is a good way to estimate TJ by simply measuring TT or TB, regardless of the
application board size.

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12

10
YJB

YJT and YJB (°C/W)

8

DRC
6
RGW

2
YJT

0
0 1 2 3 4 5 6 7 8 9 10
Board Copper Area (in2)

Figure 30. ΨJT and ΨJB vs Board Size

For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics,
refer to application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For
further information, refer to application report SPRA953, IC Package Thermal Metrics, also available on the TI
website.

TT on top
of IC

TB on PCB
TT on top of IC
surface TB on PCB

1mm 1mm

(a) Example DRC (SON) Package Measurement (b) Example RGW (QFN) Package Measurement

(1) TT is measured at the center of both the X- and Y-dimensional axes.

(2) TB is measured below the package lead on the PCB surface.

Figure 31. Measuring Points for TT and TB

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REVISION HISTORY

Changes from Revision A (February 2011) to Revision B Page

• Added AEC-Q100 info to Features. ...................................................................................................................................... 1

• Added an extra sentence to the Description. ........................................................................................................................ 1
• Removed Ordering Information table. ................................................................................................................................... 2
• Changed Abs Max condition statement. ............................................................................................................................... 2
• Changed TJ max temp limit from 125 to 150. ....................................................................................................................... 2
• Added ESD ratings to Abs Max table. .................................................................................................................................. 2
• Added RGW package to Thermal Information table. ............................................................................................................ 3
• Added TA –40°C to 125°C in Electrical Characteristics condition; changed TJ to TA. .......................................................... 4
• Changed TJ to TA in VREF test condition. ............................................................................................................................ 4
• Removed TA and TJ from Electrical Characteristics table. .................................................................................................... 4
• Added second package to Device Information section (Pinout drawing and Pin Descriptions table). ................................. 6
• Changed TJ to TA throughout entire Typical Characteristics section. ................................................................................... 7
• Image update - changed Junction Temperature to Ambient Temperature. .......................................................................... 9
• Changed 125°C to 150°C in Thermal Protection section. .................................................................................................. 15
• Image update - changed temperature from 125°C to 150°C in equation. .......................................................................... 15
• Replaced ΨJT and ΨJB vs Board Size with 2-package image. ........................................................................................... 17
• Replaced Measuring Points for TT and TB with 2-package image. ..................................................................................... 17

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 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS74801QRGWRQ1 ACTIVE VQFN RGW 20 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TPS
74801Q
TPS74801TDRCRQ1 ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 QVK

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

OTHER QUALIFIED VERSIONS OF TPS74801-Q1 :

• Catalog: TPS74801

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 31-Mar-2017

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS74801QRGWRQ1 VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TPS74801TDRCRQ1 VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 31-Mar-2017

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS74801QRGWRQ1 VQFN RGW 20 3000 367.0 367.0 35.0
TPS74801TDRCRQ1 VSON DRC 10 3000 367.0 367.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
DRC 10 VSON - 1 mm max height
3 x 3, 0.5 mm pitch PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4226193/A

www.ti.com
 PACKAGE OUTLINE
DRC0010J SCALE 4.000
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

3.1 B
A
2.9

PIN 1 INDEX AREA

3.1
2.9

1.0 C
0.8

SEATING PLANE
0.05
0.00 0.08 C

1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED 4X (0.25)
THERMAL PAD

5 6

2X 11 SYMM
2
2.4 0.1

10
1
8X 0.5 0.30
10X
0.18
PIN 1 ID SYMM
0.1 C A B
(OPTIONAL)
0.5 0.05 C
10X
0.3

4218878/B 07/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
DRC0010J VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(1.65)
(0.5)

10X (0.6)

1
10

10X (0.24)
11
SYMM (2.4)
(3.4)

(0.95)
8X (0.5)

5 6

(R0.05) TYP

( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:20X

0.07 MIN
0.07 MAX EXPOSED METAL ALL AROUND
ALL AROUND
EXPOSED METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4218878/B 07/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DRC0010J VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

2X (1.5)
(0.5)
SYMM
EXPOSED METAL
11 TYP

10X (0.6)
1
10
(1.53)
10X (0.24) 2X
(1.06)

SYMM

(0.63)

8X (0.5)

6
5

(R0.05) TYP
4X (0.34)

4X (0.25)
(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 11:

80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X

4218878/B 07/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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